JP2003330390A - Active matrix substrate and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix substrate using an opaque plastic substrate. <P>SOLUTION: The active matrix substrate is provided with a substrate, a plurality of signal wiring 5 formed on the substrate, a plurality of scanning wiring 2 and a plurality of auxiliary capacity wiring 20 crossing the signal wiring 5, a plurality of thin film transistors 10 which are formed on the substrate and are operated in response to signals applied to corresponding scanning wiring 2, a plurality of lower layer pixel electrodes 14B which can be electrically connected to corresponding signal wiring 5 via the thin film transistors 10, and upper layer pixel electrodes 14A which are formed in the upper layer of the lower layer pixel electrodes 14B with an inter-layer insulating film between them and are electrically connected to the lower layer pixel electrodes 14B via contact holes 22 formed in the inter-layer insulating film. Further, the active matrix substrate is provided with conductive members 9 for connecting the lower layer pixel electrodes 14B to the corresponding thin film transistors 10, and the conductive members 9 project from the lower layer pixel electrodes 14B in the extending direction of the signal wiring 5, and the scanning wiring 2 crosses the conductive members 9. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate used for an active matrix type liquid crystal display device such as a liquid crystal television, a liquid crystal monitor, a notebook computer, a sensor, an organic EL and the like, and a manufacturing method thereof. The invention also relates to electronic devices made from this active matrix substrate.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been used not only as image display terminals of desktop computers and television devices used indoors, but also as mobile phones, notebook or laptop personal computers, portable televisions, and digital cameras. It is also widely used as an information display element in various portable electronic devices such as digital camcorders, and in-vehicle electronic devices such as car navigation devices.

Among various liquid crystal display devices, an active matrix type using a thin film transistor (TFT) can maintain high image quality and can easily increase the size of the display device.
It has become mainstream these days.

On the other hand, mobile phones and PDAs (personal digital assistants)
It is strongly desired to provide a liquid crystal display device using a plastic substrate which is light and has excellent impact resistance, as its application to mobile applications such as is expanding.

However, the plastic substrate has a larger linear expansion coefficient due to heat than the glass substrate, and is more likely to absorb moisture and chemicals. As a result, the substrate dimensions change significantly during the manufacture of the active matrix substrate. For example, the linear expansion coefficient of glass substrate is 3 to 5 ppm / ° C, while that of plastic substrate is 50 to 100 ppm.
/ ° C. Substrate expansion and contraction due to water absorption hardly occurs in the glass substrate, but in the plastic substrate,
Expansion and contraction of 6000 ppm occurs.

The conventional active matrix substrate cannot cope with such a large expansion and contraction of the substrate. The above reason will be described with reference to FIGS. 6 and 7. FIG. 6 shows a layout of a unit pixel region of a general active matrix substrate, and FIG. 7 is a sectional view thereof.

In the active matrix substrate shown, a plurality of scanning wirings 102 and a plurality of signal wirings 105 are provided on a glass substrate 101. The scanning wirings 102 and the signal wirings 105 are located at the levels of different layers and intersect with each other while being insulated and separated by the insulating film 104 located in the intermediate layer.

A pixel electrode 114 is formed in a rectangular area surrounded by the scanning wiring 102 and the signal wiring 105. The pixel electrode 114 receives a signal charge from the signal wiring 105 via the thin film transistor 110 formed in the vicinity of the intersection of the scanning wiring 102 and the signal wiring 105. An auxiliary capacitance line 120 parallel to the scan line 102 is formed below the pixel electrode 114, and
An auxiliary capacitance is formed between 14 and the auxiliary capacitance line 120.

The thin film transistor 110 is composed of the scanning wiring 10
2, a branch line (gate electrode 103) protruding vertically, a gate insulating film 104 that covers the gate electrode 103, an intrinsic semiconductor layer 106 that overlaps with the gate electrode 103 through the gate insulating film, and an intrinsic semiconductor layer 106. The formed impurity-doped semiconductor layer 107 and the impurity-doped semiconductor layer 107
Source electrode 108 and drain electrode 109 connected to the source / drain region of the intrinsic semiconductor layer 106 via
Is equipped with. The source electrode 108 is a branch line that vertically projects from the signal line 105, and is formed integrally with the signal line 105.

The drain electrode 109 is a conductive member that electrically connects the drain region of the thin film transistor 110 and the pixel electrode 114, and is formed together with the signal wiring 105 and the source electrode 108 by patterning a metal film. That is, in this example, the signal wiring 1
05, the source electrode 108, and the drain electrode 109 belong to the same layer, and the mutual positional relationship is defined by the mask pattern used in the photolithography process.

The source electrode 108 and the drain electrode 109 are connected via the channel region of the intrinsic semiconductor layer 106, and the conduction state of the channel region is the gate electrode 1.
Controlled by the 03 potential. Thin film transistor 11
0 is generally an n-channel type, and when the potential of the gate electrode 103 exceeds a threshold value, the thin film transistor is turned on, and the source electrode 108 and the drain electrode 109 are electrically connected.

In order for the thin film transistor 110 to operate normally, the source electrode 108 and the drain electrode 10
It is necessary to overlap at least a part of 9 with the gate electrode 103. Since the line width of the gate electrode 103 is about 10 μm or less, the signal wiring 105 and the source electrode 1
In the photolithography process for forming the gate electrode 08 and the drain electrode 109, it is necessary to perform alignment with the gate electrode 103 already formed on the substrate 121 (hereinafter referred to as alignment) with high accuracy. Usually, an alignment accuracy of ± several μm or less is required.

On the other hand, even if the temperature and humidity are controlled during the process, the dimensional change of the plastic substrate during the TFT process reaches 500 to 1000 ppm. As an example, consider the case of manufacturing a 3.9 inch QVGA active matrix substrate. 24 pixel size
7.5 μm × 82.5 μm, and the display area size is 59400 mm in the Y direction and 792000 mm in the X direction.
1000 pp between the photolithography process for the gate electrode and the photolithography process for the source electrode
± 29.7μ in the Y direction when the substrate expands or contracts by m
A misalignment of ± 39.6 μm occurs in the m and X directions.

As described above, the conventional active matrix substrate requires the alignment accuracy of ± several μm or less, so that the TFT active matrix substrate cannot be formed on the plastic substrate.

On the other hand, the present applicant filed Japanese Patent Application No. 2001-1527.
According to the active matrix substrate disclosed in Japanese Patent No. 79, it is possible to deal with large substrate expansion and contraction. This active matrix substrate will be described with reference to FIGS. 8 and 9. FIG. 8 is a plan view showing a layout example of the active matrix substrate disclosed in Japanese Patent Application No. 2001-152779. FIG. 9 is a cross-sectional view taken along the line AA ′ of FIG. 8 and shows a cross section of the thin film transistor portion.

This active matrix substrate employs a channel-etch type TFT. The scanning wiring 2 also serving as a gate electrode and the auxiliary capacitance wiring 20 are formed of a metal layer such as tantalum. The gate insulating film 4 and the semiconductor layer 6 formed of amorphous silicon are present in the upper layer. A resist mask (not shown) for patterning the semiconductor layer 6 is formed by forming a resist layer on the semiconductor layer 6 and then exposing the back surface of the substrate using the scanning wiring 2 as a mask. As a result, since the semiconductor layer 6 is patterned using the obtained resist mask, the semiconductor layer 6 is self-aligned with the scan wiring 2, and the size and position of the semiconductor layer 6 are the same as the size of the scan wiring 2. And position.

A signal wiring 5 also serving as a source electrode, and
The conductive member 9 also serving as the drain electrode intersects with the lower semiconductor layer 6 via the gate insulating film 4. On the other hand, the auxiliary capacitance line 20 intersects the lower layer pixel electrode 14B via the gate insulating film 4 and the semiconductor layer 6 to form an auxiliary capacitance. The lower layer pixel electrode 14B and the conductive member 9 are electrically connected.

An interlayer insulating film 21 is arranged on the TFT 10, the scanning wiring 2, the signal wiring 5, the conductive member 9 and the lower layer pixel electrode 14B. The upper layer pixel electrode 14A formed on the interlayer insulating film 21 is made of a reflective electrode material such as Al. A contact hole 22 reaching a part of the lower layer pixel electrode 14B is formed in the interlayer insulating film 21, and the upper layer pixel electrode 14A and the lower layer pixel electrode 14B are electrically connected through the contact hole 22. ing.

According to the active matrix substrate having the above structure, the necessary alignment margin ± Δy in the Y-axis direction between the scanning wiring layer and the signal wiring layer is expressed by the following equation.

Δy = (P _pitch −W _g −W _cs −3G _sd −2W _s ) / 4 Formula (1)

Here, P _pitch is the _pitch of the pixels in the Y-axis direction, W _g is the line width of the scanning wiring 2 (size in the Y-axis direction), W _cs
Is the line width (size in the Y-axis direction) of the auxiliary capacitance line 20, G _sd is the gap in the Y-axis direction between the source electrode and the drain electrode,
W _s is the line width of the signal wiring 5 (the Y-axis direction size of the portion extending in the X-axis direction). On the other hand, theoretically, the alignment is completely free from misalignment in the X-axis direction.

3.9 inch QVG having such a structure
When manufacturing the A active matrix substrate, for example, an alignment margin of ± 39.4 μm can be secured in the Y direction, so that an active matrix array that operates normally even when the substrate expands or contracts by 1327 ppm can be realized.

[0023]

[Problems to be Solved by the Invention] However, Japanese Patent Application No. 2
In order to manufacture the active matrix substrate disclosed in No. 001-152779, it is necessary to perform an exposure process from the back surface side of the substrate. Therefore, the substrate needs to be transparent to the light for exposing the resist.

However, a general plastic material has a property that the higher the light transmittance thereof is, the lower the heat resistance temperature is. Therefore, in order to increase the heat resistance temperature (softening point) of the plastic substrate, if a plastic material is mixed with a filler or the like. , The substrate becomes opaque.

In order to form a TFT on a plastic substrate, it is necessary that the plastic substrate withstand processing at 220 ° C. or higher. At present, the heat resistant temperature of the transparent plastic substrate that can be used is as low as about 100 to 200 ° C and 250 ° C.
The plastic substrate material having the above softening point is opaque.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an active matrix substrate which can avoid the problem of misalignment even when an opaque plastic substrate is used.

[0027]

An active matrix substrate according to the present invention includes a substrate, a plurality of signal wirings formed on the substrate, a plurality of scanning wirings and a plurality of auxiliary capacitance wirings intersecting the signal wirings. A plurality of thin film transistors that are formed on the substrate and operate in response to a signal applied to the corresponding scanning wiring, and a plurality of lower layers that can be electrically connected to the corresponding signal wiring through the thin film transistors. A pixel electrode and an upper layer pixel electrode formed in an upper layer of the lower layer pixel electrode via an interlayer insulating film and electrically connected to the lower layer pixel electrode via a contact hole formed in the interlayer insulating film. An active matrix substrate comprising: a conductive member for connecting the lower layer pixel electrode to a thin film transistor corresponding to the lower pixel electrode. Protrudes from the lower pixel electrode in a direction in which the signal line extends, the scanning lines intersect with the conductive members.

In a preferred embodiment, a plurality of auxiliary capacitance lines intersecting with the signal lines via the insulating film are further provided, and each of the auxiliary capacitance lines intersects with a corresponding lower layer pixel electrode. ing.

In a preferred embodiment, both the scanning wiring and the auxiliary capacitance wiring are formed by patterning the same conductive film.

In a preferred embodiment, the extending direction of the scanning line is the X axis, the extending direction of the signal line is the Y axis, the length of the conductive member in the Y axis direction is L1, and the length of the lower layer pixel electrode is the Y axis direction. L2, the scanning wiring line width is W _g , the auxiliary capacitance wiring line width is W _cs , and the scanning wiring pitch is P _gg , (L1−W _g ) ≦ (L2−W _cs ), and L1 + L2 The relationship of ≦ P _gg is satisfied.

In a preferred embodiment, the signal line, the lower layer pixel electrode, and the conductive member are all formed by patterning the same conductive film.

In a preferred embodiment, the substrate is
It is formed of a material that is opaque to the light used for exposing the photosensitive resin.

In a preferred embodiment, the material is mainly composed of an opaque resin.

In a preferred embodiment, a source electrode that branches from the signal line and intersects the scanning line is provided, and an intersection of the conductive member and the scanning line is an intersection of the signal line and the scanning line. It is also sandwiched at the intersection of the source electrode and the scanning wiring.

In a preferred embodiment, the distance between the signal line and the conductive member is substantially equal to the distance between the conductive member and the source electrode.

In a preferred embodiment, the channel portion of the thin film transistor is located substantially in the center of adjacent signal lines.

In a preferred embodiment, the channel portion of the thin film transistor is covered with the upper layer pixel electrode.

In a preferred embodiment, the semiconductor layer of each thin film transistor is self-aligned with the scanning line located thereabove, and the semiconductor layer intersects with the signal line and the conductive member.

The electronic device of the present invention is characterized by having any one of the above active matrix substrates.

A method of manufacturing an active matrix substrate according to the present invention comprises a plurality of signal wirings, lower pixel electrodes,
And a step of forming a conductive member protruding from the lower layer pixel electrode, a step of forming a semiconductor thin film so as to cover the signal wiring, the lower layer pixel electrode, and the lower layer pixel electrode, and a gate insulating film on the semiconductor thin film. Forming a conductive film on the gate insulating film, forming a resist mask for defining the scanning wiring on the conductive film, the conductive film, the gate insulating film, and A portion of the semiconductor thin film that is not covered by the resist mask is removed to form the scanning wiring that intersects with the conductive member from the conductive film, and then a semiconductor layer that is self-aligned with the scanning wiring. Of the semiconductor thin film, a step of forming an interlayer insulating film so as to cover the scanning wiring, and a contact hole formed on the interlayer insulating film. Comprising a step of forming the lower-layer pixel electrode electrically connected upper pixel electrode on the interlayer insulating film through.

In a preferred embodiment, the resist mask has a pattern that defines an auxiliary capacitance line in addition to the scan line, and the trap line is formed so as to intersect with the lower layer pixel electrode when the scan line is formed. Form capacitance wiring.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of an active matrix substrate according to the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is a plan view showing the layout of the active matrix substrate in this embodiment. Figure 2
2 is a cross-sectional view taken along the line AA ′ of FIG. 1, showing a cross section along the channel direction of the thin film transistor (TFT) 10.

The TFT 10 in the active matrix substrate of this embodiment has a so-called staggered structure, and the gate electrode (scanning wiring) 2 is located above the semiconductor layer of the TFT 10.

In the present embodiment, the signal wiring 5, the lower layer pixel electrode 14B, and the conductive member 9 are formed on the plastic substrate 1. These are all formed by patterning the same conductive film and are located in the same layer.

The conductive member 9 plays a role of connecting the lower layer pixel electrode 14B to the TFT corresponding thereto, and protrudes from the lower layer pixel electrode 14B along the direction (Y-axis direction) in which the signal line 2 extends, and has a predetermined length. It grows by the length.

The scanning line 2 and the auxiliary capacitance line 20 are located above the signal line 5, the lower layer pixel electrode 14B, and the conductive member 9 with the insulating film interposed therebetween. The layout is configured such that the scanning line 2 intersects with the conductive member 9 and the auxiliary capacitance line 20 intersects with the lower layer pixel electrode 14B.

The lower layer pixel electrode 14B is connected to the TFT 10 via the conductive member 9. The TFT 10 switches the electrical conduction / non-conduction state between the signal line 5 and the lower layer pixel electrode 14B.

An interlayer insulating film 21 is formed on the plastic substrate 1 so as to cover the above structure, and an upper layer pixel electrode 14A is arranged on the interlayer insulating film 21. As shown in FIG. 1, the upper layer pixel electrode 14A is located almost directly above the lower layer pixel electrode 14B, and is electrically connected to the lower layer pixel electrode 14B through a contact hole 22 formed in the interlayer insulating film 21. ing. The upper layer pixel electrode 14A is formed of, for example, a reflective electrode material such as Al, and preferably completely covers the TFT 10.

As shown in FIG. 2, in the present embodiment,
Under the scan line 2, the gate insulating film 4 and the semiconductor layer 6 are provided.
Exists. The semiconductor layer 6 is formed of, for example, amorphous silicon and provides a channel region of the TFT 10.
The TFT 10 is provided under the gate insulating film 4 and the semiconductor layer 6.
The signal wiring 5 also serving as the source electrode and the conductive member 9 also serving as the drain electrode exist. The semiconductor layer 6 is shown in FIG.
Although it exists in the entire region of the lower layer of the scanning wiring 2 shown in FIG. 1, the portion functioning as the channel of the TFT is only in the region indicated by reference numeral “10” in FIG.

On the other hand, the gate insulating film 4 and the semiconductor layer 6 are present under the auxiliary capacitance wiring 20, and the lower layer pixel electrode 14B is present under these. Auxiliary capacitance wiring 20
The auxiliary capacitance 20 is formed between the lower pixel electrode 14B and the lower layer pixel electrode 14B.

Next, FIGS. 3A to 3C and FIG.
An example of a method for manufacturing the active matrix substrate will be described with reference to (a) to (c).

FIGS. 3 (a) to 3 (c) show a planar layout in a main process step for a certain arbitrary pixel region, and FIGS. 4 (a) to 4 (c) show a layout from FIG. 3 (a). FIG. 9 is a cross-sectional view of the TFT at a process step corresponding to (c).

First, as shown in FIGS. 3 (a) and 4 (a), a plurality of signal lines 5, conductive members 9 and lower layer pixel electrodes 14B are formed on an opaque plastic substrate 1. The signal line 5 and the lower layer pixel electrode 4B have a film thickness of 200
It is formed from titanium (Ti) having a thickness of about nm.

More specifically, after depositing a Ti film having a thickness of about 200 nm on the plastic substrate 1 by the sputtering method or the like, the impurity-added semiconductor layer 7 is formed by the plasma CVD method.
Is deposited on the Ti film. In this embodiment, as the impurity-added semiconductor layer 7, an amorphous silicon layer (n ⁺ -type a-Si layer: thickness 10 to 50 n) doped with n-type impurities is used.
m) is used. Then, the impurity-doped semiconductor layer 7 and the Ti film are patterned by the photolithography and etching process using the first mask to form the signal line 5, the conductive member 9, and the lower layer pixel electrode 14B. Signal wiring 5, conductive member 9, and lower layer pixel electrode 14
B is formed of a Ti film, but T is formed on the upper surface thereof.
Impurity-doped semiconductor layer 7 patterned similarly to the i film
Exists. The impurity-added semiconductor layer 7 includes the signal wiring 5 and the conductive member 9 formed of a metal material such as Ti.
Function as a contact layer that forms ohmic contact with the semiconductor layer deposited in the next step.

In the present specification, the signal wiring 5,
The conductive member 9 and the lower layer pixel electrode 14B are collectively referred to as
Sometimes referred to as the "source layer".

Next, the intrinsic semiconductor layer 6 (thickness 100 to 200 nm) made of non-doped amorphous silicon and the gate insulating film 4 made of silicon nitride (SiN _x ) were formed by chemical vapor deposition (CVD method).
(Thickness 200-500 nm) is deposited on the plastic substrate 1 in this order. In this way, the signal line 5, the conductive member 9, and the lower layer pixel electrode 14B are completely covered with the semiconductor layer 6 and the gate insulating film 4.

Next, the scanning line 2 and the auxiliary capacitance line 20 are formed on the gate insulating film 4. In this specification, the scanning line 2 and the auxiliary capacitance line 20 are collectively referred to as a “gate layer”. The scanning wiring 2 and the auxiliary capacitance wiring 20 have a thickness of, for example, 200 n by using a sputtering method or the like.
After depositing a titanium (Ti) film having a thickness of about m, the Ti film is patterned by a photolithography and etching process using a second mask. As shown in FIGS. 3B and 4B, the scanning wiring 2 is patterned so as to intersect with the conductive member 9, and the auxiliary capacitance wiring 20 is patterned so as to intersect with the lower layer pixel electrode 14B.

Next, the scanning wiring 2 and the auxiliary capacitance wiring 20
The TFT 10 is completed by etching the gate insulating film 4, the semiconductor layer 6, and the impurity-added semiconductor layer 7 using the as a mask. The semiconductor layer 6 is formed in self-alignment with the scanning wiring 2. Since the impurity-doped semiconductor layer 7 is patterned again by the mask for patterning the semiconductor layer 6, the impurity-doped semiconductor layer 7 is
A region where the scanning wiring 2 overlaps with the signal wiring 5 and the conductive member 9 and the auxiliary capacitance wiring 20 are formed in the lower layer pixel electrode 1.
It exists only in the area overlapping with 4B. As a result, the linear semiconductor layer 6 immediately below the scanning wiring 2 is electrically connected to the lower signal wiring 5 and the conductive member 9 via the impurity-added semiconductor layer 7.

After that, after covering the TFT 10 with an interlayer insulating film (thickness: for example, 0.5 to 3 μm) 21 made of an inorganic insulating film or an organic insulating film, a contact hole is formed by photolithography using a third mask. 22 is formed.
As shown in FIG. 3C, the contact hole 22 is formed so as to reach the lower layer pixel electrode 14B, but is arranged at a position where it does not overlap the auxiliary capacitance line 20.

In the step of depositing the interlayer insulating film 21, it is preferable to select a material or a film forming method in which the expansion and contraction of the substrate 1 does not easily occur. Generally, the deposition process of the organic insulating film is less likely to cause the expansion and contraction of the substrate than the deposition process of the inorganic insulating film, and therefore the interlayer insulating film is preferably formed of an organic insulating material.

On the interlayer insulating film 21, Al, Al alloy,
Alternatively, a reflective electrode film formed of a material such as Ag alloy is deposited. The thickness of the reflective electrode film is set to about 50 to 100 nm, for example. Then, the reflective electrode material film is patterned by the photolithography and etching process using the fourth mask to form the upper layer pixel electrode 14A. (FIG. 3 (c), FIG. 4 (c)).

In this embodiment, the lower layer pixel electrode 14B is
Strictly speaking, it does not function as a pixel electrode, but the upper layer pixel electrode 1
Since it functions as a lower layer electrode for 4A, it is referred to as a "lower layer pixel electrode".

Next, a method of driving the above active matrix substrate will be described.

When a positive bias is applied to the scanning wiring 2 by a driving circuit (driver) (not shown), the TFT 10 is turned on (conductive state). Along with this, the signal wiring 5 that contacts the semiconductor layer 6 via the impurity-doped semiconductor layer 7
A current flows between the conductive member 9 and the conductive member 9. As a result, the signal charges are supplied from the signal line 5 to the upper layer pixel electrode 14A through the lower layer pixel electrode 14B.

On the contrary, when a negative bias is applied to the scanning wiring 2, the TFT 10 becomes "OFF state (non-conduction state)". Since no current flows between the signal line 5 and the conductive member 9, the potential of the pixel electrode 14A is held.

In order for the TFT 10 to operate normally, it is necessary that the semiconductor layer 6 is positioned without protruding to the scanning wiring 2 and that the scanning wiring 2 surely intersects the signal wiring 5 and the conductive member 9. There is. Further, since variations in the auxiliary capacitance lead to variations in the pixel potential, the auxiliary capacitance line 20 also needs to reliably cross the lower layer pixel electrode 14B.

In the method disclosed in Japanese Patent Application No. 2001-152779, the semiconductor layer is formed by self-alignment with the lower scanning wiring by backside exposure. For this reason, when the light transmittance of the plastic substrate becomes low, the back surface cannot be exposed and the semiconductor layer cannot be formed in a self-aligned manner. On the other hand, in the present embodiment, the backside exposure is not necessary because the semiconductor layer 6 located below is etched using the scanning wiring 2 located above the semiconductor layer 6 as a mask. Therefore, according to the present embodiment, even on an opaque substrate that does not transmit light used when exposing a resist (photosensitive resin), the semiconductor layer 6 having substantially the same shape as the scanning wiring 2 can be formed without misalignment. Can be formed.

In this embodiment, as is clear from FIG. 1, a part of the signal wiring 5 is bent in a rectangular shape, so that a part of the signal wiring 5 is close to the conductive member 9.
Further, the portion branched from the signal wiring 5 is the conductive member 9
Is bent in the direction parallel to the signal wiring 5 through the vicinity of the end portion of. The portion branched from the signal wiring 5 sandwiches the conductive member 9 from the side surface together with the signal wiring 5. Two portions of the signal wiring 5 sandwiching the conductive member 5 are respectively connected to the source electrode 5A and the source electrode 5B.
Shall be called. The scanning wiring 2 includes a source electrode 5A,
It is patterned so as to intersect the conductive member 5 and the source electrode 5B.

As shown in FIG. 2, since the semiconductor layer 6 remains entirely under the scanning wiring 2, the source electrode 5
A region between A and the conductive member 9 and the source electrode 5B
Both of the regions between and the conductive member 9 function as thin film transistors.

On the other hand, the source electrode 5B and the adjacent signal wiring 5
Since the semiconductor layer also exists between (source electrode 5A), this region can function as a parasitic thin film transistor. However, the signal on the adjacent signal wiring 5 is
Since it is shielded by B, it does not affect the potential of the pixel electrode 14B through the conductive member 9.

In the example shown in FIG. 1, the conductive member 9 and the source electrodes 5A and 8B are orthogonal to the scanning wiring 2, but the angle formed by the conductive member 9 and the source electrodes 5A and 8B and the scanning wiring 2 is equal to that of the scanning wiring 2. , Is not necessarily limited to 90 °.

According to the structure of the present embodiment, the scanning wiring 2 must surely intersect the signal wiring 5 (source electrodes 5A and 5B) and the conductive member 9, while the auxiliary capacitance wiring 20 is provided between the lower layer pixel electrodes 14B. And definitely need to intersect. It is also necessary to form the contact hole 22 on the lower layer pixel electrode 14B so as not to overlap the auxiliary capacitance line 20. In order to reliably achieve such an arrangement, it is necessary to limit the misalignment in the Y-axis direction within a predetermined range. In this embodiment, as is clear from FIG. 1, the misalignment in the Y-axis direction may be suppressed to be equal to or less than the alignment margin Δy represented by the following expression (2).

Δy = (P _pitch −W _g −W _cs −L _jas −3G _sd −2W _s ) / 6 Formula (2)

Here, P _pitch is the pixel _pitch in the Y-axis direction, W _g is the line width of the scanning wiring 2 (size in the Y-axis direction), W _cs
Is the line width (size in the Y-axis direction) of the auxiliary capacitance line 20, L _jas
Is the size of the contact hole in the Y-axis direction, G _sd is the gap between the source electrode and the drain electrode in the Y-axis direction, and W _s is the line width of the signal wiring 5 (the size of the portion extending in the X-axis direction in the Y-axis direction). ). On the other hand, theoretically, the alignment is completely free from misalignment in the X-axis direction.

The contact hole 21 should not overlap with the auxiliary capacitance line 20. Therefore, the length of the conductive member 9 in the Y-axis direction is L1, and the lower layer pixel electrode 14B is
When the size in the Y-axis direction is L2 and the scanning wiring pitch is P _gg , the active matrix substrate of this embodiment needs to satisfy the following expressions (3) and (4).

(L1−W _g ) ≦ (L2−W _cs ) Formula (3)

L1 + L2 ≦ P _gg Expression (4)

By satisfying the above two expressions, the active matrix substrate can be manufactured with high accuracy.

In order to ensure that the scanning wiring 2 intersects the conductive member 9, it is necessary to satisfy 2Δy ≦ (L1−W _g ).

A reflective liquid crystal display device can be manufactured by combining the active matrix substrate of this embodiment with a counter substrate or the like and sealing a liquid crystal layer therebetween. The application of the active matrix substrate of this embodiment is
The present invention is not limited to the reflective liquid crystal display device, and can be used in various electronic devices including other types of display devices.

Example 1 An example of the above active matrix substrate was experimentally manufactured using a 5-inch square opaque plastic substrate. Specifically, a substrate made of polyimide resin was used. The panel size is 3.9 inches diagonal and the resolution is 1/4 VGA. 24 pixel size
7.5 μm × 82.5 μm, and the display area size is 59400 mm in the Y direction and 792000 mm in the X direction.

The width W _g of the scanning wiring 2 is 10 μm, the width W _cs of the auxiliary capacitance wiring is 20 μm, the contact hole length L _jas is 12.5 μm, and the source-drain gap G _sd is 5 μm.
m and the signal wiring width W _s is set to 5 μm, the pixel pitch P _{pitch in} the Y-axis direction is 247.5 μm. The alignment margin (± Δy) in the Y-axis direction (vertical direction) is 30 μm. With an alignment margin of this size, it is possible to accommodate substrate expansion and contraction of ± 1010 ppm. Therefore, even if a plastic substrate having a large dimensional change is used, the active matrix substrate can be manufactured with high yield.

(Second Embodiment) Next, a second embodiment of the active matrix substrate according to the present invention will be described with reference to FIG. FIG. 5 is a plan view showing the layout of the active matrix substrate in this embodiment. The cross-sectional view taken along the line AA 'of FIG. 5 is the same as that of FIG.

In the active matrix substrate of this embodiment, the auxiliary capacitance wiring is not formed.
It has the same configuration as that of the first embodiment.

When a display device such as a liquid crystal display device is constructed using an active matrix substrate, the auxiliary capacitance wiring is not an essential element. The auxiliary capacitance wiring can be omitted by optimizing the physical properties of the liquid crystal material and the value of the gate-drain capacitance C _GD .

The TFT 10 of this embodiment has the same structure as the TFT 10 of the first embodiment. Therefore, detailed description of its structure and operation will be omitted.

In order for the TFT 10 to operate normally, the semiconductor layer 6 must be aligned with the scanning wiring 2 without protruding, and the scanning wiring 2 must cross the signal wiring 5 and the conductive member 9 without fail. There is. Further, the contact hole 21 needs to be surely formed on the lower layer pixel electrode 14B.

In this embodiment, the semiconductor layer 6 is manufactured by the same method as that of the first embodiment, and the semiconductor layer 6 is self-aligned with the scanning wiring 2. Therefore, the semiconductor layer 6 does not protrude from the scanning wiring 2.

According to the structure of this embodiment, since the auxiliary capacitance wiring is not used, the scanning wiring 2 surely intersects the signal wiring 5 (source electrodes 5A and 8B) and the conductive member 9 and the contact hole 21 surely. Lower layer pixel electrode 14B
It may be formed above. Therefore, in this embodiment, as shown in FIG.
As is clearer, the misalignment in the Y-axis direction
It may be suppressed to be equal to or less than the alignment margin Δy represented by the following formula (5).

Δy = (P _pitch −W _g −L _jas −3G _sd −2W _s ) / 4 Formula (5)

Here, P _pitch is the pixel _pitch in the Y-axis direction, W _g is the line width of the scanning wiring 2 (size in the Y-axis direction), L _jas
Is the size of the contact hole in the Y-axis direction, G _sd is the gap between the source electrode and the drain electrode in the Y-axis direction, and W _s is the line width of the signal wiring 5 (the size of the portion extending in the X-axis direction in the Y-axis direction). ). On the other hand, theoretically, the alignment is completely free from misalignment in the X-axis direction.

Example 2 Using a plastic substrate of the same type and size as the plastic substrate used in Example 1,
An example of the active matrix substrate having the configuration shown in FIG. 5 was prototyped. The panel size is 3.9 inches diagonal and the resolution is 1/4 VGA. Pixel size is 247.5 μm x 8
2.5 μm, display area size is 59400 m in Y direction
m, the X direction is 792000 mm.

When the width W _g of the scanning wiring 2 is 10 μm, the contact hole length L _jas is 12.5 μm, the source-drain gap G _sd is 5 μm, and the width W _{s of the} signal wiring is 5 μm, the Y-axis of the pixel is set. Direction pitch P _pitch is 24
Since it is 7.5 μm, from the above formula (2). The alignment margin (± Δy) in the Y-axis direction (vertical direction) is 50 μm. With an alignment margin of this size, ±
It can handle substrate expansion and contraction of 1683 ppm. Since the alignment margin in the present embodiment is larger than the alignment margin in the first embodiment, it is possible to manufacture the active matrix substrate with a high yield even if the substrate material having a larger dimensional change than that of the first embodiment is used. Become.

[0095]

According to the present invention, the conductive member for connecting the pixel electrode to the thin film transistor extends from the lower layer pixel electrode and is arranged so as to surely intersect the scanning wiring. Further, since the semiconductor layer is patterned using the scanning wiring, a thin film transistor self-aligned with the scanning wiring can be formed without using the backside exposure method. For this reason,
An array of thin film transistors can also be integrated on top of an opaque plastic substrate.

When a substrate made of a material mainly composed of an opaque resin is used, the softening point of the substrate can be increased, so that a higher temperature process is possible and the reliability of the thin film transistor can be improved. .

Further, when the auxiliary capacitance wiring is not used, the conductive member extends in the width direction of the scanning wiring, intersects with one corresponding scanning wiring, and the lower layer pixel electrode connected to the conductive member is connected to the scanning wiring. It does not intersect. Therefore, the alignment margin between the scanning wiring and the conductive member becomes sufficiently large, and it becomes possible to use a substrate having a larger expansion / contraction rate.

[Brief description of drawings]

FIG. 1 is a layout diagram of an active matrix substrate according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ of FIG.

3A to 3C are plan views showing main steps in the process of manufacturing the active matrix substrate of FIG.

4A to 4C are cross-sectional views showing main steps in the process of manufacturing the active matrix substrate of FIG.

FIG. 5 is a layout diagram of an active matrix substrate according to a second embodiment of the present invention.

FIG. 6 is a layout diagram of a conventional active matrix substrate.

7 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 8 is a layout diagram of an active matrix substrate disclosed in Japanese Patent Application No. 2001-152779.

9 is a cross-sectional view taken along the line AA ′ of FIG.

[Explanation of symbols]

1 plastic substrate 2 scan wiring 4 Gate insulation film 5 signal wiring 5a source electrode 5b source electrode 6 semiconductor layers 7 Impurity added semiconductor layer 9 Conductive member (drain electrode) 10 TFT (thin film transistor) 14A upper layer pixel electrode 14B lower layer pixel electrode 20 auxiliary capacitance wiring 21 Interlayer insulation film 22 Contact holes 101 glass substrate 102 scan wiring 103 gate electrode 104 insulating film 105 signal wiring 106 intrinsic semiconductor layer 107 impurity-doped semiconductor layer 108 source electrode 109 drain electrode 109 110 thin film transistor 114 pixel electrodes 120 auxiliary capacitance wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) // G02F 1/1368 H01L 29/78 612C F term (reference) 2H090 JB02 JB03 JD01 JD10 LA04 2H092 JA26 JA29 JA38 JA42 JB05 JB13 JB23 JB32.JB38 JB51 JB57 JB63 JB69 GG15 GG24 GG30 GG35 GG44 HK04 HK09 HK16 HK21 HK33 HK35 HL03 HL06 HM04 HM13 NN02 NN44 NN47 NN73 QQ01 5G435 AA12 AA13 AA17 BB05 BB12 CC09 HH14 KK05 LL04 LL06 LL07 LL07 LL05

Claims (15)

[Claims] 1. A substrate, a plurality of signal wirings formed on the substrate, a plurality of scanning wirings and a plurality of auxiliary capacitance wirings intersecting the signal wirings, and the corresponding scannings formed on the substrate. A plurality of thin film transistors that operate in response to a signal applied to the wiring; a plurality of lower layer pixel electrodes that can be electrically connected to the corresponding signal wirings through the thin film transistors; and a lower layer through an interlayer insulating film. An active matrix substrate comprising: an upper layer pixel electrode formed in an upper layer of the pixel electrode and electrically connected to the lower layer pixel electrode through a contact hole formed in the interlayer insulating film; The pixel electrode further includes a conductive member connected to a thin film transistor corresponding to the pixel electrode, the conductive member extending in the direction in which the signal line extends in the lower layer pixel electrode. Luo projects the scanning lines intersect with the conductive member, the active matrix substrate. 2. A plurality of auxiliary capacitance lines intersecting the signal line via the insulating film are provided, and each of the auxiliary capacitance lines intersects a corresponding lower layer pixel electrode. The active matrix substrate according to. 3. The active matrix substrate according to claim 2, wherein both the scanning wiring and the auxiliary capacitance wiring are formed by patterning the same conductive film. 4. A direction in which the scanning wiring extends is an X axis, a direction in which the signal wiring extends is a Y axis, a length of the conductive member in the Y axis direction is L1, a length of the lower layer pixel electrode in the Y axis direction is L2, and When the line width of the scan line is W _g , the line width of the auxiliary capacitance line is W _cs , and the scan line pitch is P _gg , the relationship of (L1−W _g ) ≦ (L2−W _cs ) L1 + L2 ≦ P _gg is _satisfied . The active matrix substrate according to claim 3, which satisfies: 5. The active matrix substrate according to claim 1, wherein the signal line, the lower layer pixel electrode, and the conductive member are all formed by patterning the same conductive film. 6. The active matrix substrate according to claim 1, wherein the substrate is made of a material that is opaque to the light used for exposing the photosensitive resin. 7. The active matrix substrate according to claim 6, wherein the material is mainly an opaque resin. 8. A source electrode branching from the signal line and intersecting the scanning line, wherein an intersection of the conductive member and the scanning line is an intersection of the signal line and the scanning line and the source. The active matrix substrate according to claim 1, wherein the active matrix substrate is sandwiched between intersections of electrodes and the scanning wiring. 9. The active matrix substrate according to claim 8, wherein a distance between the signal line and the conductive member is substantially equal to a distance between the conductive member and the source electrode. 10. The active matrix substrate according to claim 1, wherein a channel portion of the thin film transistor is located substantially at the center of adjacent signal wirings. 11. The channel portion of the thin film transistor is covered by the upper layer pixel electrode.
0. The active matrix substrate according to any one of 0. 12. The semiconductor layer of each thin film transistor is self-aligned with the scanning wiring located in an upper layer, and the semiconductor layer intersects with the signal wiring and the conductive member. The active matrix substrate according to any one. 13. An electronic device comprising the active matrix substrate according to claim 1. Description: 14. A step of forming a plurality of signal lines, a lower layer pixel electrode, and a conductive member protruding from the lower layer pixel electrode on a substrate, and covering the signal line, the lower layer pixel electrode, and the lower layer pixel electrode. A step of forming a semiconductor thin film on the conductive thin film, a step of forming a gate insulating film on the semiconductor thin film, a step of depositing a conductive film on the gate insulating film, and a resist mask defining the scanning wiring on the conductive film. And removing the portions of the conductive film, the gate insulating film, and the semiconductor thin film that are not covered by the resist mask, thereby forming the scanning wiring intersecting the conductive member with the conductive film. And then forming a semiconductor layer that is self-aligned with the scanning wiring from the semiconductor thin film, and interlayer insulation so as to cover the scanning wiring. An active matrix including a step of forming a film, and a step of forming an upper layer pixel electrode electrically connected to the lower layer pixel electrode through a contact hole formed in the interlayer insulating film on the interlayer insulating film. Substrate manufacturing method. 15. The resist mask has a pattern that defines an auxiliary capacitance line in addition to the scan line, and when the scan line is formed, the trap line is formed so as to intersect with the lower layer pixel electrode. The method for manufacturing an active matrix substrate according to claim 14, wherein the active matrix substrate is formed.