JP2003318109A - Method for manufacturing silicon epitaxial wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon epitaxial wafer, which further improves the crystalline property of an epitaxial layer. <P>SOLUTION: The silicon epitaxial layer 1 is grown on a silicon monocrystalline substrate W by chemical vapor deposition using a monosilane (SiH<SB>4</SB>) gas as a material at a growth temperature, for instance, of 700°C and in a reduced pressure atmosphere (hydrogen gas atmosphere). Thus formed silicon epitaxial wafer EPW is then subjected to thermal treatment without being taken out from a reactor where chemical vapor deposition has been performed. In this way, polycrystalline silicon 2 which is partially contained in the silicon epitaxial layer 1 is turned to monocrystal. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for manufacturing a silicon epitaxial wafer.

[0002]

2. Description of the Related Art A silicon epitaxial layer (hereinafter also simply referred to as an epitaxial layer) is formed on a silicon single crystal substrate.
In the silicon epitaxial wafer formed with, the crystallinity of the epitaxial layer is required to be improved because the performance of the semiconductor device manufactured thereby may be greatly affected.

When the epitaxial layer is formed by vapor phase growth, the crystallinity of the epitaxial layer is easily improved by increasing the growth temperature. However, silicon epitaxial wafers having various characteristics are manufactured depending on the type of semiconductor device to be manufactured, and some of them are intentionally manufactured at a low growth temperature. For example, when a buried layer is formed on the surface of a silicon single crystal substrate and then an epitaxial layer is formed on the silicon single crystal substrate, or when manufacturing a silicon epitaxial wafer for MOSFET, a silicon single crystal substrate or a silicon epitaxial wafer is used. When a trench is formed on the surface of the wafer and a silicon epitaxial layer is formed in the trench of the wafer in which the trench is formed, vapor phase growth at a relatively low growth temperature (eg, less than 1000 ° C.) Done. However, there is a dilemma that the crystallinity of the epitaxial layer is lowered during the vapor phase growth at such a low temperature.

[0004]

For example, a silicon epitaxial layer is formed on a main surface (plane orientation (100)) of a silicon single crystal substrate from a monosilane (SiH ₄ ) gas at a growth temperature of about 700 ° C. Then, when the surface is selectively etched, many pits as shown in FIG. 7 are observed. For example, if such a pit exists on the surface of a silicon epitaxial wafer, the film thickness distribution becomes nonuniform when an insulating film is formed on the surface,
This may cause poor performance in the semiconductor device.

Therefore, conventionally, the supply amount of the source gas (for example, monosilane gas) during vapor phase growth is reduced, or the temperature of vapor phase growth is controlled to be as constant as possible. However, even if such measures are taken, for example, the pits exposed on the surface of the epitaxial layer by selective etching are not completely eliminated.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method for manufacturing a silicon epitaxial wafer capable of forming a silicon epitaxial layer having good crystallinity.

[0007]

In order to solve the above problems, a method for manufacturing a silicon epitaxial wafer according to the present invention is a silicon epitaxial layer in which polycrystalline silicon is partially formed in a reaction container. Is subjected to a vapor phase growth step of performing vapor phase growth on a silicon single crystal substrate, and a single crystallization step of heat-treating the silicon epitaxial wafer after the formation of the silicon epitaxial layer to single crystallize polycrystalline silicon is performed. And

The inventors of the present invention have shown in FIG. 7 before performing selective etching on an epitaxial layer obtained by vapor phase growth using a monosilane gas as a raw material at a growth temperature of about 700 ° C.
The cross section of the silicon epitaxial wafer was observed by a transmission electron microscope (TEM) in a portion where a pit like this is expected to be formed (for example, a portion whose color is different from other areas). FIG. 5 shows the observation result. In FIG.
The portion that is observed in a dark shape in the shape of an inverted triangle is etched by selective etching, and becomes a pit as shown in FIG. Furthermore, near the deepest part of the densely observed part, energy dispersive X-ray spectroscopy (EDX: En
The composition was analyzed by energy dispersive X-ray spectroscopy. FIG. 6 is the obtained EDX profile. The profile in which Matorix is described is an EDX profile obtained as a result of composition analysis of a portion having the same depth in a region where the epitaxial layer is normally formed. In the darkly observed portion in the inverted triangular shape in FIG. 5, only Si is detected as in Matorix. From this, the inventors of the present invention have found that the portion of FIG. 5 that is darkly observed in the shape of an inverted triangle is made of polycrystalline silicon, and this polycrystalline silicon is etched by selective etching, as shown in FIG. It was found that various pits become apparent on the surface of the epitaxial layer.

Therefore, the inventors of the present invention can form a more homogeneous epitaxial layer by single-crystallizing the polycrystalline silicon in the silicon epitaxial layer obtained by vapor phase growth as described above. The inventors have found that it is possible to significantly reduce the pits that are exposed on the surface of the silicon epitaxial layer and to form an epitaxial layer having good crystallinity inside the trench, thus completing the present invention.

Further, when the polycrystalline silicon partially formed in the epitaxial layer is single-crystallized, the single-crystallizing step is performed after the vapor phase growth step without taking out the silicon epitaxial wafer from the reaction container. Is good. After the vapor phase growth process is completed, without taking out the silicon epitaxial wafer from the reaction container in which the vapor phase growth was performed once, if heat treatment is performed in the same reaction container and a single crystallization process is performed, outside air in which particles float Since the chance of being exposed to the atmosphere is reduced accordingly, the crystallinity of the silicon epitaxial layer can be further improved. Further, according to this method, since the single crystallization step is performed subsequent to the vapor phase growth step in the same reaction container, it is possible to reduce the manufacturing time.

The single crystallization process is preferably performed at a temperature higher than the growth temperature in the vapor phase growth process. Furthermore, in the same reaction vessel, the temperature in the reaction vessel can be adjusted only when the single crystallization step is performed following the vapor phase growth step.
After the vapor phase growth process, increase without decreasing,
It is preferable to set the temperature at which the single crystallization process is performed. As a result, the single crystallization step can be performed while the epitaxial layer remains active, and the polycrystalline silicon is likely to be single crystallized.

More specifically, a trench is formed in the silicon single crystal substrate in the thickness direction from the main surface of the silicon single crystal substrate, and a silicon epitaxial layer in which polycrystalline silicon is partially formed is formed inside the trench. It is preferable to apply it when vapor phase growth is performed. In such a case, the epitaxial growth at a relatively low temperature as described above is performed because, when the growth temperature is relatively high, the growth rate is increased near the opening of the trench and the epitaxial layer is formed inside the trench. This is because the opening will be blocked before the opening. If the opening of the trench is closed during vapor phase growth, a cavity is created inside the trench, which leads to deterioration of the performance of a semiconductor device such as MOSFET. However, in order to solve such a problem, if the growth temperature is relatively low (for example, below 1000 ° C.),
Polycrystalline silicon is more likely to be formed in the silicon epitaxial layer. Therefore, by adopting the method of the present invention to single crystallize the polycrystalline silicon partially formed in the epitaxial layer,
A silicon epitaxial layer having good crystallinity can be formed without blocking the opening of the trench. Then, a silicon epitaxial wafer having good crystallinity can be obtained for a semiconductor device, particularly for MOSFET.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The method of manufacturing a silicon epitaxial wafer of the present invention is preferably carried out as follows. That is, a silicon single crystal substrate is placed in a reaction container of a vapor phase growth apparatus, and while reducing the pressure in the reaction container, a silicon epitaxial layer on which polycrystalline silicon is partially formed is vapor-deposited on the silicon single crystal substrate. A vapor phase growth process for growing is performed. Then, the silicon epitaxial wafer on which the silicon epitaxial layer has been formed is heat-treated in a hydrogen gas atmosphere at a temperature higher than the vapor phase growth temperature to thereby single-crystallize the polycrystalline silicon in the silicon epitaxial layer. The conversion process is performed.

FIG. 1 is a schematic view for explaining the method for manufacturing a silicon epitaxial wafer according to the present invention. First, the silicon single crystal substrate W is placed in the reaction container. And
As shown in FIG. 1A, the silicon single crystal substrate W is heated to a baking temperature while hydrogen (H ₂ ) gas is introduced into the reaction container, and a baking process is performed. As a result,
As shown in (b), the natural oxide film 3 on the silicon single crystal substrate W is removed. The baking temperature is, for example, 950.
It can be up to 1000 ° C. The baking time at that time is about 0.1 to 1 hour.

Next, as shown in FIG. 1C, the silicon epitaxial layer 1 is vapor-phase grown on the silicon single crystal substrate W (vapor-phase growth step). The vapor phase growth step is performed by reducing the pressure inside the reaction vessel. In the present embodiment, the silicon epitaxial layer is formed at a relatively low temperature. As described above, in the case of epitaxial growth at a relatively low temperature, the crystallinity of the formed epitaxial layer tends to deteriorate. This is because it is difficult for silicon to diffuse on the silicon single crystal substrate W, and it is difficult to form an epitaxial layer having good crystallinity. At this time, if the vapor phase growth step is performed in a reduced pressure atmosphere lower than atmospheric pressure, an epitaxial layer having relatively good crystallinity can be formed even if the growth temperature is relatively low.

The pressure in the reaction vessel is reduced as described above, and the temperature in the reaction vessel is set to the vapor phase growth temperature as shown in FIG. In the present invention, the vapor phase growth step may be performed at a temperature lower than 1000 ° C. In the case of such epitaxial growth at a relatively low temperature, polycrystalline silicon is likely to be partially formed in the silicon epitaxial layer. Therefore, it becomes an effective application range of the method for manufacturing a silicon epitaxial wafer of the present invention. The vapor growth temperature in the vapor growth step is, specifically, 550 to 95.
It can be 0 ° C.

When the vapor phase growth step is performed at the growth temperature as described above, the vapor phase growth step can be performed by bringing monosilane (SiH ₄ ) gas into contact with the silicon single crystal substrate W. When vapor phase growth is performed at a relatively low temperature as in the present embodiment, it is preferable to use a monosilane gas that causes vapor phase growth at about 550 to 750 ° C. Also,
A dichlorosilane (SiH ₂ Cl ₂ ) gas, which allows vapor phase growth at a growth temperature of about 850 ° C. to 950 ° C., may be used, but monosilane gas is preferably used from the viewpoint of the growth rate. However, monosilane gas is epitaxially grown at a considerably lower temperature than dichlorosilane gas, and it is particularly difficult to obtain a silicon epitaxial layer having good crystallinity. Further, vapor phase growth using monosilane gas is basically due to thermal decomposition, and if the vapor phase growth temperature is high, silicon is precipitated in the vapor phase, resulting in the formation of polycrystalline silicon in the epitaxial layer. It is easy to be done. Therefore, when vapor phase growth is performed using monosilane gas, the method for producing a silicon epitaxial wafer of the present invention is preferably adopted.

As shown in FIG. 1C, the silicon epitaxial layer 1 is formed on the silicon single crystal substrate W by the low temperature vapor phase growth process using the monosilane gas as described above, and the silicon epitaxial wafer EPW is obtained.
Polycrystalline silicon 2 is likely to precipitate in the silicon epitaxial layer 1 due to the above-described vapor phase growth at a relatively low temperature.

When the vapor phase growth process is completed, the flow of the raw material gas (monosilane gas) is stopped, and then the inside of the reaction vessel is purged with hydrogen gas. Then, as shown in FIG. 2, the temperature in the reaction vessel is increased while inflowing hydrogen gas to set the temperature higher than the vapor phase growth temperature. And
The silicon epitaxial wafer EPW is heat-treated in a hydrogen gas atmosphere to perform a single crystallization process (see FIG. 1).
(D)). The temperature for performing the single crystallization step is, for example, 9
Set to 50 ° C. Further, the single crystallization step is preferably performed for 1 hour or more. Thereby, the polycrystalline silicon 2 formed in the silicon epitaxial layer 1 becomes a silicon single crystal 2 ', and as a result, the crystallinity of the silicon epitaxial layer 1 is improved.

After the completion of the single crystallization step, as shown in FIG. 2, the temperature in the reaction vessel is lowered and the silicon is taken out from the reaction vessel. The silicon epitaxial layer 1'having good crystallinity is formed on the silicon. Epitaxial wafer EP
W can be obtained (FIG. 1 (e)).

In the above embodiment, the case of performing the single crystallization step in a hydrogen gas atmosphere has been described, but the present invention is not limited to this. For example, the same effect can be achieved by performing the single crystallization process in an inert gas atmosphere, particularly in an argon (Ar) gas atmosphere.

Further, the above-described method for manufacturing a silicon epitaxial wafer can be used in manufacturing a silicon epitaxial wafer for MOSFET as follows. FIG. 3 illustrates an outline of a vertical power MOSFET. The power MOSFET 100 is
A gate G, a columnar n-type region 20a formed below the gate G, a source S, and n below the source S.
A columnar p-type region 20b formed between the mold regions 20a
And a drain region 20c that is locked at a position separated from the gate G and the source S and is connected to the drift region 20 formed of the columnar region. The n-type silicon single crystal substrate serves as the drain region 20c, and the epitaxial layer formed on the silicon single crystal substrate is the drift region 2
It is set to 0. Then, on the surface of the epitaxial layer,
Further, a silicon single crystal thin film 5 is formed, and a buried layer 30 is formed on this thin film 5.

In the power MOSFET 100 as described above, in order to form a mode in which the columnar n-type regions 20a and the p-type regions 20b are alternately arranged, for example, a trench is formed in an n-type silicon single crystal wafer and the trench is formed. It can be obtained by forming the p-type region 20b inside the trench. Hereinafter, a specific method for manufacturing such a silicon epitaxial wafer for the power MOSFET 100 will be described. FIG. 4 illustrates the outline of the manufacturing method. First, the n-type silicon epitaxial layer 10 is formed on the n-type silicon single crystal substrate W ′ by a conventionally known manufacturing method. Then, on the formed silicon epitaxial layer 10, as shown in FIG.
The trench T is formed. Trench T is formed such that its bottom reaches the main surface of silicon single crystal substrate W ′. The trench T can be formed by, for example, photolithography and etching. The width of the trench T and the like are appropriately set according to the desired structure of the power MOSFET 100.

Next, as shown in FIG. 4B, a p-type silicon epitaxial layer 4 is grown inside the trench T of the wafer in which the trench T is formed. At this time, the silicon epitaxial layer 4 is formed inside the trench T.
A relatively low growth temperature is employed to prevent the opening of the trench T from being blocked before the formation of. Specifically, it can be performed at a vapor growth temperature in the range of 550 to 950 ° C. Also, as the source gas, one corresponding to the growth temperature is used. For example, 85
In the case of vapor phase growth in the temperature range of 0 to 950 ° C, dichlorosilane gas can be used, and 550 to 75
When vapor phase growth is performed at 0 ° C., it is preferable to use monosilane gas. However, for the purpose of not blocking the opening of the trench T, it is preferable to carry out vapor phase growth at a temperature as low as possible, and it is more preferable to use monosilane gas as a source gas. Furthermore, this vapor phase growth step is preferably performed in a reduced pressure atmosphere. By performing vapor phase growth under a reduced pressure atmosphere, the growth temperature can be set low and the plane orientation dependency is reduced, so that the opening of the trench T is less likely to be blocked.

Such a vapor phase growth process can be carried out, for example, by a single-wafer type vapor phase growth apparatus, but may be carried out by using another apparatus. For example, batch type hot wall LPCVD (Low Pressure Chemical Vapor Deposi)
device).

In vapor phase growth at a relatively low temperature as described above, since polycrystalline silicon is likely to be partially formed in the silicon epitaxial layer 4 to be formed, the single crystallization step according to the present invention is performed. Thereby, the polycrystalline silicon partially formed in the silicon epitaxial layer 4 becomes a single crystal, and the crystallinity of the silicon epitaxial layer 4 is improved. Regarding the conditions of the single crystallization process, the same conditions as those described above are adopted.

Further, when the silicon epitaxial layer 4 is vapor-deposited inside the trench T, the vapor-phase growth step and the single crystallization step are alternately repeated a plurality of times to fill the inside of the trench T with the silicon epitaxial layer. Is good.
Specifically, as shown in FIG. 4B, after the silicon epitaxial layer 4 is formed and the single crystallization process is performed, the vapor phase growth process is further performed under the same conditions as shown in FIG. As described above, the silicon epitaxial layer 4 ′ is formed. A single crystallization process is performed on the formed silicon epitaxial layer 4 ′ to partially crystallize the polycrystalline silicon that is partially formed. Further, a silicon epitaxial layer 4 ″ is formed, and a single crystallization process is also performed on the silicon epitaxial layer 4 ″. In this way, the inside of the trench T is filled with the silicon epitaxial layer. Then, the inside of the trench T can be filled with the silicon epitaxial layer having good crystallinity. Furthermore, by performing the single crystallization process in multiple steps, it becomes easier to promote single crystallization of polycrystalline silicon in each silicon epitaxial layer, and the inside of the trench T is formed in the silicon epitaxial layer having higher crystallinity. Can be filled. Note that the vapor phase growth step and the single crystallization step may be repeated any number of times as long as they are a plurality of times.

In this way, when the inside of the trench T is filled with the silicon epitaxial layers 4, 4 ', 4'',
The p-type silicon epitaxial layers 4, 4 ′, 4 ″ are formed not only inside the trench T but also on the main surface of the n-type silicon epitaxial layer 10. Therefore, the main surface of the wafer is, for example, CMP (Chemical Mechanical).
By polishing with a cal polishing method, excess p-type silicon epitaxial layers 4, 4 ′, 4 ″ on the main surface of the n-type epitaxial layer are removed and the surface of the n-type silicon epitaxial layer 10 is made flat. To do.

A thin film 5 of a silicon single crystal substrate is formed on the main surface of the thus-planarized n-type silicon epitaxial layer 10 as shown in FIG. 4 (d). As shown in FIG. 3, this thin film 5 has a desired power MOSFET 10
Depending on the structure of 0, a p-type region or an n-type region, an insulating film and the like are appropriately formed to provide a source S and a gate G, and a drain D on the back surface side of the wafer. Used as a silicon epitaxial wafer.

By the method for manufacturing a silicon epitaxial layer according to the present invention as described above, the MOSFET 100 in which the inside of the trench T is filled with the p-type silicon epitaxial layers 4, 4 ', 4''having good crystallinity is formed. can do.

[0031]

EXAMPLES The following experiments were conducted to investigate the effects of the present invention. (Comparative Example) First, after a baking step using a vapor phase growth apparatus, monosilane (SiH ₄ ) gas was brought into contact with a silicon single crystal substrate having a plane orientation (100) of a main surface and a thickness of 750 μm so that polycrystalline silicon was formed. The partially formed silicon epitaxial layer is vapor-deposited by 2-3 μm to obtain a silicon epitaxial wafer. The pressure in the vapor phase growth apparatus is about 40 Pa (0.3 torr), and the vapor phase growth temperature is 7
Set to 00 ° C. The flow rate of monosilane gas is 1.0 liter / min.

Selective etching was performed on the main surface of the obtained silicon epitaxial wafer, and the surface was observed by an optical microscope. The observed image is shown in FIG.
The selective etching was performed using an etching solution containing hydrofluoric acid, nitric acid and acetic acid. By selective etching, as shown in FIG. 7, the surface density of the epitaxial layer was 1.48 × 10.
⁵ pits / cm ² were observed. Also, the diameter is approximately 2μ
As a result of measuring the pit depth and the like using a stylus of m, the diameter of the pit was about 5 μm and the depth was about 250 nm, as shown in FIG.

Further, the flatness of the surface of the silicon epitaxial wafer was examined by AFM. The surface roughness of the surface of the silicon epitaxial wafer is the maximum roughness (R
max) is 1.536 nm, root mean square roughness (Rq)
Is 0.142 nm and the arithmetic mean roughness (Ra) is 0.111
nm, and it was confirmed that unevenness was formed on the surface to some extent.

(Example) Next, using the same vapor phase growth apparatus as in the comparative example, after the baking step, the plane orientation of the main surface (10
0), a silicon epitaxial layer in which polycrystalline silicon is partially formed is vapor-deposited on a silicon single crystal substrate having a thickness of 750 μm by 2 to 3 μm, and then a single crystallization step is performed by the method according to the present invention. It was Specifically, after the same vapor phase growth step as in the comparative example, the silicon epitaxial wafer was not taken out in the same reaction container, the pressure inside the reaction container was reduced to about 267 Pa (2 torr), and in a hydrogen gas atmosphere, The temperature in the reaction vessel was raised to 950 ° C., and heat treatment was performed for about 1 hour to perform a single crystallization process. During the single crystallization process, hydrogen gas in the reaction vessel is 20 liters /
The flow was made to flow at a flow rate of min.

When the obtained silicon epitaxial wafer was subjected to the above selective etching and the main surface thereof was observed with an optical microscope, almost no pits were seen as shown in FIG. The surface density of the pits is such that the surface of the silicon epitaxial layer is scanned and the pits shown in the enlarged view are somehow observed. In other words, the single crystallization step single-crystallizes the polycrystalline silicon in the epitaxial layer formed by the vapor phase growth step, and as a result, the pits exposed on the surface of the epitaxial layer are reduced.
The number of pits that appeared on the surface of the silicon epitaxial wafer was 20 / cm ² or less, and the crystallinity of the epitaxial layer was significantly improved as compared with the comparative example.

Further, the flatness of the surface of the silicon epitaxial wafer was investigated by AFM. The maximum roughness (Rmax) of the silicon epitaxial wafer is 0.
984 nm, and the root mean square roughness (Rq) is 0.
100 nm, arithmetic mean roughness (Ra) is 0.079
nm, and the flatness of the surface is significantly improved as compared with the comparative example.

Next, after performing the same vapor phase growth process as in the above experiment, the heat treatment time is variously changed to perform the single crystallization process, and the heat treatment time and the silicon epitaxial layer after the single crystallization process are changed. The relationship with the density of pits revealed by selective etching on the surface was investigated. The result is shown in FIG. From FIG. 10, it was found that by setting the heat treatment time in the single crystallization step to 1 hour or more, the areal density of pits exposed on the surface of the silicon epitaxial layer after the single crystallization step was significantly reduced. That is, in the single crystallization step, by setting the heat treatment time to 1 hour or more, the single crystallization of the polycrystalline silicon is favorably performed, and the epitaxial layer having better crystallinity can be formed.

As described above, according to the method of manufacturing a silicon epitaxial wafer of the present invention, it is difficult to suppress the formation of polycrystalline silicon in epitaxial growth at a relatively low temperature (for example, 1000 ° C. or less). Since it can be crystallized, the crystallinity of the epitaxial layer can be improved. Thus, by adopting the method of the present invention, even when a silicon epitaxial layer is vapor-deposited on a silicon wafer having a trench formed on the main surface, the epitaxial layer having good crystallinity allows the epitaxial layer to be formed inside the trench. Can be filled with. Further, in the single crystallization step, the crystallinity of the epitaxial layer can be further improved by setting the heat treatment time to 1 hour or more. Furthermore, according to the present invention, the surface of the epitaxial layer can be made even flatter.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an outline of a method for manufacturing a silicon epitaxial wafer according to the present invention.

FIG. 2 is a diagram showing a temperature sequence in the method for manufacturing a silicon epitaxial wafer of the present invention.

FIG. 3 is a sectional view showing an example of the structure of a power MOSFET.

FIG. 4 is a diagram for explaining an outline of a method for manufacturing a silicon epitaxial wafer for power MOSFET according to the present invention.

FIG. 5 is a TEM observation image of a cross section of a silicon epitaxial layer before selective etching.

FIG. 6 is an EDX analysis result near the deepest part of the pit.

FIG. 7 is an enlarged observation result of an epitaxial layer surface in a comparative example.

FIG. 8 is a diagram showing a measurement result of pit depth.

FIG. 9 is an enlarged observation result of the surface of the epitaxial layer in the example.

FIG. 10 is a diagram showing the relationship between the heat treatment time in the single crystallization process and the density of pits that are exposed on the surface of the epitaxial layer.

[Explanation of symbols]

1, 4, 4 ', 4 "silicon epitaxial layer 2 Polycrystalline silicon 2'silicon single crystal W, W'silicon single crystal substrate T trench EPW Silicon epitaxial wafer

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Claims (11)

[Claims] 1. A vapor phase epitaxy step of vapor-depositing a silicon epitaxial layer, in which polycrystalline silicon is partially formed, on a silicon single crystal substrate in a reaction vessel, the silicon after the silicon epitaxial layer is formed. A method for manufacturing a silicon epitaxial wafer, which comprises performing a single crystallization step of heat-treating an epitaxial wafer to single crystallize the polycrystalline silicon. 2. The method for producing a silicon epitaxial wafer according to claim 1, wherein after the vapor phase growth step, the single crystallization step is performed without taking out the silicon epitaxial wafer from the reaction container. . 3. The method for producing a silicon epitaxial wafer according to claim 1, wherein the single crystallization step is performed in a hydrogen gas atmosphere. 4. The method for producing a silicon epitaxial wafer according to claim 1, wherein the single crystallization step is performed in an inert gas atmosphere. 5. The method for producing a silicon epitaxial wafer according to claim 1, wherein the single crystallization step is performed at a temperature higher than a growth temperature in the vapor phase growth step. 6. The method for producing a silicon epitaxial wafer according to claim 1, wherein the single crystallization step is performed by reducing the pressure inside the reaction vessel. 7. The method for producing a silicon epitaxial wafer according to claim 1, wherein the vapor phase growth step is performed while reducing the pressure inside the reaction vessel. 8. The method for producing a silicon epitaxial wafer according to claim 1, wherein the vapor phase growth step is performed by bringing monosilane gas into contact with the silicon single crystal substrate. 9. A silicon single crystal substrate is placed in a reaction vessel, and while reducing the pressure in the reaction vessel, a silicon epitaxial layer in which polycrystalline silicon is partially formed is vapor-phased on the silicon single crystal substrate. After performing the vapor phase growth step of growing, a single crystallization step of single crystallizing the polycrystalline silicon in the silicon epitaxial layer is performed by heat treatment in a hydrogen gas atmosphere at a temperature higher than the vapor phase growth temperature. A method for manufacturing a silicon epitaxial wafer, comprising: 10. A trench is formed in the silicon single crystal substrate in a thickness direction from a main surface of the silicon single crystal substrate, and a silicon epitaxial layer in which the polycrystalline silicon is partially formed is provided inside the trench. The method for producing a silicon epitaxial wafer according to claim 9, wherein vapor phase growth is performed. 11. The silicon epitaxial wafer according to claim 10, wherein the vapor phase growth step and the single crystallization step are alternately repeated a plurality of times to fill the inside of the trench with a silicon epitaxial layer. Production method.