JP2003298414A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which supplies an oscillation signal of a stable frequency. <P>SOLUTION: The semiconductor integrated circuit is provided with a voltage controlled oscillator 50 for outputting an oscillation signal Fout of a frequency corresponding to a control signal VCOin, a frequency divider 60 for outputting a comparison signal Fosc, a phase comparator 20 for outputting first and second phase difference signals UP and DN corresponding to the phase difference of signals Fref and Fosc, a charge pump circuit 30 for outputting the signal VCOin based on currents to be supplied by first and second current sources 31 and 34 in accordance with the signals UP and DN from a control signal node N1, a filter circuit 40 for smoothing the signal VCOin, and a voltage compensation circuit for validating a current path reaching a filter circuit 40 from the first and second current sources 31 and 34 when any one of the signals UP and DN is asserted or for invalidating the current path by opening a portion between the first and second current sources 31 and 34 and the control signal node N2 when both the signals UP and DN are negated. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit. In particular, the present invention relates to a technique for providing a stable oscillation signal in a PLL (Phase Locked Loop) circuit.

[0002]

2. Description of the Related Art Conventionally, PLL circuits have been used in various applications such as a recording medium reading device. In recent years, further performance improvement has been demanded, such as shortening the lock time to the desired frequency and stabilizing the frequency after locking.

A conventional PLL circuit will be described with reference to FIG. FIG. 11 is a circuit block diagram showing a configuration example of the PLL circuit. As shown in the figure, the PLL circuit 100 includes a phase comparator 200, a charge pump circuit 300, a low-pass filter (LP
An F) 400, a voltage controlled oscillator (VCO) 500, and a frequency divider 600 are provided.

A reference signal Fref having a predetermined frequency is input to the phase comparator 200 from the outside, and a frequency-divided signal Fosc is applied to the frequency divider.
Input from 600. Then, the phase comparator 200 outputs the reference signal Fr
The phase difference between ef and the frequency-divided signal Fosc is detected, and phase difference signals UP and DN having pulse widths corresponding to the phase difference are output. The charge pump circuit 300 outputs the control voltage signal VCOin based on the phase difference signals UP and DN. The control voltage signal VCOin is smoothed by the filter circuit 400 and supplied to the voltage controlled oscillator circuit 500. The voltage controlled oscillator circuit 500 has a control voltage signal VCO
An oscillation signal Fout having a frequency based on in is generated. This oscillation signal Fout is also sent to the frequency divider 600, and the frequency divider 600 outputs the oscillation signal.
The frequency of Fout is divided into 1 / N and the divided signal Fosc is output.

FIG. 12 is a circuit diagram of a portion of the charge pump circuit 300 and the low pass filter 400. As shown in the figure, the charge pump circuit 300 has a CMOS buffer in the output stage. The CMOS buffer includes a pMOS transistor 310 having a gate to which the phase difference signal UP is input, a source connected to the power supply potential VDD, and a drain, a gate to which the phase difference signal DN is input, a source connected to the ground potential, And an nMOS transistor 320 having a drain connected to the drain of the pMOS transistor 310.
The connection node between the drain of the pMOS transistor 310 and the drain of the nMOS transistor 320 becomes the output node N10 of the charge pump circuit 300, and the potential of the output node N10 becomes the control voltage signal VCOin. Also low-pass filter 4
00 is configured by connecting a capacitor 410 and a resistance element 420 in series.

Next, the operation of the PLL circuit having the above configuration will be described. The phase comparator 200 has a reference signal Fref and a divided signal F.
It monitors the phase difference at the rising edge of osc. Then, when the phase of the divided signal Fosc is behind the phase of the reference signal Fref, the phase difference signal UP is asserted for the time width corresponding to the phase difference. Conversely, the divided signal Fosc
When the phase of is ahead of the phase of the reference signal Fref, the phase difference signal DN is asserted.

The charge pump circuit 300 includes a phase difference signal U
Charges and discharges current according to P and DN. That is, when the phase difference signal UP is asserted (“L” level), the pMOS transistor 310 is turned on, so that a current flows from the charge pump circuit 300 to the low-pass filter 400. This causes charges to flow into the capacitor 410 of the low-pass filter 400. As a result, the potential of the control voltage signal VCOin rises and the frequency of the oscillation signal Fout rises. Conversely, when the phase difference signal DN is asserted (“H” level), the nMOS transistor 320 is turned on.
A current starts to flow from the charge pump circuit 300 to the charge pump circuit 300. As a result, the charge of the capacitor 410 is discharged. as a result,
The potential of the control voltage signal VCOin drops and the frequency of the oscillation signal Fout drops.

By the above operation, the reference signal Fref and the divided signal
The voltage controlled oscillator circuit 500 is controlled so that the phases of Foscs match. As a result, the frequency of the divided signal is
It is possible to obtain the oscillation signal Fout that is N times the

[0009]

However, the conventional PLL circuit described above has a problem that the control voltage signal VCOin is not fixed to a constant value and the frequency of the oscillation signal Fout varies. This point will be described with reference to FIG. FIG. 13 is a time chart of the reference signal Fref, the frequency division signal Fosc, the phase difference signals UP and DN, and the control voltage signal VCOin.

As shown in the figure, it is assumed that the phase of the divided signal Fosc is behind the phase of the reference signal Fref. Then, the phase comparator 200 displays the time width Δt corresponding to the phase difference.
Assert the phase difference signal UP by 1. As a result, the charge pump circuit 300 raises the potential of the control voltage signal VCOin in order to raise the frequency of the oscillation signal Fout (time t1.
~ T2). However, when a leak current occurs in the MOS transistors 310 and 320 in the charge pump circuit 300, the charge amount of the capacitor 410 in the low pass filter 400 changes, and the potential of the control voltage signal VCOin changes accordingly. Figure 11
In the above example, the case where a leak current occurs in the nMOS transistor 320 is shown. When a leak current flows through the nMOS transistor 320, the electric charge of the capacitor 410 in the low-pass filter 400 is released, so that the potential of the control voltage signal VCOin at time t3 drops by ΔV1 from the initial (time t2) set value. (Time t2 to t3). Therefore, the oscillation signal
The frequency of Fout is also lowered by the amount corresponding to this ΔV1.
As a result, even at time t3, the reference signal Fref and the divided signal
Fosc phases will not match.

In FIG. 14, the phase of the divided signal Fosc is the reference signal.
6 is a time chart of various signals in the case where the phase is advanced from the phase of Fref. Since the reference signal Fref has a delayed phase, the phase difference signal DN is asserted. This lowers the potential of the control voltage signal VCOin and lowers the frequency of the oscillation signal Fout. However, when a leak current occurs in the nMOS transistor 320, the control voltage signal VCOin is initially set (at time t
It will be lower than the set value of 2) by ΔV2. as a result,
The frequency of the oscillation signal Fout will drop more than necessary.

A similar problem occurs even when a leak current occurs in the pMOS transistor 310, and in that case, the frequency of the oscillation signal Fout becomes too high.

As described above, in the conventional PLL circuit,
Configure CMOS buffer in charge pump circuit
Leakage current may flow through the MOS transistor. Then, the charge amount of the capacitor in the low pass filter fluctuates, resulting in an error in the frequency of the oscillation signal.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor integrated circuit capable of supplying an oscillation signal having a stable frequency.

[0015]

A semiconductor integrated circuit according to the present invention includes a voltage-controlled oscillator that outputs an oscillation signal having a frequency corresponding to a control signal, and a frequency divider that outputs a comparison signal obtained by dividing the oscillation signal. A phase comparator that compares the phases of a reference signal and the comparison signal, and outputs first and second phase difference signals according to the phase difference obtained as a result of the comparison;
A first current source that supplies a current corresponding to the phase difference signal to the control signal node, and a second current source that supplies a current corresponding to the second phase difference signal to the control signal node; Any one of the charge pump circuit that outputs the control signal based on the current value supplied by the second current source from the control signal node, the filter circuit that smoothes the control signal, and the first and second phase difference signals. Is asserted, the current path that reaches the filter circuit from any one of the first and second current sources via the control signal node is enabled, and the first and second phase difference signals are When both are negated, the current path is disabled by substantially opening the first and second current sources and the control signal node, and the potential of the control signal is held constant. Configured as It is characterized by comprising a voltage compensation circuit.

In the semiconductor integrated circuit having the above configuration, when the first and second phase difference signals are asserted, the current path from either the first or second current source to the control signal node is effective. As a result, the charge pump circuit outputs a control signal. Further, when the first and second phase difference signals are negated, the current path becomes invalid,
The second current source and the control signal node are substantially opened. Therefore, while the first and second phase difference signals are negated, it is possible to suppress the potential change of the control signal due to the leak current from the first and second current sources flowing to the control signal node. Therefore, the potential of the control signal can be held constant, and the fluctuation of the frequency of the oscillation signal output from the voltage controlled oscillator can be suppressed. Further, the frequency of the oscillation signal can be controlled with high accuracy.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. When explaining this,
Common parts are designated by common reference numerals.

A semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a circuit block diagram showing a configuration example of a PLL circuit. As shown, the PLL circuit 10 includes a phase comparator 20, a charge pump circuit 3
0, low pass filter (LPF) 40, voltage controlled oscillator (VCO) 5
It has 0, a frequency divider 60, and a voltage compensation circuit 70.

The phase comparator 20 has a reference signal of a predetermined frequency.
Fref is input from the outside, and the divided signal Fosc is input from the frequency divider 60. Then, the phase comparator 20 detects the phase difference between the reference signal Fref and the frequency-divided signal Fosc, and outputs the phase difference signals UP and DN having a pulse width corresponding to the phase difference. Charge pump circuit
30 is a control voltage signal VCOi based on the phase difference signals UP and DN.
Output n. The filter circuit 40 has a control voltage signal VCOin.
Is smoothed. Then, the smoothed control voltage signal VCOin
Is supplied to the voltage controlled oscillator circuit 50. Voltage controlled oscillator circuit 50
Is the oscillation signal Fout of the frequency based on the control voltage signal VCOin.
To generate. The frequency divider 60 sets the frequency of the oscillation signal Fout to 1 / N
The frequency division signal Fosc is output. Voltage compensation circuit 70
Holds the potential of the control voltage signal VCOin appearing at the output node of the charge pump circuit 30 constant.

FIG. 2 shows a portion of the charge pump circuit 30,
6 is a circuit diagram of a low pass filter 40 and a voltage compensation circuit 70. FIG. As shown in the figure, the charge pump circuit 30 includes a CMOS buffer including pMOS transistors 31, 32 and nMOS transistors 33, 34 at its output stage. The pMOS transistor 31 has a gate to which the phase difference signal UP is input, a source connected to the power supply potential VDD, and a drain. The pMOS transistor 32 has a gate to which a voltage higher than a threshold value is constantly applied, a source connected to the drain of the pMOS transistor 31, and an output node N1 of the charge pump circuit 30.
Has a drain connected to. nMOS transistor
33 is a gate or node to which a voltage above the threshold is constantly applied
It has a drain connected to N1, and a source. nM
The OS transistor 34 has a gate to which the phase difference signal DN is input, a drain connected to the source of the nMOS transistor 33, and a source connected to the ground potential. Then, the potential of the node N1 becomes the control voltage signal VCOin.

The low-pass filter 40 comprises a capacitor 41 and a resistance element 42 connected in series. It is provided between the node N1 and the power supply potential VDD.

The voltage compensation circuit 70 comprises a differential amplifier 71 and transfer gates 72 and 73. Differential amplifier 71
Is a voltage follower having a non-inverting input terminal (+) connected to the node N1, an inverting input terminal (-) connected to an output terminal, and an output terminal. The voltage follower has a very high input impedance and a low output impedance, and its voltage amplification factor is almost 1. Therefore, the potential of the output terminal of the differential amplifier 71 is always set to the same potential as the node N1. The transfer gate 72 is a pMOS transistor
It is provided between a connection node N2 between the drain of 31 and the source of the pMOS transistor 32 and the output terminal of the differential amplifier 71. The transfer gate 73 is provided between a connection node N3 between the source of the nMOS transistor 33 and the drain of the nMOS transistor 34 and the output terminal of the differential amplifier 71. Each of the transfer gates 72 and 73 is composed of, for example, a combination of an nMOS transistor and a pMOS transistor whose sources and drains are commonly connected. Then, it is closed (non-conducting) while any of the phase difference signals UP and DN is asserted, and is open (conducting) during the negated period.

Next, the operation of the above-configured PLL circuit will be described together with the relationship between the reference signal Fref and the frequency-divided signal Fosc.

[When the phases of the reference signal Fref and the frequency-divided signal Fosc are aligned] First, the phase of the frequency-divided signal Fosc obtained by frequency-dividing the oscillation signal Fout into 1 / N is the reference signal Fref input from the outside.
The case where the phases are aligned with each other will be described with reference to FIG. FIG. 3 shows the reference signal Fref, the divided signal Fosc, and the phase difference signal.
7 is a time chart of UP, DN, and a control voltage signal VCOin.

The phase comparator 20 includes a reference signal Fref and a divided signal.
The phase difference at the rising edge of Fosc is monitored. Then, when the phase of the divided signal Fosc is behind the phase of the reference signal Fref, the phase difference signal UP is asserted for the time width corresponding to the phase difference. Conversely, the divided signal Fosc
When the phase of is ahead of the phase of the reference signal Fref, the phase difference signal DN is asserted. The phase difference signal UP has a negative logic and is asserted when it goes to “L” level.
On the other hand, the phase difference signal DN has a positive logic and is asserted when it goes to "H" level. Then, the charge pump circuit 30 charges and discharges a current according to the phase difference signals UP and DN.

As shown in FIG. 3, when the phases of the reference signal Fref and the divided signal Fosc are aligned, at time t1,
The rising edges of both signals are aligned. Therefore, the phase comparator 20 keeps negating both the phase difference signals UP and DN, and the potential of the control voltage signal VCOin is constant. The voltage-controlled oscillator circuit 50 determines that the frequency of the divided signal Fosc is the reference signal.
The oscillation signal Fout that is N times Fref is output.

[When Frequency-Divided Signal Fosc is in Delay Phase with respect to Reference Signal Fref] Next, the phase of the frequency-divided signal Fosc is equal to the reference signal Fref.
A case in which the phase is delayed from the phase will be described with reference to FIG. FIG. 4 is a time chart of the reference signal Fref, the frequency division signal Fosc, the phase difference signals UP and DN, and the control voltage signal VCOin.

As shown in the figure, when the phase of the divided signal Fosc is behind the phase of the reference signal Fref, the divided signal
Fosc rises later than the reference signal Fref. That is, the reference signal Fref rises at time t1, while the divided signal Fosc rises at time t2 which is delayed by Δt1 from time t1.

Then, the phase comparator 20 asserts the phase difference signal UP during the time width Δt1 corresponding to the phase difference.
The circuit diagram of FIG. 5A shows the state from time t1 to t2 when the phase difference signal UP is asserted. That is, the MOS transistors 31 to 33 are turned on, and the MOS transistor 3
4 is turned off. Further, since the phase difference signal UP is asserted, the transfer gates 72 and 73 are closed.

Therefore, from the power supply potential VDD to the MOS transistor
A path is generated through 31 and 32 to reach the node N1, and current flows out from the node N1 to the low pass filter 40. As a result, the electric charge flows into the capacitor 41 of the low pass filter 40. Therefore, as shown from time t1 to t2 in FIG. 4, the potential of the control voltage signal VCOin rises.

Next, at time t2, the phase difference signal UP is negated. The circuit diagram of FIG. 5B shows the state after the time t2. As shown, M together with MOS transistor 34
The OS transistor 31 is turned off. However, the MOS transistors 32 and 33 are still on. Further, since the phase difference signals UP and DN are negated, the transfer gates 72 and 73 are open. That is, after time t2, node N1 is fixed by voltage follower circuit 71 to control voltage signal VCOin at the potential set at time t2.

Further, since the potential of the control voltage signal VCOin is increased, the frequency of the oscillation signal Fout generated by the voltage controlled oscillator circuit 50 is increased. As a result, the voltage controlled oscillator circuit 50 outputs the oscillation signal Fout such that the frequency of the divided signal Fosc is N times the reference signal Fref, and the rising edges of the divided signal Fosc and the reference signal Fref match at time t3. .

[When the Divided Signal Fosc Leads the Phase of the Reference Signal Fref] Next, the phase of the divided signal Fosc is the reference signal Fref.
A case in which the phase is advanced from the phase will be described with reference to FIG. FIG. 6 is a time chart of the reference signal Fref, the frequency division signal Fosc, the phase difference signals UP and DN, and the control voltage signal VCOin.

As shown in the figure, when the phase of the divided signal Fosc is ahead of the phase of the reference signal Fref, the divided signal
Fosc rises earlier than the reference signal Fref. That is,
The frequency-divided signal Fosc rises at time t1, while the reference signal Fref rises at time t2 which is delayed by Δt2 from time t1.

Then, the phase comparator 20 asserts the phase difference signal DN during the time width Δt2 corresponding to the phase difference.
The circuit diagram of FIG. 7 shows the state between the times t1 and t2 when the phase difference signal DN is asserted. That is, the MOS transistor 31 is turned off and the MOS transistors 32 to 34 are turned on. Further, since the phase difference signal DN is asserted, the transfer gates 72 and 73 are closed.

Therefore, from the node N1 to the MOS transistor 3
A path reaching the ground potential is generated through 3, 34, and current flows from the node N1 to the ground potential. As a result, the electric charge is discharged from the capacitor 41 of the low pass filter 40. Therefore, as shown from time t1 to t2 in FIG.
The potential of the control voltage signal VCOin drops.

Next, at time t2, the phase difference signal UP is negated. The state after time t2 is the same as that in FIG. 5B, in which the MOS transistors 31 and 34 are off and the MOS transistors 32 and 33 are on. In addition, the transfer gates 72 and 73 are opened. That is, after time t2,
The node N1 is controlled by the voltage follower circuit 71 to control voltage signal VC
Oin is fixed at the potential set at time t2.

Further, since the potential of the control voltage signal VCOin is lowered, the frequency of the oscillation signal Fout generated by the voltage controlled oscillator circuit 50 is lowered. As a result, the voltage controlled oscillator circuit 50 outputs the oscillation signal Fout such that the frequency of the divided signal Fosc is N times the reference signal Fref, and the rising edges of the divided signal Fosc and the reference signal Fref match at time t3. .

The PLL circuit 10 can set the oscillation signal Fosc to a desired frequency by performing the above operation.

As described above, in the PLL circuit according to the present embodiment, the potential of the node N1 is kept constant by adding the MOS transistors 32, 33 and the voltage compensation circuit 70. As a result, it is possible to supply an oscillation signal whose frequency is more stable than in the conventional case. This effect will be described in detail below.

The cause of the error in the frequency of the oscillation signal in the conventional PLL circuit is that the charge amount of the capacitor 41 in the low-pass filter 40 fluctuates due to the leak current flowing in the MOS transistor forming the buffer in the charge pump circuit 30. I was there. However, the PLL according to the present embodiment
In the case of a circuit, as shown in FIG. 5B, after the potential of the node N1 is set to a predetermined value, the transfer gate 7
2, 73 are open. As a result, the nodes N2 and N3 are connected to the output terminal of the differential amplifier 71, which is a voltage follower in which the node N1 is connected to the non-inverting input terminal, that is, the potential of the node N1 is the reference potential. The voltage follower is
Since the circuit is such that "input = output",
The nodes N1 and N2, and the nodes N1 and N3 have the same potential. Therefore, the MOS transistors 3 provided between the nodes N1 and N2 and between the nodes N1 and N3, respectively.
No current flows between the source and drain of 2, 33. That is, if attention is paid only to the current path, as shown in the circuit diagram of FIG. 8, nodes N1 and N2, and nodes N1 and N3 are shown.
It can be regarded that they are equivalently opened (non-conducting) during the period (of course, the MOS transistors 32 and 33 are in the ON state).

Then, let us consider the leak current flowing through the pMOS transistor 31 or the nMOS transistor 34 in the off state. Then, as shown in FIG.
The leak current I (leak1) flowing through the transistor 31 is the node N1.
To the output terminal of the differential amplifier 71 via the transfer gate 72. This leakage current I (leak1)
Contributes to increasing the potentials of the output terminal of the differential amplifier 71 and the inverting input terminal. That is, it tries to increase the potential of the node N2 that is at the same potential as the node N1.
However, since the node N1 is connected to the non-inverting input terminal of the differential amplifier 71, the differential amplifier 71 acts in the direction of lowering the potential of the output end. As a result, the potential of the output terminal of the differential amplifier 71 is fixed to the potential of the node N1, and the potential of the node N2 remains the same as that of the node N1.

The leak current I (leak2) flowing through the nMOS transistor 34 does not flow from the node N1 to the ground potential, but is transferred from the output end of the differential amplifier 71 to the transfer gate.
Flows to ground potential through 73. This leakage current I (leak
2) contributes to decrease the potentials of the output terminal of the differential amplifier 71 and the inverting input terminal. That is, the potential of the node N3, which has the same potential as that of the node N1, is reduced. However, the node N1 is connected to the non-inverting input terminal of the differential amplifier 71.
Are connected, the differential amplifier 71 acts in the direction of increasing the potential of the output end. As a result, the potential of the output terminal of the differential amplifier 71 is fixed to the potential of the node N1, and the potential of the node N3 is the same as that of the node N1 and remains unchanged.

As a result of the above, even if a leak current occurs in either of the MOS transistors 31 and 34, the inflow and outflow of extra charges to the capacitor 41 in the low pass filter 40 is suppressed. Therefore, the potential of the node N1, that is, the control voltage signal VC
It is possible to keep the potential of Oin constant, suppress fluctuations in the frequency of the oscillation signal Fout, and control with high accuracy.
Further, as a result, it is possible to reduce the phase error and the jitter.

Next, a semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIG. Figure 9 is PL
It is a circuit diagram of a part of L circuit.

As shown in the figure, the PLL circuit according to the present embodiment is the charge pump circuit according to the first embodiment.
PMOS transistor 32 and nMOS transistor 33 in 30 are
The resistance elements 35 and 36 are replaced. That is, by connecting the resistance element 35 between the node N1 and the node N2,
A resistance element 36 is connected between N1 and the node N3.

The operation of the PLL circuit according to this embodiment is similar to that of the first embodiment. When either of the phase difference signals UP and DN is asserted by the phase comparator 20, the transfer gates 72 and 73 are closed. Phase difference signal UP
Is asserted, a path from the power supply potential VDD to the node N1 via the MOS transistor 31 and the resistance element 35 is generated, and current flows from the node N1 to the low-pass filter 40.
Flow to. As a result, electric charges flow into the capacitor 41 of the low pass filter 40, and the potential of the control voltage signal VCOin rises. Conversely, when the phase difference signal DN is asserted, a path from the node N1 to the ground potential via the resistance element 36 and the MOS transistor 34 is generated, and the current flows to the node.
Flow from N1 to ground potential. As a result, charges are released from the capacitor 41 of the low pass filter 40, and the potential of the control voltage signal VCOin drops.

After setting the potential of the node N1 to a predetermined value, the transfer gates 72 and 73 are opened so that the node N1 and the node N2 and the node N1 and the node N3 have the same potential. As a result, the nMOS transistor 31 and
The leak current flowing through the pMOS transistor 34 is the differential amplifier 71.
Is absorbed by the node N1 and the control voltage signal VC
The potential of Oin is not affected by the leak current. Therefore, similarly to the first embodiment, it is possible to suppress fluctuations in the frequency of the oscillation signal Fout and control with high accuracy.

Next, a semiconductor integrated circuit according to the third embodiment of the present invention will be described with reference to FIG. Figure 10
FIG. 3 is a circuit diagram of a part of the PLL circuit.

As shown in the figure, the PLL circuit according to this embodiment is the charge pump circuit according to the first embodiment.
The pMOS transistor 32 and the nMOS transistor 33 in 30 are eliminated. Then, the node N1 and the node N2 and the node N1 and the node N3 are short-circuited.

The operation of the PLL circuit according to this embodiment is the same as that of the first embodiment. When either of the phase difference signals UP and DN is asserted by the phase comparator 20, the transfer gates 72 and 73 are closed. Phase difference signal UP
Is asserted, a path from the power supply potential VDD to the node N1 via the MOS transistor 31 and the node N2 is generated, and current flows from the node N1 to the low-pass filter 40. As a result, electric charges flow into the capacitor 41 of the low pass filter 40, and the potential of the control voltage signal VCOin rises. Conversely, when the phase difference signal DN is asserted, a path from the node N1 to the ground potential is generated via the node N3 and the MOS transistor 34, and the current flows to the node N1.
Flows into the ground potential. As a result, charges are released from the capacitor 41 of the low pass filter 40, and the potential of the control voltage signal VCOin drops.

After setting the potential of the node N1 to a predetermined value, the transfer gates 72 and 73 are opened so that the node N1 and the node N2 and the node N1 and the node N3 have the same potential. As a result, the nMOS transistor 31 and
The leak current flowing through the pMOS transistor 34 is the differential amplifier 71.
Is absorbed by the node N1 and the control voltage signal VC
The potential of Oin is not affected by the leak current. Therefore, similarly to the first embodiment, it is possible to suppress fluctuations in the frequency of the oscillation signal Fout and control with high accuracy.

As described above, according to the PLL circuits according to the first to third embodiments of the present invention, the drain of the pMOS transistor 31 (node N2), which causes a leakage current, becomes a problem in the charge pump circuit. A voltage follower 71 is provided in parallel with the path reaching the output node N1. The voltage follower 71 uses the reference potential as the potential of the node N1 and the output potential as the potential of the node N2. Similarly, from the drain (node N3) of the nMOS transistor 34, where the generation of leakage current becomes a problem, to the output node N1 of the charge pump circuit.
A voltage follower 71 is provided in parallel with the path reaching the.
The voltage follower 71 uses the reference potential as the potential of the node N1 and the output potential as the potential of the node N3.

Then, by opening the nodes N2 and N3 and the voltage follower 71, the low pass filter from the node N1.
The current path reaching the node N1 from the low-pass filter 40 or from the low-pass filter 40 is enabled, and the potential of the control voltage signal VCOin is set. Further, after the potential of the control voltage signal VCOin is set, the nodes N2 and N3 are connected to the voltage follower 71 so that the node N1 and the node N2 and the node N1 and the node N3 have the same potential. As a result, the current path reaching the low-pass filter 40 from the node N2 via the node N1 and the current path reaching the node N3 from the low-pass filter 40 via the node N1 are invalidated. Therefore, the leak current generated in the MOS transistors 31 and 34 is suppressed from flowing into the node N1, and the capacitor in the low-pass filter 40 is suppressed.
The fluctuation of the charge amount of 41 is suppressed. As a result, the frequency of the oscillation signal Fout generated by the voltage controlled oscillator circuit 50 can be stabilized.

Therefore, the voltage compensation circuit 70 controls the control voltage signal.
After the potential of VCOin is set, the current path between the node N1 and the node N2 and the node N1 and the node N3 may be invalidated so that a leak current can be prevented from flowing into the node N1. It is not limited to the circuit configuration described in the third embodiment. Further, in the above-described embodiment, the MOS transistors 31 and 34 that form the charge pump circuit 30 may be those that function as a current source.
Furthermore, although the PLL circuit has been described as an example in the above embodiment, the present invention can be widely applied to semiconductor circuits in general in which the potential of a predetermined node varies due to a current flowing from another node. is there.

The invention of the present application is not limited to the above-described embodiment, and can be variously modified at the stage of implementation without departing from the spirit of the invention. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the problems described in the section of the problem to be solved by the invention can be solved, and the effects described in the section of the effect of the invention When the above is obtained, the configuration in which this constituent element is deleted can be extracted as the invention.

[0057]

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit capable of supplying an oscillation signal having a stable frequency.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a PLL circuit according to the first embodiment of the present invention.

FIG. 3 is a time chart of various signals in the PLL circuit according to the first embodiment of the present invention.

FIG. 4 is a time chart of various signals in the PLL circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram of the PLL circuit according to the first embodiment of the present invention, in which (a) is a state in which one of the phase difference signals is asserted, and (b) is a phase difference signal. The figure which shows the state in which both are negated.

FIG. 6 is a time chart of various signals in the PLL circuit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram of the PLL circuit according to the first embodiment of the present invention, showing a state in which one of the phase difference signals is asserted.

FIG. 8 is a circuit diagram of the PLL circuit according to the first embodiment of the present invention, showing a state in which both phase difference signals are negated.

FIG. 9 is a circuit diagram of a PLL circuit according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram of a PLL circuit according to a third embodiment of the present invention.

FIG. 11 is a block diagram of a conventional PLL circuit.

FIG. 12 is a circuit diagram showing a part of a conventional PLL circuit.

FIG. 13 is a time chart of various signals in a conventional PLL circuit.

FIG. 14 is a time chart of various signals in a conventional PLL circuit.

[Explanation of symbols]

10, 100 ... PLL circuit 20, 200 ... Phase comparator 30, 300 ... Charge pump circuit 31-34, 310, 320 ... MOS transistors 35, 36, 42, 420 ... Resistance element 40, 400 ... Low-pass filter 41, 410 ... Capacitor 50, 500 ... Voltage controlled oscillator 60, 600 ... Divider 70 ... Voltage compensation circuit 71 ... Differential amplifier 72, 73 ... Transfer gate

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5J055 AX37 BX16 CX24 DX22 DX57                       DX72 DX83 EY01 EY10 EY21                       EZ00 EZ08 EZ10 EZ12 EZ14                       EZ28 EZ55 FX05 FX18 FX40                       GX01 GX02 GX04 GX05                 5J106 AA04 CC01 CC24 CC41 CC52                       DD01 DD32 JJ04 JJ08 KK15

Claims (6)

[Claims] 1. A voltage-controlled oscillator that outputs an oscillation signal having a frequency according to a control signal, a frequency divider that outputs a comparison signal obtained by dividing the oscillation signal, and a phase comparison between a reference signal and the comparison signal. A phase comparator for outputting first and second phase difference signals according to the phase difference obtained as a result of the comparison, and a first current source for supplying a current according to the first phase difference signal to a control signal node And a second current source that supplies a current according to the second phase difference signal to the control signal node,
A charge pump circuit that outputs the control signal based on the current values supplied by the first and second current sources from the control signal node; a filter circuit that smoothes the control signal; and the first and second positions. When any one of the phase difference signals is asserted, the current path reaching the filter circuit from any one of the first and second current sources via the control signal node is enabled, and the first and second current sources are activated. When the phase difference signals are both negated, the current path is invalidated by substantially opening between the first and second current sources and the control signal node, and the potential of the control signal is changed. And a voltage compensating circuit configured to hold the semiconductor integrated circuit constant. 2. The first current source has a gate to which the first phase difference signal is input, one end of a current path connected to a power supply potential, and the other end of a current path connected to the control signal node. The second current source includes a gate to which the second phase difference signal is input, one end of a current path connected to a ground potential, and another current path connected to the control signal node. A second MOS transistor having an end, wherein the voltage compensating circuit is configured to select one of the power supply potential and the ground potential from the power supply potential or the ground potential when either the first or second phase difference signal is asserted. When the current path reaching the control signal node via one of the first and second MOS transistors is enabled and both the first and second phase difference signals are negated, the first and second MOS transistors are turned on. The semiconductor integrated circuit according to claim 1, wherein said substantially open between the other end and the control signal node of the current path for disabling the current path, it is characterized by the Njisuta. 3. The voltage compensating circuit, wherein a voltage follower circuit using the potential of the control signal node as a reference potential, and the first and second phase difference signals are negated,
3. The semiconductor device according to claim 2, further comprising first and second switch elements that connect between the other ends of the current paths of the first and second MOS transistors and an output node of the voltage follower circuit, respectively. Integrated circuit. 4. The voltage follower circuit is a differential amplifier having a non-inverting input terminal connected to the control signal node, an inverting input terminal connected to an output terminal, and the output terminal. The semiconductor integrated circuit according to claim 3. 5. The charge pump circuit is connected to a gate to which a voltage higher than a threshold value is always applied, one end of a current path connected to the other end of the current path of the first MOS transistor, and the control signal node. A third MOS transistor having the other end of the current path, a gate to which a voltage equal to or higher than a threshold is constantly applied, the second MO transistor
5. A fourth MOS transistor having one end of a current path connected to the other end of the current path of the S transistor and a fourth MOS transistor having the other end of the current path connected to the control signal node. The semiconductor integrated circuit according to claim 1. 6. The charge pump circuit comprises the first M
One end connected to the other end of the current path of the OS transistor,
And a first end having the other end connected to the control signal node
The resistor element and a second resistor element having one end connected to the other end of the current path of the second MOS transistor and the other end connected to the control signal node. 4. The semiconductor integrated circuit according to any one of 4 above.