JP2003298404A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To supply an electric current required for reducing a leak electric current when not operating an internal circuit provided in a semiconductor integrated circuit device, and for operating the internal circuit. <P>SOLUTION: The semiconductor integrated circuit device is provided with a first power source means equipped with a current supply element composed of a bipolar transistor for supplying a first potential required for operating the internal circuit and a second power source means for supplying a second potential set lower than the first potential, and when operating the internal circuit, the first potential is supplied but when not operating the internal circuit, the second potential is supplied. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device which realizes reduction of leak current by utilizing power supply technology.

[0002]

2. Description of the Related Art Conventionally, in order to reduce the current consumption of a semiconductor integrated circuit device, as shown in, for example, Japanese Patent Laid-Open No. 63-65714, when the internal circuit is not operated, the internal circuit is There has been proposed a technique for supplying a voltage lower than that required when operating the internal circuit. In a semiconductor integrated circuit composed of MOS transistors, when the supplied voltage is lower than the threshold value of the transistor, the magnitude of the leak current is proportional to the supplied voltage.
Therefore, by lowering the voltage supplied to the internal circuit when the internal circuit is not operated, the leakage current when the internal circuit is not operated can be reduced and the current consumption can be reduced.

In the above-mentioned prior art, a simplified semiconductor integrated circuit device comprising a power supply circuit 44 and an internal circuit 45 as shown in FIG. 6 shows how the leak current of the entire semiconductor integrated circuit device changes. Explained by.

The internal circuit 45 is connected to a power supply circuit 44, and the power supply potential Vdd is Vdd1 by the power supply circuit 44.
Alternatively, the voltage is lowered to Vdd2 (Vdd1> Vdd2).
When operating the internal circuit 45, the output potential Vd
d1 is supplied to the internal circuit 45, and the output potential Vdd2 is supplied to the internal circuit 45 when the internal circuit 45 is not operated.

As shown in FIG. 7A, the power supply potential supplied to the internal circuit 45 is lowered from the operating potential Vdd1 (for example, 1.5 V) to the non-operating potential Vdd2 (for example, 0.01 V). Suppose At this time, the voltage applied to the power supply circuit 44 increases from V1 to V1 ′, and the voltage applied to the internal circuit 45 decreases from V2 to V2 ′.

8A and 8B show the relationship between the current flowing through the power supply circuit and the internal circuit and the voltage applied to the circuit. Curve 1 represents the current-voltage curve of the power supply circuit 44, and curve 2 represents the current-voltage curve of the internal circuit 45. When the voltage applied to the internal circuit 45 drops from the operating state V2 to the non-operating state V2 ′, the leakage current of the internal circuit 45 becomes
It decreases from I2 to I2 '. On the other hand, the voltage applied to the power supply circuit 44 rises from V1 in the operating state to V1 ′ in the non-operating state, and the leak current of the power supply circuit 43 rises from I1 to I1 ′.

Since the current flowing through the entire device is the sum of the current flowing through the power supply circuit and the current flowing through the internal circuit, it is I1 + I2 in the operating state and I1 '+ I2' in the non-operating state, and the leakage current is Decrease.

[0008]

However, it is not enough to reduce the leak current of the internal circuit in order to reduce the leak current of the entire device to a predetermined leak current or less in the non-operating state of the internal circuit. The leakage current must also be reduced.

Here, the power supply circuit is similar to the internal circuit in MO
In the case of S-transistors, it is conceivable to set the threshold value of the MOS transistor large or to reduce the gate width of the MOS transistor to reduce the leak current. However, the leakage current and the operating current are
This is a trade-off relationship, and reducing the leak current also reduces the operating current.
Therefore, when the operating current flowing through the MOS transistor of the power supply circuit becomes small, when operating the internal circuit,
There is a problem that the current that can be supplied to the internal circuit becomes small and the operation speed of the internal circuit becomes slow.

The present invention solves the above-mentioned drawbacks of the prior art, reduces the leak current when the internal circuit is not operated, and can supply the current necessary for operating the internal circuit. It is intended to provide a semiconductor integrated circuit device including a power supply circuit.

In addition to solving the above-mentioned problem of leakage current, the present invention provides a power supply for supplying a potential necessary for holding a signal of the internal circuit set in an operating state when the internal circuit is not operated. An object of the present invention is to provide a semiconductor integrated circuit device including a circuit.

[0012]

A semiconductor integrated circuit device according to the present invention is provided with a current supply composed of a bipolar transistor in order to reduce current consumption when an internal circuit included in the semiconductor integrated circuit device is in a non-operating state. A first power supply unit including an element for supplying a first potential necessary for operating the internal circuit; and a second power supply for supplying a second potential lower than the first potential. And means.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. The semiconductor integrated circuit device in FIG. 1 includes a system board 1, a first power supply circuit 2, a semiconductor integrated circuit device 3 and a control signal output circuit 4, and a power supply 15
Is supplied with the power supply potential Vdd (for example, 3 V).

The power supply potential Vdd is dropped by the first power supply circuit 2, and the semiconductor integrated circuit device 3 and the control signal output circuit 4 are supplied.
Is supplied with the power supply potential Vdd3 (for example, 1.5 V). The semiconductor integrated circuit device 3 includes a first internal circuit 6 and a second power supply circuit 5, and the first internal circuit 6 is connected to the first power supply circuit 2 and the second power supply circuit 5.

The first power supply circuit 2 includes a bipolar transistor 7, a bipolar transistor 8 and a first voltage control circuit 1.
0, the second voltage control circuit 11 and the first reference potential generation circuit 13. The second power supply circuit 5 includes a PMOS transistor 9, a third voltage control circuit 12, and a second reference potential generation circuit 14.

A control signal output circuit 4 and a first reference potential generating circuit 13 are connected to the first voltage control circuit 10, and the first voltage control circuit 10 receives a control signal from the control signal output circuit 4. ON and O of bipolar transistor 7
While controlling the FF state, the potential Vref1 (here, 1.5 V) generated by the first reference potential generating circuit 13 and the output potential of the bipolar transistor 7 are compared when the bipolar transistor 7 is in the ON state, and both are equal. Thus, the voltage applied to the gate of the bipolar transistor 7 is controlled. A first reference potential generation circuit 13 is connected to the second voltage control circuit 11, and the potential Vref1 generated by the first reference potential generation circuit 13 and the output potential of the bipolar transistor 8 are compared to make them equal. Thus, the voltage applied to the gate of the bipolar transistor 8 is controlled. The control signal output circuit 4 and the second reference potential generation circuit 14 are connected to the third voltage control circuit 12, and the third voltage control circuit 12 receives the control signal from the control signal output circuit 4 and receives the PMOS transistor 9 ON, OF
In addition to controlling the F state, the potential Vref2 (0.01 V in this case) generated by the second reference potential generating circuit 14 when the PMOS transistor 9 is in the ON state and the PMOS
The output potential of the transistor 9 is compared, and the voltage applied to the gate of the PMOS transistor 9 is controlled so that they are equal.

The bipolar transistor 7 supplies to the first internal circuit 6 the power supply potential Vdd1 (for example, 1.5 V) obtained by dropping the power supply potential Vdd when in the ON state. The bipolar transistor 8 is always in the ON state and supplies the power supply potential Vdd3 obtained by lowering the power supply potential Vdd to the second power supply circuit 5 and the control signal output circuit 4. The PMOS transistor 9 supplies to the first internal circuit 6 the power supply potential Vdd2 (for example, 0.01 V) obtained by dropping the power supply potential Vdd3 when in the ON state. The power supply potential Vdd2 is a potential capable of holding the signal of the first internal circuit 6 set in the operating state in the non-operating state.

FIG. 2 shows a bipolar transistor 7 and a PM.
The relationship between the ON / OFF state of the OS transistor 9 and the power supply potential supplied to the first internal circuit 6 is shown. The control signal output circuit 4 turns on the bipolar transistor 7 and turns off the PMOS transistor 9 when the first internal circuit 6 is operated.
0 and the control signal is output to the third voltage control circuit 12. At this time, the first power supply circuit 2 supplies the power supply potential Vdd1 to the first internal circuit 6. Control signal output circuit 4
When a sleep start signal is sent from the first voltage control circuit 10 to the third voltage control circuit 12, the bipolar transistor 7 is turned off and the PMOS transistor 9 is turned off.
In the N state, the first internal circuit 6 changes from the operating state to the non-operating state. At this time, the power supply potential Vdd2 is supplied from the second power supply circuit 5 to the first internal circuit 6. afterwards,
When operating the first internal circuit 6, a sleep end signal is sent from the control signal output circuit 4 to the first voltage control circuit 10 and the third voltage control circuit 12, and the bipolar transistor 7
Is turned on, the PMOS transistor 9 is turned off, and the potential supplied to the first internal circuit 6 is the power supply potential V.
The power supply potential Vdd1 is changed from dd2, and the first internal circuit 6 returns to the operating state.

In this embodiment, the bipolar transistor 7 and the PMOS transistor 9 have a sum of a leak current flowing through the bipolar transistor 7 and a leak current flowing through the PMOS transistor 9 when the first internal circuit 6 is not operated. It is manufactured so as to have a predetermined leakage current or less.

In the bipolar transistor 7 of the present embodiment, the leakage current in the OFF state satisfies the above-mentioned conditions, and at the same time in the ON state, the current required to operate the first internal circuit 6 at a predetermined operating speed. Need to supply. In order to satisfy the above two conditions, the bipolar transistor is used because the bipolar transistor is more advantageous in characteristics than the PMOS transistor.

Further, the second power supply circuit 5 in the present embodiment is sufficient if it has the ability to supply the leak current of the semiconductor integrated circuit device 3 in the non-operating state. The gate width of the transistor 9 does not need to be large, and the area can be reduced. Since the area increase of providing the second power supply circuit 5 inside the semiconductor integrated circuit device 3 is very small, the second power supply circuit 5 can be provided inside to reduce the number of parts.

Further, from the viewpoint of holding the signal of the first internal circuit 6 set in the operating state, by providing the second power supply circuit 5, the potential Vdd2 applied to the first internal circuit 6 in the non-operating state is set. , It is possible to set any potential capable of holding a signal.

As described above, according to the structure of this embodiment, the leak current of the entire semiconductor integrated circuit device is suppressed to a predetermined value or less when the internal circuit of the semiconductor integrated circuit device is not operated, and the internal circuit of the semiconductor integrated circuit device is suppressed. (EN) When operating a circuit, a current necessary for operating the internal circuit at a predetermined speed can be supplied to the internal circuit, so that a high-performance semiconductor integrated circuit device with low current consumption is provided. You can

(Second Embodiment) FIG. 3 is a block diagram showing a schematic structure of a semiconductor integrated circuit device according to a second embodiment of the present invention. The semiconductor integrated circuit device in this embodiment is different from the configuration of the first embodiment in that
A semiconductor integrated circuit device 16, a switch 22 and a switch 23 are added. Semiconductor integrated circuit device 16
Like the semiconductor integrated circuit device 3, is composed of a third power supply circuit 17 and a second internal circuit 18.

When the first internal circuit 6 is operated, the switch 22 is closed, and the potential Vdd1 is supplied to the first internal circuit 6 from the first power supply circuit 2. Further, when the second internal circuit 18 is operated, the switch 23 is closed, and the second internal circuit 18 receives the potential Vd from the first power supply circuit 2.
d1 is supplied.

On the other hand, when the first internal circuit 6 is not operated, the switch 22 is open, and the potential Vdd2 is supplied to the first internal circuit 6 from the second power supply circuit 5. Further, when the second internal circuit 18 is not operated, the switch 23 is open, and the potential Vdd4 is supplied to the second internal circuit 18 from the third power supply circuit 17.

Further, the first internal circuit 6 and the second internal circuit 1
When both 8 are not operated, the bipolar transistor 7 is turned off and the supply of Vdd1 is stopped.

The potential Vdd2 and the potential Vdd4 hold the signals set in the first internal circuit 6 and the second internal circuit 18 during the operation of the first internal circuit 6 and the second internal circuit 18, respectively. The potential is supplied to the first internal circuit 6 and the second internal circuit 18 when the internal circuit 6 and the second internal circuit 18 are not operated. Internal circuit 6
The potential Vdd2 supplied to the second internal circuit 18 and the potential Vdd2 supplied to the second internal circuit 18 can be set to different potentials.

In the present embodiment, the number of semiconductor circuit devices including the internal circuit is set to 2. However, even when the number is 3 or more, the same effect can be obtained by connecting the first power supply circuit 2 through the switch. be able to.

As described above, according to this embodiment, the same effect as that of the first embodiment can be obtained, and when there are a plurality of semiconductor integrated circuit devices including internal circuits, the respective internal Since the potential setting in the non-operating state can be changed according to the characteristics of the circuit, there is an effect that it is possible to provide a semiconductor integrated circuit device that consumes less current.

(Third Embodiment) FIG. 4 is a block diagram showing a schematic structure of a semiconductor integrated circuit device according to a third embodiment of the present invention. The semiconductor integrated circuit device of this embodiment is obtained by adding a PMOS transistor 26 as a voltage conversion circuit to the configuration of the semiconductor integrated circuit device of the first embodiment. When the PMOS transistor 26 is in the ON state, the potential Vdd5 (for example, 1.V.
2 V) is supplied to the third internal circuit 29. Third internal circuit 2
9 is operated, the bipolar transistor 7 and the PMOS transistor 26 are turned on, and the
The transistor 9 is turned off. When the third internal circuit 29 is not operated, the bipolar transistor 7 and the PMOS transistor 26 are turned off,
The PMOS transistor 9 is turned on.

According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained. Further, by incorporating the PMOS transistor 26 in the semiconductor integrated circuit device 24 as a voltage conversion circuit, Since the controllability of the power supply potential Vdd5 supplied to the third internal circuit 29 when operating the third internal circuit 29 is improved, there is an effect that a semiconductor integrated circuit device having higher performance and less current consumption can be provided.

(Fourth Embodiment) FIG. 5 is a block diagram showing a schematic structure of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

The semiconductor integrated circuit device shown in FIG. 5 includes a system board 1, a first power supply circuit 2, a semiconductor integrated circuit device 30, and a control signal output circuit 4, and a power supply 15 supplies a power supply potential Vdd (for example, 3 V). Has been done.

There are three internal circuits inside the semiconductor integrated circuit device 30, the fourth internal circuit 41 is directly connected to the first power supply circuit 2, and the fifth internal circuit 42 and the sixth internal circuit 43. Is the first power supply circuit 2 via the fifth power supply circuit 31.
It is connected to the.

The fifth power supply circuit 31 includes a PMOS transistor 32 and a PMOS transistor 3 which are current supply elements.
4, PMOS transistor 3 that functions as a switch
3, sixth voltage control circuit 35, seventh voltage control circuit 36, eighth voltage control circuit 37, fifth reference potential generation circuit 38, sixth reference potential generation circuit 39 and seventh reference potential generation circuit 40
And the PMOS transistor 32 is
In the ON state, the power supply potential Vdd6 (for example, 0.01
V), and the PMOS transistor 34 outputs the power supply potential Vdd7 (for example, 0.05 V) when in the ON state. The PMOS transistor 33 that functions as a switch includes a fifth internal circuit 42 and a sixth internal circuit 43.
It is provided between.

When operating the fourth internal circuit 41, the fifth internal circuit 42 and the sixth internal circuit 43, the bipolar transistor 7, bipolar transistor 8 and PMO are operated.
By turning on the S transistor 33 and turning off the PMOS transistor 32 and the PMOS transistor 34, the power supply potential Vdd1 is output by the bipolar transistor 7, and the fourth internal circuit 41, the fifth internal circuit 42, and the sixth internal circuit are output. 43 is the power supply potential Vdd
1 is supplied.

On the other hand, the fourth internal circuit 41 and the fifth internal circuit 4
When both the second and sixth internal circuits 43 are not operated, the bipolar transistor 8, the PMOS transistor 32, and the PMOS transistor 34 are turned on, and the bipolar transistor 7 and the PMOS transistor 33 are turned on.
Is turned off, the output from the first power supply circuit 2 to the fourth internal circuit 41, the fifth internal circuit 42 and the sixth internal circuit 43 is stopped, and the fifth internal circuit 42 and the sixth internal circuit 43 are Be electrically independent. At the same time, the fifth internal circuit 4
2 to the power supply potential Vdd6 from the PMOS transistor 32.
However, the power supply potential Vdd7 is supplied from the PMOS transistor 34 to the sixth internal circuit 43.

In the configuration of this embodiment, when there are an internal circuit that needs to hold the signal set in the operating state and an internal circuit that does not need to hold the signal when the internal circuit is not operated, The fifth internal circuit 42 and the sixth internal circuit 43, which need to hold signals, have predetermined potentials (Vdd6, Vdd) capable of holding signals.
The fourth internal circuit 41 which supplies 7) and does not need to hold the signal can cut off the supply of the potential.

Further, the fifth internal circuit 42 and the sixth internal circuit 4
3 is provided with a PMOS transistor 33 functioning as a switch, the PMOS transistor 33 is turned off, and the fifth internal circuit 42 and the sixth internal circuit 43 are electrically separated from each other. When the fifth internal circuit 42 and the sixth internal circuit 43 have different predetermined potentials capable of holding signals when the sixth internal circuit 43 is not operated, different predetermined power supply potentials (Vdd6,
It is possible to supply Vdd7).

As described above, according to the configuration of this embodiment, the same effect as that of the first embodiment can be obtained,
Further, even when a plurality of internal circuits exist inside the non-semiconductor integrated circuit device, it is possible to set the power supply to be cut off or supplied for each internal circuit when the internal circuits are not operated. In addition, when it is necessary to supply power when the internal circuit is not operated, a different predetermined power supply potential can be set for each internal circuit, so that it is possible to provide a semiconductor integrated circuit device with less current consumption. is there.

In the first, second, third and fourth embodiments described above, the first voltage control circuit 10, the second voltage control circuit 11 and the first reference potential generating circuit 13 are:
The semiconductor integrated circuit device 3, the semiconductor integrated circuit device 16, the semiconductor integrated circuit device 24, or the semiconductor integrated circuit device 30 is provided inside the first power supply circuit 2, and the control signal output circuit 4 is provided. The semiconductor integrated circuit device 16, the semiconductor integrated circuit device 24, or the semiconductor integrated circuit device 30 is provided outside the semiconductor integrated circuit device 16. However, these first voltage control circuit 10, second voltage control circuit 11, first reference potential generation circuit 13, and The control signal output circuit 4 is used as the semiconductor integrated circuit device 3, the semiconductor integrated circuit device 16, and the semiconductor integrated circuit device 2.
4 or inside the semiconductor integrated circuit device 30. With such a configuration, there is an advantage of cost reduction due to the reduction of the chip area and the number of parts as compared with the above-mentioned embodiment.

[0044]

The effects obtained by the typical one of the inventions disclosed in the present invention will be briefly described as follows.
It is as follows. By providing a bipolar transistor in the power supply circuit, in the non-operating state of the internal circuit,
Leakage current can be reduced to a predetermined value, and
There is an effect that a current required to operate the internal circuit at a predetermined operating speed can be supplied. Further, by supplying a potential capable of holding a signal even when the internal circuit is not operated, an effect that the signal can be held is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part showing a configuration of a semiconductor integrated circuit device for explaining the present invention.

FIG. 2 is a diagram showing changes in a power supply voltage in an operating state and a non-operating state for explaining the present invention.

FIG. 3 is a principal block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 4 is a principal block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 5 is a principal block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional technique.

FIG. 7 is a diagram showing a relationship between a state of a power supply voltage and a leak current for explaining a conventional technique.

FIG. 8 is a diagram showing a voltage dependence of a leak current for explaining a conventional technique.

[Explanation of symbols]

1 System Board 2 First Power Supply Circuit 3, 16, 24, 30 Semiconductor Integrated Circuit Device 4 Control Signal Output Circuit 5 Second Power Supply Circuit 6 First Internal Circuit 7, 8 Bipolar Transistor 9, 19, 26, 32, 33, 34 PMOS transistor 10 First voltage control circuit 11 Second voltage control circuit 12 Third voltage control circuit 13 First reference potential generation circuit 14 Second reference potential generation circuit 15 Power supply 17 Third power supply circuit 18 Second internal circuit 20 Fourth voltage Control circuit 21 Third reference potential generation circuit 22, 23 Switch 25 Fourth power supply circuit 27 Fifth voltage control circuit 28 Fourth reference potential generation circuit 29 Third internal circuit 31 Fifth power supply circuit 35 Sixth voltage control circuit 36 Seventh Voltage control circuit 37 Eighth voltage control circuit 38 Fifth reference potential generation circuit 39 Sixth reference potential generation circuit 40 Seventh reference potential generation circuit 41 Fourth internal circuit 42 Fifth internal circuit 43 Sixth internal circuit 44 Power supply circuit 45 Internal circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Keiichi Kusumoto             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5J056 AA00 BB49 CC04 DD02 DD13                       EE02 EE03 EE15 FF07 GG09                       KK01 KK03

Claims (6)

[Claims] 1. An internal circuit, comprising a current supply element composed of a bipolar transistor,
A first power supply means for supplying a first potential necessary for operating the internal circuit; and a second power supply means for supplying a second potential set lower than the first potential. And a semiconductor integrated circuit device. 2. A voltage control circuit for controlling a potential supplied by the first and second power supply means, and a first voltage from the first power supply means to the internal circuit when operating the internal circuit. Supply the second
The output from the power supply is stopped, and when the internal circuit is not operated, a second potential is supplied from the second power supply means to the internal circuit, and the output from the first power supply is stopped. 2. The semiconductor integrated circuit device according to claim 1, further comprising a control circuit that operates. 3. A first and a second internal circuit, and a current supply element composed of a bipolar transistor,
First power supply means for supplying a first potential necessary for operating the first and second internal circuits; and a second power supply means set to the first internal circuit to be lower than the first potential. Second power supply means for outputting the third potential, a third power supply means for outputting a third potential lower than the first potential to the second internal circuit, and the first power supply means. And a first internal circuit, which electrically connects or disconnects the first power supply means and the first internal circuit, and a first power supply means. It is characterized by comprising a second switch means existing between the second internal circuit and electrically connecting or disconnecting the first power supply means and the second internal circuit. Semiconductor integrated circuit device. 4. When operating the first internal circuit, the first switch means is closed to supply the first potential from the first power supply means to the first internal circuit, The output of the second power supply is controlled so as to be stopped, and when the second internal circuit is operated, the second switch means is closed so that the first power supply means outputs the second power.
Is controlled to stop the output of the third power supply by supplying the first electric potential to the internal circuit of the third power supply, and when the first internal circuit is not operated, the first switch means is opened to First power supply means and the first
Of the first circuit so that it is electrically independent from the internal circuit of
Is controlled so as to supply a second potential from the second power supply means to the internal circuit, and when the second internal circuit is not operated, the second switch means is opened to open the first power supply. Means and said second
Of the second circuit so that it is electrically independent of the internal circuit of
Is controlled so as to supply a third potential from the third power supply means, and when the first internal circuit and the second internal circuit are not operated together, the first power supply means 4. The semiconductor integrated circuit device according to claim 3, further comprising a control circuit for controlling so as to stop the output from the device. 5. An internal circuit and a current supply element comprising a bipolar transistor,
First power supply means for supplying a first potential, and voltage conversion means for converting the first potential into a second potential required for operating the internal circuit and supplying the second potential to the internal circuit. A semiconductor integrated circuit device, comprising: a second power supply unit that supplies a third potential lower than the second potential to the internal circuit. 6. The semiconductor integrated circuit device according to claim 5, wherein the voltage converting means is a MOS transistor.