JP2003289269A - Demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a demodulator that can reduce power consumption, while keeping high precision. <P>SOLUTION: The demodulator has a reception intensity measuring correlator 14 for measuring the intensity of reception signal, a demodulation circuit 11 for demodulating data by, for example, 4-bit width in the case of relatively large reception intensity, a demodulation circuit 12 for demodulating data by, for example, a 6-bit width in the case of relatively small reception intensity, and a signal synthesis circuit 13 for synthesizing a data signal from the demodulation circuits 11 and 12. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for demodulating a received signal obtained by receiving a radio wave.

[0002]

2. Description of the Related Art Conventionally, code division multiple access (CDM)
A: Code Division Multiple
The receiver that constitutes the access-type communication device includes
A demodulator for demodulating a received signal obtained by receiving a radio wave transmitted from a base station is provided. To such a demodulator, a received signal received via a plurality of routes transmitted from a base station is input, and a code is generated according to the difference in arrival time of the received signal to receive it. A despreader that outputs a signal consisting of multivalued data at the arrival time by adding the product of the signal and its code, and the output from the despreader as necessary based on the pilot symbol that is the reference signal A channel estimator that estimates the decoding result by performing a process such as smoothing and inversely rotating by the inverse rotation vector of the pilot symbol, and a signal synthesizing circuit that synthesizes the decoding result from the channel estimator Has been. According to this demodulator, since each received signal received via a plurality of paths is processed by each despreader and each transmission path estimator, deterioration due to fluctuations (fading) in the transmission status of each path Can be suppressed.

FIG. 8 is a block diagram showing the structure of a conventional demodulator for demodulating a received signal received via two paths. Further, FIG. 9 is a diagram showing the reception strength of the reception signal received by the demodulator shown in FIG. 8 with respect to the arrival time.

The demodulator 100 shown in FIG. 8 includes two despreaders 110 and 120 and two transmission line estimators 130 and 1.
40 and a signal synthesizing circuit 150. The despreader 110 includes a code generator 111 and a multiplier 112.
And an adder 113. The despreader 120 also includes a code generator 121, a multiplier 122, and
It is composed of an adder 123.

Here, arrival at the demodulator 100 shown in FIG.
Reception intensity P at times T1 and T2 ₁Main pass, receive
Signal strength P₂The received signal of the sub-path is input (P₁> P
₂). Then, in the demodulator 100, the despreader 110 is constructed.
The code generator 111 to be generated, according to the arrival time T1
A code is generated, and the generated code and main
Data in the matrix is multiplied by the multiplier 112, and
The addition is performed by the adder 113, and the transmission path estimator 130 described later
Is input to one of the signal combining circuits 150 via. Well
In addition, in the code generator 121 that constitutes the despreader 120,
A code is generated according to the arrival time T2, and the generated code
No. and the data in the sub-path are multiplied by the multiplier 122.
And the transmission path estimator 14
It is input to the other side of the signal synthesis circuit 150 via 0.
In the signal synthesis circuit 150, the transmission path estimators 130, 140
Synthesize the data signal from. In this way, demodulated
The received signal is obtained.

FIG. 10 is a block diagram showing the configuration of a conventional transmission path estimator.

FIG. 10 shows a despreader 160, a despreader 170, and a transmission path estimator 180. The transmission path estimator 180 includes a filter circuit 181, an inverse rotation vector generation circuit 182, and a complex multiplier 183.

Here, the transmission path estimation (channel estimation) is to estimate the transfer function (H) of the transmission path and to calculate its inverse function (H).
^-1 ) to obtain an inverse function (H ^-1 ) for the received data
It means that the original data is obtained by performing the calculation (in a narrow sense, only obtaining the transfer function (H) may be referred to as transmission path estimation).

The original data is expressed by the following equation.

∧D = H ^-1 Din = H ^-1 HD Origin
= Dorigin Here, an example will be described showing the transmission path estimation for performing phase compensation, which is usually performed in the case of the CDMA system.

The despreader 160 extracts the pilot symbol Psymbol (i) from the received signal. The pilot symbol Psymbol (i) is, for example, (1,
0) such as known pilot data. Pilot symbol Psymbo
l (i) is input to the filter circuit 181. Generally, the pilot symbol Psymbol (i) is rotated by θ on the transmission path, and for example, (P
x, Py). In the case of using polar coordinates, it is expressed as Psymbol = | Psymbol | exp (jθ) = SQRT (Px ² + Py ² ) exp (jθ).

The filter circuit 181 has a plurality of pilot symbols Ps in order to remove noise and stabilize the noise.
ymbol, for example, each pilot symbol Psymb
For ol (i), weighted average filtering for addition is performed, and pilot symbol vector Psy
Get mbol (Px, Py). This pilot symbol vector Psymbol (Px, Py) is input to the reverse rotation vector generation circuit 182, whereby the reverse rotation vector generation circuit 182 outputs the pilot symbol vector (Px / | Psymbol |, -Py / | Psym).
bol |) is output.

The despreader 170 also extracts the data symbol Dsymbol (i) from the received signal. This data symbol Dsymbol (i) is also rotated by θ similarly to the pilot symbol Psymbol (i). Data symbol Dsym from despreader 170
bol (i) is the pilot symbol vector (Px / | Psymbol from the reverse rotation vector generation circuit 182).
|, -Py / | Psymbol |) is multiplied by the complex multiplier 183.
The original data symbol Dsymbo by multiplying by
l (i) is obtained.

That is, multiplication of a complex number is performed using the inverse function H ^-1 = exp (-jθ) = (Px / │Psymbol│, -Py / │Psymbol│).

Here, the data symbol Dsymbol
(I), the signal consisting of data representing pilot symbol Psymbol (i) is assumed to be a QPSK signal. That is, the data symbols Dsymbol (i) and the pilot symbol P which are the outputs of the despreaders 110 and 160.
The vector representing symbol (i) is expressed as (Dx, Dy), (Px, Py) using the coordinates on the IQ plane, and the bit width of each affects the demodulation accuracy and the dynamic range. Becomes

[0016]

In the demodulator 100 shown in FIG. 8 described above, the despreaders 110 and 120 generate codes in accordance with the arrival times T1 and T2 of the main path and the subpath which form the received signal. By doing so, demodulation is performed. Here, since the reception intensity varies depending on the distance from the base station or the performance of the antenna, the amplification circuit, etc., the despreaders 110 and 120 have a relatively large dynamic range (dynamic range of 20 dB or more). Those with are needed.

For example, ITU (International)
al Telecommunication Unio
According to the transmission path model (Vehicular B) of n), the difference between the maximum strength and the minimum strength is 25.2 dB. In the case of the demodulator 100 described above, the despreader 110,
A resolution of 26 dB or more is required for each 120. In order to obtain a resolution of 26 dB or more, each of the despreaders 110 and 120 has a bit width of 6 to 8 bits. Here, the despreader 110,
The circuit scale of 120 increases in proportion to the square of the bit width. Further, when performance higher than the ITU model is required, including an increase in the number of paths to be combined, there is a problem that the circuit scale of each despreader is further increased, resulting in an increase in power consumption.

In view of the above circumstances, it is an object of the present invention to provide a demodulator in which power consumption is reduced while maintaining demodulation accuracy.

[0019]

A first demodulator of the demodulators of the present invention that achieves the above object is a demodulator based on a code division multiple access system for demodulating a received signal. Despreader for extracting the data, the second despreader for extracting the data symbols from the received signal, and the reverse rotation for inputting the pilot symbols from the first despreader to obtain the inverse rotation vector of the pilot symbols At least one of the demodulation circuits includes a plurality of demodulation circuits including a vector generation circuit and a complex multiplier that reversely rotates the phase of the data symbol from the second despreader by the inverse rotation vector. One demodulation circuit selects the pilot symbol extracted by the first despreader by selecting the bit width of the pilot symbol, and performs the inverse rotation vector. And characterized in that having a bit width selector for transmitting the torque generator.

In the first demodulator of the present invention, at least one demodulation circuit selects the pilot symbol extracted by the first despreader as the inverse rotation vector generation circuit by selecting the bit width of the pilot symbol. Since it is provided with a bit width selector for transmitting, in the case of a relatively large reception intensity, a pilot symbol having a narrow bit width is transmitted to the reverse rotation vector generation circuit and demodulated to thereby generate the reverse rotation vector generation circuit and its It is possible to suppress the operation of the elements constituting the circuit at the subsequent stage of the reverse rotation vector generation circuit. Therefore, compared with the conventional demodulator that always demodulates with a relatively large bit width, power consumption can be reduced while maintaining demodulation accuracy.

The second demodulator of the present invention that achieves the above object is a demodulator based on a code division multiple access system for demodulating a received signal. The first demodulator extracts pilot symbols from the received signal. Despreader, a second despreader for extracting data symbols from the received signal, and a filter for inputting the pilot symbols from the first despreader and smoothing the pilot symbols, and smoothing by the filter A plurality of inverse rotation vector generation circuits for obtaining the inverse rotation vector of the pilot symbol generated, and a complex multiplier for inversely rotating the phase of the data symbol from the second despreader by the inverse rotation vector. The filter which comprises a demodulation circuit and constitutes a first demodulation circuit of at least one of the demodulation circuits An operation circuit including a multiplier that multiplies the output symbol with a coefficient, smoothes the pilot symbol extracted by the first despreader that constitutes the first demodulation circuit, and the filter includes: The bit width selector for transmitting the coefficient to the multiplier by selecting the bit width of the coefficient is provided.

In the second demodulator of the present invention, the filter for smoothing the pilot symbols is provided with a bit width selector for selecting the bit width of the coefficient and transmitting it to the multiplier. When the reception strength is large, the multiplication of the coefficient with a narrow bit width and demodulation can suppress the operation of the multiplier and the elements constituting the circuit at the subsequent stage.
Therefore, compared with the conventional demodulator that always demodulates with a relatively large bit width, power consumption can be reduced while maintaining demodulation accuracy.

Further, the third demodulator of the present invention which achieves the above object is a demodulator based on a code division multiple access system for demodulating a received signal, wherein the first demodulator extracts a pilot symbol from the received signal. Despreader, a second despreader for extracting data symbols from a received signal, and an inverse rotation vector generation circuit for inputting pilot symbols from the first despreader to obtain an inverse rotation vector of the pilot symbols. , A complex multiplier that reversely rotates the phase of the data symbol from the second despreader by the inverse rotation vector, and at least one of the demodulation circuits includes a first demodulator circuit. Of the second despreader, and includes a bit width selector for transmitting the bit width of the data symbol from the second despreader to the complex multiplier. And wherein the Rukoto.

In the third demodulator of the present invention, at least one demodulation circuit is provided with a bit width selector for selecting the bit width of the data symbol and transmitting the bit width to the complex multiplier. In the case of reception intensity, by transmitting a data symbol having a narrow bit width to the complex multiplier and demodulating it, it is possible to suppress the operation of the element forming the complex multiplier. Therefore, compared with the conventional demodulator that always demodulates with a relatively large bit width, power consumption can be reduced while maintaining demodulation accuracy.

Here, in any one of the first, second, and third demodulators of the present invention, the bit width selector is configured to receive signals received by the plurality of demodulation circuits at each arrival time. It is preferable that the first demodulation circuit selects a relatively narrow bit width when the first demodulation circuit shares the demodulation of a reception signal having a relatively high reception intensity.

By doing so, the power consumption can be efficiently reduced with high demodulation accuracy.

Further, a reception intensity measuring correlator for detecting the reception intensity of the received signal for each arrival time is provided, and the bit width selector is the first demodulation circuit detected by the reception intensity measuring correlator. It is also a preferable aspect that the bit width is selected in accordance with the strength of the received signal for which demodulation is shared.

In this way, the bit width of the first demodulation circuit, which shares the demodulation of the reception signal having a relatively high reception intensity, can be appropriately selected.

Further, it is also preferable that the bit width selector adaptively selects the bit width according to the signal level of the pilot symbol. For example, the past and present bit width and signal strength information are accumulated, and the bit width of the optimum condition is selected based on the information.

In this way, the bit width can be selected by following the high-speed transmission path fluctuation.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

FIG. 1 is a block diagram showing the configuration of an embodiment of the first demodulator of the present invention.

A demodulator 10 shown in FIG. 1 demodulates a received signal obtained by receiving a radio wave transmitted from a base station. The demodulator 10 includes a first demodulation circuit 11 and a first demodulation circuit 11. Two
The demodulation circuit 12, the signal synthesizing circuit 13, and the reception intensity measuring correlator 14 are provided. First demodulation circuit 11
Divides the demodulation of a received signal having a relatively high received intensity. In addition, the second demodulation circuit 12 is responsible for demodulation of a reception signal having a relatively small reception intensity. First demodulation circuit 11
Is provided with a bit width selector that selects a relatively narrow bit width. First, the configuration of the first demodulation circuit 11 will be described with reference to FIG.

FIG. 2 is a diagram showing the structure of the first demodulation circuit shown in FIG.

The first demodulation circuit 11 shown in FIG.
Despreader 11_1, second despreader 11_2, bit width selector 11_3, filter circuit 11_4, derotation vector generation circuit 11_5, and complex multiplier 11_6.
And are provided.

The first despreader 11_1 inputs the received signal, and pilot symbol Ps is input from the input received signal.
ymbol (X, Y) is taken out and bit width selector 1
Output to 1_3.

The second despreader 11_2 inputs the received signal and outputs the data symbol Dsym from the input received signal.
bolx (i), y (i) is taken out and the complex multiplier 1
Output to 1_6.

The bit width selector 11_3 outputs the pilot symbol Psym output from the first despreader 11_1.
bol (X, Y) is the pilot symbol Psym
Filter circuit 1 by selecting the bit width of bol (X, Y)
Transfer to 1_4.

The filter circuit 11_4 has a pilot symbol P of the bit width selected by the bit width selector 11_3.
The symbol (X, Y) is input and the pilot symbol Psymbol (X, Y) is smoothed. Specifically, in order to remove noise and stabilize the pilot symbols Psymbol, weighted average filtering is performed on the pilot symbols Psymbol (Psymbol (i)) to add the pilot symbol Psymbol (Px). , Py)
To get This pilot symbol vector Psymbo
l (Px, Py) is the reverse rotation vector generation circuit 11_5
Be transmitted to.

The reverse rotation vector generation circuit 11_5 obtains the reverse rotation vector of the pilot symbol vector Psymbol (Px, Py) smoothed by the filter circuit 11_4. As a result, the reverse rotation vector generation circuit 1
1_5 to pilot symbol vector (Px / | Ps
symbol |, -Py / | Psymbol |) is output.

The complex multiplier 11_6 is the second despreader 1
Data symbol Dsymbolx (i) from 1_2,
y (i) is the pilot symbol vector (Px / | Psymbol from the reverse rotation vector generation circuit 11_5).
|, -Py / | Psymbol |). By doing so, the phase of the data symbol Dsymbolx (i), y (i) from the second despreader 11_2 is inversely rotated by the above rotation vector to obtain the data Dx.
(I), Dy (i) are obtained. Returning to FIG. 1 again, the explanation will be continued.

The reception strength measuring correlator 14 constituting the demodulator 10 shown in FIG. 1 detects the reception strength of the received signal at each arrival time. For example, arrival times T1 and T as received signals
Consider a case where the received signals having the reception strengths of the main path and the sub path (denoted as P ₁ and P ₂ respectively) in ₂ are input. Here, it is assumed that the reception intensity at the arrival time T1 is −30 dBm at the reception end (antenna end) not shown, and the reception intensity at the arrival time T2 is −56.2 dBm at the reception end. The reception intensity measuring correlator 14 measures the reception intensities of the main path and the sub-path at the arrival times T1 and T2, obtains their correlation, and outputs them to a CPU (not shown). The CPU controls the bit width selector 11_3 so that the data in the main path having the reception intensity of −30 dBm is calculated and demodulated in a 4-bit width, for example. As a result, the bit width selector 11_3 causes the first despreader 11_3 to
From the pilot symbol Psymbol (X,
The bit width of Y) is selected as the upper 4 bits (MSB) and transmitted to the filter circuit 11_4. Here, the filter circuit 11_4, the inverse rotation vector generation circuit 11_5, and the complex multiplier 11_6 have a 6-bit configuration, but when a reception signal having a relatively large reception intensity is input,
By setting the bit width of the pilot symbol Psymbol (X, Y) to 4 bits, the filter circuit 11_
4, reverse rotation vector generation circuit 11_5, complex multiplier 11
It is possible to suppress (stop) the switching operation of the elements of 2 bits (6 bits-4 bits) that form _6. Therefore, power consumption can be reduced. here,
Since the main path at the arrival time T1 has a relatively large reception strength of −30 dBm, it is demodulated with high accuracy without any error. In the received signal, -56.
The data in the sub-path with the reception strength of 2 dBm is
The second demodulation circuit 12 operates with a 6-bit width and demodulates. Therefore, even if the reception intensity is relatively small as -56.2 dBm, demodulation can be performed with high accuracy without any error.

In the demodulator 10 of this embodiment, the strength of the received signal is thus measured by the reception strength measuring correlator 14, and when the reception strength is comparatively large, the data is demodulated in a 4-bit width, and the comparatively. In the case of a small reception intensity, data is demodulated with a 6-bit width, so power consumption can be reduced while maintaining demodulation accuracy, as compared with a conventional demodulator that demodulates with a relatively large bit width. .

FIG. 3 is a diagram showing the configuration of a demodulation circuit of an embodiment of the second demodulator of the present invention.

The configuration of one embodiment of the second demodulator of the present invention is compared with the configuration of one embodiment of the first demodulator of the present invention shown in FIG. The difference is that it is replaced with the demodulation circuit 21 shown.

The demodulation circuit 21 shown in FIG. 3 includes a first despreader 21_1, a second despreader 21_2, a filter circuit 21_3, and an inverse rotation vector generation circuit 21_4.
And a complex multiplier 21_5.

The first despreader 21_1, the second despreader 21_2, the inverse rotation vector generation circuit 21_4, and the complex multiplier 21_5 are the same as the first despreader 11 described above.
-1, the second despreader 11_2, the inverse rotation vector generation circuit 11_5, and the complex multiplier 11_6 have the same configurations, and thus the description thereof will be omitted. The configuration of the filter circuit 21_3 will be described with reference to FIG.

FIG. 4 is a diagram showing the configuration of the filter circuit shown in FIG.

The filter circuit 21_3 shown in FIG. 4 includes a bit width selector 21_3a and a flip-flop 21_3.
b, 21_3c, 21_3d, 21_3e are provided. In addition, the filter circuit 21_3 includes a weighting circuit 2
1_3f, 21_3j and the bit width selector 21_3g,
21_3k, multipliers 21_3h and 21_3l, addition selectors 21_3i and 21_3m, and an adder 21_3n are provided.

The bit width selector 21_3a has the 6-bit width (X) transmitted from the first despreader 21_1.
[5] to X [0]) pilot symbols Psymbo
l (X, Y) is input. Here, in the case where a reception signal having a relatively high reception intensity (the main path having a relatively high reception intensity at the arrival time T1 described above) is input,
A bit width selection signal for selecting a 4-bit width as a bit width selection signal is input to the bit width selector 21_3a. The bit width selector 21_3a transmits the pilot symbols Psymbol (X, Y) for the upper 4 bits to the multiplier 21_3h via the flip-flops 21_3b, 21_3c. In addition, flip-flop 2
It is also transmitted to the multiplier 21_3l via 1_3d.

A 4-bit coefficient is input to the bit width selectors 21_3g and 21_3k as a bit width selection signal. The bit width selectors 21_3g and 21_3k use the weighting circuits 21_3f and 21_3j to generate the pilot symbol P.
Symbol (X, Y) selects the upper 4 bits of the 8-bit width data that is moving averaged (weighted average) in the time axis direction, and transmits it to the multipliers 21_3h, 21_3l.
In the multipliers 21_3h and 21_3l, the upper 4
Multiplication between bit widths is performed, and addition selector 21_3
i, 21_3m and added by the adder 21_3n, whereby the pilot symbol Psymbol (P
X [13: 0]) is output.

As described above, by providing the filter circuit 21_3 with the bit width selection function, for example, in the case of the main path having a relatively large reception strength of −30 dBm at the arrival time T1, the upper 4 bits are selected. It Therefore, the received signal having a high strength is filtered without suppressing the receiving performance.
Further, similarly, by limiting the coefficient precision uniformly or for each coefficient, the multipliers 21_3h and 21_3l at the subsequent stage are similarly limited.
And addition selectors 21_3i, 21_3m, and adder 21_3
The switching operation of the element forming n can be suppressed. In general, the effect is expected to be the product of the ratio of the limited bits of the input data and the coefficient. If both are half, the current consumption becomes 1/4.

FIG. 5 is a diagram showing the configuration of a demodulation circuit of an embodiment of the third demodulator of the present invention.

The configuration of one embodiment of the third demodulator of the present invention is compared with the configuration of one embodiment of the first demodulator of the present invention shown in FIG. The difference is that it is replaced with the demodulation circuit 31 shown.

The demodulation circuit 31 shown in FIG. 5 includes a first despreader 31_1, a second despreader 31_2, a filter circuit 31_3, and an inverse rotation vector generation circuit 31_4.
A bit width selector 31_5 and a complex multiplier 31_6 are provided. In the present embodiment, the bit width selector 31_
5 is the data symbol D from the second despreader 31_2
The bit widths of symbolx (i) and y (i) are selected and transmitted to the complex multiplier 31_6. This will be described below with reference to FIG.

FIG. 6 is a diagram showing a structure of a main part of the demodulation circuit shown in FIG.

In FIG. 6, an inverse rotation vector generation circuit 31_4 which constitutes the demodulation circuit 31 and a bit width selector 31_5.
And the complex multiplier 31_6 are shown. The inverse rotation vector generation circuit 31_4 includes a squarer 31_4a, a complex multiplier 31_4b, and a standardizer 31_4c.

The squarer 31_4a has a θ value on the transmission line.
Rotation of the pilot symbol vector Psy
mbol (Px, Py) is input and the data Px ² + Py ²
Is output to the standard device 31_4c.

The complex multiplier 31_4b multiplies the pilot symbol vector Psymbol (Py) of the pilot symbol vector Psymbol (Px, Py) by a complex number using an inverse function, and the standardizer 31
Output to _4c.

The standardizer 31_4c normalizes the pilot symbol data Px ² + Py ² from the squarer 31_4a based on the pilot symbol vector Psymbol (Px) and the data from the complex multiplier 31_4b (1 / SQRT (Px ² + Py ² )) and then the complex multiplier 31
Output to _6.

The bit width selector 31_5 has data symbols Dsymbolx (i) and Dsymboly (i).
Is entered. Further, when a reception signal having a relatively high reception intensity is input to the bit width selector 31_5,
Data representing bit precision (bit width selection signal) is input. Then, in the bit width selector 31_5, the upper 4
The bit width for the bits is selected, and as a result, the data symbols Dsymbolx (i), Dsy of the upper 4-bit width are selected.
mboly (i) is transmitted to the complex multiplier 31_6.
In the complex multiplier 31_6, this data symbol Dsym
bolx (i), Dsymboli (i), standard device 3
Data Dx by multiplying the data from 1_4c
(I), Dy (i) are obtained. As described above, when a reception signal having a relatively high reception strength is input, the bit width selector 31_5 selects the upper 4 bits of the bit width to suppress the switching operation of the elements forming the complex multiplier 31_6. May be.

FIG. 7 is a diagram showing a structure of a demodulation circuit different from the demodulation circuit shown in FIG.

The demodulation circuit shown in FIG. 7 is different from the demodulation circuit shown in FIG. 6 in that the bit width selector 31_5 is replaced with a bit width selector 41_5.
The difference is that _7 is added.

The bit width selector 31_5 constituting the demodulation circuit shown in FIG. 6 described above receives the pilot symbol or pilot channel in advance and measures its strength, and then outputs the data indicating the bit precision (bit width selection signal). ) Is entered. Normally, the measurement of reception strength is
Intensity measurement is generally performed at 1-frame time (about 10 ms) intervals. In such a case, it is difficult to follow a high-speed transmission line fluctuation due to a frequency of 200 Hz, for example. Therefore, here, the bit selection of data is performed by measuring the strength of the pilot symbol during reception as described below. By doing so, it is possible to cope with the high-speed transmission line fluctuation due to the above-mentioned frequency of 200 Hz.

The bit selector 41_7 is a squarer 31_4.
The pilot symbol data Px ² + Py ^{2 from a} is input, and the input pilot symbol data Px ² +
Select the bit width adaptively according to the size of Py ² ,
It is input to the bit width selector 41_5. Specifically, when a reception signal having a relatively high reception intensity is input, the bit selector 41_7 outputs a bit width selection signal for selecting the 4-bit width to the bit width selector 41_5.
In response to this, the bit width selector 41_5 receives the data symbols Dsymbolx (i), Dsy of the upper 4-bit width.
The mboly (i) is transmitted to the complex multiplier 31_6. By doing so, it is possible to cope with the above-described high-speed transmission line fluctuation, and it is possible to suppress the switching operation of the elements forming the complex multiplier 31_6.

In this embodiment, as shown in FIG. 2, a demodulator having a bit width selector for selecting the bit width of the pilot symbol and transmitting it to the inverse rotation vector generating circuit,
As described in the example of the demodulator including the bit width selector for selecting the bit width of the data symbol and transmitting it to the complex multiplier as shown in FIG. 5, a demodulator combining these, that is,
The demodulator includes a bit width selector that selects the bit width of the pilot symbol and transfers it to the inverse rotation vector generation circuit, and a bit width selector that selects the bit width of the data symbol and transfer it to the complex multiplier. May be. In this way, further power consumption is realized.

[0067]

As described above, according to the demodulator of the present invention, the power consumption can be reduced while maintaining the demodulation accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a first demodulator of the present invention.

FIG. 2 is a diagram showing a configuration of a first demodulation circuit shown in FIG.

FIG. 3 is a diagram showing a configuration of a demodulation circuit of an embodiment of a second demodulator of the present invention.

FIG. 4 is a diagram showing a configuration of a filter circuit shown in FIG.

FIG. 5 is a diagram showing a configuration of a demodulation circuit of an embodiment of a third demodulator of the present invention.

6 is a diagram showing a configuration of a main part of the demodulation circuit shown in FIG.

7 is a diagram showing a configuration of a demodulation circuit different from the demodulation circuit shown in FIG.

FIG. 8 is a block diagram showing a configuration of a conventional demodulator that demodulates a received signal received via two paths.

9 is a diagram showing the reception intensity of the received signal received by the demodulator shown in FIG. 8 with respect to the arrival time.

FIG. 10 is a block diagram showing a configuration of a conventional transmission path estimator.

[Explanation of symbols]

10 Demodulators 11, 12, 21, 31 Demodulator 13 Signal combiner 14 Reception strength measurement correlators 11_1, 11_2, 21_1, 21_2, 31_1, 3
1_2 Despreader 11_3, 21_3a, 21_3g, 21_3k, 31_
5, 41_5 bit width selector 11_4, 21_3, 31_3 filter circuit 11_5, 21_4, 31_4 inverse rotation vector generation circuit 11_6, 21_5, 31_4b, 31_6 complex multiplier 21_3b, 21_3c, 21_3d, 21_3e flip-flop 21_3f, 21_3j weighting circuit 21_3h, 21_3l multiplier 21_3i, 21_3m addition selector 21_3h, 21_3l multiplier 21_3n adder 31_4a squarer 31_4c standardizer

Claims (6)

[Claims] 1. A demodulator based on a code division multiple access system for demodulating a received signal, including a first despreader for extracting pilot symbols from the received signal, a second despreader for extracting data symbols from the received signal, and An inverse rotation vector generation circuit for inputting a pilot symbol from the first despreader to obtain an inverse rotation vector of the pilot symbol and a phase of the data symbol from the second despreader are divided by the inverse rotation vector. A plurality of demodulation circuits provided with a complex multiplier for inverse rotation only, wherein at least one demodulation circuit of the demodulation circuits converts the pilot symbols extracted by the first despreader Demodulation characterized by including a bit width selector for selecting a bit width and transmitting it to the inverse rotation vector generation circuit vessel. 2. A demodulator based on a code division multiple access system for demodulating a received signal, the first despreader extracting pilot symbols from the received signal, the second despreader extracting data symbols from the received signal, and A filter for inputting the pilot symbol from the first despreader to smooth the pilot symbol; an inverse rotation vector generation circuit for obtaining an inverse rotation vector of the pilot symbol smoothed by the filter; A plurality of demodulation circuits provided with a complex multiplier for inversely rotating the phase of the data symbol from the despreader by the inverse rotation vector, the first demodulation circuit being at least one of the demodulation circuits. The filter is configured by an arithmetic circuit including a multiplier that multiplies the transmitted pilot symbol by a coefficient, A smoothing pilot symbol extracted by the first despreader constituting the first demodulation circuit, wherein the filter selects the bit width of the coefficient to the multiplier. A demodulator having a bit width selector for transmitting. 3. A demodulator based on a code division multiple access system for demodulating a received signal, the first despreader extracting pilot symbols from the received signal, the second despreader extracting data symbols from the received signal, and An inverse rotation vector generation circuit for inputting a pilot symbol from the first despreader to obtain an inverse rotation vector of the pilot symbol and a phase of the data symbol from the second despreader are divided by the inverse rotation vector. A plurality of demodulation circuits each including a complex multiplier that reverses rotation only, wherein at least one first demodulation circuit of the demodulation circuits selects a bit width of the data symbol from the second despreader. And a bit width selector for transmitting to the complex multiplier. 4. The bit width selector causes the plurality of demodulation circuits to share the demodulation of the reception signal for each arrival time, and the first demodulation circuit demodulates the reception signal having a relatively large reception intensity. The demodulator according to any one of claims 1 to 3, wherein a relatively narrow bit width is selected in the case of sharing. 5. A first demodulation circuit, comprising: a reception strength measurement correlator for detecting a reception strength of a reception signal for each arrival time, wherein the bit width selector is detected by the reception strength measurement correlator. 5. The demodulator according to claim 4, wherein the bit width is selected according to the strength of the received signal that has been shared by the demodulators. 6. The demodulator according to claim 3, wherein the bit width selector adaptively selects a bit width according to a signal level of a pilot symbol.