JP2003249076A - Boosting potential generating circuit and control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a boosting potential generating circuit in which high speed operation can be performed in a semiconductor memory, while miniaturization also can be performed, even if external power source voltage is dropped in a semiconductor memory. <P>SOLUTION: In a boosting potential generating circuit provided with a capacitive MOS transistor and a transfer MOS transistor and used for a DRAM comprising memory cells, a boosting potential generating circuit of small area and large capacitance can be realized by making a gate insulation film of the capacitive MOS transistor a thinner film than a gate insulation film of a MOS transistor constituting a memory cell. In this case, it is preferable that thickness of a gate insulation film of the transfer MOS transistor is made the same as or thicker than that of the capacitive MOS transistor. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a boosted potential generation circuit used in a semiconductor memory, a control method thereof, and a manufacturing method.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, particularly in a semiconductor memory, the memory capacity increases and at the same time, the external power supply voltage supplied from the external power supply tends to decrease. Further, there is also a demand for higher speed for semiconductor memories. In order to meet such demands, a boosted potential generation circuit for boosting an external power supply voltage is provided inside the semiconductor memory, and the boosted potential generation circuit boosts the external power supply voltage to a voltage required for the semiconductor memory, and the internal memory cell It has realized speeding up.

On the other hand, as the memory capacity increases, the current consumption also increases. Therefore, it is also necessary to reduce the current consumption. Therefore, the boosted potential generating circuit is provided in a plurality of circuits in the semiconductor memory, and each boosted potential generating circuit is usually designed according to the potential required for the circuit used. In any case, it is preferable that the boosted potential generation circuit has a small current consumption, a small chip occupying area, and can generate various boosted potentials by a simple design change.

Conventionally, this type of boosted potential generating circuit is described in Japanese Patent Laid-Open No. 2000-112547 (hereinafter referred to as reference 1). The described boosted potential generating circuit is used together with the substrate potential generating circuit section, and the boosted potential generating circuit supplies the boosted voltage (V _PP ) to the word line and the peripheral circuit of the memory array, while the substrate potential generating circuit is used. The unit supplies a predetermined negative voltage (V _BB ) to the device substrate with respect to the substrate. In the case of the reference example 1, the boosted potential (V _PP ) generated by the boosted potential generation circuit is applied to the substrate potential generation circuit section, and a desired voltage is obtained from this boosted potential (V _PP ).

Further, the substrate potential generation circuit portion described in the reference 1 is composed of an oscillator such as a ring oscillator for generating a clock and a charge pump circuit. In this case, in the charge pump circuit, the clock from the oscillator and the inverted signal of the clock are applied to a plurality of capacitive elements and transistors to boost the voltage, and the voltage level is clamped so that the boosted potential does not become excessively high. is doing.

By adopting this structure, a transistor having a thin gate oxide film (hereinafter referred to as a gate insulating film) can be used as a transistor used in the charge pump circuit. However, the reference example 1
Describes only the configuration of the substrate potential generation circuit, and does not disclose the configuration of the boosted potential generation circuit that generates the boosted voltage (V _PP ) from the external voltage (V _DD ).

On the other hand, in Japanese Unexamined Patent Publication No. 11-297950 (hereinafter referred to as Cited Example 2), the first internal circuit which operates by receiving the boosted voltage (V _PP ) generated in the internal voltage generating section is thick. Disclosed is a semiconductor integrated circuit device in which a MOSFET having a thick gate insulating film is provided, and a second internal circuit which operates by receiving a step-down voltage (V _DL ) is constituted by a MOSFET having a thin gate insulating film. There is.
However, Cited Example 2 only discloses a circuit that operates by receiving a boosted voltage, and does not disclose the configuration of a circuit that generates a boosted voltage.

Further, Japanese Patent Application Laid-Open No. 6-283667 (hereinafter referred to as Cited Example 3) discloses a high voltage generating circuit used for generating a high voltage required for erasing and writing of a nonvolatile memory. Proposed. The high voltage generating circuit according to this proposal includes a plurality of MOS transistors and boosting capacitance elements connected to an interconnection node of these transistors, and has two or more thicknesses as insulating films of the plurality of boosting capacitance elements. Is used. According to the reference example 3, it is possible to configure a high voltage generation circuit which has a small pattern area and can operate at a low voltage.

However, even in the cited example 3, the DR
It does not disclose any requirement or specific configuration for the boosted potential generation circuit used for AM.

Now, a specific configuration and requirements for a boosted potential generating circuit generally used in a DRAM will be described.

Recently, as the density and size of memory cells in DRAM have increased, an external power supply voltage such as V _DD has been increased.
Has dropped from 5V to 2V, or about 1.8V. As described above, when the external power supply voltage is reduced to about 1.8V, the booster circuit portion of the internal voltage generation circuit has a boosted voltage (V _PP ) of 3.0V or more (specifically, 3.0V). ˜3.9 V) must be generated.

Conventionally, a boosted potential generating circuit used in this type of DRAM is composed of an oscillator and a charge pump circuit.
A doubled or tripled boosted potential generation circuit is used. Here, this kind of booster circuit section not only simply supplies the boosted potential to the word line, but also supplies the boosted potential or the overdrive potential to the shared MOS transistor, the bit line precharge MOS transistor, and the sense amplifier. It is necessary to take into consideration that it is also used for this purpose, and that it is also used as these control signals.

[0013]

However, in the structure of the booster circuit section using the conventional boosted potential generation circuit, various power supply potentials including the word line boosted potential (V _PP ) described above are sufficiently applied to the memory array. The situation has become impossible to supply to.

Further, in the semiconductor memory, especially in the DRAM, as described above, even if the external power supply voltage becomes low, the transfer gate of the memory cell and the sense amplifier related to the data exchange are operated at the boosted voltage so that the memory cell is operated. After ensuring a sufficient write level, a higher speed operation is performed.

In this relation, the MOS transistor forming the memory cell of the DRAM has a MOS having a relatively thick gate insulating film (for example, 6 nm) capable of withstanding the boosted voltage.
A MOS transistor having a thin gate insulating film (for example, 3.5 nm) is usually used as a MOS transistor which uses a transistor and constitutes a peripheral circuit portion which operates with an external power supply voltage.

More specifically, a DRAM provided with a word line, a bit line, a memory cell, and a sense amplifier.
In the above, if the sense amplifier is lowered along with the decrease of the external power supply voltage, the operation speed of the sense amplifier is slowed down. Further, in order to precharge the bit line and write the memory cell at high speed, it is necessary to boost the gate voltage for controlling the operation of these transistors. As a result, the thickness of the gate oxide film of the MOS transistor forming the memory cell cannot be reduced as described above.

On the other hand, the boosted potential generating circuit for generating various voltages for the DRAM is provided with a capacitance MOS transistor and a transfer MOS transistor. These MOS transistors are related to the boosted potential. It is usually constituted by a MOS transistor having a film thickness equal to the gate oxide film of the MOS transistor of the memory cell.

Further, as described above, in order to generate the internal power supply potential corresponding to various circuits, it is only necessary to use the boosted potential generation circuit that generates the boosted potential of the external power supply voltage which is doubled. DRA including word line boosted potential
It is impossible to generate various power supply potentials required for M.
For example, in addition to the word line boosted potential, a shared MOS transistor and a bit line precharge MOS are provided for this type of boosted potential generation circuit as the external power supply voltage decreases.
It tends to be required to also supply a potential that controls the overdrive of the transistor and / or the sense amplifier.

Considering the above points, it is considered that it is necessary to generate a high boosted potential of 3.0 to 3.9 V or higher in the boosted potential generation circuit in the future.

On the other hand, in order to obtain a high boosted potential as described above, it is assumed that a doubled boosted potential generating circuit is used as in the conventional case. First, the current efficiency of the boosted potential generation circuit is usually expressed by the ratio of the load current to the consumed current (that is, load current / consumed current). When trying to occur
The current efficiency drops sharply as the voltage generated increases. As a result, when a double boosted potential generating circuit is used to generate a high boosted potential, a decrease in current efficiency cannot be avoided and sufficient current supply capability cannot be obtained. Further, in order to obtain a sufficient current supply capability using the doubled boosted potential generating circuit, it is necessary to make the capacitance MOS transistor large, resulting in a large chip size.

Under such circumstances, it is considered to use a triple boosted potential generating circuit whose current efficiency is stably maintained even at a high boosted potential. However,
Since the generated voltage itself is high in the triple boosted potential generation circuit, a capacitance MOS transistor having a thick gate insulating film is used as a MOS transistor used in the boosted potential generation circuit so as to withstand a high voltage. There must be. This means that even in the triple boosted potential generating circuit, a MOS transistor having a thick gate insulating film must be used as a capacitive MOS transistor for obtaining a desired capacitance value.

However, the capacitance MOS transistor having a thick gate insulating film must have a large area in order to realize a desired capacitance value, resulting in a large chip size and generation of a boosted potential. There is a drawback that the circuit cannot be formed in a small area.

Further, as the external power supply voltage is lowered, the capacitance MOS of the boosted potential generating circuit is in accordance with the scaling rule.
It may be considered to use a MOS transistor having a thin gate insulating film used for a peripheral circuit as the transistor and the transfer MOS transistor.

However, when it is used in a boosted potential generation circuit using a thin film transfer MOS transistor, a high potential cannot be applied to the gate insulating film, so that a high boosted potential cannot be obtained and therefore a high speed operation is possible. However, there is a drawback that the semiconductor memory cannot meet the demand for higher speed.

It is an object of the present invention to provide a boosted potential generation circuit suitable for a semiconductor memory that can generate not only a doubled boosted potential but also various potentials according to a decrease in external power supply voltage. That is.

An object of the present invention is to provide a boosted potential generation circuit and a control method thereof that can obtain a large current supply capability without increasing the chip size.

Another object of the present invention is to provide a circuit structure which can be used as a boosted potential generating circuit, in which the ultimate level and the current supply capability can be increased while suppressing an increase in consumption current.

Still another object of the present invention is to provide a boosted potential generating circuit having a small area and high efficiency by optimizing the gate insulating film of a MOS transistor.

Another object of the present invention is to provide a control method for optimally driving the above boosted potential generating circuit.

[0030]

According to one aspect of the present invention, in a boosted potential generation circuit used in a semiconductor device including a memory cell formed of a MOS transistor, the boosted potential generation circuit is used as a capacitive element. A capacitive MOS transistor connected between the two nodes, and a transfer MOS transistor connected to the second node,
Further, a precharge MO connected to the second node
An S-transistor, wherein a potential difference between the first and second nodes of the capacitance MOS transistor is equal to the capacitance M.
In order not to exceed the breakdown voltage of the gate insulating film of the OS transistor, the capacitive MOS transistor and the transfer M
A boosted potential generating circuit is obtained in which the OS transistor and the gate of the precharge MOS transistor are controlled.

In this case, it is preferable that the capacitive MOS transistor has a gate insulating film which is thinner than the gate insulating film of the MOS transistor forming the memory cell or the transfer MOS transistor.

More specifically, a control signal is applied to the gates of the capacitance MOS transistor and the precharge MOS transistor as first and second clocks, and the gate of the transfer MOS transistor is provided with a third signal. A control signal is supplied as a clock, and a charge pump period of the capacitance MOS transistor defined by the first clock overlaps with a precharge period of a precharge MOS transistor defined by the second clock. The transfer period defined by the third clock is controlled to be shorter than the charge pump period.

According to this configuration, the precharge MO
An external power supply voltage is applied to the S transistor, and the transfer MOS transistor can generate a potential twice as high as the external power supply voltage.

According to another embodiment of the present invention, in a boosted potential generating circuit for boosting an external power supply voltage, a first capacitive MOS transistor connected between first and second nodes, a third capacitive MOS transistor, and a third capacitive MOS transistor. A second capacitive MOS transistor connected between the four nodes, a power supply terminal to which the external power supply voltage is applied and the first precharge MOS transistor connected between the second node, and the power supply terminal and the Four
A second precharge MOS transistor connected between the first node and the fourth node, and a transfer MOS transistor connected to the fourth node. A switch is provided between the second node and the third node. A boosted potential generating circuit having a configuration in which circuits are connected and capable of generating a potential three times as high as the external power supply voltage is obtained from the transfer MOS transistor.

In this case, the first and second capacitance MOSs
The transistor is a MOS transistor that constitutes the memory cell, or an MO transistor that has a gate insulating film thinner than the gate insulating film of the transfer MOS transistor.
The switch circuit includes an S-transistor, and the switch circuit includes a first MOS transistor connected between the second node and the third node, and second and third MOS transistors connected between the third node and ground. Of the MOS transistor.

More specifically, the first capacitance MOS transistor and the first precharge MOS transistor will be described.
A transistor, the switch circuit, the second precharge MOS transistor, and the transfer MO
The S-transistor has a configuration in which first, second, third, fourth, and fifth clocks are respectively supplied as control signals, and the transfer MOS transistor defined by the fifth clock is used. The charge transfer period substantially overlaps the charge pump period of the first capacitive MOS transistor defined by the first clock,
It is desirable to control so as not to substantially overlap with the precharge period defined by the second and fourth clocks.

According to another aspect of the present invention, the transfer MOS transistor is a P-channel MOS transistor, and the switch circuit is a P-channel first MOS transistor connected between second and third nodes. A boosted potential generating circuit having a transistor and N-channel second and third MOS transistors connected in series between the third node and the ground is obtained.

According to another aspect of the present invention, a capacitive MOS transistor having a gate insulating film having a predetermined film thickness, and a gate insulating film having a film thickness thicker than the gate insulating film of the capacitive MOS transistor are provided. A transfer MOS transistor, and a control method of a boosted potential generating circuit including the capacitance MOS transistor and a precharge MOS transistor coupled to the transfer MOS transistor, the first clock defining a charge pump period is set to the capacitance MOS transistor. Supplying a second clock to the precharge MOS transistor, the second clock determining a precharge period ending before the start of the charge pump period by the first clock, and the first clock Charge pump period Within the third defining a charge transfer period
To supply the clock to the transfer MOS transistor, thereby limiting the voltage applied to the capacitive MOS transistor during the boosting period.

[0039]

1 shows a circuit configuration including a boosted potential generating circuit 20 according to a first embodiment of the present invention, and FIG. 2 shows a waveform diagram for explaining its operation.

Boosted potential generation circuit 2 shown in FIGS. 1 and 2.
0 has a clock oscillator 21 on the input side and a capacitance circuit 22 and a level detection circuit 23 on the output side. The clock oscillator 21 is a voltage of 1.8V is supplied as the external power supply voltage _{V DD,} first from the external power supply voltage _{V DD,} second, and third clock IN1, IN2 and, IN
3 is given at the timing described later. Here, the first to third clocks IN1, IN2, and IN3 have a role as control signals, and thus may be called control signals.

The capacitance circuit 22 on the output side smooths the output voltage of the boosted potential generating circuit 20 to generate an internal boosted potential V of about 2.9V.
_PP is generated and supplied to the internal circuit of the semiconductor memory.
Further, the level detection circuit 23 detects the internal boosted potential V _PP , and when a boosted potential equal to or higher than a predetermined potential V _PP is obtained, the level detection circuit 23 feeds it back to the clock oscillator 21 to stop the operation of the clock oscillator 21 and set the predetermined potential. When the potential is less than or equal to, the clock oscillator 21 is operated.

The clock oscillator 21, the capacitance circuit 22,
The level detection circuit 23 is similarly used in other embodiments, but the description thereof will be omitted below for simplification of the description.

The boosted potential generating circuit 20 is an inverter 20.
A MOS transistor (capacitance MOS transistor) MC as a capacitance element that receives the first clock IN1 via steps 1 and 202 to boost the voltage, that is, perform a charge pump operation.
1, a transfer MOS transistor MT1 connected to the capacitance MOS transistor MC1, and a precharge transistor MP1 connected between both transistors MC1 and MT1. Further, as shown in the figure, the capacitive MOS transistor MC1 has a substrate side node (first node N1) and a gate side node (second node).
Node N2).

The illustrated transistors MC1, MT1,
Of MP1, the transistors MC1 and MP1 are composed of MOS transistors having a thin gate insulating film, while MT1 is an MO transistor having a thick gate insulating film.
It is composed of an S transistor. The thickness of the gate insulating film of the transfer MOS transistor MT1 is the same as the thickness of the gate insulating film of the MOS transistor that constitutes the memory cell of the DRAM (here, 1-transistor, 1-cell type DRAM). To do. In this example, the transfer MOS transistors MT1 and DR
The film thickness of the gate insulating film (thick gate insulating film) of the MOS transistor forming the AM memory cell is set to 6 nm.
On the other hand, the thin gate insulating film is a gate insulating film used in a MOS transistor that operates at a voltage equal to or lower than the power supply voltage V _DD supplied from the outside, and the thickness thereof is, for example,
It is 3.5 nm.

In order to clarify the difference in film thickness in the MOS transistor, in FIG.
The gate portions of C1 and MP1 are indicated by thin lines, while
The gate portion of the MOS transistor MT1 is indicated by a thick line. Therefore, the illustrated transfer MO
The S transistor MT1 is a capacitive MOS transistor MC
It can be seen from the drawing that the gate insulating film is thicker than 1 and the precharge MOS transistor MP1. In addition, all of the illustrated MOS transistors are N
It is a channel MOS transistor.

Next, in the illustrated example, the first clock IN1 passes through the inverters 201 and 202 and the capacitive MOS.
Although provided to the transistor MC1, the inverters 201 and 202 may be provided in the clock oscillator 21, and the number of the inverters 201 and 202 need not be limited to two. In the case of the illustrated example, the capacitance MOS is provided during the high level (V _DD ) period of the first clock IN1.
Since the transistor MC1 performs a charge pump operation,
The first clock IN1 is the capacitive MOS transistor MC1
Stipulates the charge pump period.

Further, the precharge MOS transistor M
The gate of P1, from the clock oscillator 21, is given a second clock IN2 is, the power supply voltage V _{D D} is given to the drain. In addition, the source is the capacity MO
It is connected to a common connection point of the S transistor MC1 and the transfer MOS transistor MT1. In this configuration, the precharge MOS transistor MP1 is turned on during the period when the second clock IN2 is at the high level (2V _DD ) and precharges the capacitive MOS transistor MC1. Therefore, the second clock IN2 defines the precharge period, and in the illustrated example, it can be seen that the precharge period and the charge pump period do not overlap.

On the other hand, the transfer MOS transistor M
The gate of T1 is supplied with the third clock IN3 from the clock oscillator 21, and during the high level (3V _DD ) period of the third clock IN3, the transfer MOS transistor MT1 is turned on and the charge is transferred. Therefore, the third clock IN3 defines the charge transfer period of the transfer MOS transistor MT1, and this charge transfer period does not overlap with the precharge period.

With further reference to FIG. 2, the boost shown in FIG.
The operation of the potential generation circuit 20 will be described more specifically. Well
However, as shown in FIG. 2, the clock oscillator 21 has 0 potential.
To V _DDVoltage amplitude V which changes to_DDThe first clock
Generates IN1 while 2V _DDTo V_DDStrange between
Voltage amplitude V_DDSecond clock IN2 of
V_DDTo 3V_DDVoltage amplitude 2V that changes to_DDThe first
3 clock IN3 is generated.

As is apparent from FIG. 2, when the second clock IN2 drops from the level of 2V _DD to V _{DD and} the precharge is completed, the second clock IN2 changes to V _DD.
The precharge MOS transistor MP
In the period in which 1 is in the off state, the first clock IN1 rises to the level of V _DD , and the capacitance MOS transistor MC1 is charge pumped. Also, the first clock I
During the period when N1 is at V _DD level, the third clock I
N3 rises to a potential of 3V _DD . As a result, the transfer MOS transistor MT1 is turned on, and the charge of the capacitance MOS transistor MC1 is transferred to the transfer M.
It is supplied to the internal circuit of the semiconductor memory through the OS transistor MT1. In this way, the third clock IN3
Are controlled so that the first clock IN1 rises accurately within the period in which the first clock IN1 is at the V _DD level. In other words, the pulse width of the first clock IN1 is wider than the pulse width of the third clock IN3 by each margin width (for example, 0.5 ns) at the leading edge and the trailing edge. Similarly, the low level period of the second clock IN2 is controlled to be wider than the high level period of the first clock IN1.

The clock oscillator 21 that generates the first to third clocks IN1 to IN3 having the above-described voltage amplitude and the first to third clocks IN1 to IN3 in the above-described timing relationship is usually Since it can be easily realized by using the circuit technology of, the detailed description is omitted here.

FIG. 2 shows the waveforms of the potentials of the nodes N1 and N2 shown in FIG. 1 as the first to third clocks IN1 to I.
It is shown together with the waveform of N3. As it is clear from FIG. 2, prior to generation of the first clock IN1, the level of the second clock IN2 changes from _{2V D D} level to _{V DD} level. This means that before the first clock IN1 rises, the precharge MOS transistor MP
The precharge by 1 is completed, and the precharge M
This means that the OS transistor MP1 is in the off state.

In this state, when the first clock IN1 is applied to the capacitance MOS transistor MC1 via the inverters 201 and 202, the capacitance MOS transistor MC1
The potentials of the first node potential N1 and the second node N2 of 1 change as shown in FIG. The capacitive MOS transistor MC1 keeps the potential of the second node N2 constant at the first node N2.
It should be higher than 1. That is, the first node potential N1 of the capacitance MOS transistor MC1 changes between the ground potential 0 and the V _DD potential in synchronization with the first clock IN1 in the same manner as the first clock IN1, while the capacitance MOS
Since the second node potential N2 of the transistor MC1 is precharged to the potential of V _DD by the precharge MOS transistor MP1, as shown in FIG.
Varying between _{V DD} potential and _{2V DD} potential in synchronization with a clock IN1.

Here, referring to the waveform of the potential of the second node N2 and the waveform of the potential of the first node N1, in the configuration of the boosted potential generating circuit 20 shown in FIG. 1, the second node N2 is used.
The potential difference between the potential and the potential of the first node N1 is always
It is maintained at V _DD , and this potential difference is kept constant without exceeding V _DD . Therefore, the capacitive MOS transistor MC1 is an MO that constitutes a memory cell.
A desired capacitance value can be obtained by using a MOS transistor having a gate insulating film that is thinner than the gate insulating film of an S transistor or a transfer MOS transistor. This means that the capacitance MOS transistor MC1 having a small area and a desired capacitance can be configured.

With further reference to FIG. 2, the transfer MOS transistor MT1 connected to the gate side node N2 of the capacitive MOS transistor MC1 changes between the potentials of V _DD (low level) and 3 V _DD (high level). The third clock IN3 is provided. In the illustrated example, the transfer MOS transistor MT is transferred within a period in which the gate-side node potential N2 has a potential of 2V _DD.
The third clock IN3 supplied to the first gate is at high level. As a result, the third clock IN
During the high level period of 3, the transfer MOS transistor MT1 is turned on, and the charge from the capacitive MOS transistor MC1 is transferred to the capacitive circuit 22. The capacitance circuit 22 smoothes the transferred charges to obtain the boosted voltage V
Generate _PP . In the illustrated example, the high level period of the first clock IN1 described above defines the boosting period. On the other hand, the high level period of the second clock IN2 defines the precharge period of the precharge MOS transistor MP1, and the precharge period is adjusted so as not to overlap with the boosting period. In other words, in the case of this example, it is understood that the boosting is performed during the period in which it is not precharged. Also, the third clock IN
The high level period of 3 defines the charge transfer period of the transfer MOS transistor MT1 and is adjusted to be shorter than the boosting period.

According to this structure, the transfer M
The OS transistor MT1 is a precharge MOS transistor.
The recharge by Dista MP1 is completed, and
After the voltage is boosted, the charge is transferred.
It can be done reliably. In addition, transfer MOS transistor
V for the transistor MT1_DDHigher potential 3V_DDTo
A third clock IN3 having a third clock
It is turned on by the lock IN3. Illustrated
As in the example, the transfer MOS transistor MT1 and
And a MOS transistor having a thick gate insulating film
2V _DDClock having a voltage swing of
The transfer MOS transistor can be driven by IN3.
This allows for rapid charge transfer and sufficient current supply.
You can get wages.

As is clear from the above description, by using the clocks IN1 to IN3 to control the illustrated transistors, the capacitive MOS transistor MC1 is controlled.
For, a MOS transistor having a thin gate insulating film can be used.

This means that a MOS transistor having a thin gate insulating film and a low breakdown voltage can be used as a capacitive MOS transistor. A capacitive MOS transistor having a thin gate insulating film can realize a large capacity in a small area and is effective in reducing the chip size. For example, by using a MOS transistor having a gate insulating film with a thickness of 3.5 nm as a capacitive MOS transistor, a thickness of 6.0 used for a MOS transistor forming a memory cell or a transfer MOS transistor.
The area required for the boosted potential generating circuit can be reduced by about 30% as compared with the case where a MOS transistor having a gate insulating film of nm is used as a capacitive MOS transistor.

When the above boosted potential generating circuit is used in a DRAM, if the external power supply voltage V _DD is 1.8 V, the desired boosted potential is 2.9 V, and the threshold value of the transfer MOS transistor is 0.5 V, the boosted voltage is boosted. Node potential N
2 becomes 2 × 1.8V (3.6V), and at this time, the gate level of the transfer MOS transistor MT1 (I
N3) becomes 3 × 1.8V (5.4V). At this time,
The potential between the gate and the source of the transfer MOS transistor MT1 is a potential difference equal to or more than the threshold value, and the charge from the node N2 can be transferred quickly.

In this way, a margin is given to the rising / falling edge of each clock signal, and the capacitance MOS transistor M
By controlling the potential difference applied to C1 to be within V _DD, it is possible to reduce the thickness of the gate insulating film in the capacitive MOS transistor MC1.

In the illustrated embodiment, the gate insulating film of the transfer MOS transistor MT1 has a large film thickness, but as shown in FIGS. 1 and 2, the high level of the clock IN3 is set to 2V _DD. Thus, the gate thickness can be reduced.

Also in this case, the gate-source potential of the transfer MOS transistor MT1 is 2 × V _DD −
V _PP = 2 × 1.8−2.9 = 0.7 V, the transfer MOS transistor MT1 is turned on, and charges can be transferred.

As described above, by thinning all the MOS transistors, a boosted potential generating circuit having a smaller area can be obtained. On the contrary, the precharge MOS transistor MP
The gate film thickness of 1 may be increased. However, when the boosted potential is supplied to the internal circuit, a large voltage fluctuation occurs. Therefore, it is more preferable that the transfer MOS transistor MT1 has a thick gate film thickness including other embodiments described later.

Referring to FIG. 3, the boosted potential generating circuit 20a according to the second embodiment of the present invention is a transfer MO.
The S-transistor MT1 is the same as the boosted potential generation circuit 20 shown in FIG. 1 except that a P-channel MOS transistor having a thick gate insulating film is used.
Further, because the P-channel MOS transistor is used as the transfer MOS transistor MT1,
The third clock IN3 given to the gate of the P-channel MOS transistor is, as shown in FIG.
Has a polarity different from that of the third clock IN3. That is, the third clock IN3 shown in FIG.
_It has a voltage amplitude that varies between _DD and zero potential.
In the configuration shown in FIG. 3, by the third clock IN3,
As in the case of FIG. 1, it is possible to generate the boosted voltage V _PP that is double the external power supply voltage V _DD .

Further, the transfer MOS transistor M
When thinning T1, as shown by the dotted line in FIG.
If the third clock IN3 that sets DD to the low level is used, all the MOS transistors can be thinned. However, since the boosted potential supplied to the internal circuit is used in the internal circuit, the boosted potential may be significantly reduced. Also, in order to supply a high control voltage and supply the internal circuit at high speed, Transfer MOS transistor MT1
The gate film thickness is more preferably a thick film.

A boosted potential generating circuit according to the third embodiment of the present invention will be described with reference to FIG.

Boosted potential generating circuit 20b shown in FIG.
Has a configuration in which a level conversion circuit is connected to the configuration shown in FIG. 1, and has a potential V _{PP that is} double the external power supply voltage V _DD.
To occur. The boosted potential generation circuit 20b includes a capacitive MOS transistor MC1 (hereinafter referred to as a first capacitive MOS transistor), a precharge MOS transistor MP1 (hereinafter referred to as a first precharge MOS transistor), and , Transfer transistor M
In addition to having T1, it has a level conversion circuit composed of first to sixth MOS transistors M1 to M6 and a second capacitance MOS transistor MC2. The first capacitance MOS transistor MC1 has an inverter 20
The first clock IN1 is applied via 1, 202 to the precharge MOS transistor MP1.
The second clock IN2 is provided. Further, the gate of the transfer transistor MT1 is supplied with the third clock IN3 via the level conversion circuit, and the source of the second precharge MOS transistor MP2 is connected. The fourth clock IN4 is supplied to the gate of the second precharge MOS transistor MP2.

Furthermore, the first to sixth MOS transistors M1 to M6 forming the level conversion circuit are connected to the external power supply voltage V.
_{Since the} boosted voltage V _PP higher than that of _DD is applied, it is configured by a transistor having a thick gate insulating film.

More specifically, the first, third, and fourth MOS transistors M1, M3, and M4 forming the illustrated level conversion circuit are P-channel MOS.
The remaining MOS transistor M2, which is a transistor,
M5 and M6 are N-channel MOS transistors. A boosted potential generating node N3 to the same potential is applied to the output terminal of the circuit, between the ground potential V _SS, with the first and second MOS transistors M1, M2 are connected in series, fourth and 6 MOS transistors M4,
M6 is also connected in series. Furthermore, the first and second M
The common drain connection points of the OS transistors M1 and M2 are connected to the substrate side of the second capacitive MOS transistor MC2. On the other hand, the common connection point between the fourth and sixth MOS transistors M4 and M6 is the first and second MOS transistors.
It is connected to the gates of the transistors M1 and M2, and the third M
It is also connected to the gate of the OS transistor M3.

Third and fifth MOS transistors M3 and M5 are connected in series between the node N3 and the third clock IN3 terminal, and their common connection point is connected to the gate of the fourth MOS transistor M4. ing. The source of the fifth MOS transistor M5 is connected to the gate of the sixth MOS transistor M6, and the source of the fifth MOS transistor M5 is supplied with the third clock IN3. Further, a fifth MOS transistor M5
_Has its gate connected to V _DD .

The gate side of the second capacitance MOS transistor MC2 is connected to the transfer MOS transistor MT1 via the node N4, and the node N4 is connected to the node N4.
It is connected to the source of the second precharge MOS transistor MP2.

As shown in the figure, the external power supply voltage V _DD is supplied to the drains of the first and second precharge MOS transistors MP1 and MP2, and the gate of the fifth MOS transistor M5, while the source of the MOS transistors M2 and M6 of the second and sixth, are connected to the ground potential _{V SS.}

The operation of boosted potential generating circuit 20b shown in FIG. 5 will be described with reference to the waveform chart shown in FIG. First, as shown in FIG. 5, the first clock IN1
Has a voltage amplitude V _DD and changes between 0 level (low level) and V _DD level (high level) as in FIG. 2, while the second clock IN2 is 2 V _DD level (high level). ) And V _DD level (low level). Here, the high level period of the first clock IN1 is set to be shorter than the low level period of the second clock IN2. Furthermore, the third clock IN
3 changes between 0 level (low level) and V _DD level (high level), and the high level period is adjusted to be shorter than the high level period of the first clock IN1. Further, the fourth clock IN4 has a polarity opposite to that of the first clock IN1 and changes between 2V _DD level (high level) and V _DD (low level). The above-mentioned first to fourth clocks IN1 to IN4 are generated by the clock oscillator 21 as in FIG.

The second clock IN2 is at a high level (2V
_DD ) and the fourth clock IN4 is also at high level (2
The first and second precharge MOS transistors MP1 and MP2 are turned on during the period of V _DD ). At this time, the potentials of the nodes N1 and N2 of the first capacitive MOS transistor MC1 are 0 as shown in FIG.
And V _DD level. Further, the node N4 takes the level of V _DD . This is because the third clock IN3 has a low level, and in this state, the fifth, fourth, and second MOS transistors M5, M4, and M2 are turned on, and the second capacitance MOS transistor MC2. Node N5
Is at a low level (Vss).

Then, the second clock IN2 goes low.
And the first clock IN1 goes high.
When the fourth clock IN4 goes low,
And the second precharge MOS transistors MP1 and M
P2 turns off. At this time, the potential of the node N3 is approximately V
_PPIt is kept at the potential of. In this state, the third clock
When the IN3 becomes high level, the sixth and first MOS
Transistors M6 and M1 are turned on, resulting in
Boosted potential V through node N3_PPIs the second capacitive MOS
It is applied to node N5 of transistor MC2. others
Therefore, the gate side voltage of the second capacitance MOS transistor MC2 is
The position N4 is V as shown in FIG._DD+ V _PPRise to
To do. Potential V_PPIs the potential V_DDHigher than that,
As shown, transfer MO connected to node N4
The gate potential of the S transistor MT1 is 2V_DDOver
Eh, 3V_DDReach a level close to. Therefore, FIG.
Similarly to the transfer MOS transistor MT1,
The charge can be transferred quickly, and
It is possible to generate a substantially constant boosted potential VPP.

In this embodiment as well, the transfer M
It is also possible to thin the OS transistor MT1. However, as described with reference to FIG. 4, the boosted potential supplied to the internal circuit may be significantly reduced by being used in the internal circuit, and a high control voltage may be applied. In order to supply the internal circuit at high speed, it is more preferable that the transfer MOS transistor MT1 has a thick gate film.

Referring to FIG. 7, the boosted potential generating circuit 20c according to the fourth embodiment of the present invention is a transfer MO.
It differs from boosted potential generating circuit 20b shown in FIG. 5 in that a P-channel MOS transistor is used as S transistor MT1. In this regard, the circuit of FIG. 7 does not include the second precharge MOS transistor MC2 shown in FIG. In the boosted potential generating circuit 20c shown in FIG. 7, the potential of the node N4, which is the gate potential of the transfer MOS transistor MT1, is shown in FIG.
As shown in FIG. 6, the description is omitted because it is similar to FIGS. 5 and 6 except that it changes between the ground potential 0 level (V _SS ) and the V _PP level.

As is apparent from the potential at node N3 in FIG. 8, boosted potential V _PP close to the potential of 2V _DD can be generated also by the configuration shown in FIG.

Also in the boosted potential generating circuit 20c shown in FIG. 7, the film thickness of the gate insulating film of the transfer MOS transistor MT1 can be reduced, but the gate film thickness of the transfer MOS transistor MT1 is more thick. The preference is as described above.

With reference to FIG. 9, a boosted potential generating circuit 20d according to the fifth embodiment of the present invention includes a plurality of capacitance MOSs.
A configuration including transistors (here, MC1 and MC2) is provided, and by this, the tripled boosted voltage V _PP can be generated. In the illustrated example, the capacitance MOS transistor MC1 (referred to as a first capacitance MOS transistor) and the capacitance MOS transistor MC2 (referred to as a second capacitance MOS transistor) are both MOS transistors forming a memory cell or a transfer transistor. MO
It is composed of a MOS transistor having a gate oxide film that is thinner than the gate oxide film of the S transistor.

In FIG. 9, the substrate-side and gate-side nodes of the first capacitive MOS transistor MC1 are first and second nodes N1 and N2, respectively, and the first node N1 is connected to the first node N1 via an inverter. Clock IN1 is applied to the second node N2, while the second node N2 receives the first precharge M
It is connected to the OS transistor MP1. The first precharge MOS transistor MP1 has a thin gate insulating film, the drain of which is supplied with the external power supply voltage V _DD , and the gate of which is supplied with the second clock IN2.

On the other hand, the second node N2 and the ground potential (V
_SS ) between the first and third MOS transistors M1 to M1 having a thick gate insulating film as a switch circuit.
M3 is connected in series. Of these, the first MOS
The transistor M1 is a P-channel MOS transistor, and the second and third MOS transistors M2 and M3 are N-channel MOS transistors. As shown in the figure, the first and third MOS transistors M1,
The gate of M3, is given a third clock IN3, to the gate of the second MOS transistors M2, the external power supply voltage _{V D D} is supplied.

Second capacitor M having a thin gate insulating film
The OS transistor MC2 includes a substrate side node (third node) N3 and a gate side node (fourth node) N4, and the third node N3 is a common connection of the first and second MOS transistors M1 and M2. Connected to a point. on the other hand,
The fourth node N4 is a transfer MOS transistor M
It is connected to T1 and is also connected to the source of the second precharge MOS transistor MP2. these,
The second precharge MOS transistor MP2 and the transfer MOS transistor MT1 are composed of MOS transistors having a thick gate insulating film.

Second precharge MOS transistor M
An external power supply voltage V _DD is supplied to the drain of P2, a fourth clock IN4 is applied to its gate, and a fifth clock IN5 is applied to the gate of the transfer MOS transistor MT1. ing.

FIG. 10 shows each of the above clocks IN1 to IN1.
The waveform of IN5 and the potential changes at the nodes N1 to N4 are shown. First, when the clocks other than the fifth clock IN5 are not applied, that is, when the charges are at the low level and the charges are not transferred, the first to fourth nodes N1 and N1.
The potentials of 2, N3, and N4 are V _DD , 2V _DD , and 2 respectively.
It is maintained at V _DD and 3V _DD .

When the first clock IN1 is applied through the inverter, the potential of the first node N1 changes from the waveforms of the first and second nodes N1 and N2 shown in FIG. , V _DD level changes to 0 level,
On the other hand, the potential of the second node N2 changes from 2V _DD level to V _DD level. In this state, since the second clock IN2 and the fourth clock IN4 are at low level, the first and second precharge MOS transistors MP1 and MP2 are kept off.

Subsequently, the third clock IN3 becomes high level, and the second and fourth clocks IN2 and IN4.
Goes high, the first and second precharge M
The OS transistors MP1 and MP2 are turned on, and as a result, the first and second capacitance MOS transistors MC
1 and MC2 are in a state of being precharged by the external power supply voltage V _DD .

That is, the third clock IN3 goes high, and the second and third MOS transistors M2 and M3.
Is turned on by the third clock IN3,
, The potentials of the third and fourth nodes N3 and N4 drop to 0 and V _DD levels, respectively. After that, the ON state is continued until the second clock IN2 becomes low level, and the second and fourth nodes N2, N
4 is held at V _DD level.

Next, as shown in FIG. 10, the second, third,
When the fourth clocks IN2, IN3, and IN4 become low level, the first and second precharge MOS transistors MP1 and MP2 are turned off, and the first MOS transistor M1 is turned on, so that the third MO
The S transistor M3 is turned off.

When the third clock IN3 goes low, the potential of the third node N3 rises from the ground potential 0 by charging the third node N3 with the potential of the second node N2. As a result, the potential of the fourth node N4 also rises from V _DD , and the charge pump is started.

Further, when the first clock IN1 goes low, the potentials of the first node N1 and the second node N2 are boosted to V _DD and 2V _DD , respectively, and the charge pump state is set. At this time, since the first MOS transistor M1 is in the ON state, the potentials of the third and fourth nodes N3 and N4 further rise in accordance with the rise of the potential of the node N2, and the potentials of 2V _DD , It becomes 3V _DD . Therefore, in the illustrated example, the first clock I
It can be seen that the low level period of N1 defines the charge pump period.

Next, as shown in FIG. 10, when the first clock IN1 goes low and the potential of the fourth node N4 reaches 3V _DD , the fifth clock IN5 goes high. As described above, the transfer MOS transistor MT1 is turned on while the first clock IN1 is at the low level, the potential of the transfer MOS transistor MT1 becomes 3V _DD, and the charge transfer state is set.

After the charge transfer is completed, the fifth clock IN5
Goes low, and then the first clock IN1
Become high level. At this point, the second and fourth black
First and second prechas operating on the clock IN2, IN4
The MOS transistors MP1 and MP2 are in the off state.
On the other hand, on the other hand, the third MO operating at the third clock IN3
The S transistor M3 is in the on state. In this state,
When the first clock IN1 goes high, the first and
The potentials of the second nodes N1 and N2 are V _DDFrom
Ground potential, 2V_DDTo V_DDDeclines to. This conclusion
As a result, the potentials of the third and fourth nodes N3 and N4 are also
2V_DDTo V_DDTo 3V_DDTo 2V_DDStrange
Turn into.

During the high level period of the first clock IN1, the second, third and fourth clocks IN2, IN
When 3 and IN4 become high level, 3rd and 4th
The potential at the node N3, N4, and to zero potential from _{V DD} respectively, and further lowered from _{2V DD} to _{V DD,} the first and second capacitive MOS transistors MC1, MC2 is in a state to be precharged. After that, the same operation is repeated.

In the example shown in FIG. 10, the fifth clock IN5 is at high level (3V _DD ) during the low level period of the first clock IN1. This means that the charge transfer period of the transfer MOS transistor MT1 and the charge pump period defined by the low level period of the first clock IN1 overlap, while the high level period of the first clock IN1 and the second period It can be seen that the precharge period defined by the high level period of the fourth clocks IN2 and IN4 and the charge transfer period are controlled so as not to substantially overlap.

Although the first clock IN1 and the fifth clock IN5 are controlled so as not to overlap in FIG. 10, the second capacitance MOS transistor MC2 is controlled.
When a MOS transistor having a thick gate oxide film is used as, the first clock IN1 and the fifth clock IN5 may overlap to some extent.

Referring to FIG. 11, a boosted potential generating circuit 20e according to the sixth embodiment of the present invention is different from that of the first to third MOS transistors M1, M2, M3 and its gate connection circuit in FIG. The boosted potential generating circuit 20d shown in FIG. 9 operates in the same waveform diagram as FIG. That is, in the circuit 20e shown in FIG. 11, the first to third MOS transistors M1, M2, M3 are configured by MOS transistors having a thin gate insulating film,
The gates of the first and second MOS transistors M1 and M2 are commonly connected to an external power supply that supplies the external power supply voltage VDD, and the third clock IN3 is the third MO.
This is different from FIG. 9 in that it is provided only to the gate of the S transistor M3. In this configuration, the source potential of the first MOS transistor M1, which is constituted by a P-channel MOS is, than the gate potential V _{D D,} when it becomes higher than the threshold voltage of the transistor, the first MOS transistor M1 is turned on The circuit is the same as that of FIG. 9 except that the state is changed. Illustrated boosted potential generation circuit 2
0e can also generate triple boosted potential V _PP .

A boosted potential generating circuit 20f according to yet another embodiment (seventh embodiment) of the present invention will be described with reference to FIGS. The boosted potential generation circuit 20f shown in FIG. 12 is a circuit that generates a tripled boosted potential V _PP, as in FIG. More specifically, the boosted potential generating circuit 20f shown in FIG. 12 has a gate insulating film thinner than the gate insulating film of a MOS transistor or a transfer MOS transistor that constitutes a memory cell, as in FIG. First to third MOS transistors M1, M2, M3
The gates of the OS transistors M1 and M2 are external power supply voltage V
The third clock IN3 is supplied to the third MOS transistor M3 while being commonly connected to the external power supply that supplies _DD .

Further, the transfer MOS transistor M
As T1, a P-channel MOS transistor having a thick gate insulating film is used, which is a difference from the boosted potential generating circuit 20e described above. The first MOS transistor M1 is composed of a P-channel MOS transistor, and includes the first and second capacitance MOS transistors MC.
11 is similar to FIG. 11 in that the first, MC2, and the first and second precharge MOS transistors MP1, MP2 are provided.

The operation of boosted potential generating circuit 20f shown in FIG. 12 will be described with reference to FIG. First, the gate of the transfer MOS transistor MT1 is supplied with a clock having a polarity inverted from that of the fifth clock IN5 shown in FIG. 10 as the fifth clock IN5. Further, in this example, as the fifth clock IN5, a clock in which the potential of V _DD is low level and the potential of 3 V _DD is high level is used, and the fifth clock IN5 is the same as the first clock IN1. It has a wider high level period than the high level period. In the transfer MOS transistor MT1, the fifth clock IN
Since the charges are transferred during the low level period of 5, the charge transfer time in the transfer MOS transistor MT1 does not overlap with the high level period of the first clock IN1.

The second to fourth clocks IN2, IN3, IN4 shown in FIG. 13 are the same as the second to fourth clocks shown in FIG. 10, respectively.

In FIGS. 12 and 13, first, the fifth clock
Lock IN5 is V_DDTo 3V_DDChanges to
The spur MOS transistor MT1 is kept off.
It In this state, the first clock IN1 changes from 0 level
V_DDWhen the level changes, as shown in FIG.
The potentials of the terminals N1 and N2 are V_DDFrom 0 to 2V
_DDTo V_DDTo each.

In the illustrated boosted potential generation circuit 20f, first, the first clock IN1 goes high.
As a result, the potential of the first and second nodes N1 and N2 decreases respectively from _{V DD} respectively from 0,2V _DD to _{V DD.} Then, when the second, third, and fourth clocks N2, N3, and N4 become high level,
The precharge MOS transistors MP1 and MP2 and the third MOS transistor M3 are turned on,
The third node N3 drops to 0 potential, and the second and fourth nodes N2 and N4 are precharged to the _VDD level.

Next, when the second clock IN2 to the fourth clock IN4 become low level, the precharge MOS
The transistors MP1, MP2, and the third MOS transistor M3 are turned off, and the second, third, and fourth nodes N2, N3, and N4 have V _DD , 0, and V _DD levels, respectively. Hold.

Then, when the first clock IN1 goes low, the potentials at the nodes N1 and N2 are set to V
_DD and 2V _DD . The potential of the node N2 is 2V _DD
Then, the first MOS transistor M1 is turned on, and the potentials of the nodes N3 and N4 rise to 2V _DD and 3V _DD , respectively. In this state, the fifth clock I
When N5 drops to the low level (V _DD ), the transfer MOS transistor MT1 is turned on and the charge is transferred.

As a result, the boosted potential generating circuit 20f is set to 3
It is possible to output the doubled potential V _PP .

As shown in FIGS. 9, 11, and 12, a plurality of capacitance MOS transistors MC1 and MC2 are provided via a transistor as a switch element for performing on / off operation.
With the configuration in which the capacitors are connected in series, the added voltages are obtained by charge pumping the respective capacitors, and the boosted potential V _{PP of} tripled voltage can be generated.

With reference to FIG. 14, the boosted potential generating circuit 20g according to the eighth embodiment of the present invention has a positive potential V _DD.
In addition to the ground potential V _SS , a substrate voltage (V _BB ) of about −0.7 V is also used, which is a difference from the above-described embodiment.

More specifically, the boosted potential generating circuit 2
0g includes first and second MOS transistors M1 and M2 that operate by receiving first and second clocks IN1 and IN2 at their gates.
1 and M2 are connected in series between the external power supply voltage V _DD terminal and the ground potential V _SS, and both MOS transistors M1 and M2 are connected.
A node N1 which is a common connection point of 2 is connected to the substrate side of the capacitive MOS transistor MC1. Also, the node N
1 and the substrate potential (V _BB ) between the third and fourth M
The OS transistors M3 and M4 are connected in series.
Here, in the gate of the third MOS transistor M3,
The external power supply voltage VDD is supplied, while the gate of the fourth MOS transistor M4 is supplied with the third clock IN3. Each of the first to fourth MOS transistors M1 to M4 has a thin gate insulating film. Only the first MOS transistor M1 is a P channel, and the other MOS transistors M2 to M4 are N channel MOS transistors.

The gate side of the capacitance MOS transistor MC1 is connected to the node N2, and the node N2 is connected to the precharge MOS transistor MP and the transfer MOS transistor MT. Both MOS transistors MP and MT are N-channel MOS transistors, and MT has a thick gate insulating film. Fourth and fifth clocks IN4 and IN5 are applied to the gates of the MOS transistors MP and MT, respectively.

Referring also to FIG. 15, the first clock IN1 changes between the V _DD level and the V _SS level, and the second clock IN2 changes between the V _DD level and the V _BB level. . Further, the third clock IN3 is V
_It has an amplitude that varies between the _DD level and the _VBB level.

As is apparent from FIG. 15, the second clock IN2 and the third clock IN3 are at the high level during the precharge period in which the first clock IN1 is at the high level, and the first node N1 is at the V level. _SS level and V _BB
Lower to level.

[0113] Furthermore, the fourth clock IN4, as shown in FIG. 15, vary between _{2V DD} level and _{V D D} level, the timing is the same timing as the first clock IN1. Further, the fifth clock IN5, which becomes high level during the low level period of the first clock IN1, that is, during the charge pump period, changes between V _DD and 3V _DD .

[0114] In FIG. 14, when the potential of the second clock IN2 is at a high level, the first node N1 is at the _{V SS} level, the second clock IN2 goes low, the second MOS transistor M2 Is turned off, and the third clock IN3 given to the fourth MOS transistor M4 becomes high level (V _DD ),
The fourth MOS transistor M4 is turned on together with the third MOS transistor M3, and as a result, the potential of the node N1 is lowered to V _BB as shown in FIG. This means that the potential of the node N1 once lowered to V _SS (ground potential) is further lowered to V _BB and precharge is performed.

Then, when the first, third, and fourth clocks IN1, IN3, and IN4 fall to the low level,
The precharge period is completed, and the third and fourth MOS transistors M3 and M4 and the precharge MOS transistor MP are turned off. At this time, the first MOS
The transistor M1 is turned on, the potential of the first node N1 starts to rise toward the V _DD level, and the charge pump period starts. During this period, the level of the first node N1 is raised from V _BB to V _DD , so that the second node
The potential of the node N2 of the node rises to the level of 2V _DD + V _BB . At this time, the fifth clock IN5 is 3V _DD
Then, the transfer MOS transistor MT is turned on, and charges are transferred.

As described above, in this embodiment, the node N
After discharging the potential of 1 to the ground potential (V _SS ),
Further, by lowering the potential to the negative potential (V _BB ), the load on the negative power source can be reduced as compared with the case of directly reducing the potential to the negative potential. Therefore, the boosted potential generating circuit 20g shown in FIG. 14 can obtain a boosted level of 2V _DD + V _BB by using the V _BB power supply, that is, by using only one capacitive MOS transistor. In this case, the potential difference applied to the capacitive MOS transistor is larger than V _DD but smaller than 2 V _DD , so that a thin film gate can be used.

In order to manufacture the boosted potential generating circuit according to each of the above-described embodiments, it is necessary to manufacture MOS transistors having different gate insulating films.

With reference to FIGS. 16A to 16F, a multi-oxide process used for manufacturing MOS transistors having different film thicknesses will be described. First, as shown in FIG. 16A, an insulating region 32 is selectively provided on a silicon substrate 31 by STI (shallow trench isolation). As a result, the silicon substrate 31 is divided into a plurality of regions insulated from each other. Next, the first insulating film 33 is formed on the surfaces of the silicon substrate 31 and the insulating region 32 (FIG. 16B).

Then, as shown in FIG. 16C, the first
After selectively applying the resist film 34 on the insulating film 33 of the first insulating film 33,
The insulating film 33 is etched to partially expose the silicon substrate 31 and the insulating region 32 (FIG. 16D).
In this state, the resist film 34 is removed to expose the first insulating film 33 (FIG. 16E), and the first insulating film 33, the silicon substrate 31, and the insulating region 32 are exposed on the exposed first insulating film 33. The second insulating film 35 is formed.

As a result, a thick insulating film is formed in the region where the first and second insulating films 33 and 35 are laminated, and a thin insulating film is formed in the region where the first insulating film 33 is not formed. Is formed. As described above, a thick insulating film and a thin insulating film can be formed by utilizing the multi-oxide process. Further, by utilizing the thick insulating film and the thin insulating film as the gate insulating film of the MOS transistor forming the boosted potential generating circuit, the MOS transistor used in the above-described embodiment can be manufactured.

With reference to FIG. 17, a boosted potential generating circuit according to still another embodiment (9th embodiment) of the present invention will be described. The boosted potential generation circuit according to this embodiment is
It is used as an overdrive power supply circuit for a bit line sense amplifier (SA). In the illustrated example, the internal step-down circuit 41 for stepping down the external power supply voltage V _DD to obtain the internal step-down potential V _DL is connected to the overdrive power supply circuit. In this example, instead of directly using the external power supply, the internally reduced potential V _DL is supplied to the overdrive power supply circuit, and the boosted potential VDARY is supplied to the overdrive power supply circuit by the drive MOS transistor M.
It is given to the sense amplifier SA via D. In this configuration, the boosted potential VDARY due to the fluctuation of the level of the external power
The influence of the level fluctuation of can be suppressed. Further, by using the internal voltage down converter 41, the thickness of the gate insulating film of the capacitive MOS transistor MC1 having a required capacitance for the bit line can be reduced as compared with the case where an external power source is used, and the capacitance can be reduced. The area required for the MOS transistor MC1 can be reduced.

The overdrive power supply circuit shown in FIG. 17 is a series circuit of a P-channel first MOS transistor M1 and an N-channel second MOS transistor M2 connected between the internal step-down potential V _DL and the ground. Equipped with
The capacitive MOS transistor MC1 described above is connected to a common connection point of both MOS transistors M1 and M2. A precharge MOS transistor MP1 and a transfer MOS transistor MT1 are connected to the gate side of the capacitance MOS transistor MC1. Furthermore, the illustrated circuit includes a switching MOS transistor MS that selectively supplies the V _DL potential.

Here, the MOS transistors M1 and M2
Has a first clock IN 1, a gate of the precharge MOS transistor MP1 has a second clock IN 2, a gate of the transfer MOS transistor MT1 has a third clock IN 3 and a switching MOS transistor MS. Is the fourth clock IN4 and the driving MOS transistor MD
Is supplied with the fifth clock IN5.

More specifically, referring also to FIG. 18, FIG.
In the operation of No. 7, the external power supply voltage V _DD is stepped down to V _DL by the internal step-down circuit 41 and is applied to the overdrive power supply circuit. In this state, precharge M
The OS transistor MP1 has a precharge (PRE)
During the period, as shown in FIG. 18, the second clock IN2 is in the high level state, the precharge MOS transistor MP1 is turned on, and the capacitance MOS transistor MC1 is precharged. Further, in this state, the first clock IN1 is at the high level, so the first MOS
The transistor M1 is off.

Next, the first clock IN1 and the second clock IN2 become low level, and the precharge period shifts to the charge pump period. Third during this period
The clock IN3 of becomes high level. During this charge pump period, the precharge MOS transistor MP1 is turned off by the second clock IN2, and the low level of the first clock IN1 becomes the first and second ACTV signals.
Is input to the gates of the MOS transistors M1 and M2. As a result, the first MOS transistor M1 turns on, while the second clock IN2 turns off the precharge MOS transistor MP1 and turns on the transfer MOS transistor MT1. Therefore,
Boosting is performed during this period, and the boosted potential VDARY is output from the transfer MOS transistor MT1.

At this time, since the fourth clock IN4 is in the low level state, the switching MOS transistor MS is in the off state. On the other hand, the drive MOS transistor MD is turned on by the fifth clock IN5, and the overdrive charge is transferred from the transfer MOS transistor MT1 to the drive MOS transistor MD.
Is supplied to the sense amplifier (SA) via.

In the illustrated example, the first clock IN1 and the second clock IN1 are provided before and after the end of amplification of the bit line.
2 changes to a high level and the third clock IN3 changes to a low level. Further, a signal instructing a rewriting period is given to the switching MOS transistor MS as the fourth clock IN4, and the switching MOS transistor MS is turned on. To V _DL (bit line high level power supply). Upon completion of the switching, the capacitive MOS transistor is in the precharged state.

As described above, the illustrated overdrive power supply circuit can selectively supply V _DL and the boosted overdrive power supply voltage VDARY. Therefore, as in the conventional case, the overdrive power supply line and the V _DL power supply line are supplied. It has the advantage of not having to be individually wired.

Although the gate insulating film of the capacitive MOS transistor which constitutes the illustrated overdrive power supply circuit is thinner than the gate insulating film of the MOS transistor which constitutes the memory cell of the DRAM, it has the same thickness. Is also good.

[0130]

As described above, according to the present invention,
There is an advantage that the thickness of the gate insulating film of the capacitive MOS transistor can be reduced to realize a large capacitance in a small area. Further, in the present invention, a large capacity is required.
There is also an advantage that a doubled boosted potential generating circuit can be easily configured.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a boosted potential generation circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the boosted potential generating circuit shown in FIG.

FIG. 3 is a circuit diagram for explaining a boosted potential generation circuit according to a second embodiment of the present invention.

FIG. 4 is a waveform diagram for explaining the operation of the boosted potential generation circuit shown in FIG.

FIG. 5 is a circuit diagram for explaining a boosted potential generation circuit according to a third embodiment of the present invention.

FIG. 6 is a waveform diagram for explaining the operation of the boosted potential generating circuit shown in FIG.

FIG. 7 is a circuit diagram for explaining a boosted potential generation circuit according to a fourth embodiment of the present invention.

8 is a waveform diagram for explaining the operation of the boosted potential generating circuit shown in FIG.

FIG. 9 is a circuit diagram for explaining a boosted potential generation circuit according to a fifth embodiment of the present invention.

FIG. 10 is a waveform diagram for explaining the operation of the boosted potential generating circuit shown in FIG.

FIG. 11 is a circuit diagram for explaining a boosted potential generation circuit according to a sixth embodiment of the present invention.

FIG. 12 is a circuit diagram for explaining a boosted potential generation circuit according to a seventh embodiment of the present invention.

FIG. 13 is a waveform diagram for explaining the operation of the boosted potential generating circuit shown in FIG.

FIG. 14 is a circuit diagram for explaining a boosted potential generation circuit according to an eighth embodiment of the present invention.

FIG. 15 is a waveform diagram for explaining the operation of the boosted potential generating circuit shown in FIG.

16 (a), (b), (c), (d), (e),
(F) is M used in the boosted potential generating circuit according to the present invention
FIG. 6 is a diagram for explaining a method of manufacturing the OS transistor in the order of steps.

FIG. 17 is a circuit diagram for explaining a boosted potential generation circuit according to a ninth embodiment of the present invention.

FIG. 18 is a waveform chart for explaining the operation of the boosted potential generating circuit shown in FIG.

[Explanation of symbols]

MC1 capacitance MOS transistor MT1 transfer MOS transistor MP1 precharge MOS transistor 20, 20a to 20g boosted potential generation circuit 21 clock oscillator 22 capacitance circuit 201, 202 inverter M1 to M6 MOS transistor

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/108 H01L 27/04 C H02M 3/07 (72) Inventor Seiji Narui 2-chome Yaesu, Chuo-ku, Tokyo 2-1 Elpida Memory Co., Ltd. (72) Inventor Kenji Mae 22-22, Inventor Kenji Maemizu 5-2-1, Kamisuihoncho, Kodaira-shi, Tokyo Incorporated (72) Inventor, Makoto Morino 5-22-1 Kamimizuhoncho, Kodaira-shi, Tokyo Incorporated company Hitachi Ultra LSI Systems (72) Inventor Shuichi Kubo 5-22-1 Kamimizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems (reference) 5F038 AC03 AC05 AC08 AC14 AC15 AC17 BG02 BG03 BG05 CD06 DF05 EZ20 5F083 GA19 LA05 LA08 LA10 NA01 ZA07 ZA0 8 5H730 AA14 AA15 BB02 BB57 DD04 EE07 EE59 FD01 FG01 5M024 AA04 AA58 BB29 BB35 BB36 FF03 FF13 FF22 HH01 PP01 PP03 PP05 PP07

Claims (22)

[Claims] 1. A boosted potential generating circuit used in a semiconductor device including a memory cell composed of a MOS transistor, wherein the boosted potential generating circuit is used as a capacitive element,
Of the capacitance MOS transistor, a transfer MOS transistor connected to the second node, and a precharge MOS transistor connected to the second node. The potential difference between the first and second nodes is
A boosted potential generating circuit, wherein the gates of the capacitive MOS transistor, the transfer MOS transistor, and the precharge MOS transistor are controlled so as not to exceed the breakdown voltage of the gate insulating film of the capacitive MOS transistor. 2. The capacitive MOS transistor according to claim 1, wherein the capacitive MOS transistor has a gate insulating film thinner than a MOS transistor forming the memory cell or a gate insulating film of the transfer MOS transistor. A characteristic boosted potential generation circuit. 3. The control signal according to claim 1, wherein the first node is supplied with a control signal as a first clock,
A control signal is applied to the gate of the precharge MOS transistor as a second clock, and a control signal is applied to the gate of the transfer MOS transistor as a third clock. The charge pump period of the capacitance MOS transistor defined by the clock is controlled so as not to overlap with the precharge period of the precharge MOS transistor defined by the second clock, and defined by the third clock. The boosted potential generating circuit is characterized in that the transfer period is shorter than the charge pump period. 4. The precharge MOS transistor according to claim 1, wherein the precharge MOS transistor is provided with an external power supply voltage, and the transfer MOS transistor doubles the external power supply voltage. A boosted potential generation circuit characterized by being capable of generating a potential. 5. The transfer M according to claim 4,
The OS transistor has a thick gate insulating film equivalent to that of the memory cell, and the third clock applied to the gate of the transfer MOS transistor has an amplitude twice as large as the external power supply voltage. A characteristic boosted potential generation circuit. 6. The transfer M according to claim 4,
The OS transistor includes a thin gate insulating film equivalent to the capacitive MOS transistor, and
The boosted potential generating circuit is characterized in that the third clock applied to the gate of the S transistor has an amplitude equal to the external power supply voltage. 7. A boosted potential generating circuit for boosting an external power supply voltage, comprising: a first capacitive MOS transistor connected between first and second nodes; and a first capacitive MOS transistor connected between third and fourth nodes. A second capacitance MOS transistor, a first precharge MOS transistor connected between the power supply terminal to which the external power supply voltage is applied and the second node, and a second precharge MOS transistor connected between the power supply terminal and the fourth node. A precharge MOS transistor, and a transfer MOS transistor connected to the fourth node,
A switch circuit is connected between the second node and the third node, and the transfer MO
A boosted potential generation circuit characterized in that a potential three times higher than the external power supply voltage can be generated from an S transistor. 8. The MOS transistor according to claim 7, wherein the first and second capacitance MOS transistors are the MOS transistors forming the memory cell or the transfer MOS.
A boosted potential generating circuit comprising a MOS transistor having a gate insulating film thinner than the gate insulating film of the transistor. 9. The switch circuit according to claim 7, wherein the switch circuit is connected between a first MOS transistor connected between the second node and the third node and between a third node and ground. A boosted potential generating circuit, comprising: a second MOS transistor and a third MOS transistor. 10. The first MOS according to claim 9.
The transistors are P-channel MOS, while the second and third MOS transistors are N-channel MOS.
A boosted potential generation circuit characterized by: 11. The boosted potential generating circuit according to claim 10, wherein the first to third MOS transistors have a thick gate insulating film. 12. The boosted potential generation circuit according to claim 10, wherein the first to third MOS transistors have a thin gate insulating film. 13. The first capacitor M according to claim 7,
The OS transistor, the first precharge MOS transistor, the switch circuit, the second precharge MOS transistor, and the transfer MOS transistor are respectively provided with control signals as first, second, third, and third control signals. 4 and a fifth clock are applied, and the charge transfer period of the transfer MOS transistor defined by the fifth clock is the same as that of the first capacitance MOS transistor defined by the first clock. A boosted potential generating circuit, which substantially overlaps a charge pump period and does not substantially overlap a precharge period defined by the second and fourth clocks. 14. The switch circuit according to claim 13, wherein the switch circuit renders the second node and the third node non-conductive during a precharge period defined by the second and fourth clocks. Is set to a low level, and the second node and the third node are electrically connected during the charge pump period. 15. The transfer MOS transistor according to claim 13, wherein the transfer MOS transistor is configured by a P-channel MOS, and the switch circuit includes a P-channel first MOS transistor connected between second and third nodes, A boosted potential generating circuit having N-channel second and third MOS transistors connected in series between a third node and ground. 16. The gate according to claim 15, wherein the gates of the first and second MOS transistors are commonly connected to a power supply voltage terminal, while the gate of the third MOS transistor receives a third clock. Given, second and fourth
Second during the precharge period specified by the clock
And non-conducting between the third node and the node
Is set to a low level, and the second node and the third node are electrically connected during the charge pump period. 17. The boosted potential according to claim 16, wherein the first to third MOS transistors and the first and second capacitance MOS transistors have a thin gate insulating film. Generator circuit. 18. The method according to claim 17, wherein the first precharge MOS transistor has a thin gate insulating film, while the second precharge MOS transistor and the transfer MOS transistor have a thick gate insulating film. A boosted potential generation circuit characterized in that 19. A capacitive MOS transistor having a gate insulating film having a predetermined film thickness, and the capacitive MOS transistor.
A transfer MOS transistor having a gate insulating film having a thickness larger than that of a gate insulating film of the transistor, and the capacitive MOS transistor and the transfer M
In a method of controlling a boosted potential generating circuit including a precharge MOS transistor coupled to an OS transistor, a step of supplying a first clock defining a charge pump period to the capacitive MOS transistor, a charge pump according to the first clock Applying a second clock to the precharge MOS transistor that determines a precharge period that ends before the start of the period;
And a step of supplying a third clock defining a charge transfer period to the transfer MOS transistor within the charge pump period of the first clock, thereby adding to the capacitive MOS transistor during the boost period. A control method characterized by limiting a voltage. 20. The control method according to claim 19, wherein the third clock has a larger amplitude than that of the first clock. 21. The capacitor M according to claim 19 or 20, wherein the capacitor M is included in the charge pump period and the precharge period.
A control method characterized in that the voltage applied to the OS transistor is controlled to be lower than the withstand voltage of the gate insulating film of the capacitive MOS transistor. 22. In a boosted potential generating circuit used in a semiconductor device including a memory cell composed of MOS transistors, a capacitive MOS transistor used as a capacitive element and connected between a first node and a second node,
A transfer MOS transistor connected to the second node; and a precharge MOS transistor connected to the second node.
A boosted potential having a circuit connected to the first node of the transistor and boosting the capacitance MOS transistor, and a circuit for setting the potential of the first node to a substrate potential equal to or lower than the ground potential. Generator circuit.