JP2003131766A - Information-processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the order for shifting/returning to/from the power-saving mode between a CPU and a peripheral equipment. SOLUTION: A register 13141 which is accessible from the CPU via a system bus is provided in the control circuit of the peripheral equipment. After the CPU makes access to the resister 13141, it shits to the power-saving mode, and after a peripheral control circuit receives the access from the CPU, it shifts the peripheral equipment to the power-saving mode by a timer 13145 after a prescribed period of time passes. Similarly, after a prescribed returning signal is inputted, it returns the peripheral equipment to the original state by a timer 13146 after a prescribed period of time passes. In this case, the CPU returns by a delayed signal generated by delaying a return signal 193 by a prescribed time with a delayed circuit. Timer-setting time and so on are set by the CPU in the registers 13142 and 13143 connected to the system bus. The order for shifting/returning is controlled by the magnitude of the time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to power saving in an information processing device.

[0002]

2. Description of the Related Art In recent years, CPUs have been used to extend battery life with the spread of portable small computers.
In addition, power saving of information processing devices including peripheral devices has become an important issue. As a general power saving method of the information processing apparatus, when an idle state in which the CPU is not in a particular work state such as a key input waiting state for a predetermined time is detected, the CPU is set to the power saving mode. There is something to move. This power saving mode is a standby state (interrupt standby state) waiting for the input of a predetermined interrupt signal, and even if the interrupt signal is detected, the circuit other than the minimum necessary circuits (parts) is necessary to return to the original state. The power supply is stopped. For the purpose of minimizing the power consumption in the power saving mode, Japanese Patent Laid-Open No. 7-121259
When the idle state of the CPU is detected in the publication, the CP
While U shifts to the interrupt standby state (power saving mode), it also stops the clock signal to the CPU and shifts other peripheral devices (hard disk drive, etc.) to the power saving mode (stops the control circuit, etc.). Proposed. As a result, the information processing apparatus as a whole can be in a state where the power consumption is lower. By the way, CP
U and power saving mode, ROM and RA
When trying to save more power by shifting peripheral devices such as M to power saving mode such as circuit stop at the same time, CPU
ROM and RA until the transition to the power saving mode
We need to ensure that we can access M. Otherwise, the CPU is in ROM, R even while shifting to the power saving mode.
This is because the peripheral device such as the AM is accessed, so that the power saving mode cannot be normally performed. Further, even between peripheral devices, there is a case where it is necessary to consider the order of transition to the power saving mode, for example, when there is a peripheral device that accesses a RAM that is another peripheral device when shifting to the power saving mode. . The above is the same when returning from the power saving mode to the original state. For example, ROM or RAM
If the CPU recovers and resumes the processing before the access is guaranteed, there arises a problem that the normal operation cannot be guaranteed. In particular, in recent information processing devices, PLLs (Phase Locked
Loop) circuit is built in and many operate in synchronization with the clock of the same phase, and this problem becomes remarkable. That is, P
The LL requires a long time of ms unit from the start of the clock input until the output is stable. Therefore, when the peripheral device operating by the clock output of the PLL is accessed before the stable clock output, Normal operation cannot be guaranteed.

[0003]

However, the technique disclosed in the above publication has means for controlling the sequence of transition to the power saving mode and return to the original state between the CPU and peripheral devices. Not mentioned above, ROM or RAM
When peripheral devices such as the above are also shifted to the power saving mode or operate using the PLL, there is a problem that the shift to the power saving mode and the return to the original state cannot be normally performed. was there. Further, in the technique disclosed in the above publication, in order to output a signal indicating that the CPU is in the idle state to the peripheral device side, it is necessary to provide the CPU with an output line or the like separately from an interface such as an existing bus.
There is also a problem that the characteristic of the CPU that can flexibly deal with the change of the system configuration is lost. Therefore, the present invention has been made in view of the above circumstances, and it is an object of the present invention to control the sequence of transition to the power saving mode and return to the original state between the CPU and peripheral devices. The purpose is to provide an information processing device that can flexibly respond to changes in the system configuration.

[0004]

In order to achieve the above object, a first invention is a CPU having a function of shifting to a power saving mode under a predetermined condition, one or a plurality of peripheral devices, and the CPU. An information processing apparatus comprising: a peripheral device control unit that is connected via a predetermined bus and that controls the peripheral device to shift to the power saving mode in response to the shift of the CPU to the power saving mode. , The peripheral device control means corresponds to the peripheral device after a predetermined access indicating the transition to the power saving mode from the CPU via the bus and a lapse of a predetermined power saving mode transition time. In the power saving mode. Accordingly, if the power saving mode shift time is set to be longer than the time required for the CPU to shift to the power save mode, the peripheral devices such as ROM and RAM that need to be accessed when the CPU shifts to the power save mode. Access from CPU (notification)
It is possible to shift to the power saving mode according to the above. Of course, if the access is not performed from the CPU, it is possible to deal with peripheral devices that do not want to shift to the power saving mode in conjunction with the CPU. Further, since the access (notification) from the CPU to the peripheral device is performed via the bus provided as standard in the CPU, it is not necessary to provide a special signal line or the like, and the system configuration can be flexibly changed. This does not impair the characteristics of the CPU. Further, if the power saving mode transition time is set appropriately for each peripheral device, the order of transition to the power saving mode between the peripheral devices can also be controlled.

Further, the peripheral device control means is characterized by the CP
A power-saving mode shift timer setting register provided with a power-saving mode shift control register that is accessed from U, and a power-saving mode shift timer setting register that can set the power-saving mode shift time for each of the peripheral devices via the bus. It is also possible to have those equipped with. As a result, even if it is necessary to change the power saving mode transition time due to a change in system configuration or the like, it can be easily dealt with by simply changing the time information of the power saving transition timer setting register from the CPU or the like. .

A second aspect of the present invention is a CPU having a function of returning from the power saving mode based on the input of a predetermined return interrupt signal when the power saving mode is entered, and 1 or Peripheral device control means connected to a plurality of peripheral devices and the CPU via a predetermined bus, and controlling the peripheral devices to return from the power saving mode in response to the return of the CPU from the power saving mode. And an interrupt signal delay means for outputting a delayed interrupt signal obtained by delaying the restore interrupt signal by a predetermined restore interrupt signal delay time,
The information processing apparatus is characterized in that the CPU is configured to return from the power saving mode in response to the input of the delayed interrupt signal. Accordingly, if the return interrupt signal delay time is equal to or longer than the time required to restore peripheral devices such as ROM and RAM accessed when the CPU returns from the power saving mode, the CPU can be restored normally. It is also conceivable to include an interrupt delay timer setting register provided so that the return interrupt signal delay time can be set via the bus.

A third aspect of the present invention is a case where the CPU and one or more peripheral devices are connected to the CPU through a predetermined bus, and the peripheral devices are in a predetermined power saving mode. An information processing device comprising: peripheral device control means for controlling the peripheral device to recover from the power saving mode based on the input of a predetermined recovery interrupt signal, wherein the peripheral device control means includes the recovery interrupt signal. After inputting, and after the elapse of the predetermined power saving mode recovery time,
The information processing apparatus is configured to return the corresponding peripheral device from the power saving mode. As a result, if the power saving mode return time is set appropriately for each peripheral device, the order of returning from the power saving mode among the peripheral devices can be controlled.

It is also conceivable to provide a power-saving mode return timer setting register provided so that the power-saving mode return time for each of the peripheral devices can be set via the bus. As a result, even if the order of recovery from the power saving mode between peripheral devices changes due to changes in the system configuration or the like, it is easy to change the time information in the power saving recovery timer setting register from the CPU or the like. Will be available.

A return interrupt mask instruction is provided so that a return interrupt mask instruction that does not cause a return from the power saving mode in response to the power saving mode return signal by the peripheral device control means can be set via the bus. A register and a forced return instruction for forcibly returning the corresponding peripheral device from the power saving mode by the peripheral device control means regardless of the power saving mode return signal,
It is also conceivable that each of the peripheral devices is provided with a power saving mode forcible return register provided so as to be set through the bus. Thus, by setting the restoration interrupt mask instruction, it is possible to deal with a peripheral device which does not want to be restored from the power saving mode in cooperation with the CPU, and the forced restoration instruction causes the peripheral device to be in the power saving mode at any timing. Can be recovered from.

Further, an internal interrupt signal generating means for generating a predetermined internal interrupt signal for each of the peripheral devices under a predetermined condition, and either the internal interrupt signal or an external interrupt signal inputted from the outside are inputted. A recovery interrupt signal generating means for generating the recovery interrupt signal at that time may be considered. As a result, the trigger for returning from the power saving mode can be generated not only by the interrupt signal from the outside but also by the condition of the peripheral device. For example, in a peripheral device that is a communication interface with an external device, when a communication input from the external device occurs, it is possible to generate the internal interrupt signal and return from the power saving mode.

An internal / external interrupt mask instruction for causing the return interrupt signal generation means to ignore the internal interrupt signal and the external interrupt signal and generate the return interrupt signal via the bus. It is also conceivable to have an internal / external interrupt mask register provided so as to be able to be set. As a result, it is possible to select which peripheral device is to be returned from the power saving mode in response to the internal interrupt signal, so that the flexibility is further increased. Further, it may be an information processing apparatus combining the first to third inventions.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings to provide an understanding of the present invention. The following embodiments are examples of embodying the present invention and are not of the nature to limit the technical scope of the present invention. 1 is a block diagram showing the configuration of the information processing device X according to the embodiment of the present invention, and FIG. 2 is a configuration example of a peripheral device control circuit configuring the information processing device X according to the embodiment of the present invention. 3 is a block diagram showing an example of a configuration of an interrupt control circuit that constitutes the information processing apparatus X according to the embodiment of the present invention. FIG. 4 is a block diagram showing the information processing apparatus X according to the embodiment of the present invention. FIG. 5 is a block diagram showing an example of the configuration of the clock control circuit 16 constituting the system. FIG. 5 is a flowchart showing a procedure for shifting to the power saving mode in the information processing apparatus X according to the embodiment of the present invention. 6 is a flowchart showing a procedure for returning from the power saving mode in the information processing apparatus X according to the present invention.

First, the configuration of the information processing apparatus X according to the embodiment of the present invention will be described with reference to FIG. The information processing devices X are connected to each other by a system bus 181 and are connected to the CP.
U11, clock control circuit 16, interrupt control circuit 14, and a plurality of peripheral device control circuits 131, 132, ...
And the peripheral device control circuits and control lines 1821, 1
, Peripheral devices 121, 122, ... Connected by 822, 1823, .. (that is, connected to the CPU 11 via the system bus 181), and a high-speed oscillator 151 and a low-speed oscillator 152. ing. The CPU 11 performs various arithmetic processes according to programs and data acquired from the peripheral devices 121, 122, ... Such as ROM, RAM, keyboard, etc., and outputs the arithmetic results to the peripheral devices 121, 122, such as display devices and hard disks.
Output to ... Data transmission / reception with the peripheral devices 121, 122, ... Is performed via the system bus 181. When the CPU 11 enters the idle state due to waiting for input from the keyboard or the like, the CPU 11 automatically shifts to the power saving mode and enters the interrupt standby state, and a predetermined interrupt signal (in the present embodiment, a delayed interrupt signal described later). ), It has a function of automatically returning to the original state (the CPU described in the above publication).
etc). Further, the CPU 11 is responsive to the high-speed clock signal 1711 from the high-speed oscillator 151 for the peripheral device 1
The PLL 111 for operating at high speed in synchronization with a clock having the same phase as 21, 22 ,. To achieve this synchronization, the clock control circuit 16 described later
Similarly, the PLL 161 is also incorporated in the PLL.
The peripheral devices 121, 122, ... Operate based on the main clock signal 1721 generated by 161.

Next, the configuration of the peripheral device control circuits 131, 132, ... Will be described with reference to FIG. For convenience, the number in FIG. 2 is one of the peripheral device control circuits.
(131), the same applies to the other peripheral device control circuits 132, 133, .... The peripheral device control circuit 131 controls the peripheral device 121 connected by a control line 1821,
It has the following components. That is, the system bus 18
Power saving mode shift control register 13141, which is five registers (temporary storage devices) connected to 1, power saving mode shift timer setting register 13142, power saving mode reset timer setting register 13143, power saving mode forced restore register 13144, interrupt Mask register 1
3151, a peripheral device main control circuit 1311, which is also connected to the system bus 181, a power saving mode transition timer circuit 13145, and a power saving mode return timer circuit 13
146, interrupt mask circuit 13152, main clock mask circuit 1313, and power saving mode control circuit 13
It is composed of 12 and. The five registers 131
41 to 13144 and 13151 are accessed by the CPU 11 via the system bus 181 and various information is set. The peripheral device main control circuit 131
1 is a control command from the CPU 11 via the system bus 181 and the power saving mode control circuit 1312.
The peripheral device 121 is controlled according to a control signal 1318 from Other functions of each component will be described later.

Next, the configuration of the interrupt control circuit 14 will be described with reference to FIG. The interrupt control circuit includes the CPU 11, the clock control circuit 1
6, and the peripheral device control circuits 131, 132, ..., An interrupt signal (return interrupt signal 193 and delay described later) for notifying the timing of returning from the state in which a predetermined power saving mode is entered to the original state. It generates an interrupt signal 194) and has the following components. That is, the interrupt mask register 142 and the interrupt delay timer setting register 1 which are two registers connected to the system bus 181.
44, an external interrupt mask circuit 1431 for inputting an external interrupt signal 191 input from the outside of the information processing apparatus X, and the peripheral device control circuits 131, 13
Internal interrupt signals 1921, 19 output by 2, ...
22. Each of the internal interrupt mask circuits 1432, 1433, ... Is input, and the reset interrupt generation circuit 141 and the interrupt delay timer circuit 145 are provided. The external and internal interrupt mask circuits 1431, 1432, ... Are connected so that the information set in the interrupt mask register 142 can be read. In addition, the two registers 142 and 14
4 is accessed by the CPU 11 via the system bus 181 and various information is set. Other functions of each component will be described later.

Next, the configuration of the clock control circuit 16 will be described with reference to FIG. The clock control circuit 16 inputs the high-speed clock signal 1711 and the low-speed clock signal 1712, which are the outputs of the high-speed oscillator 151 and the low-speed oscillator 152, and inputs the main clock signal 1721 having the same phase as the clock used by the CPU 11. , And the like, which are used when the peripheral device control circuits 131, 132, ... Are in the power saving mode state and generate a sub clock signal 1722 that does not require synchronization with the CPU 11, and the peripheral devices 121, 122 ,. It has the following components. That is, the system bus 18
Main clock stop control register 1631, main clock stop timer setting register 1632, and main clock recovery timer setting register 1 which are three registers connected to 1.
641, main clock stop timer circuit 1633, main clock recovery timer circuit 1642, high-speed clock control circuit 1
621, the PLL 161, main clock control circuit 162
2, and a sub clock selection circuit 165. The sub clock selection circuit 165 is a circuit that switches which of the high speed clock signal 1711 and the low speed clock signal 1712 is output as the sub clock signal 1722 with a switch or the like. The circuit 16
No. 5 is not necessary when it is not necessary to switch the sub clock signal 1722, which is to be selected. The three registers 1631 and 163
2, 1641 are accessed by the CPU 11 via the system bus 181 and various information is set. Other functions of each component will be described later.

Next, referring to FIG. 5, when the CPU 11 is in the idle state, the CPU 11
And the operation procedure of the other devices shifting to the power saving mode will be described. Hereinafter, S101, S102,
Represents the operation procedure (step) number. First, the CPU
In No. 11, in the idle state, the peripheral devices 121, 122, ... Which also shift to the power saving mode in association with the shift to the power saving mode of their own.
The peripheral device control circuit 1 connected to the
The power saving mode shift control registers 13141 of 31, 132, ... Are accessed via the system bus 181 and a notification of shifting to the power saving mode is notified (S101). As a result, the operation of shifting the peripheral device control circuits 131, 132, ..., Which will be described later, to the power saving mode is started. Which of the peripheral devices 121,
Information about whether or not to shift the 122, ... To the power saving mode is registered in advance in a storage means such as a non-volatile RAM which is one of the peripheral devices 121, 122 ,.
This is read by the CPU 11. (Less than,
The information registered in advance in the storage means such as the nonvolatile RAM is referred to as the information registered in the CPU 11 for the sake of simplicity. )

Next, each peripheral device control circuit 131, 1
Whether or not the supply of the main clock signal 1721 to 32, ... Can not be stopped is determined based on the determination information (“stop disabled” / “stop enabled”) registered in advance in the CPU 11 (S102). . Each of the peripheral devices 121 and 12
, 2, there may be a main clock signal 1721 required (such as an external communication interface) and an unnecessary one (such as a hard disk) even when the power saving mode is entered. The determination information is “unstoppable” if there is any one of the peripheral devices 121, 122, ... That requires the main clock signal 1721 in the power saving mode. Is stored as ". When it is determined in S102 that the main clock signal 1721 is "stoppable", the CPU 11 accesses the main clock stop control register 1631 of the clock control circuit 16 to stop the main clock signal 1721. After being notified to do so (S103), the process proceeds to S104.
Meanwhile, in S102, the main clock signal 1721
Is determined to be "unstoppable", S104 is directly
Move to. In S104, after the CPU 11 itself shifts to the power saving mode (interrupt standby state),
The operation of shifting to the power saving mode in the CPU 11 is completed.

By the way, the fact that the CPU 11 is in the idle state can be notified (S101, S03) to the peripheral devices 121, 122, ...
In order to perform the notification via the system bus 181 which is a standard input / output means, the CPU 11
Must be in operation (before shifting to the power saving mode). Nevertheless, at the time of shifting to the power saving mode (S104), the CPU 11 reads out a predetermined program and the like, so that the peripheral devices 121, 122, ... Such as ROM and RAM guarantee the access. , And the transition to the power saving mode of the peripheral devices 121, 122, ... Must be performed after the CPU 11 completely transitions to the power saving mode. In order to solve this, a feature of the present invention is to provide a timer circuit for each of the peripheral devices 121, 122, ..., And after receiving a notification (access to a register) from the CPU 11 to the power saving mode, CP
The point is that the peripheral devices 121, 122, ... Are shifted to the power saving mode after the time required for the U11 to shift to the power saving mode. Hereinafter, with reference to FIG. 5, the peripheral device control circuit 131 having the above characteristics,
, 132, and the operation of shifting to the power saving mode in the clock control circuit 16 will be described.

The peripheral device control circuits 131, 132, ...
In FIG. 2, while the power saving mode shift timer circuit 13145 confirms the contents of the power saving mode shift control register 13141 (S111), the CPU 11 waits until access (notification) from the CPU 11. (S112 → S111). When the access from the CPU 11 is detected (Yes in S112), the power saving mode transition timer circuit 1314
5, the power saving mode transition timer setting register 1
Time information is read from 3142 (S113). The time information is the waiting time after the access from the CPU 11 until the peripheral devices 121, 122, ... Connected to the peripheral device control circuits 131, 132 ,. (Hereinafter, referred to as power saving mode transition time), and information registered in advance in the CPU 11 is stored in the CP when the information processing apparatus X is started.
It is preset from U11 via the system bus 181.

The power saving mode transition time depends on the CPU
11 is set to be equal to or longer than the time required to shift to the power saving mode, and the relationship with other peripheral devices 121, 122, ... Is also taken into consideration. The peripheral devices 121, 122, ...
In some cases, such as a PCI bus controller, the peripheral device 1 is used when shifting to the power saving mode.
, 122, ..., which is one of the peripheral devices 121, 122, 122, etc. on the accessing side. The power saving mode transition time longer than ... Is set.

Next, the power saving mode transition timer circuit 1
When the 3145 starts clocking and the power saving mode transition time has elapsed, the power saving mode transition signal 13165 is output to the power saving mode control circuit 1312 (S11).
4). Next, the power saving mode control circuit 1312, to which the power saving mode shift signal 13165 is input, causes the peripheral devices 121, 122, ... To the main clock mask circuit 1313 and the peripheral device main control circuit 1311.
A mode control signal 1318 indicating that the operation is stopped is output (S115). Further, the mode control signal 131
After the connected peripheral devices 121, 122, ... Are controlled by the main clock mask circuit 1313 and the peripheral device main control circuit 1311 that input 8 to shift to the power saving mode (S116), The transition operation to the power saving mode in the device control circuits 131, 132, ... Is completed. Here, the main clock mask circuit 1313 and the peripheral device main control circuit 1311 are individually configured according to the connected peripheral device 121. For example, the corresponding peripheral device 121 is
In the power saving mode, the main clock signal 1721
Is unnecessary, the main clock mask circuit 1313 outputs the input mode control signal 1318.
Is a signal indicating that the peripheral device 121 is suspended, the supply of the main clock signal 1721 to the peripheral device 121 is cut off.

As shown above, the peripheral devices 121,
.. are controlled so as to shift to the power saving mode after the elapse of the time set in each of them after receiving the notification from the CPU 11 (S111), the CPU 11 and other CPUs are controlled depending on the size of the set time. It is possible to control the order of transition to the power saving mode among the peripheral devices 121, 122, ... And to reliably shift to the power saving mode. Further, since the notification from the CPU 11 to the peripheral devices 121, 122, ... Is sent via the system bus 181 which is provided as a standard, it is not necessary to provide a special output line or the like, and the CPU 1
The flexible expandability, which is the characteristic of No. 1, is not impaired. In addition, the transition time to the power saving mode is the system bus 18
Since it can be set via the peripheral device 1, the peripheral device 121,
Even if the configuration of 122, ... Is changed, it can be easily dealt with by changing the time stored in the non-volatile RAM or the like, and the information processing apparatus can be made more flexible.

On the other hand, the clock control circuit 16 (FIG. 4)
In the above, while the main clock stop timer circuit 1633 confirms the contents of the main clock stop control register 1631 (S121), the main clock stop timer circuit 1633 waits until an access from the CPU 11 (S122).
→ S121). When the access from the CPU 11 is detected (Yes in S122), the main clock stop timer circuit 1633 reads time information from the main clock stop timer setting register 1632 (S123). The time information is from the time of access from the CPU 11 to the time of stopping the supply of the main clock signal 1721 (that is, the clock control circuit 1).
6) to the power saving mode) (hereinafter referred to as main clock stop mode transition time), and the information registered in advance in the CPU 11 is used when the information processing device X is started. It is preset from the CPU 11 via the system bus 181. The main clock stop mode transition time is set to a time longer than the longest time among the power saving mode transition times in the peripheral device control circuits 131, 132, ... (FIG. 2) described above.

Next, the main clock stop timer circuit 16
33 starts clocking, and when the main clock stop mode transition time elapses, the high-speed clock control circuit 162
1 and the main clock stop signal 1673 is output to the main clock control circuit 1622 (S124). Further, the high-speed clock control circuit 1621 and the main clock control circuit 16 to which the main clock stop signal 1673 is input.
22, the high speed clock 1 to the PLL 161
After the supply of 711 and the output of the main clock 1721 are stopped (S125), the operation of shifting to the power saving mode in the clock control circuit 16 ends. In this way, after receiving the notification from the CPU 11 (S1
21), since the output of the main clock 1721 is stopped after the elapse of a predetermined time, the peripheral devices 121, 122,
The main clock 1721 is not stopped during the transition to the power saving mode, and the power saving mode can be surely shifted.

Next, referring to FIG. 6, the CPU 11, the clock control circuit 16, and the peripheral devices 121, 1
22 ...., the operation procedure for returning from the power saving mode to the original state and the operation procedure of the interrupt control circuit 14 for generating a signal that triggers the return will be described. First, in the interrupt control circuit 14 (FIG. 3), the external interrupt mask circuit 1431 and the internal interrupt mask circuits 1432, 143.
3, ..., the interrupt mask register 142
Is confirmed, and if a predetermined mask instruction (corresponding to the internal / external interrupt mask instruction) is set, this is read (S201). The mask instruction is preset by the CPU 11 via the system bus 181 when the information processing apparatus X is activated, and the external and internal interrupt signals 19 to be described later.
Of 1,1921,1922, ..., Only those that ignore the input are set. As a result, it is possible to set what is used as a trigger for restoration and what is not used as a trigger, so that it is more flexible. Further, the external and internal interrupt mask circuits 1431 and 143.
2, a predetermined external interrupt signal 191 input from the outside of the information processing apparatus X and the predetermined internal interrupt generated by the peripheral device main control circuit 1311 in the peripheral device control circuits 131, 132 ,. Input of the signals 1921, 1922, ... Is confirmed (S202). These interrupt signals 191, 192
1, 1922 ... Are signals that serve as triggers for returning from the power saving mode. The internal interrupt signal 19
An example of the reference numeral 21 is a signal generated when there is a key input or a communication input from the external device when the peripheral devices 121, 122, ... Are keyboards or communication devices with an external device. The internal interrupt signal 1921,
The peripheral device main control circuit 131 for generating 1922, ...
1 is individually configured according to the characteristics of the corresponding peripheral devices 121, 122, .... The external and internal interrupt mask circuits 1431, 1432, ... ignore the input of the external and internal interrupt signals 191, 1921, 1922, ... for which the mask command is set, and set the mask command. Not said external and internal interrupt signals 191, 1921, 192
Only when 2, ... Is input, the predetermined signals 1471, 1
.. are output to the return interrupt generation circuit 141.

Next, the restore interrupt generation circuit 14
1, the external and internal interrupt signals 191, 1921, 192 for which the mask instruction is not set.
2, the presence or absence of the inputs (that is, the presence or absence of predetermined signals 1471, 1472, ... From the external and internal interrupt mask circuits 1431, 1432, 1433, ...) Is checked (S203), and if there is no input. Is S
Returning to step 201, the above-described operation is repeated (S201).
~ S203). On the other hand, the restoration interrupt generation circuit 1
41, the external and internal interrupt signals 191, 1921, 192 for which the mask instruction is not set.
If any one of 2, ... is input (S
(Yes side of 203), predetermined return interrupt signal 19
3 is generated, and the signal is output to the clock control circuit 16, the peripheral device control circuits 131, 132, ... And the interrupt delay timer circuit 145 (S20).
4). The return interrupt signal 193 triggers the clock control circuit 16 and the peripheral device control circuits 131, 132, ... Into the return operation from the power saving mode. These return operations will be described later. Next, the interrupt delay timer circuit 145, to which the restore interrupt signal 193 is input, reads a predetermined delay time (hereinafter referred to as a restore interrupt signal delay time) from the interrupt delay timer setting register 144, and the restore interrupt signal. After the delayed interrupt signal 194 (corresponding to the delayed interrupt signal), which is a signal obtained by delaying the signal 193 by the return interrupt signal delay time, is generated and output to the CPU 11 (S206), the interrupt control circuit 14 recovers. The operation ends. The C
The PU 11 is restored from the power saving state to the original state by the input of the delayed interrupt signal 194. The return interrupt signal delay time is at least the CPU 11
The peripheral devices 121, 122, ... That are accessed when returning from the power saving mode to the original state are set to be longer than the time required for returning from the power saving mode. As a result, the CPU 11 causes the peripheral devices 121, 1
, 22 ... Are not accessed before the restoration is completed and can be restored normally.

On the other hand, the clock control circuit 16 (FIG. 4)
, The main clock recovery timer circuit 1642 and the high speed clock control circuit 1621 are waiting for the input of the recovery interrupt signal 193 generated by the interrupt control circuit 14 (FIG. 3) (S221, S).
222), when the restoration interrupt signal 193 is input (Yes side of S222), the high-speed clock control circuit 1621 restores the output of the high-speed clock signal 1711 to the PLL 161 (S223). As a result, the PLL 161 returns from the stopped state to the operating state. Next, the main clock recovery timer circuit 1642
Causes the main clock recovery timer setting register 164
The time information is read from 1 (S224), and after the waiting time has elapsed, the main clock recovery signal 1672 is output to the main clock control circuit 1622 (S225).
Further, when the main clock recovery signal 1672 is input, the main clock control circuit 1622 receives the PLL1.
The output of the main clock signal 1721 which is the output signal of 61 (supply to the interrupt control circuit 14 and the peripheral device control circuits 131, 132, ...) Is restored (S226), and then the clock control circuit 16 is restored. The operation ends. Main clock recovery timer setting register 16
The time information set to 41 is until the supply of the main clock signal 1721 is restarted after the recovery interrupt signal 193 is input (that is, until the clock control circuit 16 is recovered from the power saving mode). )
Is the waiting time (hereinafter referred to as the main clock stop mode return time) of, and the information registered in advance in the CPU 11 is
It is preset from the CPU 11 via the system bus 181 when the information processing device X is started. The main clock stop mode return time is the PLL
It is set to be longer than the time required for the main clock signal 1721, which is the output of the PLL 161, to stabilize after the output of the main clock 1711 is restarted at 161. Accordingly, it is possible to prevent the peripheral devices 121, 122, ... from malfunctioning due to the main clock signal being supplied to the peripheral devices 121, 122 ,.

On the other hand, the peripheral device control circuits 131, 13
2, ... (FIG. 2), the power saving mode control circuit 1312 causes the power saving mode forced recovery register 1
If the contents of 3144 are confirmed (S211), and a predetermined forced recovery command described later is not set (S212).
No side), the contents of the interrupt mask register 13151 are confirmed by the interrupt mask circuit 13152, and if a predetermined return interrupt mask instruction (corresponding to the return interrupt mask instruction) is set, this is read ( S213).

Further, the interrupt mask circuit 13
The input of the return interrupt signal 193 output from the interrupt control circuit 14 is confirmed by 152 (S214). The return interrupt signal 193 is
The peripheral device control circuits 131, 132, ... serve as triggers for returning from the power saving mode. The interrupt mask circuit 13152 is configured to output a predetermined signal 13172 to the power saving mode return timer circuit 13146 only when the restore interrupt mask instruction is not set in the interrupt mask register 13151. That is, when the restore interrupt mask instruction is set, the input of the restore interrupt signal 193 is ignored.

Next, the power saving mode recovery timer circuit 1
According to 3146, the restore interrupt signal 193 when the restore interrupt mask instruction is not set
Whether or not there is input (that is, the interrupt mask circuit 13
The presence or absence of the predetermined signal 13172 from 152 is checked (S215), and if there is no such input, the process returns to S211 and the above-described operation is repeated (S211 to S21).
5). On the other hand, when the restore interrupt signal 193 is input in a state where the restore interrupt mask instruction is not set (Yes in S215), the power save mode restore timer circuit 13146 causes the power save mode restore timer to be executed. Predetermined time information is read from the setting register 13143 (S216). The time information is changed from the power saving mode to the original state of the peripheral devices 121, 122, ... Connected to the peripheral device control circuits 131, 132, ... After the input of the return interrupt signal 193. It is a waiting time until restoration (hereinafter referred to as a power saving mode restoration time), and information registered in advance in the CPU 11 is, for example, when the information processing device X is started.
It is set in advance via the system bus 181. The power saving mode return time is set so that the clock control circuit 16 and the other peripheral device control circuits 131, 132, ... Are in the correct return order, like the power save mode transition time.

Next, the power saving mode recovery timer circuit 1
3146 starts clocking, and when the power saving mode return time has elapsed, the power saving mode return signal 13166 is output to the power saving mode control circuit 1312 (S217). Next, the power saving mode return signal 131
The power saving mode control circuit 1312, which has input 66, supplies the peripheral devices 121, 1 to the main clock mask circuit 1313 and the peripheral device main control circuit 1311.
Mode control signal 1318 indicating that 22, ...
Is output (S218). Further, the main clock mask circuit 131 to which the mode control signal 1318 is input
3 and the peripheral device main control circuit 1311, after the connected peripheral devices 121, 122, ... Are controlled to return from the power saving mode to the original state (S21).
9), the operation of returning from the power saving mode in the peripheral device control circuits 131, 132 ,.

On the other hand, when the forced recovery instruction is set in the power saving mode forced recovery register and is read by the power saving mode control circuit 1312 (Yes in S212), other conditions are taken into consideration. First, the peripheral device 1 is controlled by the power saving mode control circuit 1312.
A mode control signal 1318 indicating that the peripheral devices 121, 122, ... Are restored (S218), and the connected peripheral devices 121, 122, ... Are connected by the main clock mask circuit 1313 and the peripheral device main control circuit 1311. It is controlled to return from the power saving mode to the original state (S219). The restore interrupt mask instruction is
The CPU 11 is preset for each of the peripheral device control circuits 131, 132, ... Via the system bus 181, and is set only for those ignoring the input of the return interrupt signal 193. By setting the restore interrupt mask instruction and accessing the power saving mode forced restore register,
The peripheral devices 121, 122, ... Are not linked with the CPU 11 returning from the power saving mode.
It is possible to return from U11 at any timing. For example, for the peripheral devices 121, 122, ... Which are not always used, such as a hard disk, the restoration interrupt mask instruction is set and the CPU 1
After the 1 is restored, when the access is required, the power saving mode forced restoration register 13144 is accessed and the control is performed to restore the power saving mode.

[0034]

As described above, according to the present invention,
Since there is a means for controlling the sequence of the transition to the power saving mode and the return to the original state between the CPU and the peripheral device, when the transition to the power saving mode or the return to the original state is performed. Even if a peripheral device such as a ROM or a RAM that is accessed by the CPU is shifted to the power saving mode, or the peripheral device is operated by using the PLL, the shift to the power saving mode and the return to the original state are performed. Can be done normally. Furthermore, as a result, more power saving can be achieved. Also,
The order of the transition to the power saving mode and the return to the original state can be changed simply by resetting the time information in the register connected to the bus, so it is possible to flexibly respond to changes in the system configuration and expand further. It becomes an information processing device with high property. Further, since the CPU notifies the peripheral device of the shift to the power saving mode through the bus provided as a standard, there is no need to provide an output line or the like, and the system configuration can be changed flexibly. There is no loss of the CPU's feature of being compatible with.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing device X according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a peripheral device control circuit which constitutes the information processing device X according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of an interrupt control circuit configuring the information processing device X according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of a clock control circuit 16 included in the information processing device X according to the embodiment of the present invention.

FIG. 5 is a flowchart showing a procedure for shifting to the power saving mode in the information processing apparatus X according to the embodiment of the present invention.

FIG. 6 is a flowchart showing a procedure for returning from the power saving mode in the information processing device X according to the embodiment of the present invention.

[Explanation of symbols]

11 ... CPU 14 ... Interrupt control circuit 16 ... Clock control circuit 111, 161, ... PLL (Phase Locked Loop) 121, 122, ... Peripheral devices 131, 132, ... Peripheral device control circuit 141 ... Return interrupt generation circuit 142 ... Interrupt mask register 144 ... Interrupt delay timer setting register 145 ... Interrupt delay timer circuit 151 ... High-speed oscillator 152 ... Low speed oscillator 165 ... Sub clock selection circuit 181 ... System bus 191 ... External interrupt signal 193 ... Return interrupt signal 194 ... Delayed interrupt signal 1311 ... Peripheral device main control circuit 1312 ... Power saving mode control circuit 1313 ... Main clock mask circuit 1431 ... External interrupt mask circuit 1432, 1433, ... Internal interrupt mask circuit 1621 ... High-speed clock control circuit 1622 ... Main clock control circuit 1631 ... Main clock stop control register 1632 ... Main clock stop timer setting register 1633 ... Main clock stop timer circuit 1641 ... Main clock recovery timer setting register 1642 ... Main clock recovery timer circuit 1711 ... High-speed clock signal 1712 ... Low-speed clock signal 1721 ... Main clock signal 1722 ... Sub clock signal 1821, 1822, ... Control lines 1921, 1922, ... Internal interrupt signal 13141 ... Power saving mode transition control register 13142 ... Power saving mode transition timer setting register 13143 ... Power saving mode recovery timer setting register 13144 ... Power saving mode forced recovery register 13145 ... Power saving mode transition timer circuit 13146 ... Power saving mode recovery timer circuit 13151 ... Interrupt mask register 13152 ... Interrupt mask circuit S101, S102, ... Processing procedure (step)

Claims (13)

[Claims] 1. A CPU having a function of shifting to a power saving mode under a predetermined condition, one or a plurality of peripheral devices, and the CPU are connected via a predetermined bus, and the CPU is in the power saving mode. In the information processing apparatus, the peripheral device control means controls the peripheral device to shift to the power saving mode in response to the shift of the above. Information processing, characterized in that the corresponding peripheral device is shifted to the power saving mode after a lapse of a predetermined power saving mode shift time after a predetermined access indicating the shift to the power saving mode. apparatus. 2. The information processing apparatus according to claim 1, wherein the peripheral device control means comprises a power saving mode shift control register which is accessed by the CPU. 3. The information according to claim 1, further comprising a power saving mode shift timer setting register provided so that the power saving mode shift time for each of the peripheral devices can be set via the bus. Processing equipment. 4. A CPU having a function of returning from the power saving mode on the basis of input of a predetermined return interrupt signal when in a state of shifting to a predetermined power saving mode, and one or a plurality of peripheral devices. Peripheral device control means connected to the CPU via a predetermined bus and controlling the peripheral device to return from the power saving mode in response to the return of the CPU from the power saving mode. The processing device includes an interrupt signal delay means for outputting a delayed interrupt signal obtained by delaying the restored interrupt signal by a predetermined restored interrupt signal delay time, and the CPU saves power according to the input of the delayed interrupt signal. An information processing apparatus configured to return from a mode. 5. The information processing apparatus according to claim 4, further comprising an interrupt delay timer setting register provided so that the return interrupt signal delay time can be set via the bus. 6. A predetermined return interrupt signal when the CPU and one or more peripheral devices are connected to the CPU via a predetermined bus and the peripheral device is in a predetermined power saving mode. In the information processing apparatus, the peripheral device control means controls the peripheral device to return from the power saving mode based on the input of An information processing apparatus, which is configured to return the corresponding peripheral device from the power saving mode after the elapse of the power saving mode recovery time. 7. The information processing apparatus according to claim 6, further comprising a power-saving mode return timer setting register provided so that the power-saving mode return time for each of the peripheral devices can be set via the bus. . 8. A return interrupt mask provided so that a return interrupt mask instruction that does not cause a return from the power saving mode in response to the power saving mode return signal by the peripheral device control means can be set via the bus. A register and a force recovery instruction for forcibly returning the corresponding peripheral device from the power saving mode by the peripheral device control means regardless of the register and the power saving mode return signal are set so as to be set through the bus. The information processing apparatus according to claim 6, further comprising: a power saving mode forcible return register for each of the peripheral devices. 9. An internal interrupt signal generating means for generating a predetermined internal interrupt signal for each of the peripheral devices under a predetermined condition, and either the internal interrupt signal or an external interrupt signal input from the outside is input. A return interrupt signal generating means for generating the return interrupt signal at the time,
The information processing apparatus according to claim 6, further comprising: 10. The recovery interrupt signal generating means,
An internal / external interrupt mask register provided so that an internal / external interrupt mask instruction for ignoring the internal interrupt signal and the external interrupt signal and generating the return interrupt signal can be set via the bus. The information processing apparatus according to claim 9, which is provided. 11. A CPU having a function of returning from the power saving mode based on input of a predetermined return interrupt signal after shifting to the power saving mode under a predetermined condition, and the CP.
One or a plurality of peripheral devices connected to U via a predetermined bus, and the peripheral devices to the power saving mode in response to the shift of the CPU to the power saving mode and the return from the power saving mode. In a power-saving information processing device comprising a peripheral device control means for controlling transition and return from the power saving mode, a delayed interrupt signal obtained by delaying the return interrupt signal by a predetermined return interrupt signal delay time is output. A predetermined power saving mode transition time elapses after the peripheral device control means includes a predetermined access indicating that the CPU shifts to the power saving mode via the bus. Later, the corresponding peripheral device is shifted to the power saving mode, and the CP
An information processing apparatus, wherein U is configured to recover from the power saving mode in response to the input of the delayed interrupt signal. 12. The peripheral device control means is configured to recover the corresponding peripheral device from the power saving mode after a lapse of a predetermined power saving mode recovery time after inputting the return interrupt signal. Item 11. The information processing device according to item 11. 13. A configuration in which one or more of the return interrupt signal delay time, the power saving mode transition time, and the power saving mode return time can be set in a predetermined register via the bus. 11. The information processing device according to either 11 or 12.