JP2003115512A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2003115512A JP2003115512A JP2001307729A JP2001307729A JP2003115512A JP 2003115512 A JP2003115512 A JP 2003115512A JP 2001307729 A JP2001307729 A JP 2001307729A JP 2001307729 A JP2001307729 A JP 2001307729A JP 2003115512 A JP2003115512 A JP 2003115512A
- Authority
- JP
- Japan
- Prior art keywords
- clip
- source pad
- semiconductor device
- solder
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明はワイヤレス構造を有
する半導体装置に関するものである。
【０００２】
【従来の技術】近年の携帯電話等の小型機器は目覚しい
発展を遂げ、これらの小型機器の品質を向上させること
が、開発者に課されたテーマである。ユーザサイドはよ
り安定した優良の半導体装置を求め、開発サイドはその
需要を満たすため半導体装置の不良品率をいかに低下さ
せようと努力している。
【０００３】図３は、従来のワイヤレス構造を有する半
導体装置（縦型ＭＯＳＦＥＴ）である。この半導体装置
は主に、携帯電話におけるスイッチング電圧に用いるこ
とが多い。
【０００４】図３が表す平面図の半導体装置は、半導体
基板の上にあるソースパッド（１０１）、パッシベーシ
ョン膜としてのシリコン窒化膜（１０２）、ゲートパッ
ド（１０３）にて構成されている。ソースパッド（１０
１）は、半導体基板の表面の９０％以上を占める。シリ
コン窒化膜（１０２）はソースパッド（１０１）の外周
を取り囲むように形成している。ゲートパッド（１０
３）は、半導体基板の一角に四角形を為し、外部のリー
ドフレームとワイヤボンディングにて接続されている。
クリップ（１０４）は銅板の一枚板からなり、長方形を
したクリップ（１０４ａ）が図３に示すように、ソース
パッド（１０１）の略中央となるように配置されてい
る。クリップ（１０４）の形状については、後述する図
４について述べる。半田は、ソースパッド（１０１）表
面とクリップ（１０４ａ）とを密着させるための接着剤
としての働きがあり、ソースパッド（１０１）上に広が
ったものが半田もれ（１０５）である。
【０００５】図４は、図３のＹ―Ｙ線断面図を表す。図
中、図３と同一構成要素には、同一符号を付した。半導
体チップ（１０６）の表面上の両端にシリコン窒化膜
（１０２）が形成され、それらシリコン窒化膜（１０
２）の中央にソースパッド（１０１）が形成されてい
る。クリップ（１０４）は、クリップ（１０４ａ）が半
導体チップ（１０６）と合金電極（１０７）を介し固着
し、クリップ（１０４ａ）の一端が斜め上方向に延び
て、再び半導体チップ（１０６）の表面と平行となるよ
うに半導体チップ（１０６）外部へと延在している。
【０００６】
【発明が解決しようとする課題】これらの半導体装置に
おいて、不良品率を増加させている原因のひとつには、
半田の酸化（腐食）が挙げられる。図３において、半田
はクリップ（１０４ａ）の外側にまではみ出し、半田も
れ（１０５）として、ソースパッド（１０１）の表面上
を広範囲に渡って広がる。
【０００７】一方、半導体装置には図４に示す矢印が示
す方向から湿気が入り込んでくる。これはワイヤレス構
造であるがために、クリップ（１０４）が板状をしてい
るため、湿気（水分）がその板状の表面上を進入してく
る。半田もれ（１０５）と湿気（水分）とが接触するこ
とで酸化（腐食）が始まる。酸化（腐食）が進行する
と、その箇所においては電気的に不通となり、正常な動
作が困難となり、耐圧の点で劣化するという欠点を有し
ていた。
【０００８】本願は上記欠点に鑑みて為されたものであ
り、ソースパッド（１０１）の面積を縮小することで、
半導体装置全体の耐湿性を向上し、且つ半田もれ（１０
５）が広がる範囲を制限するものである。
【０００９】
【課題を解決するための手段】本願は、半導体チップ
と、前記半導体チップ上に形成したパッシベーション膜
と、前記パッシベーション膜に開口したパッドと、外部
と接続し金属板で形成したクリップの先端部と、前記ク
リップの先端部が前記パッド内の前記半導体チップの表
面に固着するワイヤレス構造の半導体装置において、前
記パッシベーション膜と前記クリップ先端部とのマージ
ン（余地）が１００μｍ以下であることを特徴とする半
導体装置を提供する。
【００１０】
【発明の実施の形態】図１は本願のワイヤレス構造を有
する半導体装置（縦型ＭＯＳＦＥＴ）を表す平面図であ
る。（１）はソースパッド、（２）はシリコン窒化膜、
（３）はゲートパッド、（４）はクリップ、（４ａ）は
クリップ（４）の先端、（５）は半田もれ、をそれぞれ
表す。ｄはシリコン窒化膜（２）とクリップ（４ａ）と
が形成するマージン（余地）を表す。
【００１１】図１が表す平面図の半導体装置は、半導体
基板の上にあるソースパッド（１）、シリコン窒化膜
（２）、ゲートパッド（３）にて構成する。ソースパッ
ド（１）は、半導体基板の表面の略中央に配置する。こ
のとき、ソースパッド（１）が占める面積は、半導体チ
ップ表面全体に対して約６０％以上の面積を有する。シ
リコン窒化膜（２）はソースパッド（１）の外側のゲー
トパッド（３）を除くすべての領域を被覆するパッシベ
ーション膜である。ゲートパッド（３）は、半導体基板
の一角に四角形を為し、外部のリードフレームとワイヤ
ボンディングにて接続する。
【００１２】クリップ（４）は銅板の一枚板からなり、
長方形をしたクリップ（４ａ）が図１に示すように、ソ
ースパッド（１）の略中央となるように配置されてい
る。このとき、クリップ（４ａ）とシリコン窒化膜
（２）が形成するマージンｄは１００μｍ程度以下とな
るように形成する。また、クリップ（４）の形状につい
ては、後述する図２について述べる。
【００１３】半田は、ソースパッド（１）表面とクリッ
プ（４ａ）とを密着させるための接着剤としての働きが
あり、シリコン窒化膜（２）上に広がったものが半田も
れ（５）である。本願の特徴は、半田もれ（５）がマー
ジンｄの範囲に留まるように、ソースパッド（１）を形
成することである。
【００１４】図２は、図１のＸ―Ｘ線断面図を表す。図
中、図１と同一構成要素には、同一符号を付した。
（６）は半導体基板、（７）は合金電極、を表す。
【００１５】半導体基板（６）は以下の構成である。シ
リコン半導体基板の上にエピタキシャル成長法によって
形成したエピタキシャル層を形成し、エピタキシャル層
内には、不純物拡散により拡散領域を形成し、多数のセ
ルが存在する。これら多数のセルが動作することで、半
導体装置は機能する。
【００１６】以上のプロセスで形成した半導体基板
（６）上の略中央にソースパッド（１）を形成する。ソ
ースパッド（１）は半導体基板（６）上のシリコン窒化
膜（２）の略中央部を開口してソースアルミ電極の表面
を露出するように形成する。
【００１７】半導体チップ（６）の表面上の両端にシリ
コン窒化膜（２）が形成され、それらシリコン窒化膜
（２）の中央にソースパッド（１）が形成されている。
クリップ（４）は、先端のクリップ（４ａ）が半導体チ
ップ（６）と合金電極（７）を介して接続される。クリ
ップ（４）の一端が斜め上方向に延びて、再び半導体チ
ップ（６）の表面と平行となるように半導体チップ
（６）外部へと延在している。
【００１８】半田もれ（５）は、半導体基板（１）表面
に付した合金電極（７）の上に形成される。このとき、
半田もれ（５）はその周囲に配置されているシリコン窒
化膜（２）よりも高く、盛り上がるように形成する。ソ
ースパッド（１）の周囲には、シリコン窒化膜（４）が
壁として存在するため、半田もれ（５）が必要以上に広
がることを防止する。つまり、シリコン窒化膜（２）
が、半田もれ（５）のストッパーとしてのはたらきを担
う。また、合金電極（７）は半田と半導体基板（６）と
を接続する接着剤としてのはたらきがある。
【００１９】次に、耐湿試験（ＰＣＴ；pressure cooke
r test）の実験結果について、本願と従来例とを比較す
る。耐湿試験は、温度１２０℃、気圧２atom、湿度５０
〜６０％の条件下において、２５時間以上電圧を印加し
た。図３に示す従来例では、３０個のサンプルを用意し
て上記条件下で行った。その結果、２０個サンプルの特
性が劣化した。一方、ソースパッド（１）を縮小した本
願においても同様に３０個のサンプルを用意して同様な
条件下で耐湿試験を実施した。その結果、３０個すべて
において特性が劣化することはなかった。加えて、耐湿
試験時間を２倍の５０時間に延長しても、サンプル３０
個すべてが耐湿性を維持するという結果を得た。
【００２０】以上より、クリップ（４a）の外周にソー
スパッド（１）のマージンｄを１００μm程度以下に抑
え、ソースパッド（１）を縮小することで耐湿性が向上
する。
【００２１】尚、本願ではＭＯＳＦＥＴのワイヤレス構
造について説明したが、本願のクリップ（４）に相当す
るようなワイレス構造を有し、パッド部分がクリップ
（４ａ）に対して充分広く形成した半導体装置について
有効なものである。
【００２２】
【発明の効果】以上より、ソースパッド（１）を縮小化
することで、耐湿性が向上する。また、シリコン窒化膜
（２）が半田もれ（５）のストッパーとしての働きを
し、半田もれ（５）が必要以上に拡大することを防止す
る。これにより、湿気によって半田が腐食する領域を最
低限に留めることができ、半導体装置が不安定な動作を
する可能性を低減できる。よって、耐圧性が劣化しにく
いという効果を有する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a wireless structure. 2. Description of the Related Art In recent years, small devices such as mobile phones have made remarkable developments, and improving the quality of these small devices has been a theme for developers. The user side seeks a more stable and superior semiconductor device, and the development side strives to reduce the reject rate of the semiconductor device to meet the demand. FIG. 3 shows a conventional semiconductor device (vertical MOSFET) having a wireless structure. This semiconductor device is often used mainly for a switching voltage in a mobile phone. The semiconductor device shown in the plan view of FIG. 3 includes a source pad (101) on a semiconductor substrate, a silicon nitride film (102) as a passivation film, and a gate pad (103). Source pad (10
1) occupies 90% or more of the surface of the semiconductor substrate. The silicon nitride film (102) is formed so as to surround the outer periphery of the source pad (101). Gate pad (10
In 3), a square is formed at one corner of the semiconductor substrate, and the semiconductor substrate is connected to an external lead frame by wire bonding.
The clip (104) is formed of a single copper plate, and the rectangular clip (104a) is disposed so as to be substantially at the center of the source pad (101) as shown in FIG. The shape of the clip (104) will be described later with reference to FIG. The solder has a function as an adhesive for bringing the surface of the source pad (101) into close contact with the clip (104a), and the solder spread (105) is spread on the source pad (101). FIG. 4 is a sectional view taken along line YY of FIG. In the figure, the same components as those in FIG. 3 are denoted by the same reference numerals. Silicon nitride films (102) are formed at both ends on the surface of the semiconductor chip (106), and these silicon nitride films (10
A source pad (101) is formed at the center of 2). The clip (104) is such that the clip (104a) is fixed to the semiconductor chip (106) via the alloy electrode (107), one end of the clip (104a) extends obliquely upward, and the clip (104a) again It extends to the outside of the semiconductor chip (106) so as to be parallel. [0006] One of the causes of an increase in the defective product rate in these semiconductor devices is as follows.
Oxidation (corrosion) of solder may be mentioned. In FIG. 3, the solder protrudes to the outside of the clip (104a) and spreads over a wide area on the surface of the source pad (101) as a solder leak (105). On the other hand, moisture enters the semiconductor device from the direction indicated by the arrow shown in FIG. Since this is a wireless structure, since the clip (104) has a plate shape, moisture (moisture) enters on the plate-like surface. Oxidation (corrosion) starts when the solder leak (105) comes into contact with moisture (moisture). As oxidation (corrosion) progresses, the portion is electrically disconnected, making normal operation difficult and deteriorating in terms of withstand voltage. The present invention has been made in view of the above-mentioned drawbacks, and by reducing the area of the source pad (101),
The moisture resistance of the entire semiconductor device is improved, and solder leakage (10
5) limits the spread range. [0009] The present invention relates to a semiconductor chip, a passivation film formed on the semiconductor chip, a pad opened in the passivation film, and a clip formed of a metal plate connected to the outside. In a semiconductor device having a wireless structure in which a tip and a tip of the clip are fixed to a surface of the semiconductor chip in the pad, a margin between the passivation film and the tip of the clip is 100 μm or less. A semiconductor device is provided. FIG. 1 is a plan view showing a semiconductor device (vertical MOSFET) having a wireless structure according to the present invention. (1) is a source pad, (2) is a silicon nitride film,
(3) indicates a gate pad, (4) indicates a clip, (4a) indicates a tip of the clip (4), and (5) indicates a solder leak. d represents a margin formed by the silicon nitride film (2) and the clip (4a). The semiconductor device shown in the plan view of FIG. 1 includes a source pad (1), a silicon nitride film (2), and a gate pad (3) on a semiconductor substrate. The source pad (1) is arranged substantially at the center of the surface of the semiconductor substrate. At this time, the area occupied by the source pad (1) is about 60% or more of the entire surface of the semiconductor chip. The silicon nitride film (2) is a passivation film covering all regions except the gate pad (3) outside the source pad (1). The gate pad (3) forms a square at one corner of the semiconductor substrate and is connected to an external lead frame by wire bonding. The clip (4) is made of a single sheet of copper plate,
As shown in FIG. 1, the rectangular clip (4a) is disposed so as to be substantially at the center of the source pad (1). At this time, the margin (d) formed by the clip (4a) and the silicon nitride film (2) is formed to be about 100 μm or less. The shape of the clip (4) will be described later with reference to FIG. The solder has a function as an adhesive for bringing the surface of the source pad (1) into close contact with the clip (4a), and the solder spread on the silicon nitride film (2) is the solder leakage (5). is there. A feature of the present application is that the source pad (1) is formed so that the solder leakage (5) remains within the margin d. FIG. 2 is a sectional view taken along line XX of FIG. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals.
(6) represents a semiconductor substrate, and (7) represents an alloy electrode. The semiconductor substrate (6) has the following configuration. An epitaxial layer formed by an epitaxial growth method is formed on a silicon semiconductor substrate. In the epitaxial layer, a diffusion region is formed by impurity diffusion, and a large number of cells exist. The semiconductor device functions by operating these many cells. A source pad (1) is formed substantially at the center on the semiconductor substrate (6) formed by the above process. The source pad (1) is formed so as to open a substantially central portion of the silicon nitride film (2) on the semiconductor substrate (6) to expose the surface of the source aluminum electrode. Silicon nitride films (2) are formed at both ends on the surface of the semiconductor chip (6), and a source pad (1) is formed at the center of the silicon nitride films (2).
The clip (4) has the clip (4a) at the tip connected to the semiconductor chip (6) via the alloy electrode (7). One end of the clip (4) extends obliquely upward and extends outside the semiconductor chip (6) again so as to be parallel to the surface of the semiconductor chip (6). The solder leakage (5) is formed on the alloy electrode (7) provided on the surface of the semiconductor substrate (1). At this time,
The solder leak (5) is higher than the silicon nitride film (2) disposed around the solder leak and is formed so as to swell. Since the silicon nitride film (4) is present as a wall around the source pad (1), the solder leakage (5) is prevented from spreading more than necessary. That is, the silicon nitride film (2)
However, it acts as a stopper for the solder leak (5). Further, the alloy electrode (7) has a function as an adhesive for connecting the solder and the semiconductor substrate (6). Next, a moisture resistance test (PCT; pressure cooke)
r test) is compared between the present application and the conventional example. The moisture resistance test was conducted at a temperature of 120 ° C, a pressure of 2 atoms, and a humidity of 50.
Under the condition of ２５60%, a voltage was applied for 25 hours or more. In the conventional example shown in FIG. 3, 30 samples were prepared and performed under the above conditions. As a result, the characteristics of the 20 samples deteriorated. On the other hand, also in the present application in which the source pad (1) was reduced, 30 samples were similarly prepared and subjected to a moisture resistance test under similar conditions. As a result, the characteristics did not deteriorate in all of the 30 samples. In addition, even if the moisture resistance test time is doubled to 50 hours, the sample 30
The result was that all the pieces maintained moisture resistance. As described above, the margin d of the source pad (1) on the outer periphery of the clip (4a) is suppressed to about 100 μm or less, and the moisture resistance is improved by reducing the size of the source pad (1). Although the wireless structure of the MOSFET has been described in the present application, a semiconductor device having a wireless structure corresponding to the clip (4) of the present invention and a pad portion formed sufficiently wide with respect to the clip (4a). It is valid. As described above, the moisture resistance is improved by reducing the size of the source pad (1). Further, the silicon nitride film (2) functions as a stopper for the solder leak (5), and prevents the solder leak (5) from expanding more than necessary. Accordingly, the region where the solder is corroded by moisture can be minimized, and the possibility of the semiconductor device performing unstable operation can be reduced. Therefore, there is an effect that the pressure resistance is hardly deteriorated.
【図面の簡単な説明】 【図１】本願の実施の形態を表す平面図である。 【図２】本願の実施の形態を表す断面図である。 【図３】従来例を表す平面図である。 【図４】従来例を表す断面図である。[Brief description of the drawings] FIG. 1 is a plan view illustrating an embodiment of the present application. FIG. 2 is a sectional view illustrating an embodiment of the present application. FIG. 3 is a plan view illustrating a conventional example. FIG. 4 is a cross-sectional view illustrating a conventional example.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 池田 憲史 大阪府守口市京阪本通２丁目５番５号 三 洋電機株式会社内 (72)発明者 及川 慎 大阪府守口市京阪本通２丁目５番５号 三 洋電機株式会社内 (72)発明者 圓井 幹将 大阪府守口市京阪本通２丁目５番５号 三 洋電機株式会社内 (72)発明者 秋庭 隆史 大阪府守口市京阪本通２丁目５番５号 三 洋電機株式会社内 Ｆターム(参考） 5F044 RR00 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kenji Ikeda 2-5-5 Keihanhondori, Moriguchi-shi, Osaka 3 Yo Electric Co., Ltd. (72) Inventor Shin Oikawa 2-5-5 Keihanhondori, Moriguchi-shi, Osaka 3 Yo Electric Co., Ltd. (72) Inventor Mikimasa Eni 2-5-5 Keihanhondori, Moriguchi-shi, Osaka 3 Yo Electric Co., Ltd. (72) Inventor Takashi Akiba 2-5-5 Keihanhondori, Moriguchi-shi, Osaka 3 Yo Electric Co., Ltd. F term (reference) 5F044 RR00
Claims (1)
プの表面に固着するワイヤレス構造の半導体装置におい
て、 前記パッシベーション膜と前記クリップ先端部とのマー
ジン（余地）が１００μｍ以下であることを特徴とする
半導体装置。Claims: 1. A semiconductor chip, a passivation film formed on the semiconductor chip, a pad opened in the passivation film, a tip of a clip connected to the outside and formed of a metal plate, A semiconductor device having a wireless structure in which a tip of the clip is fixed to a surface of the semiconductor chip in the pad, wherein a margin between the passivation film and the tip of the clip is 100 μm or less. apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001307729A JP2003115512A (en) | 2001-10-03 | 2001-10-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001307729A JP2003115512A (en) | 2001-10-03 | 2001-10-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003115512A true JP2003115512A (en) | 2003-04-18 |
Family
ID=19127152
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001307729A Pending JP2003115512A (en) | 2001-10-03 | 2001-10-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003115512A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006040928A (en) * | 2004-07-22 | 2006-02-09 | Nec Electronics Corp | Semiconductor device |
| US20180166397A1 (en) * | 2016-12-09 | 2018-06-14 | Fuji Electric Co., Ltd. | Semiconductor device |
| US10128345B2 (en) | 2016-12-09 | 2018-11-13 | Fuji Electric Co., Ltd. | Semiconductor device |
| US11211353B2 (en) | 2019-07-09 | 2021-12-28 | Infineon Technologies Ag | Clips for semiconductor packages |
| US11387210B2 (en) | 2019-03-15 | 2022-07-12 | Fuji Electric Co., Ltd. | Semiconductor module and manufacturing method therefor |
-
2001
- 2001-10-03 JP JP2001307729A patent/JP2003115512A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006040928A (en) * | 2004-07-22 | 2006-02-09 | Nec Electronics Corp | Semiconductor device |
| JP4550503B2 (en) * | 2004-07-22 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US20180166397A1 (en) * | 2016-12-09 | 2018-06-14 | Fuji Electric Co., Ltd. | Semiconductor device |
| JP2018098282A (en) * | 2016-12-09 | 2018-06-21 | 富士電機株式会社 | Semiconductor device |
| US10128345B2 (en) | 2016-12-09 | 2018-11-13 | Fuji Electric Co., Ltd. | Semiconductor device |
| US10332845B2 (en) | 2016-12-09 | 2019-06-25 | Fuji Electric Co., Ltd. | Semiconductor device |
| US11387210B2 (en) | 2019-03-15 | 2022-07-12 | Fuji Electric Co., Ltd. | Semiconductor module and manufacturing method therefor |
| US11211353B2 (en) | 2019-07-09 | 2021-12-28 | Infineon Technologies Ag | Clips for semiconductor packages |
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