JP2003109396A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce occupancy area of a redundancy circuit by making apparently a defective block nothing from a user system side and omitting the control, in a flash memory. SOLUTION: This device is provided with a cell array having a plurality of main body memory blocks and redundancy blocks, row sub-decoders provided corresponding to each block, block shift registers selecting row sub-decoders corresponding to each stage register output, and a defective block flag circuit storing a flag indicating that a corresponding block is a defective block, in the case of increment by data shift operation of the block shift register, a defective block is made a non-activation state by bypassing a register corresponding to a defective block flag circuit in which a flag exists using a flag, continued block addresses in which a defective block is omitted are mapped on a cell array.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a memory block and a redundancy block, which is used, for example, in a flash type memory integrated circuit capable of batch erasing in block units. It is a thing.

[0002]

2. Description of the Related Art In a flash memory, for example, in general, when a defective erase block, which is a unit of batch erasing, exists, a defective block is replaced with a redundant block (redundancy block) prepared in advance. A redundancy circuit is included to realize the function.

FIG. 14 shows an example of a flash memory equipped with a conventional redundancy circuit.

This flash memory has a plurality of (many) main body memory blocks and a plurality (several to several dozen) of redundancy blocks, and a cell array 10 corresponding to the respective blocks. A row decoder (row decoder) 13 and a row sub decoder (row sub decoder) 14 for selecting a block corresponding to an address specified from the outside and a defective block of the plurality of main body memory blocks are provided. Redundancy detection to detect defective address (redundancy address to be relieved)
n) The circuit 15 and a row predecoder (row) which disables selection of the main body memory block when the redundancy address is detected by the redundancy detection circuit 15.
pre decoder) 16, and a redundancy selection signal generation circuit (included in the redundancy detection circuit 15) for selecting and designating a desired redundancy block among a plurality of redundancy blocks when the redundancy address is detected by the redundancy detection circuit 15. To have.

Since the redundancy circuit in the above flash memory occupies the area on the chip including the wiring for connecting the respective constituent parts to each other, especially when the die size is reduced in consideration of the chip cost. If possible, it is required not to introduce a redundancy circuit or to make the circuit occupying area as small as possible. Further, when the redundancy circuit is not introduced, or when there are more defective blocks than the redundancy circuit can replace, the user system must manage the defective blocks.

Therefore, conventionally, for example, after writing a specific data pattern in a defective block during a product test, the product is shipped, and the user system side reads the data of all the blocks to detect the defective block, and to determine the address of the defective block. A method of managing so as not to access is adopted.

[0007]

As described above, the conventional flash memory having a redundancy circuit for performing replacement in units of memory blocks requires a controller dedicated to the flash memory in order to manage defective blocks. It is general and has a problem of imposing a burden on the user system.

The present invention has been made to solve the above-mentioned problems, and apparently no defective block exists from the user system side, the management of the defective block on the user system side can be omitted, and the circuit occupying area can be reduced. An object of the present invention is to provide a semiconductor memory device capable of realizing a small redundancy circuit.

[0009]

A semiconductor memory device of the present invention includes a cell array having a plurality of main body memory blocks and a plurality of redundancy blocks, a row decoder for selecting a block corresponding to an externally designated address, and A row sub-decoder provided corresponding to each of the blocks, a block shift register included in the row decoder, having a register corresponding to each of the blocks, and selecting a corresponding row sub-decoder by output of each stage register, A defective block flag circuit included in the row decoder, provided corresponding to each of the blocks, and storing a defective block flag indicating that the corresponding block is a defective block. When incrementing by shift operation, defective block By registering a register corresponding to a defective block flag circuit having a flag by using the defective block flag, the defective block is inactivated, and consecutive block addresses excluding the defective block are mapped on the cell array. Is characterized by.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
3 shows a block configuration of a NAND flash memory according to the embodiment.

This flash memory is different from the flash memory of the conventional example described above with reference to FIG. 14 mainly in the following points, and is otherwise the same, and therefore is designated by the same reference numeral as in FIG.

In this flash memory, a row decoder 13a for selecting a block corresponding to an externally designated address is a row sub-decoder.
A block shift register (Block Shift Register) 20 for selectively designating (rowsub decoder) 14 and a bad block flag circuit (Bad Block Flag) 18 are included. When the block shift register 20 is incremented by the data shift operation, the defective block flag circuit 18 is configured to bypass the register stage corresponding to the block in which the defective block flag exists.

In FIG. 1, a cell array 10
Has a plurality (a large number) of main body memory blocks and a plurality (several to several ten) of redundancy blocks as memory blocks.

Row sub decoder 14
Are provided corresponding to each memory block.

The row decoder 13a has a register corresponding to each block, and a row sub decoder corresponding to each stage register output.
Select Block Shift Register (Block Shift Reg
20) and a bad block flag circuit (Bad Block fla) that stores a bad block flag indicating that the block is a bad block, corresponding to each main body memory block.
g) Including 18.

In this case, at the time of increment by the data shift operation of the block shift register 20, for the register corresponding to the defective block flag circuit 18 in which the defective block flag exists, the defective block flag is used to bypass between the input and output of the register. By doing so, the defective block is made inactive, and continuous block addresses excluding the defective block are mapped on the cell array.

A sense amplifier (sence amp.) 21 is provided at one end of the cell array 10 in the column direction, and an output buffer (Output Buffer) 22 is a sense amplifier (sence amp.) 21. The read output of is output to the outside.

Command Register 23
Has a general configuration, which takes in various command inputs in synchronization with the external clock WEN and generates control signals for activating a series of operations such as reading, writing, and erasing of the flash memory.

The sequencer 24 controls the state of each circuit according to the control signal from the command register 23, and controls a series of internal operations such as reading, writing and erasing of the flash memory. A block address register 25 has a state machine for controlling state transitions as shown in FIG.

Word line / select gate driver (CG,
SG driver) 26 sends signals CGi, SGD,
It supplies SGS.

Write / Read Driver (VRDEC Drive
r) 27 supplies the write voltage Vpgmh or the read voltage Vreadh to the input node VRDEC of the row sub-decoder 14, as will be described later with reference to FIG.

The charge pump (step-up circuit) 28 is controlled by the sequencer 24 to perform a step-up operation and write voltage.
Vpgm, a write non-selected word line voltage Vpass, a read voltage Vread, and an erase voltage Vera are generated, and required voltages are supplied to the word line / select gate driver 26 and the write / read driver 27.

Address Register 29
During the period when the signal ADDL from the sequencer 24 is "H",
Column address, in synchronization with external clock WEN
It takes in the page address and holds it for the subsequent operation period.

The block address register 25 is shown in FIG.
Signal AD from the sequencer 24, as described below with reference to
Io synchronized with external clock WEN while DL is "H"
An address is set by fetching i (i = 0-7), and this address is set in the block shift register 20 as an address initial value.

The NAND type flash memory having the above structure has a defective block flag circuit 18 for storing a defective block flag corresponding to each block as an erase unit, each stage register of the block shift register 20, and a row sub-decoder. Have 14.

When selecting the erase block, the block shift register 20 and the block address register 25
Set the initial address value from the block shift register
A method for selecting an erase block corresponding to address data input from the outside by shifting 20 data in order from the start address and transferring the selected data to the row sub-decoder 14 corresponding to the selected block for activation control. Has been adopted.

In the data shift operation of the block shift register 20, a defective block flag exists in the register corresponding to the defective block flag circuit 18, and the defective block flag is used to bypass the input / output of the register, thereby causing a defective state. It is possible to deactivate a block and map a continuous block address space without defective blocks on the cell array.

Therefore, the defective block cannot be seen from the user system, management of the defective block on the user system side can be omitted, and a redundancy circuit having a small circuit occupying area can be realized.

The configuration and operation of each section in FIG. 1 will be described in detail below.

FIG. 2 shows a defective block flag circuit shown in FIG.
FIG. 9 is a circuit diagram showing a specific example of (Bad Block flag) 18.

In this defective block flag circuit, a CMOS inverter 30 to which a signal RDECE for activating the entire row decoder is input and a fuse element (metal fuse) f are connected in series between a Vcc node and a Vss node. . A latch circuit 31 including a CMOS inverter and a feedback control PMOS transistor is connected to the output node of the CMOS inverter 30.

The fuse element f is cut for a defective block detected in a test before shipping the product,
If it is not a bad block, it will not be cut (conductive state).

In the circuit of FIG. 2, when the signal RDECE for activating the entire row decoder becomes "H", "L" or "H" is latched at the output node BBLKn depending on whether the fuse element f is cut or not. . As for the defective block, since the fuse element f is blown during the test before shipping the product, the output node BBLKn is always "L" during actual use, indicating that the defective block. If it is not a bad block, the output node BBLKn is "H" in actual use.

FIG. 3 is a block shift register shown in FIG.
FIG. 6 is a circuit diagram showing a specific example by extracting one stage of each stage register of (Block Shift Register) 20.

This register includes a master / slave type register 32 controlled by complementary clocks RK and RKn, and a complementary clock BBL between an input node D and an output node Q.
A first CMOS transfer gate 33, which is switch-controlled by K and BBLKn, is connected in series, and a second CMOS which is switch-controlled complementarily to the first CMOS transfer gate 33.
The transfer gate 34 is directly connected between the data input terminal D and the data output terminal Q. The output node RDECAD of the master / slave type register
Signal is supplied to the corresponding row sub-decoder 14. The slave stage register of the master / slave type register 32 has an output node of the defective block flag circuit 18.
The BBLKn signal is input.

In the register of FIG. 3, when the defective block is supported, the node BBLKn is "H", the data of the input node D is received by the control of the clocks RK and RKn, and the output node RDECAD is set to "H". Output and output node Q
"H" is output to.

On the other hand, when it corresponds to a bad block, the node BBLKn is "L" and the output node RDECAD
"L" is output to and the input node D and the output node Q are bypassed.

That is, the block shift register in FIG.
After the selected data is transferred to the selected block, the output node RDECAD of the register stage corresponding to the row sub-decoder 14 corresponding to only one selected block is "20".
It becomes H ", indicating that the corresponding block has been selected. For a defective block, the output node RDECAD of the corresponding register stage is fixed to" L ", and therefore is always inactive.

FIG. 4 is a circuit diagram showing a specific example of the block address register 25 shown in FIG.

This block address register has a NAND gate 41 which takes in the signal ADDL from the sequencer 24 in synchronization with the external clock WEN, an inverter 42 which inverts its output, and an output of the inverter 42 which controls activation of the block address register to set a block address. Registers AR0-AR10 of multiple stages that take in the value Ioi (i = 0-7) and perform the increment operation by receiving the shift clock INC and the increment block signal
Complementary clock based on Inc-block and clock CLK
And a circuit 43 for generating RK and RKn and supplying them to each stage register of the block shift register 20.

FIG. 5 shows the row sub-decoder (row s) in FIG.
2 is a circuit diagram showing a specific example by extracting one set of NAND type cells (units) in the memory block of the ub decoder) 14 and the cell array 10. FIG.

The NAND type cell CELL has one drain side select transistor between the bit line BL and the source line SL.
STD and, for example, 16 non-volatile cell transistors CTi
And one source side select transistor STS is connected in series.

The row sub-decoder section has an input node RDECAD.
Is received at the output node RDECAD of the corresponding register stage of the block shift register 20, and the input node VRDEC receives the write voltage Vpgmh or read voltage Vreadh from the write / read driver 27 in FIG.
A precharge pulse is input to E and is configured to control the intermediate node node A to a desired potential according to the operation mode. Here, Q1 is a depletion type N channel transistor, Q2 is a P channel transistor, and Q3 is a depletion type N channel transistor.

In addition, select signal SGD line, gate signal CG
Signals SGD, CGi, from the word line / select gate driver 26 shown in FIG. 1 are connected to the i (i = 0-n) line and the select signal SGS line.
Entered by SGS. The select signal SGD line is connected to the gate of the drain side select transistor STD via the transfer gate NMOS transistor DT, and the gate signal CGi line is connected to each cell of the NAND cell via the transfer gate NMOS transistor GTi. Transistor CTi
The select signal SGS line is connected to the gate of the source side select transistor STS via the transfer gate NMOS transistor ST. Each transistor for the above transfer gate
DT, GTi, ST are controlled by the potential of the intermediate node node A of the row sub decoder, and select signals
It controls whether or not a signal can pass from the SGD line, the gate signal CGi (i = 0-N) line, and the select signal SGS line to the corresponding NAND cell side.

During the operation of the row sub-decoder, the row sub-decoder corresponding to the selected block has the node RDEC.
AD is "H".

First, by inputting a precharge pulse of amplitude Vcc to the node PRE, in the row sub-decoder corresponding to the selected block, the intermediate node node A is charged to the power supply voltage Vcc. Then, the write voltage Vpgmh or the read voltage Vreadh is applied to the input node VRDEC.

At the time of writing or reading, the write voltage Vpgmh or the read voltage Vreadh of the input node VRDEC is transferred to the intermediate node via the transistors Q1 and Q2.
It is transmitted to nodeA, which turns on the transistors DT, GTi, ST for the transfer gate, and the signals CGi, SGD, SGS from the word line / select gate driver 26 are selected to the selected word line WLi and the selected select gate. SG1, SG
Output to 2. At the time of erasing, the intermediate node node A becomes the power supply voltage VCC, and the word line WLi of the selected block is grounded via the gate signal CGi line.

In the non-selected block, the input node RDECAD is "L", the intermediate node node A is grounded through the transistor Q3, and the word line WLi becomes floating.

FIG. 6 shows the sequencer (row sub dec) in FIG.
block address register 25 in FIG.
It is a figure which shows the state transition of the state machine which controls.

In the state transition diagram shown in FIG. 6, AREG_MSB indicates the most significant bit AR10 of the block address register 25. init is the initial state (initial state), inc_bloc
k indicates an increment operation mode of the block shift register 20, and EXCFLG indicates a termination register provided in addition to the final stage register of the block shift register 20.

This state machine starts its operation when the signal SELBLK shown in FIG. 7 becomes "H". Initial state init
After transitioning from the increment block (inc_block) operation mode to the block address register 25, the signal INC is generated until the most significant bit AR10 of the block address register 25 becomes "H", that is, AREG_MSB = "H" is satisfied, and the block address is generated. register
Increment the value of 25.

FIG. 7 is a timing waveform chart showing an operation example (assuming a read operation) of the flash memory of FIG.

In FIG. 7, com_A is a command for inputting an address, com_R is a read command, BUSYn is a busy signal for notifying a busy state to the outside of the chip, and ELBLK.
Is a signal defining the timing to start the operation of transferring the selection flag to the block corresponding to the input block address, and READ is a flag defining the internal read operation. Others will be described later in the description of the operation.

Next, the operation of the flash memory shown in FIG. 1 will be described in detail with reference to FIGS.

The command register 23 fetches and reads various command inputs in synchronization with the external clock WEN.
Start a series of operations such as writing and erasing,
The sequencer 24 controls each internal operation. The charge pump 28 also generates the voltages Vread, Vpgm, and Vera necessary for reading, writing, and erasing by boosting.

The address register 29 fetches a column address and a page address in synchronization with the external clock WEN while the signal ADDL from the sequencer 24 is "H", and holds them for the subsequent operation period. .

In the read operation, first, the command com_A for inputting an address is input, and subsequently the column address, page address and block address are synchronized with the external clock WEN and the address register 29 and the address register 29 shown in FIG. It is input to the block address register 25.

The one-complement of the address data input from the outside is stored in each stage register ARi (i = 0-9) in the block address register 25 shown in FIG.

Subsequently, when the read command com_R is input, the device enters the busy state and outputs the signal BUSYn to notify the busy state to the outside of the chip. At the same time, the clock CLK is generated inside the chip, and the signal SELBLK shown in FIG. 7 becomes "H" to start the operation of transferring the selection flag to the block corresponding to the input block address.

Such an operation is performed by the sequencer (s
The state machine is defined as a part of the sequencer 24, and this state machine starts its operation when the signal SELBLK shown in FIG. 7 becomes "H".

That is, as shown in FIG. 6, the state machine starts from the initial state (initial state) init to inc_bloc.
Block address register after transition to k operation mode
Until the most significant bit AR10 of 25 becomes "H", that is, AREG_M
The signal INC is generated and the value of the block address register 25 is incremented until SB = "H" is satisfied. During this time,
Clocks RK and RKn are generated in the block shift register 25, and the data input from the input node D0 of the head register of the block shift register 20 is sequentially shifted.

Here, for example, in blocks I, J, and K,
Assuming that blocks I and K are normal (good) blocks and block J is a bad block, as shown in FIG. 7, the respective bad block flags are BBLKni = "H" and BBLKnj = ".
L "and BBL Knk =" H ". As a result, the input / output of the register stage corresponding to the defective block J is bypassed, and the output node RDECADi of the register stage corresponding to the normal (good) block I is set to" H ". At the next clock, the output node RD of the register stage corresponding to the normal (good) block K
ECADk becomes "H".

When the most significant bit AR10 of the block address register 25 becomes "H", the data is shifted to the register stage corresponding to the block L which is the selected block, and the output node RDECADl of this register stage is "H". Becomes After this, the device reads the flag READ that defines the internal read operation.
Becomes "H", and the read operation is performed for the selected block L.

In the above-mentioned operation, the case is shown in which the address of the selected block smaller than M is specified with respect to the number M of effective blocks obtained by removing the number of defective blocks from the total number of blocks. On the other hand, if the number of valid blocks M is exceeded and the address of the selected block is specified, the end register EXCFLG provided additionally to the final stage register of the block shift register 20 shown in FIG. The fact that the number of valid blocks is exceeded is fed back to the state machine of FIG.

When the address of the selected block is specified by exceeding the total number M of valid blocks excluding the number of defective blocks, the data is shifted to the end register EXCFLG,
When the shift register of the end register EXCFLG holds the data, the selection flag transfer operation of FIG. 6 ends, and the device enters the READY state.

In this case, since the block corresponding to the input address data cannot be selected, the circuit should be configured to output the status in order to inform the user system side that the selection flag transfer operation has failed. Is also possible.

For example, consider a case where the total number of blocks is 1024 and n defective blocks are present. When the user recognizes the memory area as 1024 blocks and uses it, if a block address larger than 1024-n is specified, the selection flag transfer operation fails. In this case, ROM that cannot be rewritten by the user
It is possible to use such a method that the information of the number of effective blocks is written into the area for each chip, the user reads this information, inputs it to the user system and recognizes the size of the memory area.

Further, there may be provided means for counting the number of effective blocks obtained by removing the number of defective blocks from the total number of blocks in the cell array inside the chip, and outputting the count result of this counting means to the outside.

If the number of defective blocks is estimated from the beginning and the total number of blocks exceeds the capacity specified in the specifications and the product is designed, and the number of effective blocks does not satisfy the specified capacity in the product test, Of course, it can be treated as a defective product.

<Second Embodiment> FIG. 8 shows a second embodiment of the present invention.
3 shows a block configuration of a NAND flash memory according to the embodiment.

Compared to the flash memory of the first embodiment described above with reference to FIG. 1, the flash memory of FIG. 8 is configured so that the bad block flag latch circuit 18a in the row decoder 13b latches the bad block flag. It has been changed and the sense amplifier driver (SAIO Driver) 8
0, ROM area (ROM AREA) 81 and the like are added, and the same parts as those in FIG. 1 are denoted by the same reference numerals.

That is, 10 is a cell array having a plurality (a large number) of main body memory blocks and a plurality (several to a few dozen) of redundancy blocks.
ray), 13b is a row decoder, 14 is a row sub decoder, 18a is a bad block flag latch circuit, 20 is a block shift register, and 21 is a block shift register. Sense amplifier (sence amp.), 22 is an output buffer
, 23 is a command register, 24 is a sequencer, 25 is a block address register
(Block Address Register), 26 is a word line / select gate driver (CG, SG driver), 27 is a write / read driver (VRDEC Driver), 28 is a charge pump (boost circuit), 29 is an address register (Address Register),
80 is a sense amplifier driver, and 81 is a ROM area.

That is, also in the flash memory according to the second embodiment, as in the flash memory according to the first embodiment, the block shift register 20 is provided in the row decoder 13b, and data is sequentially specified to be designated from the outside. The circuit system that selects the block corresponding to the specified address is adopted.

In the flash memory of the second embodiment, the information of the defective block flag indicating whether each block is a good block can be written in a special memory area in the device. This memory area is written / erased only during product testing, and after shipment of the product, it cannot be accessed by the user from a specific area.
The ROM area 81 is used.

The defective block flag information is read from the specific ROM area 81 to the defective block flag latch circuit 18a automatically or by inputting a specific command after the power is turned on. .
Also, the defect information for each block in the product test is latched in the defective block flag latch circuit 18a, and the information is
The ROM area 81 is writable.

The configuration and operation of each unit in FIG. 8 will be briefly described below.

In FIG. 9, one bad block flag latch circuit (Bad Block flag latch) 18a and one stage register of the block shift register (Block Address Register) 20 shown in FIG. It is a circuit diagram which shows a specific example of a structure and a connection relation.

Bad block flag latch circuit section 18a-1
Uses the logical product of the signal of the output node RDECAD of the register unit 20-1 and the set signal SET as the set input, and the reset signal RST
Latch circuit LT with the reset input
A circuit unit that outputs the BBDATAn signal by logically ANDing the output of LT and the BBLD signal, and a circuit unit that outputs the complementary BBLK signal and BBLKn by ANDing the output of the latch circuit LT and the BBFEN signal. Have and.

In the register unit 20-1, the two-input NAND gate G2 in FIG. 3 is changed to a three-input NAND gate G3 as compared with the register unit of the first embodiment described above with reference to FIG. The difference is that RDECE is added as one of the inputs, the inverter I in FIG. 3 is changed to a two-input NAND gate NA, and the BBDATAn signal is added as one of the inputs.

FIG. 10 is a timing waveform chart showing an operation example of the row decoder 13b at the product test of the flash memory of the second embodiment.

FIG. 11 is a timing waveform chart showing an operation example of writing the defective block flag information to the specific ROM area 81 after the product test of the flash memory of the second embodiment.

FIG. 12 is a timing waveform chart showing an operation example of reading the defective block flag information of a specific ROM area 81 into the defective block flag latch circuit 18a immediately after the power supply of the flash memory of the second embodiment is turned on.

FIG. 13 shows the relationship between the input / output signals of the defective block flag latch circuit 18a and the block shift register 20 shown in FIG.

Next, referring to FIGS. 8 to 13, the second
The operation of the flash memory according to the embodiment will be described in detail.

In normal operation, RDECE = "H", BBFEN = "H"
, BBLD = “L” (see FIG. 13), and according to “H” or “L” of the defective block flag BBFLAG being latched, the block shift register 20 of the block shift register 20 is operated at the time of the selection flag transfer operation shown in the first embodiment. Whether or not to bypass the corresponding register stage is determined, and the row decoder of the first embodiment is determined.
Performs the same operation as 13a.

At the time of product test, as shown in FIG.
ECE = "H", BBFEN = "L", BBLD = "L" (see Fig. 13),
The selection flag transfer operation is performed with all blocks being enabled, and each test of reading, writing, and erasing is performed.

At the beginning of all tests, the latch circuit LT of the defective flag latch circuit 18a is reset by the signal RST, and at the end of each test, the latch circuit LT of the defective flag latch circuit 18a is set for the selected block by the signal SET.

When writing defective block flag information to the ROM area 81, RDECE = "H", BBFEN = "L", BBLD = "H"
Then, as shown in FIG. 11, after setting the contents of the defective block flag latch circuit 18a in the block shift register 20, the contents of the block shift register 20 are shifted and read, and the output QM is "H". If so, write the block address to ROM area 81.

In the first read operation of the defective block flag information from the ROM area after power-on, RDECE = "H", BB
With FEN = "L" and BBLD = "L" (see FIG. 13), as shown in FIG. 12, the latch circuit LT of the defective block flag latch circuit 18a is first reset by the signal RST, and the defect read from the ROM area is read. Data is shifted and input to the block shift register 20 while referring to the address of the block, and finally, the defective flag is transferred from the shift register block shift register 20 to the latch circuit LT of the defective block flag latch circuit 18a by the signal SET.

During operation standby, RK = L, RDECE = "L", BBFE
Since N = "L" and BBLD = "L", the shift registers are all reset, but the defective block flag BBFLG is held unless the power is turned off.

In the second embodiment, as shown in FIG. 8, the ROM area 81 is assigned a normal one-block memory area, and a specific command is input when writing or reading data to or from the ROM area 81. By doing
The output RDECAD_rom of the row sub-decoder corresponding to the ROM area 81 shown in FIG. 8 becomes "H", and it is directly selected without using the shift register.

Note that the sense amplifier driver (SAIO Driver) 80 shown in FIG. 8 sets the address of the block having the defective flag to the block address according to the control from the sequencer 24 when writing the defective block information to the ROM area 81. It is received from the register 25 and transferred to the sense amplifier 21.

Further, the sense amplifier driver 80 is
In the bad block flag read operation from M area 81,
The block address of the defective block in the sense amplifier 21 is compared with the contents of the block address register 25, and if they match, the signal BACOMP is returned to the sequencer 24. As a result, the sequencer 24 receives the input of the block shift register 20.
Give "H" to D0.

Next, with reference to FIG. 10, the manner in which the defect flag is set in the defect flag latch circuit when there is a defective block in the product test will be described.

When the command com_P is input at the start of the product test, a pulse is output to the signal RST and the defect flag latches of all blocks are reset.

Thereafter, the address input command com_A is input, the block address data to be tested is input, and then the test mode command test_X is input.

During the test, the signals BBFEN and BBLD are both "L".
Therefore, in the selection flag transfer operation, the block shift register 20 performs the shift operation without bypassing all blocks. In FIG. 10, the i-th block is selected and RDECADi is "H".

After this, the device is put into operation for testing. In this example, a read operation is performed. When the read operation reveals that the selected block is defective, the signal SET is output and the defective block flag is set in the defective flag latch circuit 18a of the selected block. In FIG. 10, BBFLGi is "H" in the signal SET.

By repeating the above operation for all blocks, the defective flag is set only in the defective flag latch of the defective block.

The defective flag information of the defective block detected as a result of the above test is stored in the ROM area 81. For this storage, it is necessary to convert the information of the defective flag latch in the row decoder 13b into a block address and load it into the sense amplifier 21.

Hereinafter, this operation will be described in detail.

First, after transferring the defect flag of each block in the row decoder 13b to the block shift register 20,
At the same time when the block shift register 20 is shifted to read the data, the block address register 25 is incremented from address 0, and a defective flag exists, that is, the terminal output QM of the block shift register 20 becomes "H". At this point, the block address Ari indicated by the block address register 25 is transferred to the sense amplifier 21.

This operation is performed by the block address register 25.
Is repeated until the final address is indicated, the block addresses of all defective blocks are transferred to the sense amplifier 21 as write data to the ROM area 81.

After that, the ROM area 81 is selected and the normal write operation is performed to store the address of the defective block in the ROM area 81.

As shown in FIG. 11, when the command com_D is input, the device becomes busy and the internal clock CL
K is output. Further, the column address Aci and the block address ARi are reset to the address 0.

Next, RDECE = "H", BBFEN = "L", BBLD = "H"
As a result, the defect flag of each block in the row decoder 13b is transferred to the block shift register 20. In the example of FIG. 11, the i-th block is a defective block and the signal BBLD is set to "
By setting "H", BBDATAni is "L" and RDECADi is "H"
Has become.

This operation is simultaneously performed for all blocks, and the defective flags are transferred to the shift register side for all the blocks in which the defective flags are latched.

After that, the block shift register 20 is shifted by the clock RK, and in synchronization with this, the block address register 25 is also incremented by the signal INC.
In this case, since BBFEN and BBLD are both set to "L", the shift operation is performed on all the blocks of the block shift register 20 regardless of the presence or absence of the defect flag.

Terminal output QM of block shift register 20
When "H" is output to the block address register
The complement / Ari of the address of the defective block indicated by 25 is transferred to the sense amplifier 21 via the sense amplifier driver 80.

After this transfer, the column address is incremented, and then the block shift register 20 and the block address register 25 are incremented. In the example of FIG. 11, the kth block also has a defect flag,
The complement / ARk of the block address is transferred to the sense amplifier 21 of the column address 01h.

In the present embodiment, the defective block information is treated as a defective block address instead of a metal fuse.
Since it is stored in the ROM area 81, prior to all operations after power-on, the defective flag is set in the defective block flag latch circuit 18a in the row decoder 13b based on the address information of the defective block in the ROM area 81. Will be required. This operation will be described with reference to FIG.

In the example of FIG. 12, the above-mentioned operation is activated by the command com_E. Instead of the command com_E, it is also possible to have a configuration in which power-on is detected and automatically started. When command com_E is input, the device becomes busy and the internal clock CLK is output.

Further, the column address Aci and the block address ARi are reset to 0, and the defective flag latch circuit 18a of each block is reset by the signal RST.

Next, RDECE = "H", BBFEN = "L", BBLD = "L"
Then, all the block shift registers 20 are enabled to start shifting the block shift registers 20, and the block address register 25 also increments by the signal INC.

At the same time, the sense amplifier driver 80 compares the block address indicated by the block address register 25 with the address of the defective block in the sense amplifier 21. When the two address data match, the sequencer 24 inputs "H" to the input D0 of the head register of the block shift register 20.

In the example shown in FIG. 12, the i-th and k-th blocks are defective blocks, and when the block address register 25 becomes / ARi and / ARk, the sense amplifier driver 80 outputs the signal BACOMP. The sequencer 24 sets the input D0 of the head register of the block shift register 20 to "H".

By repeating the above operation until the block address register 25 indicates the final address, the ROM area 81
"H" is set in the register of the block shift register 20 corresponding to the block address corresponding to the address of the defective block stored in.

Finally, the signal SET is output, and the data of the block shift register 20 is transferred to the defect flag latch circuit 18a in each defective block. In FIG. 12, RD
ECADi and RDECADk become "H" due to shift operation, and signal
The defective flags BBFLGi and BBFLGk are set to "H" by SET.

[0120]

As described above, according to the semiconductor memory device of the present invention, there is apparently no defective block from the user system side, management of the defective block on the user system side can be omitted, and the circuit occupying area can be reduced. A small redundancy circuit can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a NAND flash memory according to a first embodiment of the present invention.

FIG. 2 shows a bad block flag circuit (Bad Block f) in FIG.
lag) is a circuit diagram showing a specific example.

3 is a block shift register shown in FIG.
Register) is a circuit diagram showing one concrete example by extracting one stage of each register of (Register).

FIG. 4 is a block address register (Block Add
FIG. 6 is a circuit diagram showing a specific example of ress Register).

5 is a row sub decoder in FIG.
And a circuit diagram showing a specific example of taking out one set of NAND type cells in a memory block of a cell array.

6 is a diagram showing a state transition of a state machine for controlling the block address register in FIG. 1 of the sequencer (row sub decoder) in FIG.

7 is a timing waveform chart showing an operation example (assuming a read operation) of the flash memory of FIG.

FIG. 8 is a block diagram showing a configuration of a NAND flash memory according to a second embodiment of the present invention.

9 is a schematic diagram of a bad block flag latch circuit (Bad B in FIG. 8).
FIG. 3 is a circuit diagram showing a specific example of a circuit configuration and connection relationship by taking out one lock flag latch and one stage register of each block shift register.

FIG. 10 is a timing waveform chart showing an operation example of a row decoder during a product test of the flash memory according to the second embodiment.

FIG. 11 is a timing waveform chart showing an operation example of writing defective block flag information to a specific ROM area after a product test of the flash memory according to the second embodiment.

FIG. 12 is a timing waveform chart showing an operation example of reading defective block flag information of a specific ROM area into a defective block flag latch circuit in a row decoder immediately after power-on of the flash memory according to the second embodiment.

13 is a diagram showing a relationship between the input / output signals of the defective block flag latch circuit and the block shift register shown in FIG.

FIG. 14 is a block diagram showing an example of a flash memory equipped with a conventional redundancy circuit.

[Explanation of symbols]

10 ... Cell array, 13a ... Row decoder, 14 ... Row sub decoder, 18 ... Bad block flag circuit, 20 ... Block shift register , 21 ... Sense amplifier (sence amp.), 22 ... Output buffer (Output Buffer), 23 ... Command register, 24 ... Sequencer, 25 ... Block Address Register
r), 26 ... Word line / select gate driver (CG, SG drive
r), 27 ... Write / read driver (VRDEC Driver), 28 ... Charge pump (boost circuit), 29 ... Address Register.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroto Nakai             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F term (reference) 5B025 AA03 AB01 AC01 AD01 AD13                       AE00                 5L106 AA10 CC04 CC12 CC13 CC16                       CC31 CC32 GG07

Claims (10)

[Claims] 1. A cell array having a plurality of main body memory blocks and a plurality of redundancy blocks, a row decoder for selecting a block corresponding to an externally designated address, and a row sub provided corresponding to each block. A decoder, a block shift register included in the row decoder, having a register corresponding to each block, selecting a corresponding row sub-decoder by output of each stage register, and a block shift register included in the row decoder and provided in each block A defective block flag circuit which is provided correspondingly and stores a defective block flag indicating that the corresponding block is a defective block, and the defective block flag exists when incremented by the data shift operation of the block shift register. Bad block flag circuit The semiconductor memory device is characterized in that a defective block is deactivated by bypassing the register corresponding to the defective block flag by using the defective block flag, and continuous block addresses excluding the defective block are mapped on the cell array. 2. The semiconductor memory device according to claim 1, wherein the selection flag is transferred to a block corresponding to an input block address by a data shift operation of the block shift register. 3. The semiconductor memory device according to claim 1, wherein the defective block flag circuit stores the presence / absence of a defective block flag by cutting / non-cutting a fuse element. 4. Writing / writing a defective block flag indicating whether each block of the cell array is a good block or not.
3. An erasable / readable memory area is further provided, and the defective block flag circuit has a latch circuit capable of latching a defective block flag read from the memory area. Semiconductor memory device. 5. The memory area is a specific ROM area which is written and erased only during a product test of a device and is inaccessible from a user side after product shipment. Semiconductor memory device. 6. The defective block flag is read from the specific ROM area to the defective block flag latch circuit automatically or after a specific command is input after the device is powered on. The semiconductor memory device according to claim 4 or 5. 7. A defective block flag corresponding to each block of the cell array is latched by the defective block flag latch circuit in a device product test, and the latched defective block flag can be written in the memory area. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is a semiconductor memory device. 8. Each of the blocks of the cell array has an array of NAND cells, and the NAND cells are selectively driven by the output of the row sub-decoder. 2. The semiconductor memory device according to item 1. 9. A means for detecting a case where an address of a selected block is designated by exceeding the number of valid blocks excluding the number of defective blocks from the total number of blocks of the cell array, and the detection result of this means is externally provided. 9. The semiconductor memory device according to claim 1, wherein the semiconductor memory device outputs the data to the device. 10. The method according to claim 1, further comprising means for counting the number of effective blocks obtained by removing the number of defective blocks from the total number of blocks of the cell array, and outputting the count result of this means to the outside. 13. The semiconductor memory device according to any one of 1.