JP2003100938A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2003100938A JP2003100938A JP2001293578A JP2001293578A JP2003100938A JP 2003100938 A JP2003100938 A JP 2003100938A JP 2001293578 A JP2001293578 A JP 2001293578A JP 2001293578 A JP2001293578 A JP 2001293578A JP 2003100938 A JP2003100938 A JP 2003100938A
- Authority
- JP
- Japan
- Prior art keywords
- base material
- insulating base
- semiconductor device
- insulating
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、絶縁基板の表面
側に回路パターンが形成されると共に裏面側に放熱板が
接合される半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a circuit pattern is formed on the front surface side of an insulating substrate and a heat dissipation plate is joined to the back surface side.
【0002】[0002]
【従来の技術】図10は、例えば特開昭61−5194
7号公報に示された従来の半導体装置を示す断面図であ
り、図において、1は絶縁基材で、その両面の周縁に突
部1aと1bが形成されている。2は上記絶縁基材1の
表面に形成された銅箔からなる回路パターン、3は上記
絶縁基材1の裏面に形成された銅箔からなる裏面パター
ン、4は上記絶縁基材1と上記回路パターン2と上記裏
面パターン3で構成される絶縁基板である。5は放熱板
であり、上記裏面パターン3に一致して対面する接合部
5aとこの接合部5aよりも低く形成された段部5bを
有し、半田6を介して上記裏面パターン3に上記接合部
5aが接合されている。また、上記突部1bは上記段部
5bにより、放熱板5の上面との空間距離が確保され
る。2. Description of the Related Art FIG. 10 shows, for example, Japanese Patent Laid-Open No. 61-5194.
FIG. 8 is a cross-sectional view showing a conventional semiconductor device disclosed in Japanese Patent Laid-Open No. 7-74, in which reference numeral 1 is an insulating base material, and projections 1a and 1b are formed on the peripheral edges of both surfaces thereof. 2 is a circuit pattern made of a copper foil formed on the surface of the insulating base material 1, 3 is a back surface pattern made of a copper foil formed on the back surface of the insulating base material 1, 4 is the insulating base material 1 and the circuit The insulating substrate is composed of the pattern 2 and the back surface pattern 3. Reference numeral 5 denotes a heat radiating plate, which has a joint portion 5a that faces the back surface pattern 3 and faces it, and a step portion 5b formed lower than the joint portion 5a. The part 5a is joined. Further, the stepped portion 5b of the protrusion 1b secures a spatial distance from the upper surface of the heat dissipation plate 5.
【0003】この構成においては、上記回路パターン2
の端面2aから上記裏面パターン3の端面3aまでの沿
面距離は上記突部1aと1bに沿うので、突部が存在し
ない場合に比べて長くなり、耐電圧が向上する。つま
り、上記突部1aと1bの高さを高くするか幅を大にし
て沿面距離を長くすることで所定の耐電圧を得ていた。In this structure, the circuit pattern 2 described above is used.
Since the creepage distance from the end face 2a to the end face 3a of the back surface pattern 3 is along the protrusions 1a and 1b, the creepage distance is longer than in the case where no protrusion is present, and the withstand voltage is improved. That is, the predetermined withstand voltage is obtained by increasing the height or the width of the protrusions 1a and 1b to increase the creepage distance.
【0004】[0004]
【発明が解決しようとする課題】従来の半導体装置は、
所定の耐電圧を得るために、絶縁基材1の両面の周縁に
上記突部1aと1bを設け、この突部1aと1bの高さ
を高くするか幅を大にして沿面距離を長くしていた。従
って、高価な絶縁基材1の素材の厚さが大となったり、
又は面積が大となり、半導体装置が高価となるという問
題を有していた。The conventional semiconductor device is
In order to obtain a predetermined withstand voltage, the protrusions 1a and 1b are provided on the periphery of both surfaces of the insulating base material 1, and the height of the protrusions 1a and 1b is increased or the width is increased to increase the creepage distance. Was there. Therefore, the thickness of the expensive insulating base material 1 becomes large,
Alternatively, there is a problem that the area becomes large and the semiconductor device becomes expensive.
【0005】本発明は、上記のような問題点を解消する
ためになされたものであり、回路パターン2の端面2a
から裏面パターン3の端面3aまでの沿面距離を、絶縁
基材1の高さと長さを縮小でき、絶縁基材1を安価に構
成できる半導体装置を提供することを目的とする。The present invention has been made to solve the above-mentioned problems, and the end face 2a of the circuit pattern 2 is formed.
It is an object of the present invention to provide a semiconductor device in which the creepage distance from to the end surface 3a of the back surface pattern 3 can be reduced in height and length of the insulating base material 1, and the insulating base material 1 can be configured at low cost.
【0006】[0006]
【課題を解決するための手段】第1の発明に係わる半導
体装置は、絶縁基材における表面側と裏面側のいずれか
一方の外周に沿って形成され、回路パターンから放熱板
までの沿面距離を所定値以上に構成する溝部を設けたも
のである。A semiconductor device according to a first aspect of the present invention is formed along the outer periphery of either the front surface side or the back surface side of an insulating base material, and the creepage distance from a circuit pattern to a heat sink is set. A groove portion having a predetermined value or more is provided.
【0007】さらに、第2の発明に係わる半導体装置
は、絶縁基材の外周に沿って突条部を形成し、上記突条
部に上記外周に沿う溝部を設けたものである。Further, in the semiconductor device according to the second invention, a ridge is formed along the outer circumference of the insulating base material, and a groove along the outer circumference is provided in the ridge.
【0008】さらに、第3の発明に係わる半導体装置
は、突条部は樹脂製の絶縁板で構成したものである。Further, in the semiconductor device according to the third aspect of the present invention, the ridge portion is formed of a resin insulating plate.
【0009】さらに、第4の発明に係わる半導体装置
は、絶縁基材における表面側と裏面側のいずれか一方の
外周と上記絶縁基材の周縁を覆って接合され、回路パタ
ーンから放熱板までの沿面距離を所定値以上に構成する
絶縁部材を設けたものである。Further, in the semiconductor device according to the fourth aspect of the present invention, the semiconductor substrate is bonded so as to cover the outer periphery of either the front surface side or the back surface side of the insulating base material and the peripheral edge of the insulating base material, and from the circuit pattern to the heat sink. An insulating member is provided which has a creepage distance equal to or greater than a predetermined value.
【0010】さらに、第5の発明に係わる半導体装置
は、絶縁部材には、絶縁基材の外周に沿って溝部が形成
され、上記溝で回路パターンから放熱板までの沿面距離
を所定値以上に構成したものである。Further, in the semiconductor device according to the fifth aspect of the present invention, a groove is formed in the insulating member along the outer periphery of the insulating base material, and the creepage distance from the circuit pattern to the heat sink is set to a predetermined value or more in the groove. It is composed.
【0011】さらに、第6の発明に係わる半導体装置
は、放熱板における絶縁基材に対面する側の全周に上記
絶縁基材と離間して絶縁板を接合したものである。Further, in the semiconductor device according to the sixth aspect of the present invention, the insulating plate is joined to the entire circumference of the heat dissipation plate on the side facing the insulating base material while being separated from the insulating base material.
【0012】[0012]
【発明の実施の形態】実施の形態1.この発明の実施の
形態1を図1により説明する。なお、図1は半導体装置
の断面図である。図において、1は絶縁基材で、その表
面の周縁には外周部1cに沿って複数の溝部1dが形成
されている。2は上記絶縁基材1の表面に形成された銅
箔からなる回路パターン、3は上記絶縁基材1の裏面に
形成された銅箔からなる裏面パターン、4は上記絶縁基
材1と上記回路パターン2と上記裏面パターン3で構成
される絶縁基板である。5は放熱板であり、上記裏面パ
ターン3に一致して対面する接合部5aとこの接合部5
aよりも低く形成された段部5bを有し、半田6を介し
て上記裏面パターン3に上記接合部5aが接合されてい
る。BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Embodiment 1 of the present invention will be described with reference to FIG. Note that FIG. 1 is a cross-sectional view of the semiconductor device. In the figure, reference numeral 1 denotes an insulating base material, and a plurality of groove portions 1d are formed along the outer peripheral portion 1c on the peripheral edge of the surface thereof. 2 is a circuit pattern made of a copper foil formed on the surface of the insulating base material 1, 3 is a back surface pattern made of a copper foil formed on the back surface of the insulating base material 1, 4 is the insulating base material 1 and the circuit The insulating substrate is composed of the pattern 2 and the back surface pattern 3. Reference numeral 5 denotes a heat radiating plate, which is joined to the back surface pattern 3 and faces the joint portion 5a.
It has a step portion 5b formed lower than a, and the joint portion 5a is joined to the back surface pattern 3 via a solder 6.
【0013】この構成においては、上記回路パターン2
の端面2aから上記裏面パターン3の端面3aまでの沿
面距離は複数の上記溝部1dに沿うので、上記溝部1d
の深さと個数を決めることで、所定の沿面距離を確保で
きることになる。つまり、上記絶縁基材1の厚さや幅を
大にすることなく、所定の耐電圧を確保できる。なお、
この実施の形態1では、溝部1dは所定の沿面距離を確
保を確保できるものであればよく、必ずしも上記絶縁基
材1の全周に設けるものではなく、部分的に設けても良
い。In this configuration, the circuit pattern 2 described above is used.
Since the creepage distance from the end face 2a of the back surface to the end face 3a of the back surface pattern 3 is along the plurality of groove portions 1d, the groove portion 1d
A predetermined creepage distance can be secured by determining the depth and the number of the. That is, a predetermined withstand voltage can be secured without increasing the thickness or width of the insulating base material 1. In addition,
In the first embodiment, the groove portion 1d only needs to secure a predetermined creepage distance, and is not necessarily provided all around the insulating base material 1 and may be provided partially.
【0014】実施の形態2.この発明の実施の形態2を
図2により説明する。なお、図2は半導体装置の断面図
である。図において、1は絶縁基材で、その表面側には
外周部1cに沿って突条部1aが形成されており、この
突条部1aには上記外周部1cに沿う複数の溝部1dが
形成されている。この構成では、突条部1aに溝部1d
が形成されており、溝部1dの深さ寸法を大にできるの
で、溝部1dの個数を少なくでき、絶縁基材1の幅寸法
を小さくでき、高価な絶縁基材1の材料を削減でき、所
定の耐電圧を安価な構成で確保できる。Embodiment 2. The second embodiment of the present invention will be described with reference to FIG. 2 is a cross-sectional view of the semiconductor device. In the figure, reference numeral 1 is an insulating base material, and a ridge portion 1a is formed along the outer peripheral portion 1c on the surface side thereof, and a plurality of groove portions 1d are formed along the outer peripheral portion 1c on the ridge portion 1a. Has been done. With this configuration, the groove 1d is formed on the ridge 1a.
Since the depth dimension of the groove portion 1d can be increased, the number of the groove portions 1d can be reduced, the width dimension of the insulating base material 1 can be reduced, and the material of the expensive insulating base material 1 can be reduced. Withstand voltage can be secured with an inexpensive structure.
【0015】実施の形態3.この発明の実施の形態3を
図3により説明する。なお、図3は半導体装置の断面図
である。図において、1は絶縁基材、7はこの絶縁基材
1の表面側の外周部1cに接合され、上記絶縁基材1の
表面側に突出する絶縁板で、エポキシ樹脂などの樹脂で
成形されて構成される。7aはこの絶縁板7に形成さ
れ、上記絶縁基材の外周部1cに沿う複数の溝部であ
る。この構成では、上記絶縁板7は上記絶縁基材1とは
別個に構成されるので、共通の上記絶縁基材1を用い、
単に絶縁板7の形状を変えることで必要な沿面距離を確
保でき、高価な上記絶縁基材1を標準化でき、より一層
のコストダウンを図れる。なお、この実施の形態3で
は、絶縁板7と溝部7aは所定の沿面距離を確保を確保
できるものであればよく、必ずしも上記絶縁基材1の全
周に設けるものではなく、部分的に設けても良い。Embodiment 3. A third embodiment of the present invention will be described with reference to FIG. Note that FIG. 3 is a cross-sectional view of the semiconductor device. In the figure, 1 is an insulating base material, 7 is an insulating plate which is joined to the outer peripheral portion 1c on the front surface side of the insulating base material 1 and protrudes toward the front surface side of the insulating base material 1, and is molded with a resin such as epoxy resin. Consists of Reference numeral 7a denotes a plurality of grooves formed on the insulating plate 7 and extending along the outer peripheral portion 1c of the insulating base material. In this configuration, since the insulating plate 7 is configured separately from the insulating base material 1, the common insulating base material 1 is used.
The required creepage distance can be secured by simply changing the shape of the insulating plate 7, the expensive insulating base material 1 can be standardized, and the cost can be further reduced. In the third embodiment, the insulating plate 7 and the groove portion 7a may be provided as long as they can secure a predetermined creepage distance, and are not necessarily provided on the entire circumference of the insulating base material 1 but partially provided. May be.
【0016】実施の形態4.この発明の実施の形態4を
図4により説明する。なお、図4は半導体装置の断面図
である。図において、1は絶縁基材、8はこの絶縁基材
1の表面側の外周部1cと絶縁基材1の周縁部1eとを
覆って接合され、上記絶縁基材1の表面側に突出する絶
縁部材である。この構成では、上記絶縁部材8は上記絶
縁基材1の周縁部1eを覆っているので、高価な上記絶
縁基材1の寸法を小さくできると共に標準化でき、より
一層のコストダウンを図れる。なお、上記絶縁部材8は
図5のように上記絶縁基材1の表面側と裏面側の双方を
覆うと、更に効果を奏することができる。Fourth Embodiment A fourth embodiment of the present invention will be described with reference to FIG. Note that FIG. 4 is a cross-sectional view of the semiconductor device. In the figure, reference numeral 1 denotes an insulating base material, and 8 denotes an outer peripheral portion 1c on the front surface side of the insulating base material 1 and a peripheral edge portion 1e of the insulating base material 1 which are joined to each other and project to the front surface side of the insulating base material 1. It is an insulating member. In this structure, since the insulating member 8 covers the peripheral edge portion 1e of the insulating base material 1, the size of the expensive insulating base material 1 can be reduced and standardized, and the cost can be further reduced. Note that the insulating member 8 can exert further effects by covering both the front surface side and the back surface side of the insulating base material 1 as shown in FIG.
【0017】実施の形態5.この発明の実施の形態5を
図6により説明する。なお、図6は半導体装置の断面図
である。8aは上記絶縁部材8に上記絶縁基材1の外周
部1cに沿って形成された複数の溝部である。この構成
では、溝部8aの個数で容易に所定の沿面距離を確保で
き、また、上記絶縁基材1の幅寸法を大幅に低減でき
る。Embodiment 5. A fifth embodiment of the present invention will be described with reference to FIG. Note that FIG. 6 is a cross-sectional view of the semiconductor device. Reference numeral 8a denotes a plurality of groove portions formed on the insulating member 8 along the outer peripheral portion 1c of the insulating base material 1. With this configuration, a predetermined creepage distance can be easily ensured by the number of grooves 8a, and the width dimension of the insulating base material 1 can be significantly reduced.
【0018】実施の形態6.この発明の実施の形態6を
図7により説明する。なお、図7は半導体装置の断面図
である。図において、9は上記放熱板5の上記絶縁基材
1に対面する側の全周に上記絶縁基材1と離間して接合
された絶縁板である。10は回路パターン2に半田11
を介して接合された半導体素子である。この構成では、
上記絶縁基材1と放熱板5との距離が接近して空間距離
が少なくても、絶縁板9で絶縁されるため、上記回路パ
ターン2と上記放熱板5との間の耐電圧は、上記裏面パ
ターン3までの沿面距離に依存できることになり、耐電
圧特性が一層向上する。なお、隣り合う絶縁基板4の間
の絶縁板9は図8のように分離されても同様の効果を奏
する。Embodiment 6. A sixth embodiment of the present invention will be described with reference to FIG. Note that FIG. 7 is a cross-sectional view of the semiconductor device. In the figure, reference numeral 9 is an insulating plate which is joined to the entire circumference of the heat dissipation plate 5 facing the insulating base material 1 while being separated from the insulating base material 1. 10 is solder on the circuit pattern 2
It is a semiconductor element bonded via the. With this configuration,
Even if the distance between the insulating base material 1 and the heat sink 5 is short and the space distance is small, insulation is performed by the insulating plate 9. Therefore, the withstand voltage between the circuit pattern 2 and the heat sink 5 is It becomes possible to depend on the creepage distance to the back surface pattern 3, and the withstand voltage characteristics are further improved. The insulating plate 9 between the adjacent insulating substrates 4 has the same effect even if it is separated as shown in FIG.
【0019】実施の形態7.この発明の実施の形態7を
図9により説明する。なお、図9は半導体装置の断面図
である。図において、5は放熱板であり、上記絶縁基材
1よりも小さい面積で突出した接合部5aとこの接合部
5aよりも低く形成された段部5bを有し、上記接合部
5aが上記絶縁基材1に接合される。9は上記段部5b
における上記絶縁基材1に対面する側の全周に上記絶縁
基材1と離間して接合された絶縁板である。この構成
も、この発明の実施の形態7と同様の効果を奏する。Embodiment 7. The seventh embodiment of the present invention will be described with reference to FIG. Note that FIG. 9 is a cross-sectional view of the semiconductor device. In the figure, reference numeral 5 denotes a heat dissipation plate, which has a joint portion 5a protruding in an area smaller than that of the insulating base material 1 and a step portion 5b formed so as to be lower than the joint portion 5a. It is bonded to the base material 1. 9 is the step portion 5b
Is an insulating plate bonded to the insulating base material 1 over the entire circumference on the side facing the insulating base material 1 while being separated from the insulating base material 1. This structure also has the same effects as the seventh embodiment of the present invention.
【0020】[0020]
【発明の効果】この発明は、以上のように構成されてい
るので、以下に示すような効果を奏する。Since the present invention is configured as described above, it has the following effects.
【0021】絶縁基材における表面側と裏面側のいずれ
か一方の外周に沿って形成され、回路パターンから放熱
板までの沿面距離を所定値以上に構成する溝部を設けた
ので、絶縁基材の厚さや幅を大にすることなく、所定の
耐電圧を確保できる効果がある。Since the groove portion is formed along the outer periphery of either the front surface side or the back surface side of the insulating base material and the creepage distance from the circuit pattern to the heat sink is set to a predetermined value or more, the insulating base material is provided. There is an effect that a predetermined withstand voltage can be secured without increasing the thickness or width.
【0022】絶縁基材の外周に沿って突条部を形成し、
上記突条部には上記外周に沿う溝部を設けたので、高価
な絶縁基材の材料を削減でき、所定の耐電圧を安価な構
成で確保できる効果がある。A ridge is formed along the outer periphery of the insulating base material,
Since the groove is provided along the outer circumference of the ridge, the material of the expensive insulating base material can be reduced, and the predetermined withstand voltage can be secured with an inexpensive structure.
【0023】突条部は樹脂製の絶縁板で構成したので、
絶縁板は上記絶縁基材とは別個に構成されることにな
り、高価な上記絶縁基材を標準化でき、より一層のコス
トダウンを図れる効果がある。Since the ridge portion is made of a resin insulating plate,
Since the insulating plate is configured separately from the insulating base material, the expensive insulating base material can be standardized, and there is an effect that the cost can be further reduced.
【0024】絶縁基材における表面側と裏面側のいずれ
か一方の外周と上記絶縁基材の周縁を覆って接合され、
上記回路パターンから上記放熱板までの沿面距離を所定
値以上に構成する絶縁部材を設けたので、高価な絶縁基
材の寸法を小さくできると共に標準化でき、より一層の
コストダウンを図れる効果がある。The outer periphery of either the front surface side or the back surface side of the insulating base material and the peripheral edge of the insulating base material are covered and bonded.
Since the insulating member having the creepage distance from the circuit pattern to the heat dissipation plate is set to a predetermined value or more is provided, the size of the expensive insulating base material can be reduced and standardized, and further cost reduction can be achieved.
【0025】絶縁部材には、絶縁基材の外周に沿って溝
部が形成され、上記溝部で上記回路パターンから上記放
熱板までの沿面距離を所定値以上に構成したので、溝部
の個数で容易に所定の沿面距離を確保でき、絶縁基材の
幅寸法を大幅に低減できる効果がある。Since a groove is formed on the insulating member along the outer periphery of the insulating base material, and the creepage distance from the circuit pattern to the heat sink is set to a predetermined value or more in the groove, the number of grooves makes it easy. A predetermined creepage distance can be secured, and the width of the insulating base material can be significantly reduced.
【0026】放熱板の上記絶縁基材に対面する側の全周
に絶縁基材と離間して絶縁板を接合したので、耐電圧特
性が一層向上する効果がある。Since the insulating plate is joined to the entire circumference of the heat dissipation plate facing the insulating base material so as to be separated from the insulating base material, there is an effect that the withstand voltage characteristic is further improved.
【図1】 この発明の実施の形態1を示す半導体装置の
断面図である。FIG. 1 is a sectional view of a semiconductor device showing a first embodiment of the present invention.
【図2】 この発明の実施の形態2を示す半導体装置の
断面図である。FIG. 2 is a sectional view of a semiconductor device showing a second embodiment of the present invention.
【図3】 この発明の実施の形態3を示す半導体装置の
断面図である。FIG. 3 is a sectional view of a semiconductor device showing a third embodiment of the present invention.
【図4】 この発明の実施の形態4を示す半導体装置の
断面図である。FIG. 4 is a sectional view of a semiconductor device showing a fourth embodiment of the present invention.
【図5】 この発明の実施の形態4の他の形態を示す半
導体装置の断面図である。FIG. 5 is a sectional view of a semiconductor device showing another embodiment of the fourth embodiment of the present invention.
【図6】 この発明の実施の形態5を示す半導体装置の
断面図である。FIG. 6 is a sectional view of a semiconductor device showing a fifth embodiment of the present invention.
【図7】 この発明の実施の形態6を示す半導体装置の
断面図である。FIG. 7 is a sectional view of a semiconductor device showing a sixth embodiment of the present invention.
【図8】 この発明の実施の形態6の他の形態を示す半
導体装置の断面図である。FIG. 8 is a sectional view of a semiconductor device showing another embodiment of the sixth embodiment of the present invention.
【図9】 この発明の実施の形態7を示す半導体装置の
断面図である。FIG. 9 is a sectional view of a semiconductor device showing an embodiment 7 of the present invention.
【図10】 従来の半導体装置の断面図である。FIG. 10 is a cross-sectional view of a conventional semiconductor device.
1 絶縁基材、1a 突条部、1c 外周部、1d 溝
部、1e 周縁部、2回路パターン、4 絶縁基板、5
放熱板、7 絶縁板、7a 溝部、8 絶縁部材、8
a 溝部、9 絶縁板。DESCRIPTION OF SYMBOLS 1 Insulating base material, 1a ridge, 1c outer peripheral portion, 1d groove, 1e peripheral portion, 2 circuit pattern, 4 insulating substrate, 5
Heat sink, 7 insulating plate, 7a groove, 8 insulating member, 8
a groove, 9 insulating plate.
Claims (6)
された絶縁基板、及びこの絶縁基板に接合される放熱板
を備えた半導体装置において、上記絶縁基材における上
記表面側と裏面側のいずれか一方の外周に沿って形成さ
れ、上記回路パターンから上記放熱板までの沿面距離を
所定値以上に構成する溝部を設けたことを特長とする半
導体装置。1. A semiconductor device comprising an insulating substrate having a circuit pattern formed on the front surface side of an insulating base material, and a heat dissipation plate joined to the insulating substrate, wherein the front surface side and the back surface side of the insulating base material are A semiconductor device having a groove portion formed along one of the outer peripheries, the groove portion having a creepage distance from the circuit pattern to the heat dissipation plate of a predetermined value or more.
し、上記突条部には上記外周に沿う溝部を設けたことを
特徴とする請求項1に記載の半導体装置。2. The semiconductor device according to claim 1, wherein a ridge is formed along the outer periphery of the insulating base material, and a groove along the outer periphery is provided in the ridge.
を特徴とする請求項2に記載の半導体装置。3. The semiconductor device according to claim 2, wherein the ridge portion is formed of a resin insulating plate.
された絶縁基板、及びこの絶縁基板に接合される放熱板
を備えた半導体装置において、上記絶縁基材における上
記表面側と裏面側のいずれか一方の外周と上記絶縁基材
の周縁を覆って接合され、上記回路パターンから上記放
熱板までの沿面距離を所定値以上に構成する絶縁部材を
設けたことを特長とする半導体装置。4. A semiconductor device comprising an insulating substrate having a circuit pattern formed on the front surface side of the insulating base material, and a heat dissipation plate joined to the insulating substrate, wherein the front surface side and the back surface side of the insulating base material are A semiconductor device, comprising: an insulating member, which is bonded to one of the outer peripheries so as to cover the peripheral edge of the insulating base material and has a creepage distance from the circuit pattern to the heat dissipation plate of a predetermined value or more.
部が形成され、上記溝部で回路パターンから放熱板まで
の沿面距離を所定値以上に構成したことを特長とする請
求項4に記載の半導体装置。5. The insulating member is formed with a groove along the outer periphery of the insulating base material, and the creepage distance from the circuit pattern to the heat sink is set to be a predetermined value or more in the groove. The semiconductor device described.
された絶縁基板、及びこの絶縁基板に接合される放熱板
を備えた半導体装置において、上記放熱板における上記
絶縁基材に対面する側の全周に上記絶縁基材と離間して
絶縁板を接合したことを特長とする半導体装置。6. A semiconductor device comprising an insulating substrate having a circuit pattern formed on the surface side of an insulating base material, and a heat dissipation plate joined to the insulating substrate, the side of the heat dissipation plate facing the insulating base material. A semiconductor device characterized in that an insulating plate is bonded to the entire circumference of the insulating substrate while being separated from the insulating base material.
Priority Applications (1)
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JP2001293578A JP2003100938A (en) | 2001-09-26 | 2001-09-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2001293578A JP2003100938A (en) | 2001-09-26 | 2001-09-26 | Semiconductor device |
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JP2003100938A true JP2003100938A (en) | 2003-04-04 |
Family
ID=19115335
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JP2001293578A Pending JP2003100938A (en) | 2001-09-26 | 2001-09-26 | Semiconductor device |
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JP2005116934A (en) * | 2003-10-10 | 2005-04-28 | Dowa Mining Co Ltd | Metal-ceramic bonding substrate and manufacturing method thereof |
JP2008028006A (en) * | 2006-07-19 | 2008-02-07 | Mitsubishi Electric Corp | Semiconductor device |
JP5134161B2 (en) * | 2011-01-13 | 2013-01-30 | パナソニック株式会社 | Mounting board, light emitting device and lamp |
JP2013118299A (en) * | 2011-12-05 | 2013-06-13 | Mitsubishi Materials Corp | Substrate for power module |
JP2015015275A (en) * | 2013-07-03 | 2015-01-22 | 三菱電機株式会社 | Ceramic circuit board, ceramic circuit board with heat sink, and manufacturing method of ceramic circuit board |
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2001
- 2001-09-26 JP JP2001293578A patent/JP2003100938A/en active Pending
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2005116934A (en) * | 2003-10-10 | 2005-04-28 | Dowa Mining Co Ltd | Metal-ceramic bonding substrate and manufacturing method thereof |
JP4496404B2 (en) * | 2003-10-10 | 2010-07-07 | Dowaメタルテック株式会社 | Metal-ceramic bonding substrate and manufacturing method thereof |
JP2008028006A (en) * | 2006-07-19 | 2008-02-07 | Mitsubishi Electric Corp | Semiconductor device |
JP5134161B2 (en) * | 2011-01-13 | 2013-01-30 | パナソニック株式会社 | Mounting board, light emitting device and lamp |
JP2013038430A (en) * | 2011-01-13 | 2013-02-21 | Panasonic Corp | Mounting substrate |
JP2013118299A (en) * | 2011-12-05 | 2013-06-13 | Mitsubishi Materials Corp | Substrate for power module |
JP2015015275A (en) * | 2013-07-03 | 2015-01-22 | 三菱電機株式会社 | Ceramic circuit board, ceramic circuit board with heat sink, and manufacturing method of ceramic circuit board |
JP6081042B1 (en) * | 2015-12-16 | 2017-02-15 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
WO2017221750A1 (en) * | 2016-06-22 | 2017-12-28 | 株式会社村田製作所 | Capacitor |
JPWO2017221750A1 (en) * | 2016-06-22 | 2018-08-02 | 株式会社村田製作所 | Capacitors |
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