JP2003195838A - Display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device, which is fast in memory read speed and small in effect of noise of a signal and can be made small-sized, and its driving method. <P>SOLUTION: The display has a frame memory formed integrally on a substrate (pixel substrate) where pixel parts are formed. In this arrangement, one line can be read out of the frame memory at the same time and inputted to a driving circuit for pixels in parallel. Consequently, image data need not be transferred in series and none of a parallel/serial converting circuit, a serial output circuit, a serial/parallel converting circuit, a parallel input circuit, etc,. is needed. The display which has the frame memory and pixel parts can, therefore, be constituted having simpler constitution and simple circuits. Consequently, noise reducible and low power consumption can be realized. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having a plurality of pixels on an insulating surface. Further, the present invention relates to an electronic device using the display device.

[0002]

2. Description of the Related Art Recently, as a flat display, a liquid crystal display device using a liquid crystal display element, OLED (Organic Light)
An OLED display device using an Emitting Diode (M) (Met)
Attention is focused on a field effect display device using an electron source element such as an al Insulator Metal) type or an FE (Field Emission) type.

These display devices are produced at low cost by forming pixels on an insulating surface using thin film transistors (hereinafter referred to as "Thin Film Transistor").

The structure of a conventional display device will be described below.

FIG. 4 is a block diagram showing the structure of a conventional display device.

In FIG. 4, the display device is composed of a pixel substrate 1000 in which a pixel portion 1001 having a plurality of pixels and a latch circuit 1007 are formed, and an external substrate 1002 in which a frame memory 1003 is formed.

At this time, different substrates are used for the substrate on which the pixel portion 1001 is formed and the substrate on which the frame memory 1003 is formed.

In the display device having the above structure, the signal stored in the frame memory formed on the external substrate is transferred to the pixel substrate 1000. Therefore, a cable 1005 connecting the pixel substrate 1000 and the external substrate 1002 is provided. Will be needed. When the cable 1005 is used, it is usually difficult to transfer one line of image data in parallel using the cable although it depends on the image data. Therefore, transfer of an image signal from the frame memory 1003 to the pixel substrate 1000 is not possible. It is sent in serial.

Therefore, a serial / parallel conversion circuit 1006 for converting a serial signal into a parallel signal is formed on the pixel substrate 1000. A parallel / serial conversion circuit 1004 that converts a parallel signal into a serial signal is formed on the external board 1002.

[0010]

In the conventional display device as shown in FIG. 4, the parallel image data stored in the frame memory is input to the pixel substrate as a serial signal and converted into a parallel signal again. Had to do.

Therefore, there is a problem that the speed of transferring a signal from the frame memory to the pixel portion is limited and the image display speed is slow.

Further, since a signal is transferred from the frame memory to the pixel portion using a long wiring, there is a problem that the influence of noise is great.

Further, the external substrate requires a parallel / serial conversion circuit and a serial output circuit, and the pixel substrate requires a serial / parallel conversion circuit and a parallel input circuit, which makes the circuit complicated.
There is also a problem that the power consumption is large.

It is an object of the present invention to solve the above problems and to provide a display device which can be read out from a memory at high speed, is less affected by signal noise, and can be miniaturized.

[0015]

In order to solve the above-mentioned problems, the following means have been taken in the present invention.

The conventional frame memory is usually formed on single crystal silicon and mounted on an external substrate, but the frame memory is integrally formed on the substrate (pixel substrate) on which the pixel portion is formed.

According to the present invention, there is provided a display device having a plurality of pixels formed by using thin film transistors on an insulating surface, a memory composed of a plurality of memory cells, and a drive circuit composed of a source driver and a gate driver. hand,
A display device is provided, which outputs serial signal data input from the outside to a plurality of pixels via a memory in a plurality of lines in parallel. In the above description, the serial signal data input from the outside may be input not only from the outside of the pixel substrate but also from the CPU formed on the pixel substrate.

A display device having a plurality of pixels formed by using thin film transistors on an insulating surface, a memory including a plurality of memory cells, and a drive circuit including a source driver and a gate driver. , A driving circuit formed on the insulating surface for simultaneously reading out the digital signals stored in the plurality of memory cells and inputting the digital signals to the plurality of pixels through a plurality of wirings formed on the insulating surface. A display device characterized by the above is provided.

In the above description, the device holds the output digital signal, the input of the held digital signal to the plurality of pixels all at once, or the output digital signal. Means and converting the held digital signal into an analog signal,
The display device may have a means for simultaneously inputting to the plurality of pixels.

In the above, the input to the pixels performed at one time may be one row or one column of pixels, or may be a part divided into a plurality of them.

In the above, the memory needs to have a capacity capable of storing at least digital signals for several rows of pixels, and the memory may be SRAM or DRAM.

Further, in the above, the element used for the pixel may be any one of liquid crystal, OLED and electron source element, and the thin film transistor used in the device may be formed by using either a polycrystalline semiconductor thin film or an amorphous semiconductor thin film. good.

According to the present invention, a plurality of pixels formed using thin film transistors on an insulating surface, a memory including a plurality of memory cells, and a driver circuit including a source driver and a gate driver are provided, There is provided a driving method of a display device, which outputs serial signal data input from a plurality of pixels to a plurality of pixels in parallel through a memory through a plurality of wirings.

According to the present invention, there are provided a plurality of pixels formed by using thin film transistors on an insulating surface, a memory composed of a plurality of memory cells, and a drive circuit composed of a source driver and a gate driver. A method for driving a display device is provided, in which data stored in a plurality of memory cells are simultaneously read as digital signals and are simultaneously input to the plurality of pixels.

In the above, the method is characterized in that the data stored in one row of the plurality of memory cells is read as a digital signal, the read digital signal is held, and the data is simultaneously input to the plurality of pixels. A method of driving the display device may be used.

In the above method, the driving method of the display device may be characterized in that the held digital signal is converted into an analog signal and is input to the plurality of pixels at the same time.

In the above description, the pixels input at one time may be one row of pixels or may be a method of driving the display device which is a part of a plurality of divided pixels.

With such a structure, it is possible to read out one row from the frame memory at the same time and input the data in parallel to the pixel drive circuit. as a result,
No need to transfer image data serially, parallel /
Circuits such as a serial conversion circuit, a serial output circuit, a serial / parallel conversion circuit and a parallel input circuit are unnecessary.

As described above, it is possible to construct a display device having a frame memory and a pixel portion with a simpler configuration and a simple circuit. As a result, noise can be reduced and low power consumption can be realized.

Further, since all the image data for one line of the frame memory is processed in parallel, the transfer speed of the image data is greatly improved as compared with the serial transfer.
As a result, the image can be displayed at a higher speed, and the image quality can be improved.

Further, the frame memory is similar to the pixel section.
Since it is configured using TFTs (or capacitors and resistors), it can be manufactured with almost no change in the process of forming the pixel portion, and when the frame memory is integrally formed, another chip is mounted. The cost can be reduced as compared with the case.

Conventionally, when a frame memory is manufactured on a pixel substrate, there is a problem that the operation speed of the memory is slower than that of the memory on single crystal silicon and the memory cells are large. However, it is understood that these difficulties can be reduced or avoided, as described below.

First, regarding the operation speed of the memory, a TFT having a higher mobility than that of a TFT formed on a substrate having a conventional insulating surface is realized by using the process described in the embodiments of the present specification. Therefore, it is possible to form a practical memory as a frame memory in terms of operation speed.

Even when other polysilicon or amorphous silicon is used, depending on the number of pixels, the display method, the structure of the frame memory, and the contents of the image, it is possible to use it without worrying about the demerit of the operating speed. Is.

In consideration of the area of the entire memory, it is possible to reduce the size of the memory as compared with the increase of the area by using an external substrate. Even if the memory is mounted by COG technology, the memory area does not matter if the margin required for mounting is considered. Furthermore, the miniaturization of TFTs is progressing, and it is expected that the configuration will be advantageous even in miniaturization in the future.

In the present invention, the frame memory is a memory for storing a video signal input from the outside of the display device for one frame or several frames. The video signal for one frame once stored in the frame memory is read in an arbitrary order according to the display method.

[0037]

FIG. 1 is a block diagram showing a typical configuration of a display device of the present invention.

In FIG. 1, a frame memory 103 and a drive circuit are integrally formed on a pixel substrate 100 having an insulating surface on which a pixel portion 101 is formed. In the present specification, the drive circuit will be referred to below as the source driver 1 depending on its role.
07 and the gate driver 108. A signal input from the outside is temporarily stored in the frame memory 103 and then read out, and simultaneously output to a plurality of pixels of the pixel portion 101 through a plurality of wirings through the source driver 107. The gate driver 108 controls display of each pixel in the pixel portion 101 using a signal generated by an external signal.

The frame memory 103 has a plurality of memory cells arranged in a matrix.

FIG. 2 shows an example in which the frame memory 103 and pixels are connected in parallel by signal lines corresponding to the number of pixels of data for one row. Frame memory 10
The structure No. 3 has a large number of memory cells 301 arranged in a matrix as shown in FIG. At this time, signals serially input from the outside can be simultaneously output to the pixel portion 101 through signal lines connected in parallel.

The frame memory shown in this embodiment mode is an SRAM.
Composed by. A word line 302, a data line 303, and an inverted data line 304 are connected to each memory cell 301. The selection of the memory cell is performed by the row decoder 308 and the column decoder 307. The row decoder 308 selects one of the plurality of word lines 302, and the column decoder 307 selects the data line 303 and the inverted data line 304 connected to the selected memory cell 301 through the selector 306. Then, the signal from the writing circuit 305 is written in the memory cell 301 or the memory cell 3
The signal written in 01 is read by the parallel reading circuit 309. These are formed on the same insulating substrate 300. Data and address signals to the frame memory, control signals such as read signals, and power are sent from the outside.

The memory cell includes a first transistor 311, a second transistor 312 and a first inverter 3 as shown in FIG.
13 and the second inverter 314. In each memory cell, the word line 302 is the first transistor 3
11, the data line 303 is connected to the source electrode or drain electrode of the first transistor 311, and the inverted data line 304 is connected to the source electrode or drain electrode of the second transistor 312.

The output of the first inverter 313 is the second inverter of the first inverter 313 and the second inverter 314.
The flip-flop configuration is connected to the input of the inverter 314 and similarly the output of the second inverter 314 is connected to the input of the first inverter 313.

Then, the above-mentioned first transistor (hereinafter,
(Also referred to as a selection transistor) 311 is connected to the data line through the source or drain electrode and the second transistor 31.
Reference numeral 2 is connected to the inverted data line through the source or drain electrode, while the gate electrode is connected to the word line.

The operating principle of the memory cells of FIGS. 5 and 6 will be described. First, the selection transistors 311 and 31
When 2 is ON, for example, "1" is supplied to the data line,
If "0" is supplied to the inversion data line, "1" is written to the point A and "0" is written to the point B in the flip-flop, and even if the selection transistors 311 and 312 are turned off, The state is kept. Then, when the selection transistors 311 and 312 are turned on again, "1" is read to the data line and "0" is read to the inverted data line.

Signal read circuit 309 from memory cell
Take a sense amplifier as an example. FIG. 7 shows an example of the structure of the sense amplifier. Note that, here, a circuit corresponding to one data line and one inverted data line is shown as a representative.

As shown in FIG. 7, the sense amplifier is composed of five transistors 321 to 325. Power VDD32
9 and the bias potential 326 are applied, the data line 303
A High or Low signal 330 is output according to the magnitude relationship between the potential of the inverted data line 304 and the potential of the inverted data line 304. A constant current source can be used instead of the transistor 325, and the output 3
One or more inverters may be attached to 30 as required.

Digital signals stored in a plurality of memory cells are read in parallel by using a reading circuit, transferred in parallel to the source driver 107 as parallel signals, and simultaneously output to the pixel portion. A signal can be held by forming a latch circuit in the source driver 107. Similarly, by configuring a DAC in the source driver 107, it is possible to convert a digital signal into an analog signal and transfer it to the pixel portion.

The frame memory may use SRAM or DRAM. In addition, a memory having any known structure which can be manufactured on an insulating surface can be used.

The data sent from the frame memory at the same time need not be the data for one row of pixels, but may be the data for one row of pixels or less. For example, in the case of RGB color display, the data output from the frame memory may be only the data input to any one of R, G, and B of one row of pixels. In this case, one frame or one horizontal period can be divided into three and can be displayed in three times of R, G, and B. Of course, the data output in one frame is not limited to the RGB division, and the same applies to one of the data obtained by dividing one row of pixel data.

The gate driver 108 sends a signal generated by externally inputting a start pulse and a clock to each pixel in the pixel section 101. By reversing the positional relationship between the source driver 107 and the gate driver 108, not only one row of pixels but also one column or a part thereof can be simultaneously input.

Liquid crystals, OLEDs, electron source devices, etc. are used as these pixels. Details of examples using these will be described later. The present invention can be applied to pixels having known configurations other than these.

The transistors used in the pixels, memory cells, and driving circuits can be formed by TFTs. The TFT can be made of an amorphous semiconductor or a polycrystalline semiconductor. The manufacturing process will be described later.

[0054]

EXAMPLES Examples of the present invention will be described. (Embodiment 1) In this embodiment, a configuration of a display device in which a digital video signal is stored in a memory, converted into an analog signal and input to a pixel portion will be described.

FIG. 3 is a block diagram showing the configuration of this embodiment.

In FIG. 3, the display device includes a frame memory 2 formed on a pixel substrate 200 having an insulating surface.
01, source driver 205, gate driver 206,
It has a pixel portion 207. In the frame memory 201, a digital video signal input from the outside of the display device is stored.

Here, in the case of RGB color, the number of wirings A to C is the number of pixels in one row × the number of bits, and the number of wirings D is the number of pixels in one row. That is, in this case, one line of image data can be sent out at the same time.

As described above in the embodiment, the data for one row of pixels need not be stored in one row of the frame memory, and may be the data for one row of pixels or less. In that case, a selector for selecting a pixel may be provided between the DAC and the pixel in the block configuration of the source driver shown in FIG. A known selector can be used.

For example, in the case of RGB color display, one frame pixel row may contain only data of R, G, or B in one row of pixels. In this case, one frame or one horizontal period is 3 times. It can be divided and displayed in three times, R, G, and B. Then, a selector for selecting an RGB pixel may be provided between the DAC and the pixel.

Of the elements shown in FIG. 3, the frame memory 201 has been described above, so the source driver 205, the gate driver 206, and the pixel section 207 will be described in detail below.

The source driver 205 is composed of a latch 202, a level shifter 203, and a digital-analog converter (hereinafter referred to as DAC) 204. However, although the configuration is as shown in FIG. 3, the source driver 805 is connected to the level shifter 803 and the DA as shown in FIG.
You may comprise by C804. Further, by giving the role of the level shifter 203 to the DAC 204, the source driver 825 can be connected to the latch 822 and DA as shown in FIG.
It can also be configured by C824. Further, a configuration as shown in FIG. 27 may be adopted in which a plurality of DACs are included in the circuit of the pixel portion 847 so that a parallel signal can be directly sent to the pixel portion. It goes without saying that the latch, the level shifter, and the DAC mentioned here are each composed of a plurality.

FIG. 8 shows the configuration of the latch 202. The input terminals 330 of the plurality of latch circuits 331 arranged in parallel are connected to the data output terminals of the sense amplifier in the frame memory 201 shown in FIG. The signals output from the sense amplifiers are simultaneously latched by the memory latch control signal 332.

An example of the latch circuit 331 is shown in FIG. This is composed of two inverters 342 and 343, one gate transistor 341 and a control inverter 344. The input data 330 from the sense amplifier opens the gate transistor only when the memory latch control signal 332 is "1", drives the inverter, changes the state of the latch output 333, and outputs the data. When the memory latch control signal 332 is "0", the state of the output 333 does not change and holds the data.

FIG. 10 shows an example of the level shifter 203. The level shifter has six transistors 351 to 356.
Composed of. The input signal 333 from the latch is combined with the inversion signal by the inverter formed by the transistors 355 and 356, and the four transistors 351 to 35
4 and its output 359 is shifted to the voltage level of the power supply terminal 357 or the power supply terminal 358.

FIG. 11 shows an example of the DAC 204 shown in FIG.
The DAC in FIG. 11 converts an 8-bit digital signal into an analog signal, and is roughly divided into a coarse adjustment voltage selection unit and a fine adjustment voltage selection unit. Also, as shown in FIG. 11, the DAC
May have a polarity reversing circuit.

The coarse adjustment voltage selection section is composed of eight voltage selection switches 408. The voltage selection switch 408 has a potential 4 applied when the switch is operated only for a signal input of a certain pattern using a transistor as in the configuration of FIG.
29 and 430 are output to 431 and 432, respectively. Utilizing this, one of the voltage selection switches is operated according to the values of the input signals 394 to 396 of the upper 3 bits and the inverted signals 397 to 399 of the 8-bit digital signal, and the potential corresponding to the input potential 385 to 393. VH and VL are generated.

In the fine adjustment voltage selector, a current flows through the resistors 379 to 384 which differ according to the input signals 400 to 404 of the lower 5 bits, and the potentials of VL and VH are output at 32 levels of height.
You can start from 05. This output becomes the source line of the pixel portion. The analog switch 378 is closed by the control signal 406 and the inverted control signal 407 during the reset period and opened during the other periods. Although the resistors 379 to 384 are used in FIG. 11, capacitors may be used instead of the resistors.

The gate driver 206 sends out a signal generated by externally inputting a start pulse and a clock to the pixel portion through the gate line.

The liquid crystal display device given as an example of the image display device of the present embodiment can be applied to an active matrix type liquid crystal display device. As shown in FIG. 13, a plurality of pixels 441 are arranged in an m × n matrix. It has a pixel array 442 arranged in a pattern.

As shown in FIG. 14, each pixel includes a pixel capacitor 453 composed of a liquid crystal capacitor 451 and a storage capacitor 452, and a transistor 454 composed of a semiconductor layer such as amorphous or polycrystalline silicon.

The pixel 441 is formed on a light-transmissive insulating substrate 443 such as a glass substrate, and the source line 448 and the gate line 444 for driving the pixel 441 are also formed on the insulating substrate 443. ing. Each pixel 441 is arranged at a position where each source line 448 and each gate line 444 overlap.

As shown in FIG. 13, each of the above-mentioned gate lines 4
44 and source line 448 are connected to each pixel 441 in pixel array 442.

These wirings and the above-mentioned frame memory 201, source driver 205, gate driver 206
Can be manufactured by almost common processes.
Therefore, it can be integrally formed on the insulating substrate 443. In the present invention, an address signal, a read signal, a latch signal to the driver, a start pulse, a clock, etc. are externally input to the frame memory,
A controller circuit for generating these control signals from simpler external signals may be formed on the same substrate.

The rewriting period of the frame memory is as follows depending on the capacity and configuration of the frame memory. When the frame memory has a data capacity for one image, the data is rewritten in the vertical blanking period of one frame. When the frame memory has a data capacity of two images or more, it is possible to freely rewrite data other than the memory area displaying an image in each frame, and it is possible to secure a sufficient rewriting time.

Further, if the memory is a dual-port memory that can perform reading and writing at the same time by using different data lines, it is possible to freely rewrite even image data being displayed. It is possible.
In particular, even if the memory has a capacity of one image or less, an image can be displayed by updating the data in the memory area that has been displayed.

Here, the data capacity is represented by data capacity = number of pixels × number of gradations × number of colors. The number of colors is 3 for RGB colors and 1 for monochrome and black and white. Since the number of gradations is represented by the number of bits, it is 8 for 256 gradations, 6 for 64 gradations, and 3 for 8 gradations.

Further, by integrally forming a plurality of DACs on the same insulating substrate 443, it becomes unnecessary to use a serial / parallel conversion circuit or the like. Therefore, it is possible to improve the speed, prevent the influence of noise caused by passing through the serial / parallel conversion circuit, and further simplify the circuit and reduce the cost. (Embodiment 2) In this embodiment, a process for integrally forming the liquid crystal display portion, the driving circuit and the memory cell having the configuration shown in the embodiment 1 will be described. However, a CMOS circuit, which is a basic unit for the drive circuit portion and the memory cell portion, is illustrated.

The transistor 454 shown in FIG. 14 is shown as a transistor forming a pixel. For the pixel, only the write TFT, the source signal line, and the storage capacitor are shown.

First, as shown in FIG. 15A, a substrate 3001 made of glass such as barium borosilicate glass represented by Corning's # 7059 glass or # 1737 glass or aluminoborosilicate glass is oxidized. A base film 3002 made of an insulating film such as a silicon film, a silicon nitride film, or a silicon oxynitride film is formed.
For example, if the silicon oxynitride film 3002a formed of SiH ₄ , NH ₃ , and N ₂ O by plasma CVD is used for 10 to 2
00 nm (preferably 50 to 100 nm), and similarly S
A silicon oxynitride hydride film 3002b made of iH ₄ and N ₂ O is formed to have a thickness of 50 to 200 nm (preferably 100 to 15 nm).
It is laminated to a thickness of 0 nm). In this embodiment, the base film 30
Although 02 is shown as a two-layer structure, it may be formed as a single layer film of the insulating film or a structure in which two or more layers are laminated.

The island-shaped semiconductor layers 3003 to 3006 are formed of crystalline semiconductor films obtained by using a semiconductor film having an amorphous structure by a laser crystallization method or a known thermal crystallization method.
The island-shaped semiconductor layers 3003 to 3006 have a thickness of 25 to 8
It is formed with a thickness of 0 nm (preferably 30 to 60 nm). Although the material of the crystalline semiconductor film is not limited, it is preferably formed of silicon or a silicon germanium (SiGe) alloy.

To form a crystalline semiconductor film by the laser crystallization method, a pulse oscillation type or continuous oscillation type excimer laser, YAG laser, or YVO ₄ laser is used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and is applied to a semiconductor film. The crystallization conditions are appropriately selected by the practitioner, but when an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 400 mJ / cm ² (typically 200 to 30
0 mJ / cm ² ). When a YAG laser is used, its second harmonic is used and the pulse oscillation frequency is 1 to 10 kHz, and the laser energy density is 300 to 600 mJ / cm.
² (typically 350 to 500 mJ / cm ² ) is recommended. Then, laser light focused in a linear shape with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the overlapping ratio of the linear laser lights at this time (overlap ratio)
Is performed as 80 to 98%.

Next, island-shaped semiconductor layers 3003 to 3006
A gate insulating film 3007 is formed to cover the. The gate insulating film 3007 is formed by an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, the silicon oxynitride film is formed to a thickness of 120 nm. Of course, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O _{2 are} formed by the plasma CVD method.
And are mixed, reaction pressure 40 Pa, substrate temperature 300 to 400
℃, high frequency (13.56MHz), power density 0.5 ~
It can be formed by discharging at 0.8 W / cm ² . The silicon oxide film produced in this way is
Good characteristics as a gate insulating film can be obtained by thermal annealing at ˜500 ° C.

Then, a first conductive film 3008 and a second conductive film 3009 for forming a gate electrode are formed on the gate insulating film 3007. In this embodiment, the first conductive film 3008 is formed of Ta to a thickness of 50 to 100 nm, and the second conductive film 3008 is formed.
The conductive film 3009 is formed of W to a thickness of 100 to 300 nm.

The Ta film is formed by sputtering, and the Ta target is A
It is formed by sputtering with r. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film peeling can be prevented. Further, the resistivity of the α-phase Ta film is about 20 μΩcm and it can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm, which is not suitable for the gate electrode. To form an α-phase Ta film, an α-phase Ta film can be easily obtained by forming tantalum nitride having a crystal structure close to that of Ta α-phase with a thickness of about 10 to 50 nm on the underlayer of Ta. You can

When forming a W film, it is formed by a sputtering method with W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ).
In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The W film can be made to have a low resistivity by enlarging the crystal grains, but when W contains many impurity elements such as oxygen, crystallization is hindered and the resistance becomes high. From this, in the case of the sputtering method, the purity is 99.
A resistivity of 9 to 20 .mu..OMEGA.cm can be realized by using a W target of 9999% and forming a W film with sufficient consideration so that impurities are not mixed from the vapor phase during film formation.

In this embodiment, the first conductive film 300 is used.
Although 8 is Ta and the second conductive film 3009 is W, it is not particularly limited, and any of them is an element selected from Ta, W, Ti, Mo, Al, Cu, or an alloy containing the above element as a main component. It may be formed of a material or a compound material. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As a preferable example of a combination other than this embodiment, the first conductive film 3008 is formed of tantalum nitride (TaN), and the second conductive film 3009 is formed.
, W is used to form the first conductive film 3008 from tantalum nitride (TaN), the second conductive film 3009 is used to form Al, and the first conductive film 3008 is formed from tantalum nitride (TaN). A combination of Cu for the second conductive film 3009 and the like can be given.

In addition, when the LDD can be made small, the structure of W single layer or the like may be used. Even if the structure is the same, the length of the LDD can be made small by setting the taper angle. .

Next, resist masks 3010 to 3
015 is formed, and a first etching process for forming electrodes and wirings is performed. In this embodiment, ICP (Inductively
Coupled Plasma: Inductively coupled plasma) etching method is used, CF ₄ and Cl ₂ are mixed as an etching gas, and a pressure of 1 Pa is applied to a coil-type electrode of RF of 500 W (13.56 MH).
z) Power is supplied to generate plasma. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film are etched to the same degree.

Under the above etching conditions, the shape of the mask made of a resist is made appropriate, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. Become. The angle of the taper portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the overetching process. Thus, the first shape conductive layers 3017 to 3022 including the first conductive layer and the second conductive layer are formed by the first etching treatment (first conductive layer 3017).
a-3022a and second conductive layers 3017b-3022
b) is formed. At this time, in the gate insulating film 3007, regions which are not covered with the first shape conductive layers 3017 to 3022 are etched by about 20 to 50 nm to form thin regions 3016. (FIG. 15 (B)) Subsequently, as shown in FIG. 15 (C), the resist mask 3
The second etching process is performed without removing 010 to 3015. CF ₄ , Cl ₂ and O ₂ are used as etching gas,
The W film is selectively etched. At this time, the second shape conductive layers 3024 to 3029 are formed by the second etching treatment.
(First conductive layers 3024a to 3029a and second conductive layers 3024b to 3029b) are formed. At this time, in the gate insulating film 3007, the second shape conductive layer 30 is formed.
The area not covered by 24-3029 is 20-50 nm
A region 3023 which is thinned by etching is formed.

The etching reaction of the W film or the Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the radical or ion species generated and the vapor pressure of the reaction product. W and Ta
Comparing the vapor pressures of the fluorides and chlorides of W, the fluoride of W, WF _6, is extremely high, and the other WCl ₅ , TaF ₅ , TaCl ₅
Are about the same. Therefore, the W film and the Ta film are both etched by the mixed gas of CF ₄ and Cl ₂ . However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, Ta has a relatively small increase in etching rate even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ . Further, since Ta oxide does not react with fluorine or chlorine,
The etching rate of the Ta film decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and it is possible to make the etching rate of the W film higher than that of the Ta film.

Then, a first doping process is performed to add an impurity element imparting n-type. The doping method may be an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 10 ^{13 to} 5 × 10 5.
¹⁴ atoms / cm ² and accelerating voltage of 60 to 100 keV. An element belonging to Group 15 is used as the impurity element imparting n-type, typically phosphorus (P) or arsenic (As), but phosphorus (P) is used here. In this case, the conductive layer 3
024 to 3029 serve as a mask for the impurity element imparting n-type, and the first impurity region 3030 is self-aligned.
~ 3033 are formed. First impurity regions 3030 to 3030
An impurity element imparting n-type is added to 3033 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . (Fig. 15
(C)) Then, as shown in FIG. 16A, the p-type TFT and the pixel portion TFT
A second doping process is performed after the portions to be covered with the resist masks 3034 and 3035 are covered. At this time, the pixel section
All TFTs are not covered with a resist mask and the outside is opened for doping. In the second doping process, the dose amount is made lower than that in the first doping process, and an impurity element imparting n-type is doped under the condition of a high acceleration voltage. For example, the acceleration voltage is set to 70 to 120 keV and 1 × 10 ¹³ atoms is set.
This is performed with a dose amount of / cm ² , and new impurity regions 3036 to 3038 are formed in the first impurity regions 3030 to 3033 formed in the island-shaped semiconductor layer in FIG. 15B. In the doping, the second shape conductive layers 3024 and 3028 are used as a mask for the impurity element, and the first conductive layers 3024a and 302 which are not covered with the resist mask are used.
Doping is performed so that the impurity element is also added to the semiconductor layer in the region below 8a. Thus, the third impurity regions 3039 and 3040 are formed. The concentration of phosphorus (P) added to the third impurity regions 3039 and 3040 has a gentle concentration gradient according to the film thickness of the tapered portions of the first conductive layers 3024a and 3028a. In addition,
In the semiconductor layer which overlaps with the tapered portions of the first conductive layers 3024a and 3028a, the first conductive layers 3024a and 3024a
Although the impurity concentration slightly decreases from the end of the tapered portion 28a toward the inside, the impurity concentration is almost the same.

Then, as shown in FIG. 16B, the island-shaped semiconductor layer 3004 forming the p-channel TFT and the island-shaped semiconductor layer 3006 forming the storage capacitor have conductivity opposite to that of the first conductivity type. The fourth impurity regions 3043 and 3044 of the mold are formed. Second shape conductive layers 3025b and 3028b
Is used as a mask for the impurity element to form an impurity region in a self-aligned manner. At this time, the island-shaped semiconductor layer 3003 forming the n-channel TFT and the pixel portion TFT 30
Reference numeral 05 covers the entire surface with resist masks 3041 and 3042. Doping the second shape conductive layer 302
5, 3028 is used as a mask against the impurity element,
Doping is performed so that the impurity element is also added to the semiconductor layers in the regions below the first conductive layers 3025a and 3028a which are not covered with the resist mask. Thus, fifth impurity regions 3045 and 3046 are formed. Although phosphorus is added to the impurity regions 3043 and 3044 at different concentrations, they are formed by an ion doping method using diborane (B ₂ H ₆ ) and the impurity concentration is 2 × 10 ²⁰ to It should be 2 × 10 ²¹ atoms / cm ³ .

Impurity regions are formed in the respective island-shaped semiconductor layers by the above steps. Second that overlaps with the island-shaped semiconductor layer
The conductive layers 3024 to 3027 in the shape of the above function as gate electrodes. Further, 3029 functions as an island-shaped source signal line. 3028 functions as a capacitor wiring.

Then, as shown in FIG. 16C, after removing the resist masks 3041 and 3042, a step of activating the impurity elements added to the respective island-shaped semiconductor layers for the purpose of controlling the conductivity type. I do. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500.
The heat treatment is performed at ˜600 ° C. In this embodiment, the heat treatment is performed at 500 ° C. for 4 hours. However, the second shape conductive layer 3
When the wiring material used for 024 to 3029 is weak to heat, it is preferable to activate after forming an interlayer insulating film 3047 (having silicon as a main component) in order to protect the wiring and the like.

Further, a step of hydrogenating the island-shaped semiconductor layer is performed by performing heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step of terminating the dangling bond of the semiconductor layer by thermally excited hydrogen. As another means of hydrogenation,
Plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, a first interlayer insulating film 3047 is formed from a silicon oxynitride film with a thickness of 100 to 200 nm. A second interlayer insulating film 3048 made of an organic insulating material such as acrylic is formed thereon. Further, as the second interlayer insulating film 3048, an inorganic material can be used instead of the organic insulating material. Inorganic materials include inorganic SiO ₂ , SiO ₂ (PCVD-SiO ₂ ) produced by plasma CVD method, SOG (Spi
n on Glass; coated silicon oxide film) or the like is used. An etching process for forming a contact hole is performed after forming the two interlayer insulating films.

Then, a source wiring 304 for forming a contact with the source region of the island-shaped semiconductor layer in the driving circuit portion.
9, 3050 and a drain wiring 3051 that forms a contact with the drain region are formed. Further, in the pixel portion, the connection electrode 3052, the pixel electrodes 3053, 3054
Are formed (FIG. 17A). By this connection electrode 3052, the source signal line 3029 is electrically connected to the writing TFT. Note that the pixel electrodes 3053 and 30
54 and the storage capacitor are for adjacent pixels.

In this embodiment, the write TFT is
Although the double-gate structure is shown, a single-gate structure, a triple-gate structure, or a multi-gate structure may be used.

As described above, the n-channel TFT, p
A drive circuit unit having a channel type TFT, a writing TFT,
The pixel portion having a storage capacitor can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate.

In this embodiment, the end portions of the pixel electrodes are arranged so as to overlap the source signal lines and the writing gate signal lines so that the gap between the pixel electrodes can be shielded without using the black matrix. ing.

Further, according to the process shown in this embodiment, the number of photomasks required for manufacturing the active matrix substrate is 5 (island semiconductor layer pattern, first wiring pattern (source signal line, capacitance wiring), It can be used as a mask pattern, a contact hole pattern, a second wiring pattern (including a pixel electrode and a connection electrode) of the p-channel region. As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.

Subsequently, after obtaining the active matrix substrate in the state of FIG. 17A, an alignment film 3055 is formed on the active matrix substrate and rubbing treatment is performed.

On the other hand, a counter substrate 3056 is prepared. Color filter layers 3057 to 305 are formed on the counter substrate 3056.
9. Overcoat layer 3060 is formed. The color filter layer is a red color filter layer 30 above the TFT.
57 and the blue color filter layer 3058 are formed so as to overlap with each other so as to also serve as a light shielding film. Since it is necessary to shield light from at least the TFT and between the connection electrode and the pixel electrode, it is preferable to arrange the red color filter and the blue color filter in an overlapping manner so as to shield the positions thereof.

Further, a red color filter layer 3057, a blue color filter layer 3058, and a green color filter layer 3059 are overlapped with each other in accordance with the connection electrode 3052. The color filter for each color is made of acrylic resin mixed with a pigment and is formed with a thickness of 1 to 3 μm. This can be formed into a predetermined pattern using a mask using a photosensitive material. The overcoat layer 3060 is formed of a photo-curing or thermosetting organic resin material, for example, polyimide or acrylic resin is used.

The arrangement of the spacers may be determined arbitrarily.
For example, although not shown here, it may be arranged in the liquid crystal material on the connection electrode. Further, the spacer may be arranged over the entire surface of the driving circuit portion, or may be arranged so as to cover the source wiring and the drain wiring.

After forming the overcoat layer 3060,
The counter electrode 3061 is patterned to form the alignment film 306.
After forming 2, the rubbing process is performed.

Then, the active matrix substrate in which the pixel portion, the driving circuit portion, and the memory cell are formed is attached to the counter substrate with a sealant 3064. Sealant 3064
Contains a filler, and the two substrates are bonded to each other with a uniform interval by the filler and the spacer. After that, a liquid crystal material 3063 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material 3063. Thus, the active matrix type liquid crystal display device shown in FIG. 17B is completed.

Although the TFT having the CMOS structure is shown in the embodiment, such a TFT can be used to form a memory cell as shown in FIG.

Although the TFT in the active matrix type liquid crystal display device manufactured by the above process has a top gate structure, this embodiment is easy for a bottom gate structure TFT and other structure TFTs. Can be applied to. (Embodiment 3) In this embodiment, an example of a manufacturing process when the present invention is used for a reflective liquid crystal display device, which is different from the liquid crystal display device shown in Embodiment 2, will be described.

According to the second embodiment, the active matrix substrate shown in FIG. 18A (similar to FIG. 17A) is manufactured. Subsequently, after forming a resin film as the third interlayer insulating film 3201, a contact hole is opened in the pixel electrode portion and a reflective electrode 3202 is formed. As the reflective electrode 3202, it is desirable to use a material having excellent reflectivity, such as a film containing Al or Ag as a main component, or a laminated film thereof.

On the other hand, a counter substrate 3056 is prepared. The counter substrate 3056 has a counter electrode 320 in this embodiment.
5 is formed by patterning. Counter electrode 3205
Is formed as a transparent conductive film. As the transparent conductive film,
A material composed of a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used.

Although not particularly shown, a color filter layer is formed when the color liquid crystal display device is manufactured. At this time, it is preferable that adjacent color filter layers of different colors are formed to overlap each other so as to also serve as the light shielding film of the TFT portion.

Then, alignment films 3203 and 3204 are formed on the active matrix substrate and the counter substrate,
Perform rubbing treatment.

Then, the active matrix substrate on which the pixel portion and the drive circuit portion are formed and the counter substrate are sealed with a sealant 32.
Stick together at 06. A filler is mixed in the sealant 3206, and the two substrates are bonded to each other with a uniform interval by the filler and the spacer. After that, a liquid crystal material 3207 is injected between both substrates and completely sealed with a sealant (not shown). Liquid crystal material 320
A known liquid crystal material may be used for 7. Thus, the reflective liquid crystal display device shown in FIG. 18B is completed.

Further, the present invention can be easily applied to the case of manufacturing a semi-transmissive display device in which half of the pixels are reflective electrodes and the other half are transparent electrodes. (Embodiment 4) FIG. 19 shows a frame memory having a different configuration from the frame memory shown in FIG. 6 in Embodiment 1 of the present invention.
It will be described based on. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The frame memory in the liquid crystal display device of this embodiment has a DRAM structure as shown in FIG. Similar to the first embodiment, the memory capacity of the frame memory satisfies the following conditions.

Memory capacity ≧ number of pixels × number of gradations × number of colors Here, the number of colors is 3 for RGB colors and 1 for monochrome colors and black and white. Since the number of gradations is represented by the number of bits, it is 8 for 256 gradations, 6 for 64 gradations, and 3 for 8 gradations.

The source electrode of the memory transistor 601 is connected to the data line 303, while the gate electrode is connected to the word line 302.

The drain electrode of the memory transistor 601 is connected to the data storage capacitor 602. Then, by applying a predetermined voltage to the word line 302, the memory transistor 601 is turned on, and the display data supplied to the data line 303 is stored in the data holding capacitor 602.
Similarly, in reading, when a predetermined voltage is applied to the word line 302, the memory transistor 601 is turned on and the display data stored in the data holding capacitor 602 is read out through the data line 303.

If the frame memory has a sufficient capacity, the refresh circuit required for a normal DRAM can be eliminated. This is because, in the present embodiment, the display data is read and rewritten every 1 / z (z is the total frame memory capacity divided by the unit frame) of one frame period using a part of the frame memory. .

This embodiment can be implemented by freely combining with Embodiments 1 to 3. (Embodiment 5) In the present invention, a display device using a light emitting element can be used instead of the display device using liquid crystal.
In this specification, a light emitting element refers to an element which emits light with a luminance corresponding to a flowing current or an element which emits light with a luminance corresponding to an applied voltage. As a light emitting element arranged in each pixel of the display device of the present invention, an element such as an OLED or an element using an electron source element, which causes each pixel to emit light when a current flows, can be freely used.

In this embodiment, an example in which a light emitting element arranged in each pixel of the display device of the present invention is an element using an MIM type electron source element and a display device is prepared is shown.

The MIM type electron source element is drawing attention because it can be miniaturized, an element having uniform characteristics can be manufactured, and it can be driven at a low voltage.

FIG. 21 is a sectional view showing the structure of a pixel of the display device of the present invention.

As shown in FIG. 20, the pixel structure has a switching transistor 711, a driving transistor 713, an electron source element 703, and a storage capacitor 715. When a signal is input to the gate line 718 and the switching transistor 711 is turned on, the source line 7
The 16 signal is input to the gate of the drive transistor 713 and the drive transistor 713 is turned on. Then, the potential of the power supply line 717 is applied to the electron source element 703 to emit light.

The storage capacitor 715 functions to move the driving transistor 713 while charge remains in the gate line 718 even if the signal on the gate line 718 is cut off. However, this capacitance is not always necessary because the parasitic capacitance generated in the circuit can be substituted.

FIG. 21 shows a cross-sectional view of the switching transistor 711 functioning as a switching element, the driving transistor 713, the storage capacitor 715 and the light emitting element. Note that an example in which the switching transistor 711 and the driving transistor 713 are manufactured using a TFT is shown.

In FIG. 21, a substrate 7 having an insulating surface is provided.
A switching transistor 711, a drive transistor 713, a storage capacitor 715, and an electron source element 737 are formed on the semiconductor device 20. The electron source element 737 is composed of a lower electrode 738, an upper electrode 743, and an insulating film 739 sandwiched between the lower electrode 738 and the electrode 743 on the interlayer film 736 formed of an insulator. . here,
726 is a gate insulating film, 733 is an interlayer film, 741 is a protective insulating layer, 740a is a contact electrode, 740b is an upper electrode bus line, and 742 is a protective electrode.

The gate electrode 730 of the switching transistor 711 is connected to the scanning line (not shown).
Impurity region 724 of switching transistor 711
Is connected to the signal line 734, and the impurity region 725 is connected to the gate electrode 731 of the driving transistor 713 and one electrode 732 of the storage capacitor 715. The other electrode 729 of the storage capacitor 715 is connected to the power supply line W (not shown). The impurity region 727 of the drive transistor 713 is connected to the power supply line W (not shown). The impurity region 728 of the driving transistor 713 is connected to the electrode 735. The electrode 735 is connected to the lower electrode 738 of the electron source element 737. The upper electrode 743 of the electron source element 737 is given a constant potential in all pixels via the contact electrode 740a and the upper electrode bus line 740b.

Here, the impurity region corresponds to the source region or the drain region of the TFT. The impurity region 7
When 24 is the source region, the impurity region 725 corresponds to the drain region, and when the impurity region 724 is the drain region, the impurity region 725 corresponds to the source region. Similarly, when the impurity region 727 is a source region, the impurity region 728 corresponds to a drain region, and when the impurity region 727 is a drain region, the impurity region 728 corresponds to a source region.

Although the pixel electrode is the lower electrode 738 in FIG. 21, the pixel electrode may be the upper electrode. At this time, a constant potential is applied to the lower electrode in all pixels.

A substrate 744 is provided so as to face the surface of the substrate 720 on which the electron source element 737 is provided. Note that the substrate 744 has a light-transmitting property. On the substrate 744,
A phosphor 745 is disposed to face the electron emission region 749 of the electron source element 737. Phosphor 745
A black matrix 748 is arranged around the. It should be noted that the surface of the phosphor 745 has a metal back layer 74.
6 is formed. Between the substrate 720 and the substrate 744 74
7 is kept in a vacuum.

As a method of manufacturing the switching transistor 711, the drive transistor 713, and the storage capacitor 715, a known method may be freely used. Also these
After the TFT is formed, an interlayer film 736 made of an insulator is formed, and an electron source element is formed thereon. At this time, as the interlayer films 733 and 736, the switching transistor 711, the driving transistor 713, and the storage capacitor 7 are used.
15, it is necessary to select the material and thickness that can sufficiently reduce the unevenness due to the wirings 735 and the like and obtain a flat surface.

The electron source element 73 is formed on the flattened insulating surface.
Form 7. The wiring 7 of the driving TFT 713 is formed on the flattened interlayer film 736 before the electron source element is formed.
It is also possible to make a contact hole connected to the lower electrode 35 and connect the lower electrode to the wiring 735 of the driving TFT 713 at the same time when the lower electrode is formed. As a method for manufacturing the electron source element 737, a known method may be used.

Here, the lower electrode 73 of the electron source element 737 is used.
8 is a pixel TFT (switching transistor 711,
It can be used as a light-shielding film of the driving transistor 713).

Note that the electron source element does not necessarily have to be arranged so as to overlap with the TFT (switching transistor 711, drive transistor 713) that constitutes a pixel.

By applying a voltage between the upper electrode 743 and the lower electrode 738, hot carriers are injected into this insulating film 739. Among the injected hot carriers, hot carriers having an energy larger than the work function of the material of the upper electrode 743 pass through the upper electrode 743 and are discharged into a vacuum.

Thus, the electrons emitted into the vacuum are accelerated in the vacuum maintained 747 by the voltage between the metal back layer 746 and the upper electrode 743. The accelerated electrons are incident on the phosphor 745 provided on the substrate 744 via the metal back layer 746. In this way, the phosphor 745 in the region where the electrons are incident emits light.

In the display device having the pixel having the structure shown in this embodiment, since the electron source element is arranged so as to overlap the TFT of each pixel, it is possible to form a fine pixel.

In this embodiment, similarly to the embodiment using the liquid crystal in the display portion, the pixel, the driving circuit and the memory cell can be integrally formed, which makes the reading speed from the memory fast and the signal Less affected by noise,
A display device with reduced power consumption is provided.

In the present embodiment, the display device (FED) for displaying by using the MIM type electron source element having the structure as shown in FIG. 21 is shown as an example.
The present invention can be applied to any known electron source element such as an IM type electron source element and an electron source element having a structure other than the MIM type. In addition, this embodiment can be implemented by freely combining with Embodiment 1 or Embodiment 4. (Embodiment 6) A display device using a light emitting element instead of the display device using liquid crystal, which has a structure different from that of the embodiment 5 of the present invention, will be described.

Here, as the light emitting element, an OLED (Organi
c Light Emitting Diode). In this specification, the OLED has a configuration including an anode, a cathode, and an organic compound layer sandwiched between the anode and the cathode.
The anode and the cathode correspond to the first electrode and the second electrode, respectively, and by applying a voltage between these electrodes, the OL
The ED emits light.

The organic compound layer usually has a laminated structure. Typically, Tang from the Kodak Eastman Company
The layered structure of "hole transport layer / light emitting layer / electron transport layer" proposed by them is mentioned. In addition, a hole injection layer / hole transport layer / light emitting layer / electron transport layer or a hole injection layer / hole transport layer / light emitting layer / electron transport layer / electron injection layer are laminated in this order on the anode. The structure is fine. You may dope a fluorescent dye etc. with respect to a light emitting layer.

In this specification, all layers provided between the cathode and the anode are collectively referred to as an organic compound layer. Therefore, the above-mentioned hole injection layer, hole transport layer, light emitting layer, electron transport layer,
The electron injection layer and the like are all included in the organic compound layer.

When a predetermined voltage is applied to the organic compound layer having the above structure from a pair of electrodes (anode and cathode), carriers are recombined in the light emitting layer to emit light. In this specification, making the OLED emit light is called driving the OLED.

In the present specification, the OLED may use either light emission (fluorescence) from singlet excitons or light emission (phosphorescence) from triplet excitons. .

The organic compound layer of the OLED may be any of low molecular weight material, high molecular weight material and medium molecular weight material.

In the present specification, the medium molecular material does not have sublimability and the length of chained molecules is 10 μm.
The following shall apply.

In this embodiment, a method for simultaneously manufacturing a pixel portion of a display device of the present invention and a driver circuit portion provided around the pixel portion will be described. Here, an example in which the transistors included in the pixel portion and the driver circuit portion provided around the pixel portion are TFTs is shown. In addition, an example in which the light emitting element included in each pixel is an OLED is shown.

The configuration of each pixel is the example shown in FIG. Here, an OLED is used instead of the electron source element 703. However, in order to simplify the description, a CMOS circuit, which is a basic unit for the drive circuit unit, is illustrated. In addition, a switching transistor and a driving transistor are shown as transistors included in the pixel portion.

First, as shown in FIG. 22A, a substrate 5001 made of glass such as barium borosilicate glass typified by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is oxidized. A base film 5002 made of an insulating film such as a silicon film, a silicon nitride film, or a silicon oxynitride film is formed.
For example, if the silicon oxynitride film 5002a made of SiH ₄ , NH ₃ , and N ₂ O is formed by the plasma CVD method to 10 to 2
00 nm (preferably 50 to 100 nm), and similarly S
A silicon oxynitride hydride film 5002b made of iH ₄ and N ₂ O is formed to have a thickness of 50 to 200 nm (preferably 100 to 15 nm).
It is laminated to a thickness of 0 nm). In this embodiment, the base film 50
Although 02 is shown as a two-layer structure, it may be formed as a single layer film of the insulating film or a structure in which two or more layers are laminated.

The island-shaped semiconductor layers 5003 to 5006 are formed of a crystalline semiconductor film which is a semiconductor film having an amorphous structure and is formed by a laser crystallization method or a known thermal crystallization method.
The island-shaped semiconductor layers 5003 to 5006 have a thickness of 25 to 8
It is formed with a thickness of 0 nm (preferably 30 to 60 nm). Although the material of the crystalline semiconductor film is not limited, it is preferably formed of silicon or a silicon germanium (SiGe) alloy.

To form a crystalline semiconductor film by the laser crystallization method, a pulse oscillation type or continuous oscillation type excimer laser, YAG laser, or YVO ₄ laser is used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and is applied to a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When using an excimer laser, the pulse oscillation frequency is 30 [Hz] and the laser energy density is 100 to 400 mJ / cm ² (typically 200 to 3).
00 mJ / cm ² ). When a YAG laser is used, its second harmonic is used and the pulse oscillation frequency is 1 to 10 kHz.
And the laser energy density is 300 to 600 mJ / cm ²
(Typically 350 to 500 mJ / cm ² ) is good. Then, laser light linearly condensed with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the overlapping ratio (overlap ratio) of the linear laser light at this time is set to 80 to 98%.

Next, island-shaped semiconductor layers 5003 to 5006
A gate insulating film 5007 is formed to cover. The gate insulating film 5007 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, the silicon oxynitride film is formed to a thickness of 120 nm. Of course, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O _{2 are} formed by the plasma CVD method.
And are mixed, reaction pressure 40 Pa, substrate temperature 300 to 400
℃, high frequency (13.56MHz), power density 0.5 ~
It can be formed by discharging at 0.8 W / cm ² . The silicon oxide film produced in this way is
Good characteristics as a gate insulating film can be obtained by thermal annealing at ˜500 ° C.

Then, a first conductive film 5008 and a second conductive film 5009 for forming a gate electrode are formed over the gate insulating film 5007. In this embodiment, the first conductive film 5008 is formed of Ta to a thickness of 50 to 100 nm, and the second conductive film 5008 is formed.
The conductive film 5009 is formed of W to a thickness of 100 to 300 nm.

The Ta film is formed by sputtering, and the Ta target is Ar.
It is formed by sputtering. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film peeling can be prevented. Further, the resistivity of the α-phase Ta film is about 20 μΩcm and it can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm, which is not suitable for the gate electrode. To form an α-phase Ta film, an α-phase Ta film can be easily obtained by forming tantalum nitride having a crystal structure close to that of Ta α-phase with a thickness of about 10 to 50 nm on the underlayer of Ta. be able to.

When a W film is formed, it is formed by a sputtering method with W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ).
In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The W film can be made to have a low resistivity by enlarging the crystal grains, but when W contains many impurity elements such as oxygen, crystallization is hindered and the resistance becomes high. From this, in the case of the sputtering method, the purity is 99.
A resistivity of 9 to 20 .mu..OMEGA.cm can be realized by using a W target of 9999% and forming a W film with sufficient consideration so that impurities are not mixed from the vapor phase during film formation.

Note that in this embodiment, the first conductive film 500 is used.
Although 8 is Ta and the second conductive film 5009 is W, it is not particularly limited, and any of them is an element selected from Ta, W, Ti, Mo, Al, Cu, or an alloy containing the above element as a main component. It may be formed of a material or a compound material. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. A desirable example of another combination other than this embodiment is the first conductive film 50.
08 is formed of tantalum nitride (TaN), and the second conductive film 5
009 as W, the first conductive film 5008 is formed of tantalum nitride (TaN), and the second conductive film 5009 is formed.
And Al as the first conductive film 5008 made of tantalum nitride (TaN) and the second conductive film 5009 as Cu.

Next, masks 5010 to 5 are formed by resist.
015 is formed, and a first etching process for forming electrodes and wirings is performed. In this embodiment, ICP (Inductively
Coupled Plasma: Inductively coupled plasma etching method is used, CF ₄ and Cl ₂ are mixed in an etching gas, and RF of 500 W (13.56 MHz) is applied to a coil type electrode at a pressure of 1 Pa.
Power is supplied to generate plasma. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage. CF ₄
When Cl and Cl ₂ are mixed, the W film and the Ta film are etched to the same extent.

Under the above etching conditions, by appropriately adjusting the shape of the mask made of resist, the ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. Become. The angle of the taper portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the overetching process. Thus, the first shape conductive layers 5017 to 5022 (first conductive layer 5017) including the first conductive layer and the second conductive layer are formed by the first etching treatment.
a-5022a and second conductive layers 5017b-5022
b) is formed. At this time, in the gate insulating film 5007, regions that are not covered with the first shape conductive layers 5017 to 5022 are etched by about 20 to 50 nm to form thin regions 5016. (FIG. 22 (B)) Subsequently, as shown in FIG. 22 (C), a second etching process is performed without removing the resist mask. CF ₄ , Cl _2, and O ₂ are used as an etching gas, and the W film is selectively etched. At this time, the second etching process
Shaped conductive layers 5024 to 5029 (first conductive layer 50
24a to 5029a and second conductive layers 5024b to 502
9b) is formed. At this time, in the gate insulating film 5007, regions which are not covered with the second shape conductive layers 5024 to 5029 are further etched by about 20 to 50 nm to form thin regions 5023.

The etching reaction of the W film or the Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the radical or ionic species generated and the vapor pressure of the reaction product. W and Ta
Comparing the vapor pressures of the fluorides and chlorides of W, the fluoride of W, WF _6, is extremely high, and the other WCl ₅ , TaF ₅ , TaCl ₅
Are about the same. Therefore, the W film and the Ta film are both etched by the mixed gas of CF ₄ and Cl ₂ . However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, Ta has a relatively small increase in etching rate even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ . Further, since Ta oxide does not react with fluorine or chlorine,
The etching rate of the Ta film decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and it is possible to make the etching rate of the W film higher than that of the Ta film.

Then, a first doping process is performed to add an impurity element imparting n-type. The doping method may be an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 10 ^{13 to} 5 × 10 5.
¹⁴ atoms / cm ² and accelerating voltage of 60 to 100 keV. An element belonging to Group 15 is used as the impurity element imparting n-type, typically phosphorus (P) or arsenic (As), but phosphorus (P) is used here. In this case, the conductive layer 5
024 to 5029 serve as a mask for the impurity element imparting n-type, and the first impurity region 5030 is self-aligned.
~ 5033 are formed. First impurity region 5030 to
5033 is added with an impurity element imparting n-type in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . (Fig. 22
(C)) Then, as shown in FIG. 23A, a second doping process is performed. At this time, as in the case of the liquid crystal process, p-type TF
T, the switching transistor, and the driving transistor are covered with resist masks 5034 to 5036. However, the switching transistor is not entirely covered with the resist mask, and the outer portion is opened to perform doping. In the second doping process, the dose amount is made lower than that in the first doping process, and an impurity element imparting n-type is doped under the condition of a high acceleration voltage. For example, the acceleration voltage is 70 to 1
20 keV, with a dose of 1 × 10 ¹³ atoms / cm ² ,
New impurity regions 5037 are formed in the first impurity regions 5030 to 5033 formed in the island-shaped semiconductor layer in FIG.
Forming 5038. In the doping, the second shape conductive layer 5024 is used as a mask for the impurity element, and the first conductive layer 5024a which is not covered with the mask is used.
Doping is performed so that the impurity element is also added to the lower region. Thus, the third impurity region 5039 is formed. The concentration of phosphorus (P) added to the second impurity region 5039 has a gentle concentration gradient according to the film thickness of the tapered portion of the first conductive layer 5024a. Note that in the semiconductor layer which overlaps with the tapered portion of the first conductive layer 5024a, the impurity concentration is slightly lower inward from the end portion of the tapered portion of the first conductive layer 5024a, but the impurity concentration is almost the same. Is.

Then, as shown in FIG. 23B, island-shaped semiconductor layers 5004 and 500 forming a p-channel TFT.
6 is a fourth impurity region 5 having a conductivity type opposite to that of the first conductivity type.
042 and 5043 are formed. Second shape conductive layer 50
25b and 5028b are used as masks against the impurity element to form the impurity regions in a self-aligned manner. At this time,
The entire surface of the island-shaped semiconductor layer 5003 forming the n-channel TFT and the switching transistor 5005 are covered with resist masks 5040 and 5041. In the doping, the second shape conductive layers 5025 and 5028 are used as a mask for the impurity element, and the first conductive layers 5025a and 5028 which are not covered with the resist mask are used.
Doping is performed so that the impurity element is also added to the semiconductor layer in the region under a. Thus, the fifth impurity region 5
044 and 5045 are formed. Although phosphorus is added to each of the impurity regions 5042 and 5043, the impurity regions 5042 and 5043 are formed by an ion doping method using diborane (B ₂ H ₆ ), and the impurity concentration in each of the regions is 2 × 10 ²⁰ to 2 × 10.
It should be ²¹ atoms / cm ³ .

Impurity regions are formed in the respective island-shaped semiconductor layers by the above steps. Second that overlaps with the island-shaped semiconductor layer
The conductive layers 5024 to 5028 in the shape of the above function as gate electrodes. Further, 5029 functions as an island-shaped video signal input line.

After removing the resist masks 5040 and 5041, a step of activating the impurity elements added to the respective island-shaped semiconductor layers is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 400 to 700 in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less.
C., typically 500 to 600.degree. C., and in this embodiment, heat treatment is performed at 500.degree. C. for 4 hours. However,
When the wiring material used for the second shape conductive layers 5024 to 5029 is weak to heat, activation is performed after forming an interlayer insulating film 5046 (having silicon as a main component) to protect the wiring and the like. It is preferable.

Further, a step of hydrogenating the island-shaped semiconductor layer is performed by performing heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing hydrogen of 3 to 100%. This step is a step of terminating the dangling bond of the semiconductor layer by thermally excited hydrogen. As another means of hydrogenation,
Plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Then, as shown in FIG. 23C, the first
The interlayer insulating film 5046 is formed from a silicon oxynitride film by 100
It is formed to a thickness of 200 nm. After forming a second interlayer insulating film 5047 made of an insulating material on it, contact holes are formed in the first interlayer insulating film 5046, the second interlayer insulating film 5047, and the gate insulating film 5007. Each wiring (including connection wiring and signal line) 5048 to 50
After forming 53 and 5055 by patterning, the connection wiring 5
The pixel electrode 5054 in contact with 053 is formed by patterning.

As the second interlayer insulating film 5047, a film made of an organic resin can be used, and as the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene) or the like can be used. In particular, since the second interlayer insulating film 5047 has a strong implication of flattening, acrylic having excellent flatness is preferable.

An inorganic material can also be used as the second interlayer insulating film 5047. Particularly in this case, it is preferable to use an inorganic material because the OLED material can be prevented from deteriorating due to moisture absorption. Inorganic materials such as inorganic SiO ₂ and PCVD-Si
O ₂ , SOG, etc. are used. In this embodiment, the SOG film is formed with a film thickness capable of sufficiently flattening the step formed by the TFT.

The contact holes are formed by dry etching or wet etching to reach the n-type impurity region or the p-type impurity region,
A contact hole reaching the wiring, a contact hole (not shown) reaching the power supply line, and a contact hole (not shown) reaching the gate electrode are formed, respectively.

Wiring (connection wiring) 5048 to 505
As 3, 5055, a laminated film having a three-layer structure in which a Ti film having a thickness of 100 nm, an aluminum film containing Ti of 300 nm, and a Ti film having a thickness of 150 nm are continuously formed by a sputtering method is patterned into a desired shape. Of course, another conductive film may be used.

Further, in this example, an ITO film was formed as the pixel electrode 5054 to a thickness of 110 nm and patterned. Contact is made by arranging the pixel electrode 5054 so as to be in contact with and overlap with the connection wiring 5053.
In addition, 2 to 20% zinc oxide (ZnO) in indium oxide
You may use the transparent conductive film which mixed. This pixel electrode 5
054 becomes the anode of OLED. (FIG. 24 (A)) Next, as shown in FIG. 24 (B), an insulating film containing silicon (inorganic SiO ₂ film in this embodiment) is formed to a thickness of 500 nm to correspond to the pixel electrode 5054. An opening is formed at the position and a third interlayer insulating film 5056 which functions as a bank is formed. By using a wet etching method when forming the opening, it is possible to easily form a tapered side wall. If the side wall of the opening is not sufficiently gentle, the deterioration of the organic compound layer due to the step difference becomes a significant problem, so caution is required. Second interlayer insulating film 5047
And a third interlayer insulating film 5056,
PCVD-SiO ₂ and PCVD-SiO ₂ , SOG and SOG, PCVD-Si on SOG
O ₂ and PCVD-SiO ₂ , acrylic and acrylic, SiO ₂ and PCVD-SiO ₂ on acrylic, and PCVD-SiO ₂ and acrylic are good.

Next, an organic compound layer 5057 and a cathode (MgAg electrode) 5058 are continuously formed by a vacuum evaporation method without exposing to the atmosphere. The thickness of the organic compound layer 5057 is 80 to 200 nm (typically 100 to 120 n).
m) and the thickness of the cathode 5058 may be 180 to 300 nm (typically 200 to 250 nm).

In this step, the organic compound layer and the cathode are sequentially formed on the pixel corresponding to red, the pixel corresponding to green, and the pixel corresponding to blue. However, since the organic compound layer has poor resistance to a solution, it must be formed individually for each color without using a photolithography technique. Therefore, it is preferable to hide a portion other than a desired pixel by using a metal mask and selectively form the organic compound layer and the cathode only in a necessary portion.

That is, first, a mask for covering all pixels except for the pixels corresponding to red color is set, and the organic compound layer for red light emission is selectively formed using the mask. Next, a mask which hides all pixels except the pixel corresponding to green is set, and the organic compound layer for green light emission is selectively formed using the mask.
Next, similarly, a mask for hiding all the pixels other than the pixels corresponding to blue is set, and the organic compound layer for blue light emission is selectively formed using the mask. Note that although different masks are used here, the same mask may be used again.

Although a method of forming three types of OLEDs corresponding to RGB is used here, a method of combining a white light emitting OLED and a color filter, a blue or blue green light emitting OLED and a phosphor (fluorescent color conversion). Layer: CCM) may be combined, a method in which a transparent electrode is used as a cathode (counter electrode), and an OLED corresponding to RGB may be stacked.

Known materials can be used for the organic compound layer 5057. As a known material, it is preferable to use an organic material in consideration of driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the organic compound layer.

Next, a metal mask is used to form a cathode 505 on a pixel (pixel on the same line) having a switching transistor whose gate electrode is connected to the same gate signal line.
8 is formed. In this embodiment, Mg is used as the cathode 5058.
Although Ag is used, the present invention is not limited to this. Cathode 50
Other known materials may be used as 58.

Finally, a passivation film 5059 made of a silicon nitride film is formed to a thickness of 300 nm. By forming the passivation film 5059, the organic compound layer 5057 can be protected from moisture and the like, and the reliability of the OLED can be further improved.

Thus, the structure shown in FIG.
The OLED display device is completed. In addition, the OLED in this embodiment
In the manufacturing process of the display device, Ta, W which is the material forming the gate electrode is taken into consideration due to the circuit configuration and the process.
The video signal input line is formed by and the gate signal line is formed by Al, which is the wiring material forming the drain / source electrodes, but different materials may be used.

By the way, in the OLED display device of the present embodiment, by arranging the TFT having the optimum structure not only in the pixel portion but also in the driving circuit portion, it is possible to exhibit extremely high reliability and improve the operating characteristics. It is also possible to add a metal catalyst such as Ni in the crystallization step to enhance the crystallinity. Thereby, the drive frequency of the signal line drive circuit can be set to 10 MHz or higher.

First, a TFT having a structure for reducing hot carrier injection so as not to slow down the operating speed as much as possible is used as an n-channel TFT of a CMOS circuit forming a drive circuit portion.

In the case of this embodiment, the active layer of the n-channel TFT is the overlap LDD region (L) which overlaps with the gate electrode with the source region, the drain region and the gate insulating film interposed therebetween.
_OV region), an offset LDD region (L _OFF region) that does not overlap the gate electrode with a gate insulating film interposed therebetween, and a channel formation region.

In the p-channel TFT of the CMOS circuit, deterioration due to hot carrier injection is hardly noticeable, so
In particular, the LDD region may not be provided. Of course, n-channel type T
Like the FT, it is possible to provide an LDD area and take measures against hot carriers.

In addition, in the driver circuit, a CMOS circuit in which current flows bidirectionally in the channel formation region, that is, a CMOS circuit in which the roles of the source region and the drain region are interchanged
When the circuit is used, the n-channel TFT forming the CMOS circuit preferably has LDD regions formed on both sides of the channel formation region with the channel formation region sandwiched therebetween. In addition, when a CMOS circuit that needs to keep off current as low as possible is used in the driver circuit, n
The channel TFT preferably has a L _OV region.

When the state shown in FIG. 24 (B) is actually completed, a protective film (laminate film, UV curable resin film, etc.) having high airtightness and little degassing and a transparent film are provided so as not to be further exposed to the outside air. It is preferable to perform packaging (encapsulation) with an optical sealing material. At that time, the reliability of the OLED is improved by making the inside of the sealing material an inert atmosphere or disposing a hygroscopic material (for example, barium oxide) inside.

[0187] Further, when the airtightness is enhanced by a process such as packaging, a connector (flexible printed circuit: FPC) for connecting a terminal routed from an element or a circuit formed on a substrate to an external signal terminal. Is attached to complete the product. In the present specification, a display device in such a ready-to-ship state is referred to as a display device.

Further, according to the steps shown in this embodiment, the number of photomasks required for manufacturing a display device can be suppressed. As a result, the process can be shortened, the manufacturing cost can be reduced, and the yield can be improved.

This embodiment can be implemented by being freely combined with Embodiment 1 or Embodiment 4.

[0190]

According to the present invention, with the above configuration, the reading speed from the memory is high, the influence of signal noise is small,
A display device that can be miniaturized can be provided. Also,
Wiring can be simplified as compared with the case where the mounted memory is used, and the area of the margin is not required, so that the size can be further reduced.

[Brief description of drawings]

FIG. 1 is a schematic diagram of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a block diagram 1 showing the configuration of the present invention.

FIG. 4 is a conventional block diagram.

FIG. 5 is a diagram showing a structure of a frame memory.

FIG. 6 is a circuit diagram of a memory cell

FIG. 7 is a circuit diagram of a sense amplifier.

FIG. 8 is a layout diagram of a latch

FIG. 9 is a circuit diagram of a latch.

FIG. 10 is a circuit diagram of a level shifter.

FIG. 11 is a circuit diagram of a DAC.

FIG. 12 is a circuit diagram of a voltage control switch.

FIG. 13 is a diagram showing a structure of a pixel portion.

FIG. 14 is a circuit diagram of a unit pixel.

FIG. 15 is a sectional view 1 during a process of forming a liquid crystal display unit and a drive circuit.

FIG. 16 is a sectional view 2 during a process of forming a liquid crystal display unit and a drive circuit.

FIG. 17 is a sectional view 3 during a process of forming a liquid crystal display unit and a drive circuit.

FIG. 18 is a sectional view 4 in the process of forming a liquid crystal display unit and a drive circuit.

FIG. 19 is a diagram showing a structure of a frame memory of a liquid crystal display device according to still another embodiment of the present invention.

FIG. 20 is a diagram showing a structure of a pixel portion.

FIG. 21 is a cross-sectional view of a display device using an MIM type electron source element.

FIG. 22 is a sectional view 1 during a process of forming a display unit and a drive circuit using OLED.

FIG. 23 is a cross-sectional view of a display unit using an OLED and a drive circuit forming process.

FIG. 24 is a cross-sectional view 3 of a display portion using OLED and a drive circuit formation process.

FIG. 25 is a block diagram 2 showing the configuration of the present invention.

FIG. 26 is a block diagram 3 showing the configuration of the present invention.

FIG. 27 is a block diagram 4 showing the configuration of the present invention.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 621M 623 623F 623G 631 631A 631K 680 680G 3/22 3/22 E 3/30 3/30 J H05B 33/14 H05B 33/14 AF term (reference) 2H092 GA32 GA40 GA50 GA59 JA03 JA24 JA28 JA34 JA37 JA41 KA04 KA05 MA14 MA18 NA01 NA11 NA25 2H093 NA16 NC09 NC24 NC26 NC29 NC34 NC35 NC38 ND10 ND15 ND39 ND39 ND39 ND39 ND39 ND39 AB17 DB03 GA00 5C006 AC21 AC26 AF01 AF42 AF43 AF44 AF83 AF84 BB16 BC03 BC06 BC12 BC16 BC20 BC23 BF02 BF04 BF46 EB04 EB05 FA31 FA41 5C080 AA06 AA10 BB05 DD22 DD27 DD28 FF11 GG12 JJ02 JJ03 JJ06

Claims (26)

[Claims] 1. A display device having a plurality of pixels formed by using thin film transistors on an insulating surface, a memory including a plurality of memory cells, and a drive circuit including a source driver and a gate driver. A display device, wherein serial signal data input from the outside is output in parallel to the plurality of pixels via the memory through a plurality of wirings. 2. A display device having a plurality of pixels formed by using thin film transistors on an insulating surface, a memory including a plurality of memory cells, and a drive circuit including a source driver and a gate driver. A display device comprising means for simultaneously reading out data stored in the plurality of memory cells as a digital signal and inputting the data to the plurality of pixels via a plurality of wirings formed on the insulating surface. 3. A display device having a plurality of pixels formed using thin film transistors on an insulating surface, a memory including a plurality of memory cells, and a drive circuit including a source driver and a gate driver, The drive circuit is
The data stored in the plurality of memory cells are simultaneously read out as digital signals and output through a plurality of wirings formed on the insulating surface, the output digital signals are held, and the held digital signals are held. Is simultaneously input to the plurality of pixels. 4. A display device having a plurality of pixels formed using thin film transistors on an insulating surface, a memory including a plurality of memory cells, and a drive circuit including a source driver and a gate driver. The drive circuit simultaneously reads the data stored in the plurality of memory cells as a digital signal and outputs the digital signal via a plurality of wirings formed on the insulating surface, and holds the output digital signal, A display device, which converts a held digital signal into an analog signal and inputs the analog signal to a plurality of pixels at the same time. 5. A display device having a plurality of pixels formed by using thin film transistors on an insulating surface, a memory including a plurality of memory cells, and a drive circuit including a CPU, a source driver and a gate driver. Then, the display device is characterized in that serial signal data input from the CPU is output in parallel to the plurality of pixels via the memory through a plurality of wirings. 6. The method according to any one of claims 1 to 5,
The display device has a function of simultaneously inputting a plurality of data of the memory cells to one row or one column of a plurality of pixels arranged in a matrix. 7. The method according to any one of claims 1 to 5,
The display device is characterized in that the driving circuit has a function of simultaneously inputting to a plurality of divided portions of one row or one column of the plurality of pixels. 8. The method according to any one of claims 1 to 7,
The display device, wherein the source driver includes a latch, a level shifter, and a DAC. 9. The method according to any one of claims 1 to 7,
The display device, wherein the source driver includes a level shifter and a DAC. 10. The display device according to claim 1, wherein the source driver includes a latch and a DAC. 11. The source driver according to claim 1, wherein the source driver includes a latch, a level shifter, and a DAC.
And a plurality of DACs are included in a pixel portion including the plurality of pixels. 12. The display device according to claim 8, wherein the DAC has a polarity inversion function. 13. The display device according to claim 1, wherein the memory has a capacity capable of storing a digital signal for at least one frame. 14. A display device according to claim 1, wherein the memory is SRAM. 15. The display device according to claim 1, wherein the memory is a DRAM. 16. The display device according to claim 1, wherein each of the plurality of pixels has a liquid crystal display element. 17. The display device according to claim 1, wherein each of the plurality of pixels has an OLED. 18. The display device according to claim 1, wherein each of the plurality of pixels has an electron source element. 19. The display device according to claim 1, wherein the thin film transistor is formed by using a polycrystalline semiconductor thin film. 20. The display device according to claim 1, wherein the thin film transistor is formed using an amorphous semiconductor thin film. 21. A plurality of pixels formed by using thin film transistors on an insulating surface, a memory including a plurality of memory cells, and a driver circuit including a source driver and a gate driver, which are input from the outside. A method for driving a display device, wherein parallel serial data is output to a plurality of pixels through a memory in parallel with a plurality of wirings. 22. A plurality of pixels formed by using thin film transistors on an insulating surface, a memory including a plurality of memory cells, and a drive circuit including a source driver and a gate driver, wherein the plurality of memories are provided. A method for driving a display device, comprising: reading data stored in a cell as a digital signal and inputting the data to the plurality of pixels at the same time. 23. A plurality of pixels formed by using thin film transistors on an insulating surface, a memory including a plurality of memory cells, and a drive circuit including a source driver and a gate driver, wherein the plurality of memories are provided. A method for driving a display device, comprising reading out data stored in a cell as a digital signal, holding the digital signal, and inputting the digital signal to the plurality of pixels at the same time. 24. A plurality of pixels formed using thin film transistors on an insulating surface, a memory including a plurality of memory cells, and a drive circuit including a source driver and a gate driver, wherein the plurality of memories are provided. A method for driving a display device, comprising reading data stored in a cell as a digital signal, holding the digital signal, converting the digital signal into an analog signal, and inputting the digital signal to the plurality of pixels at the same time. 25. The method for driving a display device according to claim 21, wherein the data is input to one row or one column of the plurality of pixels. 26. The display device according to claim 21, wherein the data is input to a portion obtained by further dividing one row or one column of the plurality of pixels into a plurality of portions. Driving method.