JP2003186942A - Printed wiring board design supporting device and method and its program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To precisely specify wiring or wiring parts to be improved by calculating the characteristic impedance of the target wiring, and to accurately output whether or not any error is generated in the wiring. <P>SOLUTION: The design supporting device for supporting the wiring design of a printed wiring board is provided with a setting means (21) for setting a selection condition for wiring and a prescribed condition for non-defectiveness/ defectiveness judgement, a calculating means (22) for calculating the characteristic impedance of the target wiring, a judging means (23) for judging whether or not the characteristic impedance calculated by the calculating means fulfills the prescribed condition, and an error outputting means (24) for error-outputting the target wiring violating the prescribed condition. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for supporting the design of a printed wiring board, and more particularly to a method for designing a printed wiring board in consideration of the characteristic impedance of wiring.

[0002]

2. Description of the Related Art In recent years, the performance of electronic devices has been remarkably improved, and the size and weight of the electronic devices have been reduced. Along with this, printed wiring boards provided in electronic devices have been downsized and mounted at a high density, and the lengths of wirings and the distances between wirings have become significantly shorter. As a result, it is necessary to design the wiring so that the characteristic impedance of the wiring becomes constant.

In order to design such a printed wiring board, it has been proposed to use CAD. For example,
Japanese Patent Laid-Open No. 9-199863 proposes a design method in which the wiring pattern width is changed according to the position from the power supply layer so that the characteristic impedance becomes substantially constant. In this case, the characteristic impedance is calculated assuming that the width of a certain reference wiring is the reference width and the width of the adjacent target wiring is the reference width, and the difference from the characteristic impedance of the reference wiring is calculated to obtain the target wiring. The characteristic impedances are matched by changing the width of. In addition, JP 2000
Japanese Patent Laid-Open No. 357180/1975 proposes a design method for circumventing wiring so that the characteristic impedance becomes substantially constant. In this case, detect how the target wiring is in relation to the power / ground (ground) wiring,
When it is detected that there is a predetermined positional relationship, the detour is calculated assuming that the characteristic impedance of the target wiring changes.

Further, for example, Japanese Patent Laid-Open No. 2000-20573.
Japanese Patent Publication proposes a method of checking whether the clock wiring is wired in a layer adjacent to the power supply / ground layer and whether or not there are ground guard wirings on both sides of the wiring, and displaying an error if there is not. ing. Further, Japanese Patent Laid-Open No. 2001-67390 proposes a method of estimating the impedance discontinuity based on the layout information of the printed wiring board. In this case, the discontinuity point of the characteristic impedance of the target wiring is detected by detecting the positional relationship between the target wiring and the power supply / ground or the change point of the width of the wiring.

[0005]

However, in the technique disclosed in Japanese Patent Laid-Open No. 9-199863, the width of the reference wiring is determined and then the widths of other wirings are determined.
There is a problem that the calculation is complicated. Further, in this method, since the widths of other wirings are determined based on the widths of the reference wirings, the widths of the wirings change midway, and the characteristic impedance changes due to this. However, there is also a problem that the characteristic impedance cannot be accurately determined.

Further, the technique disclosed in Japanese Patent Laid-Open No. 2000-357180 judges whether the characteristic impedance changes depending on the positional relationship between the target wiring and the power supply / ground wiring without obtaining the characteristic impedance of the target wiring. Therefore, there is a problem that the characteristic impedance cannot be controlled accurately. In addition, there is a problem that it is not possible to cope with a wiring whose width changes midway and the characteristic impedance changes due to this.

Further, since the technique disclosed in Japanese Patent Laid-Open No. 2000-20573 determines whether or not there is a problem with the wiring based on the relationship between the target wiring and other wiring, the width of the wiring changes in the middle. However, there is a problem in that it is not possible to deal with the wiring whose characteristic impedance changes due to this.

Further, although the technique disclosed in Japanese Patent Laid-Open No. 2001-67390 can detect the discontinuity in the impedance of the wiring, it does not calculate the characteristic impedance value itself of the target wiring, so that the characteristic impedance is not calculated. Although there is no continuous portion, it is actually difficult to specify a wiring whose characteristic impedance value does not match the reference value.

Therefore, the present invention solves the above-mentioned problems of the prior art, calculates the characteristic impedance of the target wiring, and can accurately specify the wiring or wiring portion to be improved, and a printed wiring board design support apparatus. It is an object of the present invention to provide a method, a program for causing a computer to perform a process for supporting wiring design of a printed wiring board, and a recording medium storing the program.

Further, according to the present invention, it is possible to calculate the characteristic impedance of the target wiring, accurately specify the wiring or the wiring portion to be improved, and accurately output whether or not there is an error in the wiring. A board design support apparatus and method, a program for causing a computer to perform a process for supporting the wiring design of a printed wiring board, and a recording medium storing the program, and particularly a wiring improving means having an inappropriate characteristic impedance. The purpose is to be able to output automatically.

[0011]

In order to solve the above problems, according to the present invention, as described in claim 1, in a design support device for supporting the wiring design of a printed wiring board, the selection condition and the pass / fail judgment of the wiring are determined. Setting means for setting a predetermined condition for, a calculating means for calculating the characteristic impedance of the target wiring, a determining means for determining whether the characteristic impedance calculated by the calculating means satisfies the predetermined condition, An error output unit that outputs an error to the target wiring that violates the predetermined condition is provided. The characteristic impedance of the target wiring is calculated and compared with a specified value, and if the specified value is not satisfied, an error is output, so that the wiring or wiring portion to be improved can be accurately specified.

In order to solve the above problems, according to the present invention, as described in claim 2, in a design support device for supporting the wiring design of a printed wiring board, a predetermined condition for wiring selection condition and quality judgment. Setting means for setting conditions, calculating means for calculating the characteristic impedance of the target wiring, determining means for determining whether or not the characteristic impedance calculated by the calculating means satisfies the predetermined condition, and the predetermined condition It has an error output means for outputting an error in the violated target wiring, and an improvement method calculation means for calculating and outputting an improvement method for eliminating the error of the target wiring that has output an error.

As an example, as described in claim 3, the error output means according to claim 1 or 2 outputs the characteristic impedance of the target wiring calculated by the calculation means. As a result, it is possible to easily grasp and improve the degree to which the predetermined condition is not achieved.

As an example, as described in claim 4, in the calculation method according to claim 1 or 2, the constant potential region around the target wiring, in which the potential is maintained for at least a certain time, and the target wiring. Including the conditions for the insulator around the. As a result, the characteristic impedance can be calculated accurately.

As an example, the constant potential region according to claim 4 includes a ground region and a power source region. As a result, the characteristic impedance can be calculated accurately in a practical time.

As an example, as described in claim 6, the constant potential region according to claim 4 includes a signal line region varying at a frequency lower than a predetermined frequency. This allows
When the characteristic impedance is calculated, the conditions to be considered are expanded and set, and the characteristic impedance can be calculated more accurately.

As an example, as described in claim 7, in the calculation method according to claim 1 or 2, the conductive region located in a layer different from the target wiring and the conductivity located in the same layer as the target wiring. Area and. Thereby, the characteristic impedance can be accurately calculated.

As an example, as described in claim 8, the calculation means according to claim 1 or 2 omits the calculation of the characteristic impedance of the portion where the characteristic impedance of the target wiring changes within a predetermined range. . Thereby, the characteristic impedance can be calculated at high speed.

As an example, as described in claim 9, in the calculation means according to claim 1 or 2, the portion where the characteristic impedance of the target wiring changes within a predetermined range has the same characteristic impedance as other portions. , The target wiring is simplified. Thereby, the characteristic impedance can be calculated at high speed.

As an example, as described in claim 10,
The error output means according to claim 9 outputs the data of the simplified wiring portion. This makes it possible to easily study an improvement method including impedance matching.

As an example, as described in claim 11,
The calculation means according to claim 1 or 2 calculates the characteristic impedance of the target wiring by interpolating the numerical values of the characteristic impedance acquired in advance for a plurality of specific structures. As a result, the characteristic impedance can be calculated faster.

As an example, as described in claim 12,
A plurality of methods of calculating the characteristic impedance according to claim 1 or 2 are provided, and the calculation means has a plurality of calculation means corresponding to the plurality of calculation methods. Select one according to priority. As a result, the characteristic impedance can be calculated under the conditions suitable for the purpose.

As an example, as described in claim 13,
The improvement method calculation means according to claim 2 outputs at least one of a change in the width of the target wiring and a change in the distance from the target wiring to another constant potential region. This allows
It is possible to reliably improve the characteristic impedance of the wiring having the error.

As an example, as described in claim 14,
The improvement method calculation means according to claim 2 outputs a change in the width of the target wiring and a change in the distance from the target wiring to another constant potential region in accordance with a predetermined priority order. Thereby, the characteristic impedance of the wiring in question can be improved by an improvement method according to the purpose or situation.

As an example, as described in claim 15,
The improvement method calculating means according to claim 2 changes the width of the target wiring within a predetermined value range, and changes the distance from the target wiring to another potential region within a predetermined value range. As a result, it becomes possible to make improvements according to the purpose.

As an example, as described in claim 16,
The setting means according to claim 2 sets the improvement method for eliminating an error of the target wiring that has output an error. As a result, the user can set the desired improvement method, and the characteristic impedance can be improved as desired.

As an example, as described in claim 17,
The setting means according to claim 2 sets a plurality of the improvement methods for eliminating an error of the target wiring that has output an error, by setting priorities. As a result, it becomes possible to make improvements according to the purpose.

As an example, as described in claim 18,
The improvement method calculation means of claim 2 has a plurality of improvement means, and the setting means sets the improvement method to be selected by the improvement method calculation means. As a result, it becomes possible to make improvements according to the purpose.

Further, according to the present invention, in the design support method for supporting the wiring design of the printed wiring board, the step of setting the wiring selection condition and the predetermined condition for the quality judgment, Calculating a characteristic impedance of the target wiring, and determining whether the calculated characteristic impedance satisfies the predetermined condition,
And outputting an error in the target wiring that violates the predetermined condition.

Further, according to the present invention, in the design support method for supporting the wiring design of the printed wiring board, the step of setting a wiring selection condition and a predetermined condition for quality judgment, Calculating a characteristic impedance of the target wiring, and determining whether the calculated characteristic impedance satisfies the predetermined condition,
The method includes the steps of outputting an error in the target wiring that violates the predetermined condition, and calculating and outputting an improvement method for eliminating an error in the target wiring that has output an error.

Further, according to the present invention, as described in claim 21, in a program for causing a computer to perform a process for supporting wiring design of a printed wiring board, a wiring selection condition and a predetermined condition for pass / fail judgment. The step of setting, a step of calculating the characteristic impedance of the target wiring, a step of determining whether the calculated characteristic impedance satisfies the predetermined condition,
And outputting an error in the target wiring that violates the predetermined condition.

Further, according to the present invention, as described in claim 22, in a program for causing a computer to perform processing for supporting wiring design of a printed wiring board, a wiring selection condition and a predetermined condition for pass / fail judgment. The step of setting, a step of calculating the characteristic impedance of the target wiring, a step of determining whether the calculated characteristic impedance satisfies the predetermined condition,
The method includes the steps of outputting an error in the target wiring that violates the predetermined condition, and the step of calculating and outputting an improvement method for eliminating the error in the target wiring that has output an error.

Furthermore, the present invention is a computer-readable recording medium storing the program according to claim 21 or 22 as described in claim 23.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a diagram showing a hardware configuration of a printed wiring board design support device according to a first embodiment of the present invention. The illustrated printed wiring board design support device is a computer having an input unit 11, a calculation unit 12, an output unit 13, and a storage unit 14. The input unit 11 is for inputting data to the computer, such as a keyboard, a mouse, and an interface with an external device. The arithmetic unit 12 includes a central processing unit, a memory, and the like, and performs data processing of printed wiring board design support according to a program stored in the memory. Arithmetic unit 12
Functions as the characteristic impedance calculation unit 121 and the determination unit 122 for a predetermined condition. The output unit 13 electronically or visually outputs the data processed by the arithmetic unit 12, such as a display, a printer, a speaker, and an interface. The storage unit 14 is a magnetic disk, a magneto-optical disk, C
It is composed of a D-ROM or the like, and stores programs and data for causing a computer to perform a process for supporting the wiring design of the printed wiring board of the present invention. In addition, the storage unit 14
Is also a recording medium that stores a program for causing a computer to perform a process for supporting the wiring design of the printed wiring board.

FIG. 2 is a functional block diagram of the printed wiring board design support device shown in FIG. The printed wiring board design support device has a setting unit 21, a characteristic impedance calculation unit 22, a determination unit 23 for a predetermined condition, and an error output unit 24. The setting means 22 sets a wiring selection condition and a predetermined condition for quality judgment. The operator sets these conditions in the arithmetic unit 12 via the input unit 11.
The characteristic impedance calculator 22 calculates the characteristic impedance of the target wiring. The judging means 23 judges whether or not the calculated characteristic impedance satisfies the predetermined condition. The error output means 24 outputs an error to the target wiring that violates the predetermined condition.

The setting means 21 corresponds to the input section 11, and includes selection conditions including information such as signal names of wirings (target wirings) for which characteristic impedances are to be calculated, specified values of characteristic impedance values, and characteristic impedances. The specified value of the amount of change in the value, the specified value of the length of the wiring for which the characteristic impedance is to be calculated, the dimensional conditions of the target wiring and the conductor region for which the characteristic impedance is calculated, and a plurality of calculation means included in the determination means 23 ( A predetermined condition including information such as setting / changing the priority when selecting the method) is set.

The characteristic impedance calculating unit 22 corresponds to the characteristic impedance calculating unit 121 of the arithmetic unit 12, and for the wiring of the signal name set by the setting unit 21,
Further, the characteristic impedance is calculated from the wiring design information stored in advance in the storage unit 14 in consideration of the determination condition set by the setting unit 21.

The judging means 23 compares the calculated characteristic impedance value with the specified characteristic impedance value set by the setting means 21. Alternatively, the determination means 23
The change amount of the characteristic impedance value is compared with the specified value of the change amount of the characteristic impedance value set by the setting means 21.

The error output means 24 corresponds to the judgment part 122 and the output part 13 of the predetermined condition of the calculation part 12, and displays the wiring or a part of the wiring which has exceeded the specified allowable value by the judgment means 23. Output or output by character information.

As described above, the characteristic impedance of the target wiring is calculated and compared with the specified value, and if the specified value is not satisfied, an error is output. Therefore, the wiring or wiring portion to be improved should be specified with high accuracy. You can

When the means of each part shown in FIG. 2 is implemented by a program for operating a computer,
It can be said that FIG. 2 shows a flowchart of the program. It can be said that the storage unit 14 in FIG. 1 is a recording medium that stores the above program.

Next, some preferred embodiments of the above means will be described.

The characteristic impedance calculating means 22 has a plurality of characteristic impedance calculating methods, and selects one appropriate calculating method to calculate the characteristic impedance of the target wiring. The plurality of calculation methods include, for example, means (method) for interpolating based on the numerical values of the characteristic impedance acquired in advance for a plurality of specific structures, and when the target wiring is a microstrip line, the following analytical formula is used. There are means (methods) and means (methods) using numerical simulation.

[0044]

[Equation 1] Here, ε _r is the relative dielectric constant of an insulating layer (for example, glass epoxy resin) around the microstrip line, h is the height of the microstrip line with respect to the ground, w is the width of the microstrip line, and t is the width of the microstrip line. It is the thickness.

The characteristic impedance calculating means 22
Can also select one from these calculation means in accordance with a predetermined priority order.

FIG. 3 is a flow chart showing an operation in which the characteristic impedance calculating means 22 selects a characteristic impedance calculating method in accordance with a predetermined priority. The characteristic impedance calculation means 22 first executes step S11. In step S11, the characteristic impedance calculation means 22 determines whether or not there is an interpolation means. If it is determined that there is an interpolating means, the characteristic impedance calculating means 22 calculates the characteristic impedance of the target wiring using the interpolating means in step S12. That is, the calculation by the interpolation means has the highest priority. When it is determined from the determination result of step S11 that there is no interpolation means, the characteristic impedance calculation means 22 determines whether or not there is the above-described analytical expression in step S13. If it is determined that there is an analytical expression, the characteristic impedance calculating means 22 calculates the characteristic impedance of the target wiring using the analytical expression in step S14. That is, the use of analytic formulas is the second highest priority. If the determination result of step S13 indicates that there is no analytical expression, the characteristic impedance calculating means 22 calculates the characteristic impedance of the target wiring by numerical simulation in step S15. That is, this calculation means has the lowest priority. This priority order is determined, for example, according to the calculation accuracy of the characteristic impedance. Further, the setting and changing of the priority order can be performed via the setting means 21. As described above, by preparing a plurality of methods for calculating the characteristic impedance and selecting them appropriately, the characteristic impedance can be calculated under the conditions suitable for the purpose.

The characteristic impedance calculating means 22
Can omit the calculation of the characteristic impedance of the portion where the characteristic impedance of the target wiring changes within a predetermined range. This can simplify the calculation of the characteristic impedance and speed up the calculation within a range where the calculation accuracy of the characteristic impedance can be satisfied. It should be noted that this point will be described in detail in Examples described later. Further, the characteristic impedance calculating unit 22 can simplify the target wiring by regarding the portion where the characteristic impedance of the target wiring changes within a predetermined range as having the same characteristic impedance as the other portions. Thereby, the characteristic impedance can be calculated at high speed.

The error output means 24 can also output the characteristic impedance of the target wiring calculated by the characteristic impedance calculation means 22 together with the error output.
This makes it easy to understand how the target wiring differs from the predetermined condition, and facilitates the process of calculating and outputting an improvement method for eliminating the error of the target wiring that has output an error described later. You can do it. Further, the error output means 24 can also output the data of the wiring portion simplified by the above-described simplification processing. As a result, it is possible to easily study an improvement method including impedance matching.
(Second Embodiment) FIG. 4 is a diagram showing a hardware configuration of a printed wiring board design support device according to a second embodiment of the present invention. In the figure, the same components as those shown in FIG. 1 are designated by the same reference numerals. In the second embodiment, the configuration of the arithmetic unit 12A is different from that of the arithmetic unit 12 of the first embodiment. The calculation unit 12A has an improvement method calculation unit 123 in addition to the characteristic impedance calculation unit 121 and the determination unit 122 of a predetermined condition of the first embodiment. Improvement method calculation unit 123
Calculates and outputs a method for removing the error of the target wiring that is output as an error by the judgment of the judgment unit 122 and improving the characteristic impedance.

FIG. 5 is a functional block diagram of the printed wiring board design support device shown in FIG. The printed wiring board design support device according to the present embodiment has an improvement method calculation means 25 and an improvement method output means 26 in addition to the means 21 to 24 described above. The improvement method calculation means 25 corresponds to the improvement method calculation unit 123 in FIG. 4, and calculates an improvement method for eliminating the error of the target wiring that has output an error. The improvement method output means 26 corresponds to the output unit 13 in FIG. 4, and outputs an improvement method for eliminating the calculated error. This allows
It is possible to easily improve the impedance of the problem wiring determined to be an error.

The setting means 21 can set priority information indicating whether the improvement method is to improve the wiring width or the distance from the wiring to the constant potential region. The constant potential region is not only a region that is always kept at a constant potential (for example, a ground or power source region), but also a region (for example, a signal line) where the potential is kept constant for a certain period of time, or a target. It includes a region (for example, a signal line) that changes at a frequency sufficiently lower than the frequency of the wiring. As a result, the characteristic impedance can be calculated accurately in a practical time. In particular, since the region where the frequency fluctuates is also used as the condition for calculating the characteristic impedance, the characteristic impedance can be calculated more accurately.

Further, in order to surely improve the characteristic impedance, a plurality of improving methods are prepared in advance. For example, there are a method of changing the wiring width (pattern width) and a method of changing the distance from the wiring to the constant potential region. The improvement method to be finally output can be determined according to a predetermined priority order. For this priority, either one of the set priorities may be selected first, and if the appropriate improvement method cannot be specified, the other improvement method may be calculated, or the improvement method to be selected may be determined. Calculation (for example, calculation regarding the size of the wiring area described later),
It is also possible to specify the improvement method to be selected according to the calculation result. The priority order is set using the setting means 21. By setting the priority order, the characteristic impedance of the wiring in question can be improved by using the improvement method according to the purpose and the situation.

FIG. 6 is a flow chart showing the operation of the improvement method calculation means 25. The improvement method calculation means 25 determines the priority of the improvement method in step S21. When it is detected in step S21 that the improvement method by changing the wiring width is set to a high priority, the process proceeds to step S32. When it is detected in step S21 that the improvement method by changing the distance from the wiring to the constant potential region is set to high priority, the process proceeds to step S22. Step S
When it is detected in 21 that the calculation of the wiring area is set, the process proceeds to step S28. The calculation of the wiring region is performed to determine whether to select the improvement by changing the wiring width or the improvement method by changing the distance from the wiring to the constant potential region.

First, the case where the improvement method by changing the wiring width starting from step S32 is set will be described. The improvement method calculation means 25 calculates the change value of the wiring width of the target wiring in step S32, and determines in step S33 whether this change value is within the specified value range of the wiring width. The predetermined value range can be arbitrarily set according to various factors such as the configuration, material, and application of the printed wiring board, and thus, improvement according to the purpose can be achieved. When it is determined that the changed value is within the specified value range of the wiring width, step S38
Then, the calculated value of this improvement method, that is, the changed value of the wiring width is stored in the storage unit 14. When it is determined that the changed value is not within the specified value range of the wiring width, the improvement method calculation means 25 sets the upper limit of the wiring width in step S34, and the changed value of the distance from the wiring to the constant potential region in step S35. To calculate. When it is determined that the changed value of the distance to the constant potential region is within the specified value range, the improvement method calculation means 25 causes the improvement method calculation unit 25 to perform step S3.
At 8, the changed value of the distance to the constant potential area is stored. When it is determined that the changed value of the distance to the constant potential region is not within the specified value range, the improvement method calculation unit 25 causes the improvement method calculation unit 25 to perform step S37.
To output an error.

Next, the case where the improvement method by the distance from the wiring to the constant potential area starting from step S22 is set will be described. In step S22, the improvement method calculation means 25 calculates a change value of the distance from the wiring to the constant potential area. When it is determined that the change value of the distance to the constant potential area is within the specified value range, the improvement method calculating unit 25 stores the calculated change value of the distance to the constant potential area in step S38. When it is determined that the change value of the distance to the constant potential region is not within the specified value range, the improvement method calculating means 25 sets the upper limit of the wiring width in step S24, and calculates the change value of the wiring width in step S25. . Then, the improvement method calculation means 25 determines in step S26 whether the wiring width is within the range of the specified value. When it is determined that the wiring width is within the range of the specified value, the improvement method calculation means 25 stores the changed value of the wiring width calculated in step S38 in the storage unit 14. When it is determined that the wiring width is not within the range of the specified value, the improvement method calculation means 25 outputs an error in step S27.

Next, the case where the setting for calculating the wiring area is detected in step S21 will be described. In step S28, the improvement method calculation means 25 calculates two sizes of the wiring area of the target wiring. One is the size of the wiring region when the wiring width is changed, and one is the size of the wiring region when the distance from the wiring to the constant potential region is changed. next,
In step S29, the improvement method calculation means 25 selects a method with a small wiring area size. When it is determined that the size of the wiring area when the wiring width is changed is small, the improvement method calculation means 25 sets the improvement method by changing the wiring width to a high priority in step S30, and returns to step S21. When it is determined that the size of the wiring area when the distance from the wiring to the constant potential area is changed is small, the improvement method calculation means 25 uses the improvement method based on the distance from the wiring to the constant potential area in step S31. The priority is set, and the process returns to step S21.

Next, examples of the present invention will be described.
The example described below is an example of the second embodiment, but the second embodiment includes the first embodiment,
An example of the first embodiment is included.

First, in each embodiment, a printed wiring board having a layer structure of 6 layers shown in FIG. 7 is targeted. Figure 7
6 is a diagram showing an image of a cross section of a 6-layer substrate, in which the first layer, the third layer, the fourth layer, and the sixth layer are signal wiring layers 31 and 3, respectively.
3, 34 and 36, and the second and fifth layers are power / ground layers 32 and 35. Insulating layers 41 to 47 are interposed between these layers. The layer structure of the printed wiring board can be variously selected according to each board, and the number of layers may be different.

FIG. 8 shows an example in which the width of the signal wiring 31 of the first layer changes midway and the changed section is short. That is, this is an example of a case where the section in which the characteristic impedance has changed is shorter than the specified value. In the figure, the wiring width is W in the section between l1 and l3
1, the same as W3 and the same characteristic impedance, but in the section of l2, the wiring width changes to W2 and the characteristic impedance also changes. However, if the wiring length in the section of l2 is equal to or less than the specified value, it is possible to omit this calculation and regard it as the same characteristic impedance as the section of l1 or l3 for processing. Thereby, the characteristic impedance can be calculated at high speed.

FIG. 9 shows an example of a part of a signal wiring cross section having three layers of guard ground wiring. For example, if the dimensions of the conductor region around the three-layer signal wiring as shown in FIG. 9 are within the specified value range, the conductor region is not simplified. However, for example, in FIG.
The conductor region around the signal wiring of three layers such as 0 has a dimension exceeding the specified value range. In this case, FIG. 10 simplifies the conductor region and assumes that it is equivalent to the conductor region as shown in FIG. Further, the calculation of the characteristic impedance, for example, using an interpolating means for interpolating based on the numerical value obtained in advance for a plurality of specific structures, in the case of microstrip, using the analytical formula, or using a numerical simulation You may set and determine a priority etc.

The interpolation means will be described. For example, when the above-mentioned analytical formula is used, the calculation result of the characteristic impedance is as shown in FIG. 12, where w / h is the value (h is the height of the microstrip line with respect to the ground (in other words, the dimension of the distance between the wiring and the conductor region), The larger w is the width of the microstrip line, the lower the accuracy compared to the actual characteristic impedance. Here, the solid line in FIG. 12 is the measured value, and the broken line is the characteristic impedance value calculated by the analytical formula. Therefore, numerical interpolation is performed from the value calculated in advance by numerical simulation or the like. For example, if the characteristic impedance calculated in advance is as shown in FIG. 13, then w
When the characteristic impedance is obtained from the values of h and h, for example, assuming that w / h is 0.6, the value of the characteristic impedance is, for example, 75Ω. On the contrary, when w / h is obtained from the value of the characteristic impedance, if the value of the characteristic impedance is, for example, 51Ω, w / h of 1.5 is obtained, and w or h can be obtained. Here, when the characteristic impedance is 51Ω, the value of w / h is obtained by interpolating from the values of N6 and N7 calculated in advance. When the characteristic impedance is 75Ω, the value of w / h is N calculated in advance.
Interpolation is performed from the values of 3 and N4. If the priority is, for example, the order of the interpolating means, the analytical expression, and the numerical simulation, the priority determining flow of the characteristic impedance calculating means is as shown in FIG. 3, for example. (Embodiment 1) Next, a specific wiring example will be used to explain how the improvement method calculating means 25 shown in the flowchart of FIG. 6 calculates the improvement method. As Example 1, description will be given of a case where wiring is performed on the first layer and the third layer.

FIG. 14 is a perspective view showing the wiring 31 of the first layer shown in FIG. 7, and FIG. 15 is an image of the wiring 33 of the third layer. When the characteristic impedance of the wiring having the signal name set by the setting means 21 of FIG. 5 is calculated by the characteristic impedance calculating means 22 of FIG. 5, the calculation result of the wiring of FIG. 14 becomes 51Ω, and the calculation result of the wiring of FIG. 15 becomes It becomes 43Ω. That is, when the specified value of the characteristic impedance is set to 51Ω, the wiring pattern is formed as shown in FIG. 14 while keeping the line width constant at 300 μm in order to match the characteristic impedance. After that, when the wiring pattern 33 of the third layer in FIG. 15 is formed, if the line width is set to 300 μm as set in FIG. 14, the characteristic impedance becomes 43Ω. In this case, the determination unit 23 of the predetermined condition of FIG.
Since 3Ω is an error, the error output means 24 of FIG. 5 outputs this wiring portion as an error.

The improvement method calculating means 25 of FIG. 6 is a means for reducing the wiring width or the wiring area in which the priority set by the setting means 21 is set to the wiring having an error in the predetermined condition judging means 23. When selected, the pattern width is calculated so as to be changed from 300 μm to 190 μm. Based on this calculation result, the improvement method output means 2 of FIG.
5 outputs the corresponding improvement method. At this time, if there are two or more options for improvement, the priority order is output according to the priority order set by the setting means 21. In this way, the wirings having different characteristic impedances can be easily set to the characteristic impedance within the reference value. (Embodiment 2) Next, a case where the specified value of the characteristic impedance is set to 43Ω with the same layer structure as that of Embodiment 1 will be described as Embodiment 2. When the characteristic impedance of the wiring of the signal name set by the setting means 21 is calculated by the characteristic impedance calculating means 22 as in the first embodiment, the calculation result of FIG. 14 is, for example, 51Ω, and the calculation result of FIG. 15 is, for example, 43Ω. . Here, the specified value of the characteristic impedance is 43Ω.
Is set, and the wiring width is kept constant at 300 μm in order to match this characteristic impedance, the wiring pattern is shown in FIG.
To form. Then, when the wiring pattern 31 of the first layer of FIG. 14 is formed, if the wiring width of the third layer 33 of FIG. 15 is set to the line width of 300 μm as it is set, the characteristic impedance becomes 51Ω. In this case, since the characteristic impedance 51Ω of FIG. 14 is an error in the determination means 23 of the predetermined condition of FIG. 6, the error output means 24
Outputs this wiring part as an error.

The improvement method calculation means 25 determines the pattern width of the wiring which has an error in the predetermined condition determination means 23 to be 300 μm.
It is calculated so as to change from m to 430 μm. Based on the calculation result, the improvement method output means 25 outputs the improvement method. In this way, the wirings having different characteristic impedances can be easily set to the characteristic impedance within the reference value. (Embodiment 3) Next, a case where the priority of the improvement method is improved by the distance from the wiring to the constant potential region under the same conditions as the specified value of the characteristic impedance of Embodiment 2 will be described as Embodiment 3. When the characteristic impedance of the wiring having the signal name set by the setting means 21 is calculated by the characteristic impedance calculating means 22 as in the second embodiment, the calculation result of FIG.
Ω, and the calculation result of FIG. 15 is, for example, 43Ω. Here, the specified value of the characteristic impedance is set to 43Ω, and the line width is set to 3 to match this characteristic impedance.
A wiring pattern is formed as shown in FIG. 15 while maintaining a constant value of 00 μm. Then, the wiring pattern 3 of the first layer in FIG.
When 1 is formed, if the line width is set to 300 μm as set by the wiring width of the three layers in FIG. 15, the characteristic impedance is 5
It becomes 1Ω.

In this case, the predetermined condition judging means 23
Since the characteristic impedance of 51Ω in FIG. 14 causes an error, the error output means 24 outputs this wiring portion as an error. Since the priority set by the setting unit 21 is improved by the distance from the wiring to the constant potential region, the improvement method calculating unit 25 selects the wiring in which the error has occurred in the predetermined condition determination unit 23. Predetermined condition determining means 21
It is calculated to form a guard earth with a space of 120 μm on both sides of the wiring pattern while keeping the pattern width of the wiring having an error of 300 μm. Here, the guard ground wiring is formed on both sides of the wiring pattern, but if possible, the size of the distance between the wiring and the conductor region in the vertical direction may be changed. Based on the result calculated by the improvement method calculation means 25, the improvement method output means 25 outputs the corresponding improvement method. In this way, the wirings having different characteristic impedances can be easily set to the characteristic impedance within the reference value. (Embodiment 4) Next, a case in which the guard ground wiring is provided on both sides of the signal wiring in the same layer structure as in Embodiment 1 will be described as Embodiment 4.

FIG. 16 is an image showing the wiring of the first layer with guard ground wiring, and FIG. 17 is an image of the wiring of the third layer with guard earth wiring. In FIG. 16, first-layer guard ground wires 51 and 52 are provided side by side on the left and right of the first-layer signal wiring 31. Similarly, in FIG. 17, third-layer guard ground wires 53 and 54 are provided on the left and right of the third-layer signal wiring 33. When the characteristic impedance of the wiring having the signal name set by the setting means 21 is calculated by the characteristic impedance calculating means 22, the wiring calculation result of FIG. 16 is, for example, 48Ω, and the wiring calculation result of FIG. 17 is, for example, 40Ω. Here, the specified value of the characteristic impedance is set to 48Ω, and a wiring pattern is formed as shown in FIG. 16 while keeping the line width constant at 300 μm in order to match the characteristic impedance. After that, when forming the wiring pattern of the third layer in FIG. 17, if the line width is set to 300 μm as set by the wiring width of the first layer in FIG. 16, the characteristic impedance becomes 40Ω.

In this case, the predetermined condition determining means 23
Since the characteristic impedance of 40Ω in FIG. 17 causes an error, the error output means 24 outputs this wiring portion as an error. The improvement method calculation means 25. Predetermined condition determination means 2
If the priority set by the setting means 21 is, for example, to select a means for narrowing the wiring width or the wiring area, the wiring having an error in 3 is changed from 300 μm to 200 μm in its pattern width. calculate.
Based on the calculation result, the improvement method output means 25 outputs the improvement method. In this way, the wirings having different characteristic impedances can be easily set to the characteristic impedance within the reference value. (Example 5) Next, under the same conditions as the specified value of the characteristic impedance of Example 4, the case where the priority of the improvement method is to improve by giving priority to the wiring region, Example 5 will be described. As described below.

When the characteristic impedance of the wiring having the signal name set by the setting means 21 is calculated by the characteristic impedance calculating means 22, the calculation result of the wiring of FIG. 16 is, for example, 48Ω, and the calculation result of the wiring of FIG. 17 is, for example, 40Ω. .
Here, the specified value of the characteristic impedance is set to 48Ω, and the line width is set to 3 to match this characteristic impedance.
A wiring pattern is formed as shown in FIG. 16 while maintaining a constant value of 00 μm. After that, when the wiring pattern of the third layer in FIG. 17 is formed, if the line width is set to 300 μm as set by the wiring width of the first layer in FIG. 16, the characteristic impedance is 40%.
It becomes Ω. In this case, the determination means 23 for the predetermined condition
17 determines that 40Ω of the characteristic impedance in FIG. 17 is an error, the error output means 24 outputs this wiring portion as an error. When the priority set by the setting means 21 is, for example, to select a means for narrowing the wiring area, the improvement method calculating means 25 determines the determining means 2 for the predetermined condition.
Guard ground wiring 53 on both sides of the wiring that caused an error in 3.
54 is eliminated and the pattern width is from 300 μm to 240 μm
Calculate to change to. Based on the calculation result, the improvement method output means 25 outputs the improvement method. In this way, the wirings having different characteristic impedances can be easily set to the characteristic impedance within the reference value. (Sixth Embodiment) Next, a case where the specified value of the characteristic impedance is set to 40Ω under the same conditions as in the fourth embodiment will be described as a sixth embodiment with reference to FIGS.

When the characteristic impedance of the wiring having the signal name set by the setting means 21 is calculated by the characteristic impedance calculating means 22, the calculation result of the wiring of FIG. 16 is, for example, 48Ω, and the calculation result of the wiring of FIG. 17 is, for example, 40Ω. .
Here, the specified value of the characteristic impedance is set to 40Ω, and the line width is set to 3 to match this characteristic impedance.
A wiring pattern is formed as shown in FIG. 17 while maintaining a constant value of 00 μm. After that, when the wiring pattern of the first layer of FIG. 16 is formed, if the line width of 300 μm as set by the wiring width of the third layer of FIG.
It becomes Ω. In this case, the determination means 23 for the predetermined condition
16 determines that the characteristic impedance of 48Ω is an error, the error output means 24 outputs this wiring portion as an error. When the priority set by the setting means 21 is for selecting a means for changing the wiring width, for example, the improvement method calculating means 25 determines the predetermined condition by the determining means 23.
The pattern width of the wiring that caused an error from 300 μm to 4
It is calculated so as to be changed to 10 μm. Based on the calculation result, the improvement method output means 25 outputs the improvement method. In this way, the wirings having different characteristic impedances can be easily set to the characteristic impedance within the reference value. (Embodiment 7) Next, with reference to FIG. 16 and FIG. 1, the case where the priority of the improvement method is improved by the distance from the wiring to the constant potential region under the same conditions of the specified value of the characteristic impedance and the like in Embodiment 6.
Example 7 will be described with reference to FIG.

When the characteristic impedance of the wiring having the signal name set by the setting means 21 is calculated by the characteristic impedance calculating means 22, the calculation result of the wiring of FIG. 16 is, for example, 48Ω, and the calculation result of the wiring of FIG. 17 is, for example, 40Ω. .
Here, the specified value of the characteristic impedance is set to 40Ω, and the line width is set to 3 to match this characteristic impedance.
A wiring pattern is formed as shown in FIG. 17 while maintaining a constant value of 00 μm. After that, when the wiring pattern of the first layer of FIG. 16 is formed, if the line width of 300 μm as set by the wiring width of the third layer of FIG.
It becomes Ω. In this case, the determination means 23 for the predetermined condition
16 determines that the characteristic impedance of 48Ω is an error, the error output means 24 outputs this wiring portion as an error. When the priority set by the setting means 21 is, for example, to select a means for narrowing the wiring area, the improvement method calculating means 25 determines the determining means 2 for the predetermined condition.
The calculation is performed so that the space between the two side guard grounds 53 and 54 of the wiring pattern 33 is set to 80 μm, while the pattern width of the wiring in which error occurs in 3 is 300 μm. Based on the calculation result, the improvement method output means 25 outputs the improvement method. In this way, the wirings having different characteristic impedances can be easily set to the characteristic impedance within the reference value. (Embodiment 8) Next, in the case where the specified value of the characteristic impedance of Embodiment 7 is the same, the priority of the improvement method is also improved by the distance from the wiring to the constant potential region, and the width of the wiring and the constant potential from the wiring are fixed. The case where the prescribed value of the distance to the area is set by the setting means 21 will be described with reference to FIGS.
As described below.

The characteristic impedance of the wiring having the signal name set by the setting means 21 is calculated by the characteristic impedance calculating means 22.
When calculated with, the calculation result of the wiring of FIG.
Therefore, the calculation result of the wiring in FIG. 17 is, for example, 40Ω. Here, the prescribed value of the characteristic impedance is set to 40Ω, and the wiring pattern is formed as shown in FIG. 17 while keeping the line width constant at 300 μm in order to match the characteristic impedance. After that, when the wiring pattern 31 of the first layer of FIG. 16 is formed, if the wiring width of the third layer of FIG. 17 is set to 300 μm as it is set, the characteristic impedance becomes 48Ω. In this case, the determination means 23 of the predetermined condition determines that the characteristic impedance of 48Ω in FIG. 16 is an error, and therefore the error output means 24 outputs this wiring portion as an error. If the priority set by the setting means 21 is, for example, to select a means for narrowing the wiring area, the improvement method calculating means 35 determines that the pattern width of the wiring having an error by the determining means 23 of the predetermined condition is 300.
On the both sides of the wiring pattern 33, while keeping μm, 5
Calculation is performed so that the space of 3, 54 is 80 μm.
However, in the case where the setting value of the wiring width or the distance from the wiring to the constant potential region is set by the setting means 21, for example, the space 10 between the two side guard grounds 53 and 54 of the wiring pattern is set.
When it is set to 0 μm or more and 500 μm or less, the space between the guard grounds 53 and 54 on both sides of the wiring pattern 33 is set to 1
The pattern width of the wiring 33 is calculated to be changed from 300 μm to 330 μm. Based on the calculation result, the improvement method output means 25 outputs the improvement method. In this way, the wirings having different characteristic impedances can be easily set to the characteristic impedance within the reference value. (Ninth Embodiment) Next, as a ninth embodiment, with reference to FIG. 16 and FIG. 18, a case where the guard ground wiring is provided on both sides of the signal wiring in the first layer and the wiring width changes in the same layer explain.

FIG. 16 is a diagram showing an image of the wiring of the first layer, and FIG. 18 is a diagram showing an image of the wiring in which the width of the wiring 31 of the first layer is narrow. When the characteristic impedance of the wiring having the signal name set by the setting means 21 is calculated by the characteristic impedance calculating means 22, the calculation result of the wiring in FIG. 16 is 48Ω, and the calculation result of the wiring in FIG. 18 is 6 for example.
It becomes 3Ω. That is, the specified value of the characteristic impedance is 4
When set to 8Ω, the wiring pattern is formed as shown in FIG. 16 while keeping the line width constant at 300 μm in order to match this characteristic impedance. After that, when forming a wiring pattern in which the wiring width of the first layer in FIG.
If the guard ground wirings 51 and 52 are formed with a space interval of 200 μm as set in 6, the characteristic impedance will be 63Ω. In this case, the predetermined condition determining unit 23 determines that the characteristic impedance of 63Ω in FIG. 18 is an error, and thus the error output unit 24 outputs this wiring portion as an error. If the priority order set by the setting means 21 is, for example, to select the means for improving the distance here from the wiring to the constant potential area, the improvement method calculating means 2
5 is the wiring which has an error in the judging means 23 of a predetermined condition,
Space 200 between the guard ground wires 51, 52
Calculation is performed to change from μm to 70 μm. Based on the calculation result, the improvement method output means 25 outputs the improvement method. In this way, the wirings having different characteristic impedances can be easily set to the characteristic impedance within the reference value. (Embodiment 10) Next, as Embodiment 10, a case in which guard ground wiring is provided on both sides of the signal wiring in the third layer and the wiring width changes in the same layer will be described with reference to FIGS. 17 and 19. explain.

FIG. 17 is a diagram showing an image of the wiring of the third layer, and FIG. 19 is a diagram showing an image of the wiring in which the width of the wiring 33 of the third layer is narrow. When the characteristic impedance of the wiring having the signal name set by the setting means 21 is calculated by the characteristic impedance calculating means 22, the calculation result of the wiring of FIG. 17 is, for example, 40Ω, and the calculation result of the wiring of FIG.
It becomes 3Ω. That is, the specified value of the characteristic impedance is 4
When set to 0Ω, the wiring pattern is formed as shown in FIG. 17 while keeping the line width constant at 300 μm in order to match this characteristic impedance. After that, when forming a wiring pattern in which the width of the wiring 33 of the third layer in FIG. 19 is narrowed, the guard ground wirings 53, 5 as set in FIG. 17 are formed.
When the space interval of 4 is 200 μm, the characteristic impedance becomes 53Ω. In this case, the determination means 23 for the predetermined condition has the characteristic impedance of 53Ω in FIG.
Is determined as an error, the error output means 24 outputs this wiring portion as an error. The improvement method calculation means 25
If the priority set by the setting means 21 for the wiring in which the error has occurred in the predetermined condition determination means 23 is, for example, here, the means for improving the distance from the wiring to the constant potential region is selected, the guard ground wiring 53 , 54 space interval is changed from 200 μm to 70 μm.
Based on the calculation result, the improvement method output means 25 outputs the improvement method. In this way, the wirings having different characteristic impedances can be easily set to the characteristic impedance within the reference value. (Embodiment 11) Next, as Embodiment 11, a case in which guard ground wiring is provided on both sides of a signal wiring in the same layer and the wiring width changes in the same layer will be described in comparison with a conventional technique.

20 and 21 are examples of the prior art.
The guard ground wirings 62 and 63 for the signal wiring 61 are V
Wiring cannot be performed because of wiring prohibited areas 64 and 65 such as IA and pads. Therefore, in the case of FIG. 20, the guard wiring 62,
63 breaks on the way and the characteristic impedance is in areas A1 and A
2 is different. Further, in the case of FIG. 21, the guard wiring 6
Characteristic impedances are different between the regions A1 and A2 because the lines 2 and 63 are largely detoured. On the other hand, in the present invention, the area A2 shown in FIGS.
3 determines that there is an error, and the improvement method calculation means 25 calculates the width of the signal wiring 71 and the space interval between the guard ground wirings 72 and 73 so that the characteristic impedance satisfies the predetermined condition. As a result, as shown in FIG. 22, the signal wiring 71 becomes the designs w1 and w2, and the characteristic impedance of the regions A1, A2, and A3 can be easily made constant.

In all of the above-mentioned embodiments, the characteristic impedance calculating means 25 is selected so as not to calculate when the discontinuity of the transmission line can be ignored by the wiring shorter than the specified value by comparing with the specified value of the wiring length. Yes, the vertical and / or horizontal dimensions of the wiring and / or the vertical and / or horizontal dimensions of the ground can be selected to not be calculated if the vertical and / or horizontal dimensions of the wiring are shorter than the specified value and can be ignored. If the distance in the vertical direction and / or the horizontal direction from the power supply in the horizontal direction and / or the ground is longer than the specified value and can be ignored, it may be selected not to be calculated. At this time, the part for which calculation is omitted depending on the specified value can be output and confirmed by the output means 24.

By carrying out the present invention as described in the above embodiments, it is possible to easily form the characteristic impedance of the wiring pattern while keeping it within a certain reference value. This makes it possible to suppress the generation of unnecessary high frequency noise caused by the distortion of the generated signal or the distortion.

[0076]

As described above, according to the present invention,
A printed wiring board design support device and method capable of calculating characteristic impedance of a target wiring, accurately specifying a wiring or a wiring portion to be improved, and accurately outputting whether or not there is an error in the wiring, and a print A program for causing a computer to perform a process for supporting the wiring design of a wiring board, and a recording medium storing the program can be provided.

Further, according to the present invention, it is possible to automatically output the improvement means for the wiring having the inappropriate characteristic impedance.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a hardware configuration of a printed wiring board design support device according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram of the printed wiring board design support device shown in FIG.

FIG. 3 is a flowchart showing the operation of the characteristic impedance calculation means shown in FIG.

FIG. 4 is a functional block diagram of a hardware configuration of a printed wiring board design support device according to a second embodiment of the present invention.

5 is a functional block diagram of the printed wiring board design support device shown in FIG.

FIG. 6 is a flowchart showing the operation of the improvement method calculation means shown in FIG.

FIG. 7 is a sectional view schematically showing an example of a printed wiring board having a six-layer structure.

FIG. 8 is a perspective view showing an example of a short wiring in which the width of the signal wiring is changing midway.

FIG. 9 is a cross-sectional view schematically showing an example of a third-layer wiring with guard ground wiring.

FIG. 10 is a cross-sectional view schematically showing an example of a third-layer wiring with guard ground wiring.

11 is a diagram illustrating simplification of the conductor region shown in FIG.

FIG. 12 is a graph showing the characteristic impedance of the wiring obtained by the analytical formula and the measured value.

FIG. 13 is a diagram illustrating an interpolation unit.

FIG. 14 is a perspective view schematically showing the wiring of the first layer of the 6-layer board.

FIG. 15 is a perspective view schematically showing wiring of a third layer of a 6-layer board.

FIG. 16 is a perspective view schematically showing a wiring with a guard ground wiring of a first layer of a 6-layer board.

FIG. 17 is a perspective view schematically showing a wiring with guard ground wiring of a third layer of a 6-layer board.

FIG. 18 is a perspective view schematically showing a relatively thin wiring with a guard ground wiring of the first layer of a 6-layer board.

FIG. 19 is a perspective view schematically showing a relatively thin wiring with a third layer guard ground wiring of a 6-layer board.

FIG. 20 is a diagram showing a wiring example of a conventional technique.

FIG. 21 is a diagram showing another wiring example of the related art.

FIG. 22 is a diagram showing a wiring example of the present invention which solves the problems of FIGS.

[Explanation of symbols]

11 Input section 12, 12A
Calculation unit 13 Output unit 21 Setting means 22 Characteristic impedance calculation means 23 Predetermined condition determination means 24 Error output means 25 Improvement method calculation means 26 Improvement method output means 31, 33,
34, 36 Signal wiring 32, 35 Power supply / ground wiring 41-47
Insulating layers 51, 52 First layer guard ground wiring 53, 54 Third layer guard ground wiring 61 Signal wiring 62, 63
Guard earth wiring 64, 65 Wiring prohibited area 71 Signal wiring 72, 73 Guard earth wiring 121 Characteristic impedance calculation unit 122 Predetermined condition determination unit 123 Improvement method calculation unit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tatsushi Shimizu             Fuji Zero, 2274 Hongo, Ebina City, Kanagawa Prefecture             Co., Ltd. Ebina Office (72) Inventor Osamu Ueno             Fuji Zero, 2274 Hongo, Ebina City, Kanagawa Prefecture             Co., Ltd. Ebina Office F-term (reference) 5B046 AA08 BA04 JA01

Claims (23)

[Claims] 1. A design support device for supporting wiring design of a printed wiring board, setting means for setting wiring selection conditions and predetermined conditions for quality judgment, and calculation means for calculating characteristic impedance of target wiring. A design including: a determination unit that determines whether the characteristic impedance calculated by the calculation unit satisfies the predetermined condition, and an error output unit that outputs an error to the target wiring that violates the predetermined condition. Support device. 2. A design support device for supporting wiring design of a printed wiring board, setting means for setting wiring selection conditions and predetermined conditions for quality judgment, and calculation means for calculating characteristic impedance of the target wiring. A determining unit that determines whether the characteristic impedance calculated by the calculating unit satisfies the predetermined condition, an error output unit that outputs an error to the target wiring that violates the predetermined condition, and an error output of the target wiring that outputs the error. A design support apparatus comprising: an improvement method calculation unit that calculates and outputs an improvement method for eliminating an error. 3. The design support apparatus according to claim 1, wherein the error output unit outputs the characteristic impedance of the target wiring calculated by the calculation unit. 4. The calculation method includes a constant potential region around the target wiring, in which a potential is maintained for at least a certain time, and a condition regarding an insulator around the target wiring. The design support device according to item 1 or 2. 5. The design support device according to claim 4, wherein the constant potential region includes a ground region and a power source region. 6. The design support apparatus according to claim 4, wherein the constant potential region includes a signal line region that varies at a frequency lower than a predetermined frequency. 7. The method according to claim 1, wherein the calculation method includes a conductive region located in a layer different from the target wiring and a conductive region located in the same layer as the target wiring. Design support device. 8. The calculating means omits the calculation of the characteristic impedance of a portion in which the characteristic impedance of the target wiring changes within a predetermined range.
Alternatively, the design support device according to item 2. 9. The calculating means simplifies the target wiring by regarding a portion where the characteristic impedance of the target wiring changes within a predetermined range as having the same characteristic impedance as other portions. The design support device according to claim 1. 10. The design support apparatus according to claim 9, wherein the error output unit outputs data of the simplified wiring portion. 11. The characteristic calculating device calculates the characteristic impedance of the target wiring by interpolating a numerical value of the characteristic impedance acquired in advance for a plurality of specific structures. Design support equipment. 12. There are a plurality of methods for calculating the characteristic impedance, and the calculating means has a plurality of calculating means corresponding to the plurality of calculating methods, and the predetermined priority order is given from the plurality of calculating means. 3. The design support apparatus according to claim 1, wherein either one is selected in accordance with the above. 13. The improvement method calculation means outputs at least one of a change in a width of the target wiring and a change in a distance from the target wiring to another constant potential region. Design support equipment. 14. The improvement method calculating means outputs the change of the width of the target wiring and the change of the distance from the target wiring to another constant potential region in accordance with a predetermined priority order. 2. The design support device described in 2. 15. The improvement method calculating means changes the width of the target wiring within a predetermined value range, and changes the distance from the target wiring to another potential region within a predetermined value range. The design support device according to claim 2. 16. The design support apparatus according to claim 2, wherein the setting unit sets the improvement method for eliminating an error in the target wiring that has output an error. 17. The design support apparatus according to claim 2, wherein the setting unit sets a plurality of the improvement methods for eliminating an error of the target wiring that has output an error, with priorities. . 18. The design support apparatus according to claim 2, wherein the improvement method calculation means has a plurality of improvement means, and the setting means sets an improvement method to be selected by the improvement method calculation means. 19. A design support method for supporting a wiring design of a printed wiring board, the step of setting a wiring selection condition and a predetermined condition for quality judgment, the step of calculating a characteristic impedance of a target wiring, And a step of determining whether or not the characteristic impedance satisfies the predetermined condition, and outputting an error in the target wiring that violates the predetermined condition. 20. A design support method for supporting the wiring design of a printed wiring board, the step of setting a wiring selection condition and a predetermined condition for quality judgment, the step of calculating the characteristic impedance of the target wiring, A step of determining whether the characteristic impedance satisfies the predetermined condition, an error output of the target wiring that violates the predetermined condition, and an improvement method for eliminating the error of the target wiring that has output an error. A design support method comprising: calculating and outputting. 21. A program for causing a computer to perform a process for supporting wiring design of a printed wiring board, a step of setting a wiring selection condition and a predetermined condition for pass / fail judgment, and calculating a characteristic impedance of a target wiring. And a step of determining whether the calculated characteristic impedance satisfies the predetermined condition, and a step of outputting an error in the target wiring that violates the predetermined condition. 22. In a program for causing a computer to perform a process for supporting wiring design of a printed wiring board, a step of setting a wiring selection condition and a predetermined condition for pass / fail judgment, and calculating a characteristic impedance of a target wiring. And a step of determining whether or not the calculated characteristic impedance satisfies the predetermined condition, a step of outputting the target wiring that violates the predetermined condition as an error, and an error of the target wiring that has output an error is resolved. And a step of calculating and outputting an improvement method for performing the program. 23. A computer-readable recording medium storing the program according to claim 21 or 22.