JP2003178578A - Ferroelectric nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric nonvolatile semiconductor memory in which data is not destroyed even when a polarization attenuation phenomenon is caused in ferroelectric layers. <P>SOLUTION: A ferroelectric nonvolatile semiconductor memory comprises a bit line BL, a transistor TR for selection, a memory unit MU constituted of M pieces of memory cells MCM (M≥2), and M lines of plate lines PL. Each memory cell comprises a first electrode 21, a ferroelectric layer 22 and a second electrode 23. In the memory unit MU, the first electrode 21 of the memory cell MCM is common, the common first electrode 21 is connected to the bit line BL through the transistor TR for selection, the second electrode 23 of the (m)th memory cell is connected to the (m)th plate line PL<SB>m</SB>, a circuit TRS is provided further to ground the common first electrode 21 or to short-circuit the M lines of plate lines PLM and the common first electrode 21. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric non-volatile semiconductor memory (so-called FERAM).

[0002]

2. Description of the Related Art In recent years, much research has been conducted on large-capacity ferroelectric non-volatile semiconductor memories. A ferroelectric non-volatile semiconductor memory (hereinafter, may be abbreviated as a non-volatile memory) can be accessed at high speed and
It is non-volatile, small in size, low in power consumption, and resistant to shocks. It is expected to be used as a storage device or a recording medium for recording audio and video.

This non-volatile memory utilizes a high-speed polarization reversal of a ferroelectric thin film and its residual polarization to detect a change in the amount of accumulated charge in a capacitor section having a ferroelectric layer.
It is a high-speed rewritable non-volatile memory, and basically includes a memory cell (capacitor portion) and a selection transistor. Memory cell (capacitor section)
Is composed of, for example, a lower electrode, an upper electrode, and a ferroelectric layer sandwiched between these electrodes. Writing and reading of data in this nonvolatile memory are performed by applying the PE (V) hysteresis loop of the ferroelectric substance shown in FIG. That is, when the external electric field is removed after the external electric field is applied to the ferroelectric layer, the ferroelectric layer exhibits remanent polarization. The remanent polarization of the ferroelectric layer becomes + P _r when an external electric field in the positive direction is applied, and −P _r when an external electric field in the negative direction is applied. Here, the case where the remanent polarization is + P _r (see “D” in FIG. 60) is “0”, and the remanent polarization is −P _r (“A” in FIG. 60).
In the case of reference), it is set to "1".

In order to determine the state of "1" or "0", an external electric field in the positive direction, for example, is applied to the ferroelectric layer. As a result, the polarization of the ferroelectric layer becomes the state of "C" in FIG. At this time, if the data is "0", the polarization state of the ferroelectric layer changes from "D" to "C". On the other hand, if the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” via “B”. When the data is "0", polarization inversion of the ferroelectric layer does not occur. On the other hand, when the data is "1", polarization inversion occurs in the ferroelectric layer. As a result, a difference occurs in the amount of charge stored in the memory cell (capacitor section). By turning on the selection transistor of the selected nonvolatile memory, this accumulated charge is detected as a signal current.
When the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric layer becomes the state of “D” in FIG. 60 regardless of whether the data is “0” or “1”. That is, at the time of reading, the data “1” is once destroyed.
Therefore, when the data is "1", an external electric field in the negative direction is applied to bring the state of "A" through the paths "D" and "E", and the data "1" is written again.

The structure and operation of a non-volatile memory, which is currently the mainstream, is described in US Pat. No. 4,873,664. It was proposed by Sheffiled et al.
This non-volatile memory has a circuit diagram shown in FIG.
It is composed of two non-volatile memory cells. Incidentally, in FIG. 61, one nonvolatile memory is surrounded by a dotted line.
Each nonvolatile memory has, for example, a selection transistor TR.
₁₁ , TR ₁₂ , memory cell (capacitor part) FC ₁₁ , FC
_It consists of ₁₂ .

A two-digit or three-digit subscript, for example, a subscript "11" is originally a subscript that should be displayed as a subscript "1,1". For example, "111" is originally a subscript "1,1,". 1 "
Is a subscript to be displayed, but for simplification of the display, it is displayed with a two-digit or three-digit subscript. Also, add the subscript "M" to
For example, it is used to collectively display a plurality of memory cells or plate lines, and the subscript “m” is used, for example, to display a plurality of memory cells or plate lines individually, and the subscript “N” is used, for example. It is used to collectively display the selection transistors and memory units, and the subscript “n” is used to individually display the selection transistors and memory units, for example.

Then, one bit is stored by writing complementary data in each memory cell. In FIG. 61, reference numeral “WL” indicates a word line, reference numeral “BL” indicates a bit line, and reference numeral “PL” indicates a plate line. Focusing on one nonvolatile memory, the word line WL ₁ is connected to the word line decoder / driver WD. The bit lines BL ₁ and BL ₂ are connected to the sense amplifier SA. Furthermore, the plate line PL ₁
Are connected to the plate line decoder / driver PD.

In the nonvolatile memory having such a structure, when reading the stored data, the word line W
When L ₁ is selected and the plate line PL ₁ is driven,
Complementary data is transmitted from the paired memory cells (capacitor sections) FC ₁₁ and FC ₁₂ to the selection transistors TR ₁₁ and T.
It appears as a voltage (bit line potential) on the paired bit lines BL ₁ and BL ₂ via R ₁₂ . The voltage (bit line potential) of the paired bit lines BL ₁ and BL ₂ is detected by the sense amplifier SA.

One nonvolatile memory is a word line W.
It occupies a region surrounded by L ₁ and the paired bit lines BL ₁ and BL ₂ . Therefore, if the word lines and the bit lines are arranged at the shortest pitch, the minimum area of one nonvolatile memory is 8F ^2, where F is the minimum processing size. Therefore, the minimum area of the nonvolatile memory having such a structure is 8F ² .

When it is attempted to increase the capacity of the nonvolatile memory having such a structure, its realization can only depend on the miniaturization of the processing size. Further, two selection transistors and two memory cells (capacitor section) are required to form one nonvolatile memory. Furthermore, it is necessary to arrange the plate lines at the same pitch as the word lines. Therefore, it is almost impossible to arrange the non-volatile memory at the minimum pitch, and in reality, the area occupied by one non-volatile memory is significantly larger than 8F ² .

Moreover, it is necessary to dispose the word line decoder / driver WD and the plate line decoder / driver PD at the same pitch as that of the nonvolatile memory. In other words, two decoders / drivers are needed to select one row address. Therefore, the layout of the peripheral circuit becomes difficult, and the area occupied by the peripheral circuit becomes large.

One of means for reducing the area of a non-volatile memory
One is known from JP-A-9-121032.
As shown in the equivalent circuit of FIG. 62, the nonvolatile memory disclosed in this patent publication has a plurality of memory cells MC _1M (each lower electrode connected in parallel to one end of one selection transistor TR ₁ ( For example, a non-volatile memory cell composed of M = 4) and a plurality of memory cells MC _2M each having a lower electrode connected in parallel to one end of one selection transistor TR _2. It consists of and. In addition, a plurality of memory cells MC _1M , MC _2M
The lower electrode of is common. Here, the common lower electrodes are referred to as common nodes CN ₁ and CN ₂ . The other ends of the selection transistors TR ₁ and TR ₂ are respectively connected to the bit lines BL ₁ and
It is connected to BL ₂ . Paired bit lines BL ₁ and B
L ₂ is connected to the sense amplifier SA. The upper electrodes of the memory cells MC _1m and MC _2m (m = 1, 2 ... M) are connected to a common plate line PL _m , and the plate line PL _m is connected to a plate line decoder / driver PD. ing. Furthermore, the word line WL is connected to the word line decoder / driver WD.

Then, the paired memory cells MC _1m , M
Data complementary to C _2m (m = 1, 2 ... M) is stored. For example, memory cells MC _1m and MC _2m (where m
Is any one of 1, 2, 3, and 4), the word line WL is selected to read the data stored in the plate line PL _j
The plate line PL _m is driven with a voltage of (1/2) V _cc applied to (m ≠ j). Here, V _cc is, for example, a power supply voltage. As a result, complementary data is transmitted from the paired memory cells MC _1m and MC _2m through the selection transistors TR ₁ and TR ₂ to the paired bit line B.
It appears as a voltage (bit line potential) on L ₁ and BL ₂ . Then, the sense amplifier SA detects the voltage (bit line potential) of the paired bit lines BL ₁ and BL ₂ .

The pair of selection transistors TR ₁ and TR ₂ in the paired non-volatile memory cells are formed by the word line W.
It occupies a region surrounded by L and the paired bit lines BL ₁ and BL ₂ . Therefore, if the word line and the bit line are arranged at the shortest pitch, the minimum area of the pair of selection transistors TR ₁ and TR ₂ in the paired nonvolatile memory cells is 8F ² . However, the pair of selection transistors TR ₁ and TR ₂ are
A pair of memory cells MC _1m and MC _2m (m = 1, 2
... M), the number of selection transistors TR ₁ and TR ₂ per bit is small, and
Since the arrangement of the word lines WL is gradual, it is easy to reduce the size of the nonvolatile memory. Moreover, also in the peripheral circuit, M bits can be selected by one word line decoder / driver WD and M plate line decoders / drivers PD. Therefore, by adopting such a configuration, it is possible to realize a layout in which the cell area is close to 8F ^2.
A chip size similar to that of AM can be realized.

[0015]

By the way, it is known that a polarization attenuation phenomenon called relaxation occurs in a ferroelectric thin film. This phenomenon is a phenomenon in which the ferroelectric thin film undergoes a certain attenuation in the polarization amount for about 1 second after the polarization inversion, and then stabilizes. It is said that such a polarization decay phenomenon occurs because the charges trapped inside the ferroelectric thin film are redistributed according to the polarization state. Access to the non-volatile memory is normally performed in units of tens of nanoseconds. Therefore, even after the data is written in the memory cell and the selection transistor is turned off, the polarization attenuation phenomenon progresses.

A schematic view of the charge distribution due to the polarization decay phenomenon is shown in FIGS. 63 (A) and 63 (B). Note that, in FIGS. 63A and 63B, one memory cell and a selection transistor are illustrated for simplification. FIG. 63A shows a case where the plate electrode is grounded, a positive potential pulse is applied to the lower electrode through the selection transistor, data “1” is written, and then the lower electrode is grounded again. The charge distribution is shown. When the writing is completed, the lower electrode and the upper electrode are both grounded and at the same potential, and the charge equal to the polarization amount is distributed on the surface of each electrode to cancel the electric field associated with the polarization.

When the selection transistor TR is turned off, the lower electrode is in a floating state. At this time, the polarization of the ferroelectric layer is attenuated as shown in FIG. 63B, but the total charge amount of the lower electrode in the floating state is preserved.
The potential changes.

The initial amount of polarization is P ₀ , the amount of polarization after attenuation is P ₁ , the total charge of the lower electrode is Q, and the capacity of the memory cell is C _s.
Then, the potential variation ΔV of the lower electrode after the polarization attenuation phenomenon occurs is given by the following equation (1). Equation (1) can be modified to obtain ΔV in equation (2).

Q = P ₀ = P ₁ + ΔVC _s (1) ΔV = (P ₀ -P ₁ ) / C _s (2)

When the data "1" is written, ΔV becomes a positive value, and the potential of the lower electrode rises while holding the data. On the other hand, when the data “0” is written, ΔV becomes a negative value, and the potential of the lower electrode drops while holding the data. A variation of the lower electrode when data "1" is written is shown in the schematic view of FIG. 63 (C). Due to the polarization attenuation phenomenon, first, the potential of the lower electrode rises. After about 1 second,
When the depolarization due to relaxation saturates, the potential of the lower electrode begins to drop slowly due to leakage of the ferroelectric layer and junction. And, when it reaches the ground level, it stabilizes.

Such a change in the potential of the lower electrode does not tend to deteriorate the written data in the non-volatile memory composed of one memory cell (capacitor section) and one selecting transistor. Therefore, it does not matter. However, the non-volatile memory disclosed in Japanese Patent Laid-Open No. 9-121032 poses a serious problem.

That is, for example, one common node is shared by 16 memory cells, data "1" is written in 15 of those memory cells, and data "0" is written in the remaining one memory cell. Is written, the common node is greatly affected by the 15 memory cells in which the data “1” is written, and as a result, the potential of the common node rises. As a result, an electric field is applied to the memory cell in which the data “0” is written in the direction in which the data retention deteriorates. Moreover, this electric field is held until it is attenuated by leakage of the ferroelectric layer and the junction. Therefore, the electric field in the direction in which the data retention deteriorates is added to the memory cell in which the data “0” is written for a long time of several seconds level, and in the worst case, in the memory cell in which the data “0” is written. Data corruption occurs.

Therefore, an object of the present invention is to prevent a data stored in a memory cell from being destroyed even if a polarization attenuation phenomenon called relaxation occurs in the ferroelectric layer. To provide memory.

[0024]

A ferroelectric non-volatile semiconductor memory according to a first aspect of the present invention for achieving the above object comprises: (A) a bit line; (B) a selection transistor; (C) A memory unit composed of M (where M ≧ 2) memory cells, and (D) M plate lines, each memory cell including a first electrode and a ferroelectric layer. And a second electrode, in the memory unit,
The first electrode of the memory cell is common, and the common first electrode is connected to the bit line through the selection transistor, and is the m-th (where m =
The second electrodes of the memory cells 1, 2, ...
A ferroelectric non-volatile semiconductor memory connected to the th plate line, for grounding a common first electrode, or for short-circuiting M plate lines and a common first electrode Is further provided.

Second aspect of the present invention for achieving the above object
A ferroelectric non-volatile semiconductor memory according to the aspect of
(A) bit line, (B) selection transistor,
(C) Each includes N (however, N ≧ 2) memory units each composed of M (however, M ≧ 2) memory cells, and (D) M × N plate lines, The N memory units are stacked with an insulating layer in between, and each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. In each memory unit, the first memory cell
Electrode is common, and the common first electrode is connected to the bit line through the selection transistor, and in the n-th layer (where n = 1, 2, ..., N) memory unit. , The second electrode of the m-th (where m = 1, 2, ..., M) memory cell is connected to the [(n−1) M + m] -th plate line, and is a ferroelectric nonvolatile memory. Semiconductor memory, further comprising a circuit for grounding the common first electrode or for short-circuiting the M × N plate lines and the common first electrode. To do.

A third aspect of the present invention for achieving the above object.
A ferroelectric non-volatile semiconductor memory according to the aspect of
(A) bit lines, (B) N (where N ≧ 2) selection transistors, and (C) each for M (where M ≧)
2) N memory units composed of memory cells and (D) M plate lines, each memory cell comprising a first electrode, a ferroelectric layer and a second electrode. In each memory unit, the first electrode of the memory cell is common, and the n-th (where n = 1, 2, ...,
The common first electrode in the memory unit N) is connected to the bit line via the nth selection transistor, and the mth memory unit (where m = 1, 2, ...) In the nth memory unit. .., M) is a ferroelectric non-volatile semiconductor memory in which the second electrode of the memory cell is connected to the m-th plate line common between the memory units, and the common first It is characterized by further comprising a circuit for grounding the electrode or for short-circuiting the M plate lines and the common first electrode.

Fourth aspect of the present invention for achieving the above object
A ferroelectric non-volatile semiconductor memory according to the aspect of
(A) N (where N ≧ 2) bit lines, (B) N selection transistors, and (C) each consisting of M (where M ≧ 2) memory cells, Each of the memory cells includes N memory units and (D) M plate lines. Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. The first electrode is common, and is the n-th (where n = 1, 2 ,.
.., N), the common first electrode is connected to the nth bit line via the nth selection transistor, and in the nth memory unit, the mth (however, , M = 1, 2, ..., M) is a ferroelectric non-volatile semiconductor memory in which the second electrode of the memory cell is connected to the m-th plate line common to the memory units. In addition, a circuit for grounding the common first electrode or for short-circuiting the M plate lines and the common first electrode is further provided.

The ferroelectric non-volatile semiconductor memory according to the first to fourth aspects of the present invention (hereinafter, these may be collectively referred to simply as the ferroelectric non-volatile semiconductor memory of the present invention. In the above), the circuit can be composed of a switching transistor. It should be noted that, for the sake of convenience, such a configuration has a ferroelectric non-volatile semiconductor memory according to the first aspect of the present invention, a ferroelectric non-volatile semiconductor memory according to the second aspect of the present invention, and a third aspect of the present invention.
The ferroelectric non-volatile semiconductor memory according to the above aspect and the ferroelectric non-volatile semiconductor memory according to the fourth aspect of the present invention. Here, when the circuit is composed of a switching transistor, the common first electrode is grounded or the plate line and the common first electrode are short-circuited by the operation of the switching transistor.

Alternatively, in the ferroelectric non-volatile semiconductor memory of the present invention, the circuit can be composed of a high resistance element. Incidentally, for convenience, such a configuration
A ferroelectric non-volatile semiconductor memory according to the 1B-th aspect of the present invention, a ferroelectric non-volatile semiconductor memory according to the 2B-th aspect of the present invention, and a ferroelectric non-volatile semiconductor memory according to the 3B-th aspect of the present invention. , Referred to as a ferroelectric non-volatile semiconductor memory according to the fourth aspect of the present invention. Here, when the circuit is composed of a high resistance element, the common first electrode is grounded, or alternatively, the plate line and the common first electrode are short-circuited via the high resistance element.

Generally, the operation time of the ferroelectric non-volatile semiconductor memory is on the order of several tens of nanoseconds. Therefore,
1B aspect of the present invention, 2B aspect, 3B aspect,
In the ferroelectric non-volatile semiconductor memory according to the fourth aspect, in order that the signal transmitted through the common first electrode (may be referred to as a common node) does not deteriorate when the ferroelectric non-volatile semiconductor memory operates. The time constant for extracting charges through the high resistance element (referred to as a first time constant) is required to be sufficiently longer than the operating time of the ferroelectric non-volatile semiconductor memory. On the other hand, when the ferroelectric non-volatile semiconductor memory is inoperative (standby), the time constant of charge extraction (called the second time constant) is small in order to quickly stabilize the potential of the common node. Is required. Considering these requirements, it is desirable that the first time constant be 100 nanoseconds or more and the second time constant be 100 milliseconds or less. The parasitic capacitance of the common node is on the order of tens of fF to hundreds of fF. Therefore, the resistance value of the high resistance element is 1 × 1.
It is preferably from 0 ⁶ Ω (1 MΩ) to 1 × 10 ¹² Ω (1 TΩ). The high resistance element can be made of, for example, non-doped polysilicon.

In the ferroelectric non-volatile semiconductor memory according to the first aspect of the present invention, a plurality of memory units of the ferroelectric non-volatile semiconductor memory may be laminated with an insulating layer interposed therebetween. In the ferroelectric non-volatile semiconductor memory according to the third or fourth aspect of the present invention, the N memory units may be formed on the same insulating layer, or via the insulating layer. It may be laminated.

In the ferroelectric non-volatile semiconductor memory of the present invention, it is sufficient that M ≧ 2 is satisfied, and as a practical value of M, for example, a power of 2 (2, 4, 8 ...) Is used. Can be mentioned. In the ferroelectric non-volatile semiconductor memory according to the second to fourth aspects of the present invention, it is sufficient that N ≧ 2 is satisfied, and as a practical value of N,
For example, a power of 2 (2, 4, 8 ...) Can be mentioned.

In the ferroelectric non-volatile semiconductor memory according to the second aspect of the present invention, or alternatively, the memory units are stacked with an insulating layer interposed therebetween. In the ferroelectric non-volatile semiconductor memory according to the aspect, since the memory unit has the three-dimensional laminated structure, the number of transistors occupying the surface of the semiconductor substrate is not restricted, and the conventional ferroelectric non-volatile semiconductor is eliminated. The storage capacity can be dramatically increased as compared with the memory, and the effective occupied area of the bit storage unit can be significantly reduced.

In the ferroelectric non-volatile semiconductor memory according to the second to fourth aspects of the present invention, further, the address selection in the row direction is performed by a two-dimensional matrix composed of selection transistors and plate lines. Will be done at. For example, if a row address selection unit is made up of eight selection transistors and eight plate lines, then 16 decoder / driver circuits will provide, for example, 64 bits or 32 bits.
Bit memory cells can be selected. Therefore,
Even if the degree of integration of the ferroelectric non-volatile semiconductor memory is equal to that of the conventional one, the storage capacity can be quadrupled or doubled. In addition, the number of peripheral circuits and drive wiring in address selection can be reduced.

In the ferroelectric non-volatile semiconductor memory of the present invention, practically, the ferroelectric non-volatile semiconductor memory is paired (for convenience, the non-volatile memory-A,
The bit lines constituting the pair of ferroelectric non-volatile semiconductor memories may be connected to the same sense amplifier. In this case, the selection transistor forming the nonvolatile memory-A and the selection transistor forming the nonvolatile memory-B may be connected to the same word line or different word lines. It may have been done. Depending on the configurations and driving methods of the non-volatile memory-A and the non-volatile memory-B, it is possible to store 1 bit in each memory cell that constitutes the non-volatile memory-A and the non-volatile memory-B. One of the memory cells constituting the non-volatile memory-A and one of the memory cells constituting the non-volatile memory-B connected to the same plate line as this memory cell.
It is also possible to store two pairs of memory cells and store complementary data in these paired memory cells.

In the ferroelectric non-volatile semiconductor memory of the present invention, a plurality of ferroelectric non-volatile semiconductor memories (memory blocks) sharing the word line and plate line of the selection transistor are collectively packaged. Data is written, or data is read and rewritten. That is, all the ferroelectric non-volatile semiconductor memories in the memory block are collectively and sequentially activated, or are collectively inactivated (standby).

In the ferroelectric non-volatile semiconductor memory according to the third aspect or the fourth aspect of the present invention, which has the second aspect of the present invention or the mode in which the memory units are laminated with an insulating layer interposed therebetween. Is preferably such that the crystallization temperature of the ferroelectric layer forming the memory cell of the memory unit located above is lower than the crystallization temperature of the ferroelectric layer forming the memory cell of the memory unit located below. . Here, the crystallization temperature of the ferroelectric layer forming the memory cell can be examined by using, for example, an X-ray diffractometer or a surface scanning electron microscope. Specifically, for example, after the ferroelectric material layer is formed, the heat treatment temperature for performing crystallization of the ferroelectric material layer is variously changed to perform heat treatment for promoting crystallization, and The crystallization temperature of the ferroelectric layer can be obtained by performing X-ray diffraction analysis of the body material layer and evaluating the diffraction pattern intensity (diffraction peak height) peculiar to the ferroelectric material.

By the way, in the case of manufacturing a ferroelectric type nonvolatile semiconductor memory having a structure in which memory units are laminated, in order to crystallize the ferroelectric layer or the ferroelectric thin film constituting the ferroelectric layer. , Heat treatment (referred to as crystallization heat treatment) must be performed by the number of stacked memory units. Therefore, the lower memory unit is subjected to the crystallization heat treatment for a longer time, and the upper memory unit is subjected to the crystallization heat treatment for a shorter time. Therefore, when the optimum crystallization heat treatment is performed on the memory unit located on the upper stage, the memory unit located on the lower stage may be subjected to an excessive heat load, and the characteristics of the memory unit located on the lower stage may deteriorate. There is. Although it is possible to perform a crystallization heat treatment at once after manufacturing a multi-stage memory unit, a large volume change occurs in the ferroelectric layer during crystallization, and degassing from each ferroelectric layer occurs. It is likely to occur, and problems such as cracks and peeling of the ferroelectric layer are likely to occur. If the crystallization temperature of the ferroelectric layer forming the memory unit located above is set lower than the crystallization temperature of the ferroelectric layer forming the memory unit located below, only the number of stacked memory units will be increased. Even if the crystallization heat treatment is performed, there is no problem such as characteristic deterioration of the memory cells forming the memory unit located below. Further, the crystallization heat treatment under the optimum conditions can be performed on the memory cells forming the memory unit in each stage, and the ferroelectric non-volatile semiconductor memory having excellent characteristics can be obtained. Table 1 below shows crystallization temperatures of typical materials constituting the ferroelectric layer.
The material forming the ferroelectric layer is not limited to such a material.

[Table 1] Material name Crystallization temperature Bi ₂ SrTa ₂ O ₉ 700 to 800 ° C Bi ₂ Sr (Ta _1.5 , Nb _0.5 ) O ₉ 650 to 750 ° C Bi ₄ Ti ₃ O ₁₂ 600 to 700 ° _{C Pb (Zr 0.48, Ti 0.52} ) O 3 550~650 ° C PbTiO ₃ 500 to 600 ° C

As a material forming the ferroelectric layer in the ferroelectric non-volatile semiconductor memory of the present invention, a bismuth layered compound, more specifically, a Bi-based layered structure perovskite type ferroelectric material can be mentioned. . The Bi-based layered structure perovskite type ferroelectric material belongs to a so-called non-stoichiometric compound, and is tolerant of composition shifts at both sites of a metal element and an anion (O etc.) element. In addition, it is not uncommon to show optimum electrical characteristics when the composition deviates slightly from the stoichiometric composition. The Bi-based layered structure perovskite type ferroelectric material is, for example, a compound represented by the general formula (Bi ₂ O ₂ ) ²⁺
It can be represented by (A _m−1 B _m O _{3m +1} ) ²⁻ . here,
“A” means Bi, Pb, Ba, Sr, Ca, Na, K,
Represents one kind of metal selected from the group consisting of metals such as Cd, and “B” represents Ti, Nb, Ta, W, Mo,
It represents one kind selected from the group consisting of Fe, Co and Cr, or a combination of a plurality of kinds at an arbitrary ratio. Further, m is an integer of 1 or more.

Alternatively, the material constituting the ferroelectric layer is (Bi _X , Sr _1-X ) ₂ (Sr _Y , Bi _1-Y ) (Ta _Z , Nb _1-Z ) ₂ O _d formula (1 (However, 0.9 ≦ X ≦ 1.0, 0.7 ≦ Y ≦ 1.0, 0
≦ Z ≦ 1.0, 8.7 ≦ d ≦ 9.3) is preferably contained as the main crystal phase. Alternatively, the material forming the ferroelectric layer is Bi _X Sr _Y Ta ₂ O _d formula (2) (where X + Y = 3, 0.7 ≦ Y ≦ 1.3, 8.7 ≦ d
It is preferable that the crystal phase represented by ≦ 9.3) is contained as a main crystal phase. In these cases, the crystal phase represented by the formula (1) or (2) is used as the main crystal phase.
% Or more is more preferable. The formula (1)
In the meaning, (Bi _X , Sr _1-X ) means that Sr occupies the site originally occupied by Bi in the crystal structure, and the ratio of Bi and Sr at this time is X: (1-X). . Further, the meaning of (Sr _Y , Bi _{1 -Y} ) means that Bi occupies the site originally occupied by Sr in the crystal structure, and the ratio of Sr and Bi at this time is Y: (1-Y). . Examples of the material forming the ferroelectric layer containing the crystal phase represented by the formula (1) or (2) as a main crystal phase include Bi oxide, Ta or Nb oxide, and Bi, Ta or Nb oxide. In some cases, a small amount of complex oxide may be contained.

Alternatively, the material forming the ferroelectric layer is as follows: Bi _X (Sr, Ca, Ba) _Y (Ta _Z , Nb _{1 -Z} ) ₂ O _d Formula (3) ≤2.5, 0.6≤Y≤1.2,0
≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0) may be included. In addition, "(Sr, Ca, Ba)"
Means one kind of element selected from the group consisting of Sr, Ca and Ba. When the composition of the material forming the ferroelectric layer represented by each of these formulas is represented by a stoichiometric composition, for example, Bi ₂ SrTa ₂ O ₉ , Bi ₂ SrNb ₂ O ₉ ,
_{Bi 2 BaTa 2 O 9, Bi} 2 Sr (Ta, Nb) can be exemplified ₂ O _9, or the like. Alternatively, as a material for forming the ferroelectric layer, Bi ₄ SrTi ₄ O ₁₅ , Bi ₃ TiNb is used.
O ₉ , Bi ₃ TiTaO ₉ , Bi ₄ Ti ₃ O ₁₂ , Bi ₂ PbT
can be exemplified a ₂ O _9, etc., even in these cases, the ratio of the respective metal elements may change to the extent that the crystal structure does not change. That is, there may be a compositional shift at both the metal element and oxygen element sites.

Alternatively, as a material forming the ferroelectric layer, PbTiO ₃ or P having a perovskite structure is used.
Lead zirconate titanate [PZT, Pb (Zr _{1 -y} , Ti _y ) O ₃ (provided that bZrO ₃ and PbTiO ₃ are solid solutions.
0 <y <1)], PLZT which is a metal oxide obtained by adding La to PZT, or PZT compound such as PNZT which is a metal oxide obtained by adding Nb to PZT.

In the materials constituting the ferroelectric layer described above, the crystallization temperature can be changed by removing these compositions from the stoichiometric composition.

In order to obtain the ferroelectric layer, the ferroelectric thin film may be patterned in a step after the ferroelectric thin film is formed. In some cases, patterning of the ferroelectric thin film is unnecessary. The ferroelectric thin film is formed by, for example, MOCVD method, MOD (Metal Organic Decomposition) method using a bismuth organic metal compound (bismuth alkoxide compound) having a bismuth-oxygen bond as a raw material,
LSMCD (Liquid Source Mist Chemical Depositio)
n) method, pulse laser ablation method, sputtering method,
It can be performed by a method such as a sol-gel method, which is appropriately suitable for the material forming the ferroelectric thin film. The ferroelectric thin film can be patterned by, for example, anisotropic ion etching (RIE) method.

In the ferroelectric non-volatile semiconductor memory of the present invention, the first electrode is formed under the ferroelectric layer and the second electrode is formed over the ferroelectric layer (that is, the first electrode is formed). 1
Corresponding to the lower electrode, the second electrode corresponds to the upper electrode), and the first electrode on the ferroelectric layer.
The second electrode may be formed under the ferroelectric layer (that is, the first electrode corresponds to the upper electrode and the second electrode corresponds to the lower electrode). it can. The plate line preferably extends from the second electrode from the viewpoint of simplifying the wiring structure. First
Specifically, as a structure in which the electrodes of 1 are formed in common, a stripe-shaped first electrode is formed, and the stripe-shaped first electrode is formed.
There may be mentioned a structure in which the ferroelectric layer is formed so as to cover the entire surface of the electrode. Incidentally, in such a structure,
The overlapping region of the first electrode, the ferroelectric layer and the second electrode corresponds to the memory cell. As a structure in which the first electrode is common, a structure in which each ferroelectric layer is formed in a predetermined region of the first electrode, and a second electrode is formed on the ferroelectric layer, or Also, in a predetermined surface area of the wiring layer,
There may be mentioned a structure in which each first electrode is formed, a ferroelectric layer is formed on each of the first electrodes, and a second electrode is formed on the ferroelectric layer. However, the configuration is not limited to.

Furthermore, in the ferroelectric non-volatile semiconductor memory of the present invention, the first electrode is formed below the ferroelectric layer and the second electrode is formed above the ferroelectric layer. The first electrode forming the memory cell has a so-called damascene structure, and the first electrode is formed on the ferroelectric layer and the second electrode is formed under the ferroelectric layer. In the case of the structure, it is preferable that the second electrode forming the memory cell has a so-called damascene structure from the viewpoint that the ferroelectric layer can be formed on a flat base.

In the present invention, the first electrode or the second electrode
Examples of the material forming the electrodes of Ir include Ir and IrO.
_2-X , Ir / IrO _2-X , SrIrO ₃ , Ru, Ru
_{O 2-X, SrRuO 3,} Pt, Pt / IrO 2-X, Pt /
RuO _2-X , Pd, Pt / Ti laminated structure, Pt / Ta
Laminated structure, Pt / Ti / Ta laminated structure, La _0.5 S
Examples thereof include r _0.5 CoO ₃ (LSCO), a Pt / LSCO laminated structure, and YBa ₂ Cu ₃ O ₇ . here,
The value of X is 0 ≦ X <2. In the laminated structure, the material described after "/" is in contact with the ferroelectric layer. The first electrode and the second electrode may be made of the same material, may be made of the same kind of material, or may be made of different kinds of materials. In order to form the first electrode or the second electrode, the conductive material layer is patterned in a step after forming the conductive material layer forming the first electrode or the conductive material layer forming the second electrode. do it. The conductive material layer is formed by, for example, a sputtering method, a reactive sputtering method, an electron beam evaporation method, a MO method.
It can be performed by a method such as a CVD method or a pulse laser ablation method that is appropriately suitable for the material forming the conductive material layer. In addition, the patterning of the conductive material layer is
For example, the ion milling method or the RIE method can be used.

The selection transistor, the switching transistor, and various transistors are, for example, the well-known MI.
It can be composed of an S-type FET or a MOS-type FET. Examples of the material forming the bit line include polysilicon doped with impurities and a refractory metal material. The connection between the selection transistor and the common first electrode and the connection between the selection transistor and the bit line may be performed through a connection hole. The connection hole may be, for example, a tungsten plug or polysilicon doped with impurities. Can be obtained by embedding.

In the present invention, silicon oxide (SiO ₂ ) and silicon nitride (Si) are used as materials for the insulating layer.
N), SiON, SOG, NSG, BPSG, PSG,
BSG or LTO can be exemplified.

Since the present invention is provided with a circuit for grounding the common first electrode or for short-circuiting the plate line and the common first electrode, the ferroelectric non-volatile semiconductor memory is provided. The common first electrode does not enter a floating state during the non-operation (during standby), and as a result, the potential fluctuation of the common first electrode can be suppressed.

[0052]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the drawings on the basis of an embodiment of the invention (hereinafter, simply referred to as an embodiment).

(Embodiment 1) Embodiment 1 is a ferroelectric non-volatile semiconductor memory (hereinafter referred to as a non-volatile memory) according to the first aspect (more specifically, the first A aspect) of the present invention. Abbreviated). FIG. 1 is a schematic partial cross-sectional view of the nonvolatile memory according to the first embodiment taken along a virtual vertical plane that is parallel to the extending direction of bit lines. Further, FIG. 2 shows a conceptual circuit diagram of the non-volatile memory of the first embodiment, and FIG. 3 shows a more specific circuit diagram of the conceptual circuit diagram of FIG. In FIG. 1, two non-volatile memories adjacent to each other in the bit line direction are shown. And, the reference number of one component of the adjacent nonvolatile memory is "'".
Attached.

The nonvolatile memory M according to the first embodiment is
(A) Bit line BL and (B) selection transistor TR
And (C) M (where M ≧ 2, M = 4 in the first embodiment) memory units MU configured of memory cells MC _M , and (D) M plate lines P.
L _M, consisting of.

Each memory cell MC _m comprises a first electrode 21, a ferroelectric layer 22 and a second electrode 23, and in the memory unit MU, the first electrode 2 of the memory cell MC _m .
1 is common, and the common first electrode 21 (may be referred to as common node CN) is the selection transistor TR.
Connected to the bit line BL via the memory unit MU
In, the m-th (where, m = 1, 2 · · ·, M) a second electrode 23 of the memory cell MC _m of is connected to the m-th plate line PL _m.

One source of the selection transistor TR /
The drain region 14A is connected to the bit line BL via the connection hole 15.
Connected to the other source of the selection transistor TR /
The drain region 14B is connected to the common first electrode 21 (first common node CN) in the memory unit MU via the connection hole 18 formed in the opening 17 provided in the insulating layer 16. There is. Further, the bit line BL is connected to the sense amplifier SA. The plate line PL _M is connected to the plate line decoder / driver PD.
Further, the word line WL that controls the operation of the selection transistor TR is connected to the word line decoder / driver WD. The word line WL extends in the direction perpendicular to the paper surface of FIG. The word line WL is common to the selection transistor TR that configures the nonvolatile memory M and the selection transistor that configures the nonvolatile memory that is adjacent in the direction perpendicular to the paper surface of FIG. The second electrode 23 of the memory cell MC _m forming the non-volatile memory M is common to the second electrode of the memory cell forming the non-volatile memory adjacent in the direction perpendicular to the paper surface of FIG. Also serves as PL _m .

A circuit (hereinafter sometimes referred to as a short circuit) for short-circuiting the _M plate lines PL _M and the common first electrode (common node CN) is provided. Alternatively, the switching transistor TR _S for grounding the common first electrode (common node CN) is provided. The short circuit specifically includes the switching transistor TR _S and the plate line decoder / driver PD.
And a transistor (not shown) for grounding the plate line PL _m . Word line WL for controlling the operation of the switching transistor TR _S
S is connected to the word line decoder / driver WD. Further, one source / drain region of the switching transistor TR _S is common to the other source / drain region 14B of the selection transistor TR, the other source / drain region 14C of the switching transistor TR _S is ground line (Not shown).
The common source / drain region of one transistor and the source / drain region of another transistor mean that the source / drain region occupies one source / drain region, or is connected by wiring. Means that The same applies to the following description.

Memory cell MC_MWhen operating, that is, memory
Cell MC_MWrite data to or write data to
When reading and rewriting, switching
Register TR_SIs turned off and the plate line decoder /
The plate line PL is provided on the driver PD_mGround
The transistor (not shown) for this purpose is also turned off. So
Then, for example, the memory cell MC_m(Where m is 1,
Read data stored in either 2, 3, 4)
If the word line WL is selected, the plate line PL is selected._j(M ≠
j) is, for example, (1/2) V_ccVoltage applied
And plate line PL _mTo drive. Where V_ccIs an example
For example, the power supply voltage. As a result, the memory cell MC
_mSelect transistor depending on the data stored in
The voltage (bit line potential) is present on the bit line BL via TR.
Be done. Then, the voltage of the bit line BL (bit line voltage
Position) is detected by the sense amplifier SA. The value of M is 4
Not limited to. The value of M may satisfy M ≧ 2,
As a practical value of M, for example, a power of 2 (2, 4,
8, 16 ...).

When the memory cell MC _M is inoperative (standby), the switching transistor TR _S is turned on to ground the common node CN and is provided in the plate line decoder / driver PD to ground the plate line PL _m . A transistor (not shown) for turning on is also turned on. As a result, the common first electrode (common node CN) is not brought into a floating state, and the state shown in FIG. 63A can be obtained. As a result, the common first electrode (common node CN) can be obtained. It is possible to suppress the potential fluctuation of (1). Therefore,
It is possible to reliably prevent the data destruction in the memory cell MC _M due to the polarization attenuation phenomenon.

The non-volatile state of the nonvolatile memory according to the various embodiments described later having the switching transistor is basically the non-volatile state of the non-volatile memory according to the first embodiment. Is the same as.

The method of manufacturing the non-volatile memory according to the first embodiment will be described below, but the non-volatile memory according to the other embodiments or modifications thereof can be manufactured by substantially the same method.

[Step-100] First, a MOS transistor that functions as the selecting transistor TR and the switching transistor TR _S in the nonvolatile memory is formed on the semiconductor substrate 10. For that purpose, for example, LOC
The element isolation region 11 having the OS structure is formed by a known method. The element isolation region may have a trench structure or a combination of a LOCOS structure and a trench structure. After that, the surface of the semiconductor substrate 10 is oxidized by, for example, a pyrogenic method to form the gate insulating film 12
To form. Next, a polysilicon layer doped with impurities is formed on the entire surface by a CVD method, and then the polysilicon layer is patterned to form a gate electrode 13. The gate electrode 13 also serves as a word line. The gate electrode 13 may be made of polycide or metal silicide instead of being made of a polysilicon layer. Next, the semiconductor substrate 10 is ion-implanted to form an LDD structure. After that, a SiO ₂ layer is formed on the entire surface by a CVD method, and then the SiO ₂ layer is etched back to form a gate sidewall (not shown) on the side surface of the gate electrode 13. Next, after ion-implanting the semiconductor substrate 10, activation / annealing treatment of the ion-implanted impurities is performed to form the source / drain regions 14A, 14B, 14C.

[Step-110] Next, a lower insulating layer made of SiO _{2 is} formed by the CVD method, and then an opening is formed in the lower insulating layer above one of the source / drain regions 14A by R.
It is formed by the IE method. Then, a polysilicon layer doped with impurities is formed on the lower insulating layer including the inside of the opening by a CVD method. As a result, the connection hole (contact plug) 15 is formed. Then, the bit line BL is formed by patterning the polysilicon layer on the lower insulating layer. After that, an upper insulating layer made of BPSG is formed on the entire surface by the CVD method. After forming the upper insulating layer made of BPSG, it is preferable to reflow the upper insulating layer in a nitrogen gas atmosphere at 900 ° C. for 20 minutes, for example. Further, if necessary, it is desirable to planarize the upper insulating layer by chemically and mechanically polishing the top surface of the upper insulating layer by, for example, a chemical mechanical polishing method (CMP method). The lower insulating layer and the upper insulating layer are collectively referred to as an insulating layer 16.

[Step-120] Next, an opening 17 is formed in the insulating layer 16 above the other source / drain region 14B by R.
After the formation by the IE method, the inside of the opening 17 is filled with impurity-doped polysilicon to complete the connection hole (contact plug) 18. The bit line BL is
It extends on the lower insulating layer in the left-right direction in the drawing so as not to come into contact with the connection hole 18.

The connection hole 18 is formed in the opening 17 formed in the insulating layer 16 by, for example, tungsten, Ti, P or the like.
t, Pd, Cu, TiW, TiNW, WSi ₂ , MoS
It can also be formed by embedding a metal wiring material made of a refractory metal such as i ₂ or metal silicide. The top surface of the connection hole 18 may exist on the same plane as the surface of the insulating layer 16, or the top portion of the connection hole 18 may extend to the surface of the insulating layer 16. Opening 17 with tungsten
Table 2 below shows the conditions under which the contact holes 18 are embedded and the connection holes 18 are formed.
For example. Before the opening 17 is filled with tungsten, it is preferable that a Ti layer and a TiN layer are sequentially formed on the insulating layer 16 including the inside of the opening 17 by, for example, a magnetron sputtering method. Here, the reason for forming the Ti layer and the TiN layer is to obtain an ohmic low contact resistance, prevent damage to the semiconductor substrate 10 in the blanket tungsten CVD method, and improve the adhesion of tungsten.

[Table 2] Ti layer (thickness: 20 nm) sputtering conditions Process gas: Ar = 35 sccm Pressure: 0.52 Pa RF power: 2 kW Substrate heating: None TiN layer (thickness: 100 nm) sputtering conditions process Gas: N ₂ / Ar = 100/35 sccm Pressure: 1.0 Pa RF power: 6 kW Substrate heating: None Tungsten CVD forming conditions Working gas: WF ₆ / H ₂ / Ar = 40/400/2250
sccm pressure: 10.7 kPa formation temperature: 450 ° C. Etching conditions for tungsten layer, TiN layer, and Ti layer First stage etching: etching for tungsten layer Working gas: SF ₆ / Ar / He = 110: 90: 5 scc
m pressure: 46 Pa RF power: 275 W Second stage etching: TiN layer / Ti layer etching Working gas: Ar / Cl ₂ = 75/5 sccm Pressure: 6.5 Pa RF power: 250 W

[Step-130] Next, on the insulating layer 16,
It is desirable to form an adhesion layer (not shown) made of titanium oxide. Then, a first electrode material layer that forms the first electrode (lower electrode) 21 made of Ir is formed on the adhesion layer by, for example, a sputtering method, and the first electrode material layer and the adhesion layer are formed by a photolithography technique. And the first electrode 2 by patterning based on the dry etching technique.
1 can be obtained.

[Step-140] Thereafter, for example, MOC
By the VD method, a Bi-based layered structure perovskite-type strong
Dielectric material (specifically, for example, crystallization temperature 750 °
Bi of C₂SrTa₂O ₉) Ferroelectric thin film consisting of
To form. After that, dry in 250 ° C air
After that, heat treatment for 1 hour in an oxygen gas atmosphere at 750 ° C.
After applying heat treatment to promote crystallization, if necessary,
Strong based on lithographic technology and dry etching technology
The dielectric thin film is patterned to obtain the ferroelectric layer 22.
It

[Step-150] Next, IrO _2-X layer, P
After the t layer is sequentially formed on the entire surface by the sputtering method, the Pt layer and the IrO _2-X layer are sequentially patterned based on the photolithography technology and the dry etching technology.
The second electrode 23 is formed. When the ferroelectric layer 22 is damaged by the etching, the heat treatment may be performed at the temperature required to recover the damage.

[Step-160] After that, the insulating film 2 is formed on the entire surface.
6A is formed.

Incidentally, the third to eighth embodiments described later.
In the manufacture of the non-volatile memory in, the following steps are performed: -Formation of an interlayer insulating layer 26 and planarization-Formation of an opening 27 and formation of a connection hole 28-First electrode 31, Bi _{2 having} a crystallization temperature of 700 ° C Sr
The ferroelectric layer 32 made of (Ta _1.5 Nb _0.5 ) O ₉ , the second electrode 33, and the insulating film 36A may be sequentially formed. In addition, Bi ₂ Sr (Ta _1.5 Nb
_The ferroelectric layer 32 made of _0.5 ) O ₉ may be subjected to a heat treatment for promoting crystallization in an oxygen gas atmosphere at 700 ° C. for 1 hour.

It should be noted that each second electrode may not also serve as a plate line. In this case, after the formation of the insulating films 26A and 36A is completed, the second electrode 23 and the second electrode 33 are connected by a connection hole (via hole).
A plate wire connected to such a connection hole may be formed on A and 36A.

For example, the conditions for forming the ferroelectric thin film made of Bi ₂ SrTa ₂ O ₉ are shown in Table 3 below. Table 3
In the above, “thd” is an abbreviation for tetramethylheptanedionate. The source materials shown in Table 3 are dissolved in a solvent containing tetrahydrofuran (THF) as a main component.

Table 3 Formation by MOCVD Source material: Sr (thd) ₂ -tetraglyme Bi (C ₆ H ₅ ) ₃ Ta (O-iC ₃ H ₇ ) ₄ (thd) Formation temperature: 400 to 700 ° C Process gas: Ar / O ₂ = 1000/1000 cm ³ Formation rate: 5 to 20 nm / min

Alternatively, a ferroelectric thin film made of Bi ₂ SrTa ₂ O _{9 is} prepared by pulse laser ablation method, sol-
It can also be formed on the entire surface by a gel method or an RF sputtering method. The formation conditions in these cases are illustrated below. When forming a thick ferroelectric thin film by the sol-gel method, spin coating and drying, or spin coating and baking (or annealing treatment) may be repeated a desired number of times.

[Table 4] Target formed by pulse laser ablation method: Bi ₂ SrTa ₂ O ₉ Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 5 Hz) Forming temperature: 400 to 800 ° C Oxygen concentration: 3 Pa

[0077] [Table 5] sol - gel method by forming _{ingredients: Bi (CH 3 (CH 2} ) 3 CH (C 2 H 5) COO) 3 [ bismuth _{2-ethylhexanoate, Bi (OOc) 3] Sr} ( CH ₃ (CH ₂ ) ₃ CH (C ₂ H ₅ ) COO) ₂ [strontium.2-ethylhexanoic acid, Sr (OOc) ₂ ] Ta (OEt) ₅ [tantalum ethoxide] Spin coating conditions: 3000 rpm × 20 seconds drying : 250 ° C x 7 minutes firing: 700 to 800 ° C x 1 hour (RT if necessary
A processing is added)

[Table 6] Formation target by RF sputtering method: Bi ₂ SrTa ₂ O ₉ ceramic target RF power: 1.2 W to 2.0 W / target 1 cm ² Atmospheric pressure: 0.2 to 1.3 Pa Formation temperature: Room temperature ˜600 ° C. Process gas: Ar / O ₂ flow rate ratio = 2/1 to 9/1

When the ferroelectric layer is made of PZT or PLZT, PZ by magnetron sputtering method
The conditions for forming T or PLZT are shown in Table 7 below. Alternatively, PZT or PLZT may be formed by reactive sputtering, electron beam evaporation, sol-gel method, or MOCVD.
It can also be formed by a method.

[Table 7] Target: PZT or PLZT Process gas: Ar / O ₂ = 90% by volume / 10% by volume Pressure: 4 Pa Power: 50 W Formation temperature: 500 ° C

Further, PZT or PLZT can be formed by the pulse laser ablation method. The forming conditions in this case are illustrated in Table 8 below.

[Table 8] Target: PZT or PLZT Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Formation temperature: 550 to 600 ° C Oxygen concentration: 40 to 120 Pa

(Embodiment 2) Embodiment 2 relates to a nonvolatile memory according to the first aspect (more specifically, the 1B aspect) of the present invention. FIG. 4 is a schematic partial cross-sectional view of the nonvolatile memory according to the second embodiment taken along a virtual vertical plane parallel to the extending direction of the bit line. Further, a conceptual circuit diagram of the nonvolatile memory according to the second embodiment is shown in FIG. 5, and a more specific circuit diagram of the conceptual circuit diagram of FIG. 5 is shown in FIG. Incidentally, also in FIG. 4, two non-volatile memories adjacent to each other in the bit line direction are illustrated. And, the reference number of one component of the adjacent nonvolatile memory is "'".
Attached.

In the nonvolatile memory according to the second embodiment, instead of the switching transistor TR _S for grounding the common first electrode (common node CN), the common first electrode 21 (common node CN) is used. Since it has the same structure as the nonvolatile memory of the first embodiment except that it is provided with a high resistance element R for grounding, the detailed description thereof will be omitted. The resistance value of the high resistance element R is 1 × 10 ⁶ Ω (1M
Ω) to 1 × 10 ¹² Ω (1 TΩ). The high resistance element R and a transistor (not shown) provided in the plate line decoder / driver PD for grounding the plate line PL _m short-circuit the M plate lines and the common first electrode. Circuit is configured.

The high resistance element R is used for the semiconductor substrate 10 when the MOS type transistor is manufactured in [Step-100].
It may be formed on top. One end of the high resistance element R is connected to the other source / drain region 14B of the selection transistor TR. On the other hand, the other end of the high resistance element R is connected to the ground line 14D.

Generally, the operation time of a non-volatile memory is on the order of tens of nanoseconds. Therefore, in order to prevent the signal transmitted through the common node CN from deteriorating during the operation of the nonvolatile memory, the time constant (first time constant) for extracting the charge via the high resistance element R is the operation time of the nonvolatile memory It is required to be sufficiently larger than On the other hand, when the non-volatile memory is inoperative (standby), a small time constant (second time constant) for extracting charges is required in order to quickly stabilize the potential of the common node CN. . Considering these requirements, it is desirable that the first time constant be 100 nanoseconds or more and the second time constant be 100 milliseconds or less. The parasitic capacitance of the common node is on the order of tens of fF to hundreds of fF. Therefore, the resistance value of the high resistance element R is 1 × 10 ⁶ Ω (1
MΩ) to 1 × 10 ¹² Ω (1 TΩ).

When the memory cell MC _M is operating, that is, when data is written in the memory cell MC _M , or when data is read and rewritten, the plate line PL / _m is provided in the plate line decoder / driver PD. A transistor (not shown) for grounding is turned off.
Then, for example, the memory cell MC _m (where m is 1,
When reading data stored in any one of 2, 3, 4), the word line WL is selected and the plate line PL _j (m ≠) is selected.
In j), the plate line PL _m is driven with a voltage of (1/2) V _cc applied, for example. Here, V _cc is, for example, a power supply voltage. As a result, the memory cell MC
_A voltage (bit line potential) appears on the bit line BL via the selection transistor TR depending on the data stored in _m . Then, the voltage of the bit line BL (bit line potential) is detected by the sense amplifier SA. The value of M is 4
Not limited to. The value of M may satisfy M ≧ 2,
As a practical value of M, for example, a power of 2 (2, 4,
8, 16 ...).

The resistance value of the high resistance element R is 1 × 10 ⁶ Ω (1
Since MΩ) to 1 × 10 ¹² Ω (1 TΩ), the high resistance element R has almost no influence on the voltage (bit line potential) appearing on the bit line BL during operation of the nonvolatile memory.

When the memory cell MC _M is inoperative (standby), a transistor (not shown) provided in the plate line decoder / driver PD for grounding the plate line PL _m is turned on. First common in less than 100 ms
The electrode (common node CN) of is changed from the floating state to the grounded state, and the state shown in FIG. 63A can be obtained. As a result, the potential fluctuation of the common first electrode (common node CN) is suppressed. can do. Therefore, it is possible to reliably prevent the data destruction occurs in the memory cell MC _M due to the polarization attenuation phenomenon.

Incidentally, the non-volatile state of the non-volatile memory in various embodiments to be described later provided with the high resistance element is basically the same as the non-volatile state of the non-volatile memory of the second embodiment.
It is similar to the inoperative state.

(Third Embodiment) In the third embodiment, a memory cell M constituting a non-volatile memory M having the same structure as the non-volatile memory M described in the first embodiment.
The memory cells MC _M ′ having the same structure as the C _M and the non-volatile memory M and forming the non-volatile memory M ′ sharing the bit line BL have an insulating layer (for convenience, referred to as an interlayer insulating layer 26). Are stacked through. FIG. 7 shows a schematic partial cross-sectional view when two non-volatile memories according to a virtual vertical plane parallel to the extending direction of the bit line are cut, and FIG. 8 shows a conceptual circuit diagram of the non-volatile memory. FIG. 9 shows a more specific circuit diagram of the conceptual circuit diagram shown in FIG.

Alternatively, the same structure as the memory cell MC _M forming the nonvolatile memory M having the same structure as the nonvolatile memory M described in the second embodiment and the nonvolatile memory M sharing the bit line BL. The memory cell MC _M ′ forming the nonvolatile memory M ′ having
6 are stacked. FIG. 10 shows a schematic partial cross-sectional view when two non-volatile memories according to a virtual vertical plane parallel to the extending direction of the bit line are cut, and FIG. 11 shows a conceptual circuit diagram of the non-volatile memory. FIG. 12 shows a more specific circuit diagram of the conceptual circuit diagram shown in FIG.

Memory cell M constituting the non-volatile memory M
The memory cell MC _M ′ constituting the nonvolatile memory M ′ located above C _M includes the first electrode 31 and the ferroelectric layer 3
2 and the second electrode 33, and the first electrode 31
Is a connection hole 28 formed in an opening 27 provided in the interlayer insulating layer 26 and a pad portion 2 formed on the insulating layer 16.
5, through the connection hole 18 formed in the opening 17 provided in the insulating layer 16, it is connected to the other source / drain region 14B of the selection transistor TR ′. Also.
Memory cells MC _M 'are covered with an insulating film 36A. Except for these points, the structure of the non-volatile memory M ′ is the same as the non-volatile memory M described in the first or second embodiment, and thus detailed description thereof is omitted. The switching transistor T
R _S, TR _S 'is its operation is a circuit diagram which is controlled by the same word line WL _S, may also be configured to be controlled by a different word line.

Alternatively, the nonvolatile memory M ₁ having the same structure as the nonvolatile memory M described in the first embodiment.
Memory cell MC _1M and non-volatile memory M constituting the
Memory cells MC _2M having the same structure as ₁ and forming a non-volatile memory M ₂ sharing the plate line PL _M are stacked via an insulating layer (for convenience, referred to as an interlayer insulating layer 26). FIG. 13 shows a schematic partial cross-sectional view of the two non-volatile memories cut along an imaginary vertical plane parallel to the extending direction of the bit line, and FIG. 14 is a conceptual circuit diagram of the non-volatile memory. A more specific circuit diagram of the conceptual circuit diagram of FIG. 14 is shown in FIG. 15, and a more specific circuit diagram of the conceptual circuit diagram of FIG. 15 is shown in FIG.

Alternatively, the nonvolatile memory M ₁ having the same structure as the nonvolatile memory M described in the second embodiment.
Memory cell MC _1M and non-volatile memory M constituting the
Memory cells MC _2M having the same structure as ₁ and forming a non-volatile memory M ₂ sharing the plate line PL _M are stacked via an insulating layer (for convenience, referred to as an interlayer insulating layer 26). FIG. 18 shows a schematic partial cross-sectional view when two non-volatile memories according to a virtual vertical plane parallel to the extending direction of the bit line are cut, and FIG. 19 and a conceptual circuit diagram of the non-volatile memory. A more specific circuit diagram of the conceptual circuit diagram of FIG. 20 is shown in FIG. 21, and a more specific circuit diagram of the conceptual circuit diagram of FIG. 20 is shown in FIG.

The memory cell MC _2M forming the nonvolatile memory M ₂ located above the memory cell MC _1M forming the nonvolatile memory M ₁ has the first electrode 31 and the ferroelectric layer 3
2 and the second electrode 33, and the first electrode 31
Is a connection hole 28 formed in an opening 27 provided in the interlayer insulating layer 26 and a pad portion 2 formed on the insulating layer 16.
5, through the connection hole 18 formed in the opening 17 provided in the insulating layer 16, it is connected to the other source / drain region 14B of the selection transistor TR ₂ . Except for these points, the structure of the non-volatile memory M ₂ has the same structure as the non-volatile memory M described in the first or second embodiment, and thus detailed description thereof will be omitted.
In addition, a plate line PL _m that constitutes the memory cell MC _1m ,
The plate line PL _m forming the memory cell MC _2m is connected in a region (not shown).

FIGS. 14 and 16, and FIGS. 19 and 19
21 is a non-volatile memory M whose circuit diagram is shown.₁, M₂At
Non-volatile memory M₁, M₂Selection transistor
TR ₁, TR₂Are connected to the same word line WL. So
Then, the paired memory cell MC_1m, MC_2m(M = 1,
Data complementary to 2 ..., M) is stored. example
For example, memory cell MC_1m, MC_2m(Where m is 1, 2,
When reading the data stored in (3, 4)
If the word line WL is selected, the plate line PL_j(M ≠
j) is, for example, (1/2) V_ccVoltage applied
And plate line PL_mTo drive. Where V_ccIs an example
For example, the power supply voltage. This allows complementary data
But a pair of memory cells MC_1m, MC_2mSelect from
Langista TR ₁, TR₂Bit line B paired via
L₁, BL₂Appears as a voltage (bit line potential). That
The paired bit line BL₁, BL₂Voltage
Output line potential) is detected by the sense amplifier SA.

The selection transistors TR ₁ and TR ₂ forming the nonvolatile memories M ₁ and M ₂ are connected to different word lines WL ₁ and WL ₂ , respectively, and the memory cells MC _1m and MC _2m are independently controlled. Then, by applying the reference voltage to one of the paired bit lines BL ₁ and BL ₂ , the memory cell MC
Data can also be read from each of _1m and MC _2m . A circuit diagram when such a configuration is adopted is shown in FIG.
And FIG. 17, and FIGS. 20 and 22.
If the selecting transistors TR ₁ and TR ₂ are driven at the same time, the circuit becomes equivalent to the circuits shown in FIGS. 14 and 16, and FIGS. 19 and 21.

Thus, each memory cell MC _1m , MC _2m
One bit is stored as data in each of (m = 1, 2, 3, 4) (see FIGS. 15 and 17, and FIGS. 20 and 22) or a pair of memory cells M.
Data complementary to C _1nm and MC _2nm is stored as 1 bit (FIGS. 14 and 16 and FIGS. 19 and 21).
reference). In an actual non-volatile memory, a set of memory units storing 8 bits or 4 bits is arranged in an array as an access unit. Then, the word line WL (WL
₁ , WL ₂ ), a plurality of access unit units (memory blocks) sharing the plate line PL _M are collectively written with data or read and rewritten with data. That is, in the memory block, all the non-volatile memories are collectively brought into operation sequentially, or are collectively brought into non-operation (standby) state.

The value of M is not limited to 4. The value of M is M
It is only necessary to satisfy ≧ 2, and as a practical value of M, for example, a power of 2 (2, 4, 8, 16 ...) Can be cited. Further, the value of N only needs to satisfy N ≧ 2, and as a practical value of N, for example, a power of 2 (2,
4, 8 ...).

(Embodiment 4) Embodiment 4 relates to a nonvolatile memory according to the second aspect (more specifically, the 2A aspect) of the present invention. FIG. 23 is a schematic partial cross-sectional view of the nonvolatile memory according to the fourth embodiment, taken along a virtual vertical plane parallel to the extending direction of the bit lines. Furthermore,
FIG. 2 is a conceptual circuit diagram of the nonvolatile memory according to the fourth embodiment.
4 (A) and (B), a more specific circuit diagram of the conceptual circuit diagram of FIG. 24 (A) is shown in FIG.
2B is a more specific circuit diagram of the conceptual circuit diagram of FIG.
6 shows. Incidentally, FIG. 24, 25 and 26, although show two nonvolatile memories M _1, M _2, the structure of these nonvolatile memory M _1, M ₂ are identical and in the following, non The memory M ₁ will be described.

The nonvolatile memory M ₁ of the fourth embodiment is
(A) Bit line BL ₁ and (B) selection transistor T
R ₁ and (C) are each M (provided that M ≧ 2,
In the fourth embodiment, M = 4) memory cells MC
N memory units MU _1N composed of 1 _NM (where N ≧ 2, and N = 2 in the fourth embodiment)
And (D) M × N plate lines.

Then, N memory units MU_1NIs
Through an insulating layer (hereinafter, referred to as an interlayer insulating layer 26 for convenience)
Each memory cell has a first electrode 21,
31, the ferroelectric layers 22 and 32, and the second electrodes 23 and 33
And each memory unit MU_1nAt the memory
Le MC_1nMHave a common first electrode, and the common first
The electrode is a selection transistor TR₁Through bit line B
L₁It is connected to the. Specifically, the memory unit M
U₁₁In the memory cell MC_11MThe first electrode 21 of
Common (this common first electrode is connected to the first common node
CN₁₁,), And the common first electrode 21 (first common electrode).
CN₁₁) Is a selection transistor TR ₁Through
Line BL₁It is connected to the. Also a memory unit
MU₁₂In the memory cell MC_12MFirst electrode 31
Are common (this common first electrode is connected to the second common node
De CN₁₂Common first electrode 31 (second common
Node CN₁₂) Is a selection transistor TR₁Through
Bit line BL₁It is connected to the. Furthermore, the nth layer
(However, n = 1, 2, ..., N) Memory unit MU
_1n, The m-th (however, m = 1, 2, ..., M)
Memory cell MC_{1 nm}The second electrodes 23 and 33 of the
[(N-1) M + m] th plate line PL_{(n-1) M + m}To
It is connected. In addition, this plate line PL_{(n-1) M + m}Is
Non-volatile memory M₂The second voltage of each memory cell constituting the
It is also connected to poles 23 and 33. In the fourth embodiment
More specifically, each plate line has a second electrode 2
It extends from 3,33.

Selection transistor TR₁One source
/ Drain region 14A is connected to bit line B through connection hole 15.
L₁Connected to the selection transistor TR₁The other saw
The source / drain region 14B is connected to the insulating layer 16.
The first layer memory unit MU is passed through the continuous hole 18.₁₁To
Common first electrode 21 (first common node C
N ₁₁)It is connected to the. Furthermore, the selection transistor
TR₁The other source / drain region 14B is an insulating layer.
16 to the connection hole 18 and the interlayer insulating layer 26.
The second layer memory unit is connected through the connection hole 28 provided.
MU₁₂Common first electrode 31 (second common
Node CN₁₂)It is connected to the. In the figure, reference numbers
36A is an insulating film.

The bit line BL ₁ is connected to the sense amplifier SA. The plate line PL _{(n-1) M + m} is connected to the plate line decoder / driver PD. Furthermore, the word line WL (or the word lines WL ₁ and WL ₂ )
Are connected to the word line decoder / driver WD. The word line WL extends in the direction perpendicular to the paper surface of FIG. In addition, the memory cell M that constitutes the nonvolatile memory M ₁
The second electrode 23 of C _11m is a memory cell MC _21m that constitutes the nonvolatile memory M ₂ that is adjacent in the direction perpendicular to the paper surface of FIG.
Common to the second electrode of, and also serves as the plate line PL _{(n-1) M + m} . Further, the second electrode 33 of the memory cell MC _12m that constitutes the nonvolatile memory M ₁ is the same as the second electrode of the memory cell MC _22m that constitutes the nonvolatile memory M ₂ that is adjacent in the direction perpendicular to the paper surface of FIG. Common and plate line P
Also serves as L _{(n-1) M + m} . The word line WL includes a selection transistor TR ₁ that constitutes the nonvolatile memory M ₁ ,
This is also common to the selection transistor TR ₂ that constitutes the nonvolatile memory M ₂ that is adjacent in the direction perpendicular to the paper surface of FIG.

A circuit for short-circuiting the M × N plate lines and the common first electrode (first common node CN ₁₁ , second common node CN ₁₂ ) is provided. Alternatively,
The switching transistor TR _S1 for grounding the common first electrode (the first common node CN ₁₁ and the second common node CN ₁₂ ) is provided. The short circuit is specifically provided in the switching transistor TR _S1 and the plate line decoder / driver PD, and is connected to the plate line PL.
It is composed of a transistor (not shown) for grounding _{(n-1) M + m} . Switching transistor TR _S1
The word line WL _S for controlling the operation of is connected to the word line decoder / driver WD. Also the operation of the switching transistor TR _S2 constituting the nonvolatile memory M ₂ adjacent in the direction perpendicular to the paper surface in FIG. 23, the word line WL _S
Controlled by. Further, one source / drain region of the switching transistor TR _S1 is common and the other source / drain region 14B of the selection transistor TR _1, the other source / drain region 14C of the switching transistor TR _S1 is grounded Line (not shown)
It is connected to the.

[0107] In the nonvolatile memory M _1, M _2, which shows a circuit diagram in (A) and 25 in FIG. 24, the selection transistor TR ₁ constituting the nonvolatile memory M _1, M _2, TR ₂ is the same word line It is connected to WL. Then, the paired memory cells MC _1nm , MC _2nm (n = 1, 2, ...,
Data complementary to N and m = 1, 2, ..., M) is stored. For example, when reading the data stored in the memory cells MC _1nm and MC _2nm (where m is one of 1, 2, 3, and 4), the word line WL is selected and the plate line PL _{(n-1) is selected.} For plate lines other than _{M + m} , for example, (1 /
2) With the voltage of V _cc applied, plate line PL
Drive _{(n-1) M + m} . Here, V _cc is, for example, a power supply voltage. As a result, complementary data is transmitted from the paired memory cells MC _1nm and MC _2nm via the selection transistors TR ₁ and TR ₂ to the paired bit lines BL ₁ and BL _2.
Appears as a voltage (bit line potential). Then, the sense amplifier SA detects the voltage (bit line potential) of the paired bit lines BL ₁ and BL ₂ .

The selection transistors TR ₁ and TR ₂ forming the nonvolatile memories M ₁ and M ₂ are connected to different word lines WL ₁ and WL ₂ , respectively, and the memory cells MC _1nm and MC _2nm are connected.
Are independently controlled to apply a reference voltage to one of the paired bit lines BL ₁ and BL ₂ so that the memory cell M
Data can also be read from each of C _1nm and MC _2nm . For circuit diagrams when such a structure is adopted, see FIGS. 24B and 26. If the selecting transistors TR ₁ and TR ₂ are driven at the same time, the circuit becomes equivalent to the circuit shown in FIG. 24 (A) and FIG. 25.

In this way, each memory cell MC _1nm , MC
One bit is stored as data in each of 2 _nm (n = 1, 2, m = 1, 2, 3, 4) (see FIG. 24 (B) and FIG. 26) or a pair. Data complementary to the memory cells MC _1nm and MC _2nm is stored as 1 bit (see (A) of FIG. 24 and FIG. 25). In an actual non-volatile memory, a set of memory units storing 8 bits or 4 bits is arranged in an array as an access unit. And
Word line WL (WL ₁ , WL ₂ ) of the transistor for selection,
Data is written, or data is read and rewritten collectively to a plurality of access unit units (memory blocks) in which the plate line PL _{(n-1) M + m} is shared. That is, in the memory block, all the non-volatile memories are collectively put into an operating state,
Alternatively, they are all inoperative (standby).

The value of M is not limited to 4. The value of M is M
It is only necessary to satisfy ≧ 2, and as a practical value of M, for example, a power of 2 (2, 4, 8, 16 ...) Can be cited. Further, the value of N only needs to satisfy N ≧ 2, and as a practical value of N, for example, a power of 2 (2,
4, 8 ...).

A pair of non-volatile memories in a pair
Selection transistor TR₁And TR₂Is the word line WL,
And a pair of bit lines BL₁, BL₂Surrounded by
Occupied area. Therefore, if the word line and bit
If the wires are placed at the shortest pitch, the
A pair of selection transistors TR in a volatile memory ₁
And TR₂Area is 8F²Is. However,
A pair of selection transistors TR₁, TR₂With M pairs
Memory cell MC_11m, MC_12m, MC_21m, MC_22m
1 bit because it is shared by (m = 1, 2, ..., M)
Per-selection transistor TR₁, TR₂The number of
In addition, since the arrangement of the word lines WL is loose,
It is easy to reduce the size of the volatile memory. Moreover, in the peripheral circuit
Even with one word line decoder / driver WD and M
Select M bit with book plate line decoder / driver PD
You can choose. Therefore, such a configuration is adopted.
As a result, the cell area is 8F²Realize a layout close to
It is possible to realize a chip size comparable to DRAM.
it can.

(Embodiment 5) Embodiment 5 relates to a nonvolatile memory according to the second aspect (more specifically, the second B aspect) of the present invention. FIG. 27 shows a schematic partial cross-sectional view of the nonvolatile memory according to the fifth embodiment, taken along a virtual vertical plane parallel to the extending direction of the bit lines. Furthermore,
FIG. 2 is a conceptual circuit diagram of the nonvolatile memory according to the fifth embodiment.
8A and 8B, a more specific circuit diagram of the conceptual circuit diagram of FIG. 28A is shown in FIG.
3B is a more specific circuit diagram of the conceptual circuit diagram of FIG.
It shows in 0. 28, 29 and 30 show two non-volatile memories M ₁ and M ₂ , the non-volatile memories M ₁ and M ₂ have the same structure. The memory M ₁ will be described.

The nonvolatile memory M ₁ of the fifth embodiment has a common first electrode instead of the switching transistor TR _S1 for grounding the common first electrode (common nodes CN ₁₁ and CN ₁₂ ). Except that a high resistance element R ₁ for grounding (common nodes CN ₁₁ and CN ₁₂ ) is provided,
Since it has the same structure as the nonvolatile memory of the fourth embodiment, detailed description thereof will be omitted. The high resistance element R ₁ has a resistance value of 1 × 10 ⁶ Ω (1 MΩ) to 1 × 10 ¹² Ω (1T
Ω) polysilicon layer. The high resistance element R ₁ and a transistor (not shown ₎ provided in the plate line decoder / driver PD for grounding the plate line PL _{(n-1) M + m} are used to provide M × N plate lines. And a common first electrode (common nodes CN ₁₁ and CN ₁₂ ) are short-circuited.

The high resistance element R ₁ is used for the semiconductor substrate 1 when the MOS type transistor is manufactured in [Step-100].
It may be formed on the surface 0. One end of the high-resistance element R _1, the other source / drain region 1 of the selection transistor TR ₁
4B is connected. The other end of the high resistance element R ₁ is connected to the ground line 14D.

The operation of the non-volatile memory whose circuit diagram is shown in FIGS. 28A and 29 is the same as that shown in FIGS.
The operation of the non-volatile memory whose circuit diagram is shown in FIG. 28 can be similar to the operation of the non-volatile memory whose circuit diagram is shown in FIG. 28B and FIG. Since the operation can be the same as that of the nonvolatile memory whose circuit diagram is shown in FIG.

(Embodiment 6) Embodiment 6 relates to a non-volatile memory according to a third aspect (more specifically, the 3A aspect) of the present invention. FIG. 31 is a schematic partial cross-sectional view of the nonvolatile memory according to the sixth embodiment taken along a virtual vertical plane parallel to the extending direction of bit lines. Furthermore,
FIG. 3 is a conceptual circuit diagram of the nonvolatile memory according to the sixth embodiment.
2 to 34, a more specific circuit diagram of the conceptual circuit diagram of FIG. 32 is shown in FIG. 35, and a more specific circuit diagram of the conceptual circuit diagram of FIG. 34 is shown in FIG. 36. 32 to 3
Two nonvolatile memories M ₁ and M ₂ are shown in FIG.
The nonvolatile memories M ₁ and M ₂ have the same structure,
In the following, the nonvolatile memory M ₁ will be described.

Nonvolatile memory M of the sixth embodiment₁Is
(A) Bit line BL₁And (B) N (however, if N ≧ 2,
Yes, in the sixth embodiment, N = 2)
Register TR₁₁, TR₁₂And (C) are each M (however
However, M ≧ 2, and in the sixth embodiment, M = 4).
Memory cell MC_11M, MC_12MConsists of N
Memory unit MU ₁₁, MU₁₂And (D) M plays
Line PL_M, Consists of.

Then, N memory units MU_1NIs
They are stacked with an insulating layer (interlayer insulating layer 26) interposed therebetween. each
The memory cell has a first electrode, a ferroelectric layer, and a second electrode.
Consists of. Specifically, the first (hereinafter referred to as the first layer)
BU) memory unit MU₁₁Each memory cell M constituting the
C_11MIs the first electrode 21, the ferroelectric layer 22 and the second electrode.
It is composed of the pole 23 and is the second (hereinafter referred to as the second layer)
Memory unit MU ₁₂Memory cells MC configuring
_12MIs the first electrode 31, the ferroelectric layer 32, and the second electrode
33 and 33. Furthermore, each memory unit MU_1nTo
Memory cell MC_{1 nm}The first electrodes 21 and 31 of
It is common. Specifically, the first layer memory unit MU
₁₁In the memory cell MC_11MThe first electrode 21 of
It is common. This common first electrode 21 is connected to the first common
De CN₁₁Sometimes called. In addition, the second layer memory unit
Knit MU₁₂In the memory cell MC_12MThe first electric
The pole 31 is common. This common first electrode 31
Common node CN₁₂Sometimes called. Furthermore, the nth
Eye (however, n = 1, 2, ..., N, and hereinafter, nth layer
Memory unit MU)_1nIn the m-th
(However, m = 1, 2 ..., M)
The electrodes 23 and 33 are connected to the memory unit MU._1nCommon between
M-th plate line PL_mIt is connected to the. Fruit
In the sixth embodiment, more specifically, each plate line
Extend from the second electrodes 23, 33.

The nth layer (however, n = 1, 2, ..., N)
Memory unit MU_1nThe common first electrode in
Nth selection transistor TR_1nThrough bit line
BL ₁It is connected to the. Specifically, each selection
Dista TR₁₁, TR₁₂One source / drain region 1
4A is a bit line BL₁Connected to the first selection gate
Langista TR₁₁The other source / drain region 14B
Through the connection hole 18 provided in the insulating layer 16
Layer memory unit MU₁₁Common first electrode in
21 (first common node CN₁₁)It is connected to the. Well
The second selection transistor TR₁₂The other saw
The source / drain region 14B is connected to the insulating layer 16.
Provided in the continuous hole 18, the pad portion 25, and the interlayer insulating layer 26
The second layer memory unit through the connection hole 28 formed.
MU₁₂Common first electrode 31 (second common
De CN₁₂)It is connected to the.

The bit line BL ₁ is connected to the sense amplifier SA. Further, the plate line PL _M is connected to the plate line decoder / driver PD. Furthermore, word lines WL ₁ and WL ₂ (or word lines WL ₁₁ and WL ₁₂ ,
WL ₂₁ and WL ₂₂ ) are word line decoders / drivers WD
It is connected to the. The word lines WL ₁ and WL ₂ extend in the direction perpendicular to the paper surface of FIG. In addition, the nonvolatile memory M ₁
The second electrode 23 of the memory cell MC _11m forming the memory cell MC _21m is common to the second electrode of the memory cell MC _21m forming the nonvolatile memory M ₂ which is adjacent in the direction perpendicular to the paper surface of FIG.
It also serves as the plate line PL _m . Furthermore, the second electrode 33 of the memory cell MC _12m forming the nonvolatile memory M ₁
Is a non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.
It is also common to the second electrode of the memory cell MC _22m constituting ₂ and also serves as the plate line PL _m . These plate lines PL _m are connected in a region (not shown).
Further, the word line WL ₁ is common to the selection transistor TR ₁₁ which constitutes the non-volatile memory M ₁ and the selection transistor TR ₂₁ which constitutes the non-volatile memory M ₂ which is adjacent in the direction perpendicular to the paper surface of FIG. . Furthermore, the word line WL
₂ is common to the selection transistor TR ₁₂ which constitutes the non-volatile memory M ₁ and the selection transistor TR ₂₂ which constitutes the non-volatile memory M ₂ which is adjacent in the direction perpendicular to the paper surface of FIG.

Then, M plate lines and N common lines are used.
First electrode (first common node CN ₁₁, The second common no
De CN₁₂) And a circuit to short-circuit. Or
In addition, each common first electrode (first common node CN₁, First
2 common nodes CN₁₂) To ground
Transistor TR_S11, TR_S12Is equipped with. Incidentally, short
Specifically, the junction circuit is a switching transistor T.
R_S11, TR_S12And plate line decoder / driver PD
Installed on the plate line PL_mTran for grounding
It is composed of a register (not shown). Switching
Transistor TR_S11, TR_S12That controls the operation of
Line WL_SConnected to word line decoder / driver WD
Has been done. In addition, the switching transistor TR
_S11One source / drain region is the first selection transistor.
Langista TR₁₁The other source / drain region 14B
Common with the switching transistor TR_S12of
One source / drain region is the second selection transistor.
Star TR₁₂Common to the other source / drain region 14B of
Is. Furthermore, the switching transistor T
R_S11, TR_S12The other source / drain region 14C
Is connected to a ground wire (not shown).

In the nonvolatile memories M ₁ and M ₂ whose circuit diagrams are shown in FIGS. 32 and 35, the selection transistors TR _1n and TR _2n forming the nonvolatile memories M ₁ and M ₂ are connected to the same word line WL _n . Has been done. Then, the paired memory cells MC _1nm and MC _2nm (n = 1, 2 and m = 1, 2)
,, M) is stored as complementary data. For example,
Memory cells MC _11m , MC _21m (where m is 1, 2,
When reading the data stored in any one of 3 and 4, the word line WL ₁ is selected and the plate line PL _j (m ≠) is selected.
In j), the plate line PL _m is driven with a voltage of (1/2) V _cc applied, for example. As a result, complementary data is stored in the paired memory cells MC _11m and MC _21m.
Appears as a voltage (bit line potential) on the paired bit lines BL ₁ and BL ₂ via the selection transistors TR ₁₁ and TR ₂₁ . Then, the paired bit lines BL ₁ ,
The voltage of BL ₂ (bit line potential) is detected by the sense amplifier SA.

Nonvolatile memory M₁, M₂For selection to make up
Transistor TR₁₁, TR₁₂, TR _{twenty one}, TR_{twenty two}To it
Different word lines WL₁₁, WL₁₂, WL_{twenty one}, WL_{twenty two}
Connected to the memory cell MC_{1 nm}, MC_{2 nm}Control independently
And paired bit lines BL ₁, BL₂Reference voltage on one side
Memory cell MC by applying_{1 nm}, MC_{2 nm}
It is also possible to read data from each of the. This
34 and 36 are circuit diagrams when adopting such a configuration.
checking ... In addition, the selection transistor TR₁₁, TR_{twenty one}
Drive simultaneously and select transistor TR₁₂, TR_{twenty two}To
If they are driven at the same time, the circuits shown in FIG. 32 and FIG.
It is worth it.

In this way, each memory cell MC _1nm , MC
One bit is stored as data in each of 2 _nm (n = 1, 2, m = 1, 2, 3, 4) (see FIGS. 34 and 36) or a pair of memory cells MC.
Data complementary to _{1 nm} and MC _{2 nm} is stored as 1 bit (see FIGS. 32 and 35). In an actual non-volatile memory, a set of memory units storing 8 bits or 4 bits is arranged in an array as an access unit. Then, word lines WL ₁ and WL ₂ (or word lines WL ₁₁ and
_{WL 12, WL 21, WL 22} ), to the plate line PL _M is shared multiple access units (memory blocks), and collectively performs the data write or read and rewrite data. That is, in the memory block, all the non-volatile memories are collectively brought into operation sequentially, or are collectively brought into non-operation (standby) state.

The value of M is not limited to 4. The value of M is M
It is only necessary to satisfy ≧ 2, and as a practical value of M, for example, a power of 2 (2, 4, 8, 16 ...) Can be cited. Further, the value of N only needs to satisfy N ≧ 2, and as a practical value of N, for example, a power of 2 (2,
4, 8 ...).

A conceptual circuit diagram of the modification of FIG. 32 is shown in FIG.
Shown in. In the circuit diagram shown in FIG. 33, the first selection
Transistor TR₁₁, TR_{twenty one}, The second selection transistor
TR₁₂, TR_{twenty two}One of the source / drain regions and the
Line BL₁, BL₂Switching transistor between
TR_S1, TR_S2And a control transistor TR_C1，
TR_C2Is provided. When the non-volatile memory is operating
Is a control transistor TR_C1, TR_C2Is turned on
Switching transistor TR_S1, TR_S2Is off
It becomes a state. On the other hand, when the non-volatile memory is inactive (standby
When), the control transistor TR_C1, TR_C2Is off
And the switching transistor TR _S1, T
R_S2, Selection transistor TR₁₁, TR₁₂, TR_{twenty one}, T
R_{twenty two}Is turned on. Control transistor TR_C1, T
R_C2Is the control word line WL_CControlled by and for control
Word line WL_CIs the word line decoder / driver WD
It is connected.

(Embodiment 7) Embodiment 7 relates to a non-volatile memory according to a third aspect (more specifically, a 3B aspect) of the present invention. FIG. 37 shows a schematic partial cross-sectional view of the nonvolatile memory according to the seventh embodiment taken along a virtual vertical plane that is parallel to the extending direction of the bit lines. Furthermore,
FIG. 3 is a conceptual circuit diagram of the nonvolatile memory according to the seventh embodiment.
8 to 40, a more specific circuit diagram of the conceptual circuit diagram of FIG. 38 is shown in FIG. 41, and a more specific circuit diagram of the conceptual circuit diagram of FIG. 40 is shown in FIG. 38 to 4
Two nonvolatile memories M ₁ and M ₂ are shown in FIG.
The nonvolatile memories M ₁ and M ₂ have the same structure,
In the following, the nonvolatile memory M ₁ will be described.

The nonvolatile memory M ₁ of the seventh embodiment has switching transistors TR _S11 and TR _S12 for grounding the common first electrode (common nodes CN ₁₁ and CN ₁₂ ).
Instead of the common first electrode (common nodes CN ₁₁ , C
Since it has the same structure as the nonvolatile memory of the sixth embodiment except that it has high resistance elements R ₁₁ and R ₁₂ for grounding N ₁₂ ), detailed description thereof will be omitted. The high resistance elements R ₁₁ and R ₁₂ are composed of a polysilicon layer having a resistance value of 1 × 10 ⁶ Ω (1 MΩ) to 1 × 10 ¹² Ω (1 TΩ). The high resistance elements R ₁₁ and R ₁₂ and the transistor (not shown) provided in the plate line decoder / driver PD for grounding the plate line PL _m
A circuit for short-circuiting the plate line of the book and the N common first electrodes is configured.

The high resistance elements R ₁₁ and R ₁₂ are formed according to [Step-10
0], the MOS transistor may be formed on the semiconductor substrate 10. High resistance element R ₁₁ , R ₁₂
Is connected to the other source / drain region 14B of the selecting transistors TR ₁₁ and TR ₁₂ . Also,
The other ends of the high resistance elements R ₁₁ and R ₁₂ are connected to the ground line 14D.

A conceptual circuit diagram of the modification of FIG. 38 is shown in FIG. In the circuit diagram shown in FIG. 39, one of the source / drain regions of the first selection transistors TR ₁₁ and TR ₂₁ and the second selection transistors TR ₁₂ and TR ₂₂ and the bit lines BL ₁ and BL _{2 are included.} Between the high resistance element R ₁ ,
R ₂ and control transistors TR _C1 and TR _C2 are provided. When the nonvolatile memory operates, the control transistors TR _C1 and TR _C2 are turned on. On the other hand, when the nonvolatile memory is inoperative (standby), the control transistors TR _C1 and TR _C2 are turned off and the selection transistors TR ₁₁ , TR ₁₂ , TR ₂₁ and TR ₂₂ are turned on. The control transistors TR _C1 and TR _C2 are controlled by the control word line WL _C , and the control word line WL _C is connected to the word line decoder / driver WD.

The operation of the non-volatile memory whose circuit diagram is shown in FIGS. 38 and 41 can be the same as the operation of the non-volatile memory whose circuit diagram is shown in FIG. 32 and FIG.
And the operation of the non-volatile memory whose circuit diagram is shown in FIG.
The operation can be similar to that of the nonvolatile memory whose circuit diagram is shown in FIGS.

(Embodiment 8) Embodiment 8 relates to a nonvolatile memory according to a fourth aspect of the present invention (more specifically, a fourth A aspect). FIG. 43 shows a schematic partial cross-sectional view of the nonvolatile memory according to the eighth embodiment taken along a virtual vertical plane that is parallel to the extending direction of the bit lines. Furthermore,
FIG. 4 is a conceptual circuit diagram of the nonvolatile memory according to the eighth embodiment.
4 and FIG. 45, and a more specific circuit diagram is shown in FIG. Incidentally, FIG. 44 and FIG. 45, but show two nonvolatile memories M _1, M _2, these nonvolatile memory M _1,
The structure of M ₂ is the same, and the nonvolatile memory M ₁ will be described below.

Nonvolatile memory M of the eighth embodiment₁Is
(A) N pieces (however, N ≧ 2, and in the eighth embodiment
For N = 2) bit line BL_1NAnd (B) N choices
Transistor TR_1NAnd (C) are each M (however
However, M ≧ 2, and M = 4 in the eighth embodiment.
Memory cell MC_11M, MC_12MConsists of N
Memory unit MU _1NAnd (D) M plate lines PL
_M, Consists of.

Incidentally, in FIG. 44, FIG. 45, FIG. 46, FIG. 48, FIG. 49 and FIG. 50, a memory unit MU ₁₁ composed of a bit line BL ₁₁ , a selecting transistor TR ₁₁ and a memory cell MC _11M is shown. , A sub unit SU ₁₁ , and a memory unit MU _{12 including} a bit line BL ₁₂ , a selection transistor TR ₁₂ and a memory cell MC _12M is represented by a sub unit SU ₁₂ .

Then, N memory units MU_1NIs
They are stacked with an insulating layer (interlayer insulating layer 26) interposed therebetween. each
The memory cell has a first electrode, a ferroelectric layer, and a second electrode.
Consists of. Specifically, the first (called the first layer)
Memory unit MU₁₁Memory cells MC configuring_11M
Is the first electrode 21, the ferroelectric layer 22, and the second electrode 23.
And the second (called the second layer) memory unit.
MU₁₂Memory cells MC configuring_12MIs the first
It is composed of an electrode 31, a ferroelectric layer 32 and a second electrode 33.
It Furthermore, each memory unit MU_1nAt the memory
Cell MC_{1 nm}The first electrodes 21 and 31 of are common. Ingredient
Physically, the memory unit MU of the first layer ₁₁At
Memory cell MC_11MThe first electrode 21 of is common. This
Of the common first electrode 21 of the first common node CN₁₁Call
There are cases where In addition, the memory unit MU of the second layer₁₂
In the memory cell MC_12MThe first electrode 31 of is common
Is. This common first electrode 31 is connected to the second common node
CN₁₂Sometimes called. Furthermore, the nth (nth layer)
(Where n = 1, 2, ..., N)
MU_1n, The m-th (however, m = 1, 2 ...
,, M) second electrodes 23 and 33 of the memory cell
Reunit MU_1nThe m-th plate that was shared between the
Line PL_mIt is connected to the. In the eighth embodiment,
More specifically, each plate line has a second electrode 23, 3
It extends from 3.

The nth layer (however, n = 1, 2, ..., N)
Memory unit MU_1nThe common first electrode in
Nth selection transistor TR_1nThrough the nth
Bit line BL_1nIt is connected to the. Specifically, the nth
Th selection transistor TR_1nOne source / drain
The in-region 14A is connected to the nth bit through the connection hole 15.
Line BL_1nConnected to the first selection transistor T
R₁₁The other source / drain region 14B is the insulating layer 1
6 through the connection hole 18 provided in the first layer memory
Unit MU₁₁Common first electrode 21 (first
Common node CN ₁₁)It is connected to the. Also the second
Selection transistor TR₁₂The other source / drain of
The region 14B is formed by connecting holes 18 and holes formed in the insulating layer 16.
Connection holes provided in the pad portion 25 and the interlayer insulating layer 26
28 through the second layer memory unit MU₁₂Oke
Common first electrode 31 (second common node CN₁₂) To
It is connected.

The bit line BL _1n is connected to the sense amplifier SA. Further, the plate line PL _M is connected to the plate line decoder / driver PD. Furthermore, word lines WL ₁ and WL ₂ (or word lines WL ₁₁ and WL ₁₂ ,
WL ₂₁ and WL ₂₂ ) are word line decoders / drivers WD
It is connected to the. The word lines WL ₁ and WL ₂ extend in the direction perpendicular to the paper surface of FIG. In addition, the nonvolatile memory M ₁
The second electrode 23 of the memory cell MC _11m forming the memory cell MC _21m is common to the second electrode of the memory cell MC _21m forming the non-volatile memory M ₂ adjacent in the direction perpendicular to the paper surface of FIG.
It also serves as the plate line PL _m . Furthermore, the second electrode 33 of the memory cell MC _12m forming the nonvolatile memory M ₁
Is a nonvolatile memory M adjacent in the direction perpendicular to the paper surface of FIG.
It is also common to the second electrode of the memory cell MC _22m constituting ₂ and also serves as the plate line PL _m . These plate lines PL _m are connected in a region (not shown).
Further, the word line WL ₁ is common to the selection transistor TR ₁₁ which constitutes the nonvolatile memory M ₁ and the selection transistor TR ₂₁ which constitutes the nonvolatile memory M ₂ which is adjacent in the direction perpendicular to the paper surface of FIG. . Furthermore, the word line WL
₂ is common to the selection transistor TR ₁₂ which constitutes the non-volatile memory M ₁ and the selection transistor TR ₂₂ which constitutes the non-volatile memory M ₂ which is adjacent in the direction perpendicular to the paper surface of FIG.

Then, M plate lines and N common lines are used.
First electrode (first common node CN ₁₁, The second common no
De CN₁₂) And a circuit to short-circuit. Or
In addition, each common first electrode (first common node CN₁, First
2 common nodes CN₁₂) To ground
Transistor TR_S11, TR_S12Is equipped with. Incidentally, short
Specifically, the junction circuit is a switching transistor T.
R_S11, TR_S12And plate line decoder / driver PD
Installed on the plate line PL_mTran for grounding
It is composed of a register (not shown). Switching
Transistor TR_S11, TR_S12That controls the operation of
Line WL_SConnected to word line decoder / driver WD
Has been done. In addition, the switching transistor TR
_S11One source / drain region is the first selection transistor.
Langista TR₁₁The other source / drain region 14B
Common with the switching transistor TR_S12of
One source / drain region is the second selection transistor.
Star TR₁₂Common to the other source / drain region 14B of
Is. Furthermore, the switching transistor T
R_S11, TR_S12The other source / drain region 14C
Is connected to a ground wire (not shown).

In the nonvolatile memories M ₁ and M ₂ whose circuit diagrams are shown in FIGS. 44 and 46, the selection transistors TR ₁₁ and TR ₂₁ forming the nonvolatile memories M ₁ and M ₂ are connected to the same word line WL ₁ . Connected to select transistors TR ₁₂ , T
R ₂₂ is connected to the same word line WL ₂ . And
_Paired memory cells MC _1nm , MC _2nm (n = 1, 2,
And data complementary to m = 1, 2, ..., M) is stored. For example, when reading data stored in the memory cells MC _11m and MC _21m (where m is one of 1, 2, 3, and 4), the word line WL ₁ is selected and the plate line PL _j (m ≠. In j), the plate line PL _m is driven with a voltage of (1/2) V _cc applied, for example. As a result, complementary data is stored in the paired memory cells M.
Selection transistors TR ₁₁ and TR ₂₁ from C _11m and MC _21m
Appears as a voltage (bit line potential) on the paired bit lines BL ₁₁ and BL ₂₁ . The sense amplifier SA detects the voltage (bit line potential) of the paired bit lines BL ₁₁ and BL ₂₁ .

Nonvolatile memory M₁, M₂For selection to make up
Transistor TR₁₁, TR₁₂, TR _{twenty one}, TR_{twenty two}To it
Different word lines WL₁₁, WL₁₂, WL_{twenty one}, WL_{twenty two}
Connected to the memory cell MC_{1 nm}, MC_{2 nm}Control independently
And paired bit lines BL ₁₁, BL_{twenty one}, Or vs
Bit line BL became₁₂, BL_{twenty two}Mark the reference voltage on one side
Memory cell MC_{1 nm}, MC_{2 nm}Noso
Data can also be read from each. like this
For the circuit diagram when the configuration is adopted, see FIGS. 45 and 46.
Teru. In addition, the selection transistor TR₁₁, TR_{twenty one}The same
Sometimes driven, select transistor TR₁₂, TR_{twenty two}At the same time
If it is driven to, the circuit becomes equivalent to the circuit shown in FIG.

In this way, each memory cell MC _1nm , MC
One bit is stored as data in each of 2 _nm (n = 1, 2, m = 1, 2, 3, 4) (see FIG. 45), or a pair of memory cells MC _1nm , M
Data complementary to C _{2 nm} is stored as 1 bit (see FIG. 44). In an actual non-volatile memory, a set of memory units storing 8 bits or 4 bits is arranged in an array as an access unit. Then, the word line WL of the selecting transistor
₁ , WL ₂ (or word lines WL ₁₁ , WL ₁₂ , W
L ₂₁ , WL ₂₂ ), and a plurality of access unit units (memory blocks) in which the plate line PL _M is shared, data are collectively written, or data is read and rewritten. That is, in the memory block, all the non-volatile memories are collectively brought into operation sequentially, or are collectively brought into non-operation (standby) state.

The value of M is not limited to 4. The value of M is M
It is only necessary to satisfy ≧ 2, and as a practical value of M, for example, a power of 2 (2, 4, 8, 16 ...) Can be cited. Further, the value of N only needs to satisfy N ≧ 2, and as a practical value of N, for example, a power of 2 (2,
4, 8 ...).

(Ninth Embodiment) A ninth embodiment relates to a nonvolatile memory according to the fourth aspect (more specifically, the 4B aspect) of the present invention. FIG. 47 shows a schematic partial cross-sectional view of the nonvolatile memory according to the ninth embodiment taken along a virtual vertical plane parallel to the extending direction of the bit lines. Furthermore,
FIG. 4 is a conceptual circuit diagram of the nonvolatile memory according to the ninth embodiment.
8 and FIG. 49, and a more specific circuit diagram is shown in FIG. Incidentally, in FIGS. 48 and 49, but show two nonvolatile memories M _1, M _2, these nonvolatile memory M _1,
The structure of M ₂ is the same, and the nonvolatile memory M ₁ will be described below.

The nonvolatile memory M ₁ of the ninth embodiment includes switching transistors TR _S11 and TR _S12 for grounding the common first electrode (common nodes CN ₁₁ and CN ₁₂ ).
Instead of the common first electrode (common nodes CN ₁₁ , C
Since it has the same structure as the nonvolatile memory of the eighth embodiment except that it has high resistance elements R ₁₁ and R ₁₂ for grounding N ₁₂ ), detailed description thereof will be omitted. The high resistance elements R ₁₁ and R ₁₂ are composed of a polysilicon layer having a resistance value of 1 × 10 ⁶ Ω (1 MΩ) to 1 × 10 ¹² Ω (1 TΩ). The high resistance elements R ₁₁ and R ₁₂ and the transistor (not shown) provided in the plate line decoder / driver PD for grounding the plate line PL _m
A circuit for short-circuiting the plate line of the book and the N common first electrodes is configured.

The high resistance elements R ₁₁ and R ₁₂ are formed according to [Step-10
0], the MOS transistor may be formed on the semiconductor substrate 10. High resistance element R ₁₁ , R ₁₂
Is connected to the other source / drain region 14B of the selecting transistors TR ₁₁ and TR ₁₂ . Also,
The other ends of the high resistance elements R ₁₁ and R ₁₂ are connected to the ground line 14D.

Since the operation of the non-volatile memory whose circuit diagram is shown in FIGS. 48 and 49 can be made similar to the operation of the non-volatile memory whose circuit diagram is shown in FIG. 44 and FIG.
Detailed description is omitted.

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these. The structure of the nonvolatile memory described in the embodiments of the invention, the materials used, various forming conditions, circuit configurations, driving methods, etc. are merely examples, and can be changed as appropriate. The switching transistor and the high resistance element need not be provided in parallel with the selection transistor. For example, a wiring extending from the common node to the plate line decoder / driver PD may be formed, and a switching transistor or a high resistance element connected to the end of this wiring may be provided in the plate line decoder / driver PD. A wiring extending from the node to the word line decoder / driver WD may be formed, and a switching transistor or a high resistance element connected to the end of the wiring may be provided in the word line decoder / driver WD. Further, the ferroelectric layer is an insulator, but, for example, by ion-implanting a part of the ferroelectric layer to change the crystallinity of this part to make it a high resistance,
A circuit that short-circuits the plate line and the common first electrode may be formed from this part. In this case, the resistance value of the high resistance element is preferably 1 × 10 ⁶ Ω to 1 × 10 ¹² Ω.

Generally, if the total number of signal lines for driving the unit unit is A, the number of word lines is B, and the number of plate lines is C, then A = B + C. Here, when the total number A is constant, B = C may be satisfied in order to maximize the total number of addresses (= B × C) of the unit unit. Therefore, in order to arrange the peripheral circuits most efficiently, the number of word lines B and the number of plate lines C in the unit unit should be equal. Also, the number of word lines in the row address access unit unit matches, for example, the number of stacked stages of memory cells (N), and the number of plate lines matches the number of memory cells (M) forming the memory unit. The greater the number of word lines and the number of plate lines, the higher the degree of integration of the non-volatile memory. The product of the number of word lines and the number of plate lines is the number of accessible addresses. Here, if it is assumed that the accesses are performed collectively and continuously, the value obtained by subtracting “1” from the product is the number of times of disturbance. Therefore, the value of the product of the number of word lines and the number of plate lines is determined by the disturbance resistance of the memory cell, process factors, and the like. Here, the disturb is a direction in which the polarization is inverted with respect to the ferroelectric layer forming the non-selected memory cell,
That is, it refers to a phenomenon in which an electric field is applied in a direction in which stored data is deteriorated or destroyed.

The nonvolatile memory described in the sixth embodiment or the seventh embodiment can be modified into the structure shown in FIG. The circuit diagram is shown in FIG. still,
51 and 52, the switching transistor or the high resistance element is not shown.

This nonvolatile memory has a sense amplifier SA.
N (where N ≧ 2, N = 4 in this example) selection transistors TR ₁₁ , TR ₁₂ and T each composed of a bit line BL ₁ connected to
R ₁₃ and TR ₁₄ and N memory units MU ₁₁ and M
It is composed of U ₁₂ , MU ₁₃ , and MU ₁₄ and a plate line. The first layer memory unit MU ₁₁ has M (however,
M ≧ 2, and in this example, it is composed of M = 8) memory cells MC _11m (m = 1, 2, ..., 8). The second-layer memory unit MU ₁₂ also has M (M = 8) memory cells MC _12m (m = 1, 2 ...
8). Further, the memory unit MU ₁₃ of the third layer also has M (M = 8) memory cells MC _13m.
(M = 1, 2, ..., 8), and the memory unit MU _{14 in} the fourth layer is also M (M = 8) memory cells M.
It is composed of C _14m (m = 1, 2, ..., 8).
The number of plate lines is M (8 in this example) and is represented by PL _m (m = 1, 2, ..., 8). The word line WL _1n connected to the gate electrode of the selection transistor TR _1n is connected to the word line decoder / driver WD. On the other hand, each plate line PL _m is connected to the plate line decoder / driver PD.

Further, the memory unit MU of the first layer₁₁To
Each constituting memory cell MC_11mWith the first electrode 21A
The ferroelectric layer 22A and the second electrode 23, and the second layer
Eye memory unit MU₁₂Memory cells MC configuring
_12mIs the first electrode 21B, the ferroelectric layer 22B and the second
The memory unit MU of the third layer, which includes the electrode 23 ₁₃
Memory cells MC configuring_13mIs the first electrode 31A
And a ferroelectric layer 32A and a second electrode 33,
Layer memory unit MU₁₄Each memory cell M constituting the
C_14mIs the first electrode 31B, the ferroelectric layer 32B, and the second electrode 31B.
Electrode 33. Then, each memory unit MU
₁₁, MU₁₂, MU₁₃, MU₁₄In the memory cell
One electrode 21A, 21B, 31A, 31B is common
It This common first electrode 21A, 21B, 31A, 3
1B is a common node CN for convenience.₁₁, CN₁₂, CN₁₃，
CN₁₄Call.

Here, the first layer memory unit MU ₁₁
Common first electrode 21A (first common node C
N ₁₁ ) is connected to the bit line BL ₁ via the first selection transistor TR ₁₁ . Further, the common first electrode 21B in the memory unit MU ₁₂ of the second layer
The (second common node CN ₁₂ ) is connected to the bit line BL ₁ via the second selection transistor TR ₁₂ . Further, the common first electrode 31A (third common node CN ₁₃ ) in the memory unit MU ₁₃ of the third layer
Is connected to the bit line BL ₁ through the third selection transistor TR ₁₃ . Further, the common first electrode 31B in the fourth layer of the memory unit MU ₁₄ (4th
Common node CN ₁₄ ) is connected to the bit line BL ₁ via the fourth selection transistor TR ₁₄ .

The memory unit MU of the first layer₁₁To
Memory cell MC_11mAnd the memory unit of the second layer
MU₁₂Memory cell MC constituting the_12mIs the second power
Shares pole 23 and shares this mth second
Electrode 23 is plate line PL _mIt is connected to the. Further
Is the memory unit MU of the third layer₁₃The memory that makes up
Cell MC_13mAnd the memory unit MU of the fourth layer₁₄Construct
Memory cell MC_{1 4m}Share the second electrode 33
And the shared m-th second electrode 33 is
Rate line PL_mIt is connected to the. Specifically, this
Play from the extension of the mth second electrode 23
Line PL_mIs shared and this shared m-th second
From the extending portion of the electrode 33 of the plate line PL_mIs configured
Cage, each plate line PL_mAre connected in the area not shown
ing.

In this non-volatile memory, the memory unit
Knit MU₁₁, MU₁₂And memory unit MU₁₃, MU₁₄
Are laminated via an insulating layer (interlayer insulating layer 26).
It Memory unit MU₁₄Is covered with an insulating film 36A
There is. In addition, the memory unit MU₁₁Is the semiconductor substrate 10
Is formed above the insulating layer 16 via the insulating layer 16. Semiconductor substrate
An element isolation region 11 is formed on the plate 10. Also,
Selection transistor TR ₁₁, TR₁₂, TR₁₃, TR
₁₄Is the gate insulating film 12, the gate electrode 13, the source / drain
It is composed of rain regions 14A and 14B. That
The first selection transistor TR₁₁, The second selection
Langista TR₁₂, Third selection transistor TR₁₃,
Fourth selection transistor TR₁₄One source / drain
The in-region 14A is connected through the connection hole (contact hole) 15.
Bit line BL₁It is connected to the. Also, the first choice
Selection transistor TR₁₁Source / drain region of the other
14B is provided in the opening formed in the insulating layer 16.
Via the connection hole 18₁₁Connected to
Has been. Furthermore, the second selection transistor TR₁₂of
The other source / drain region 14B is connected via the connection hole 18.
And the second common node CN₁₂It is connected to the. Also,
Third selection transistor TR₁₃Other source / drain
The in-region 14B includes the connection hole 18, the pad portion 25, and the interlayer insulation.
Connection hole 28 provided in the opening formed in the edge layer 26
Via the third common node CN₁₃It is connected to the. Change
Includes a fourth selection transistor TR₁₄The other source of
The / drain region 14B includes the connection hole 18, the pad portion 25,
The fourth common node CN via the connection hole 28₁₄Connected to
ing.

Further, the first selection transistor TR _{11 is used.}
The other source / drain region 14B is common to one source / drain region of a switching transistor (not shown), and the other source / drain region 14B of the second selecting transistor TR ₁₂ is another switching source (not shown). And the other source / drain region 14B of the third selection transistor TR ₁₃ is also common to one of the source / drain regions of another switching transistor (not shown). Yes, fourth selection transistor TR ₁₄
The other source / drain region 14B is common to one source / drain region of another switching transistor (not shown). Alternatively, the other source / drain region 14B of the first selection transistor TR ₁₁ is
Is connected to one end of a high resistance element (not shown), the other source / drain region 14B of the second selection transistor TR ₁₂ is connected to one end of another high resistance element (not shown), and is a third selection transistor. The other source of TR ₁₃ /
The drain region 14B is connected to one end of another high resistance element (not shown), and the other source / drain region 14B of the fourth selection transistor TR ₁₄ is connected to one end of another high resistance element (not shown). ing. The structure of the non-volatile memory described above can also be applied to the non-volatile memories in the other embodiments of the invention.

The non-volatile memory of the present invention may be of so-called gain cell type. A circuit diagram of an example of such a non-volatile memory is shown in FIG. 53, a schematic layout of various transistors forming the non-volatile memory is shown in FIG. 54, and a schematic partial cross-sectional view of the non-volatile memory is shown. 55 and FIG. 56. Note that in FIG. 54, regions of various transistors are surrounded by dotted lines, active regions and wirings are shown by solid lines, and gate electrodes or word lines are shown by dashed lines.
The schematic partial cross-sectional view of the nonvolatile memory shown in FIG. 55 is a schematic partial cross-sectional view taken along the line AA of FIG. 54, and the schematic partial cross-sectional view of the nonvolatile memory shown in FIG. The partial cross-sectional view is a schematic partial cross-sectional view taken along the line BB of FIG. 54.

A case where the gain cell type is applied to the nonvolatile memory of the first embodiment will be described below. This non-volatile memory includes, for example, a bit line BL, a writing transistor (which is a selection transistor in the non-volatile memory of each embodiment) TR _W , and M (however, M ≧ 2, for example, A memory unit MU composed of M = 8) memory cells MC _M and M plate lines PL _M. Then, each memory cell MC _m has a first electrode 21
It consists DOO ferroelectric layer 22 and a second electrode 23, first electrode 21 of the memory cells MC _M constituting the memory unit MU is common in the memory unit MU, the common first electrode ( The common node CN) is connected to the bit line BL via the writing transistor TR _W, and the second electrode 23 forming each memory cell MC _m is a plate line P.
It is connected to L _m . The memory cell MC _M is an insulating film 26A.
Is covered by. Note that the number (M) of memory cells forming the memory unit MU of the nonvolatile memory is not limited to eight, and in general, M ≧ 2 should be satisfied, and a power of 2 (M = 2, 4, 4). 8 and 16 ...) is preferable.

Further, a signal detection circuit for detecting a potential change of the common first electrode and transmitting the detection result as a current or a voltage to the bit line is provided. In other words, the detection transistor TR _D and the reading transistor TR _R are provided. The signal detection circuit is a detection transistor TR.
_D and a read transistor TR _R. Then, one end of the detection transistor TR _D has a predetermined potential V
_The data stored in each memory cell MC _m is connected to a wiring having _cc (for example, a power supply line formed of an impurity layer) and the other end is connected to a bit line BL via a read transistor TR _R. When read transistor TR
_R is rendered conductive, and the potential of the common first electrode (common node CN) generated based on the data stored in each memory cell MC _m controls the operation of the detection transistor TR _D. In addition, the switching transistor TR
_S is connected to the common node CN, and is turned off when the nonvolatile memory is operating, and is turned on when the nonvolatile memory is not operating (standby).

Specifically, various transistors are MOS
One of the source / drain regions of the writing transistor (selecting transistor) TR _W is connected to the bit line BL through a connection hole (contact hole) 15 formed in the insulating layer 16. , The other source / drain region is connected to a common first electrode (common node CN) via a connection hole 18 provided in an opening formed in the insulating layer 16 and for switching. It is common to one source / drain region of the transistor TR _S. The other source / drain region of the switching transistor TR _S is connected to a ground line (not shown). Further, one source / drain region of the detecting transistor TR _D is connected to a wiring having a predetermined potential V _cc , and the other source / drain region is connected to one source / drain region of the reading transistor TR _R. Has been done. More specifically, the detection transistor T
The other source / drain region of R _D and one source / drain region of the read transistor TR _R occupy one source / drain region. Further, the other source / drain region of the read transistor TR _R is connected to the bit line BL via a connection hole (contact hole) 15, and further, a common first electrode (common node CN or write). The other source / drain region of the use transistor TR _W is connected to the gate electrode of the detection transistor TR _D via the connection hole 18A provided in the opening and the word line WL _D. In addition, the writing transistor TR
The word line connected WL _W to the gate electrode of _W, the word line W connected to the gate electrode of the readout transistor TR _R
The word line WL _S connected to L _R and the gate electrode of the switching transistor TR _S is connected to the word line decoder / driver WD. On the other hand, each plate line PL _m is connected to the plate line decoder / driver PD. Further, the bit line BL is connected to the sense amplifier SA.

For example, the memory cell M of this nonvolatile memory
When reading data from C ₁ , the switching transistor TR _S is turned off and V is applied to the selected plate line PL ₁ .
_{Apply cc} . At this time, if data “1” is stored in the selected memory cell MC ₁ , polarization inversion occurs in the ferroelectric layer, the amount of accumulated charge increases, and the potential of the common node CN rises. On the other hand, if the data “0” is stored in the selected memory cell MC ₁ , polarization inversion does not occur in the ferroelectric layer and the potential of the common node CN hardly rises. That is, since the common node CN is coupled to the plurality of non-selected plate lines PL _j via the ferroelectric layer of the non-selected memory cell, the potential of the common node CN is kept at a level relatively close to 0 volt. Be drunk In this way, the selected memory cell MC ₁
The potential of the common node CN changes depending on the data stored in. Therefore, a sufficient electric field for polarization reversal can be applied to the ferroelectric layer of the selected memory cell. Then, the bit line BL is brought into a floating state and the reading transistor TR _R is turned on.

On the other hand, the selected memory cell MC₁Remembered by
To the common first electrode (common node CN) based on the data
Depending on the generated potential, the detection transistor TR_DThe operation of
Controlled. Specifically, the selected memory cell MC₁Remember
The common first electrode (common node C
If a high potential occurs in N), the detection transistor TR _D
Becomes conductive, and the detection transistor TR_DOne of
The source / drain region has a predetermined potential V_ccTo the wiring that has
Since it is connected, the transition for detection is
Star TR_DAnd read transistor TR_RA bit through
A current flows through the line BL and the potential of the bit line BL rises.
That is, the common first electrode (common node)
The change in the electrical potential of the
The voltage (potential) is transmitted to the power line BL. Where the inspection
Output transistor TR_DThe threshold of V_{t h}, Detection transistor
Star TR_DPotential of the gate electrode (that is, the common node CN
Potential)_gIf so, the potential of the bit line BL is approximately
(V_g-V_th). The detection transistor TR_DTo
If a depletion type NMOSFET is used, the threshold value V
_thTakes a negative value. As a result, the load on the bit line BL
A stable sense signal amount can be secured regardless of the size.
The detection transistor TR_DFrom PMOSFET
It can also be done.

The predetermined potential of the wiring to which one end of the detection transistor is connected is not limited to _Vcc and may be grounded, for example. That is, the predetermined potential of the wiring to which one end of the detection transistor is connected may be 0 volt.
However, in this case, when the potential (V _cc ) appears on the bit line when reading the data in the selected memory cell, the potential of the bit line is set to 0 volt when rewriting, and 0 when reading the data in the selected memory cell. When the volt appears on the bit line, it is necessary to set the potential of the bit line to V _cc when rewriting. To this end, transistors TR _IV-1 , TR _IV-2 , TR as illustrated in FIG.
A kind of switch circuit (inversion circuit) composed of _IV-3 and TR _IV-4 is arranged between the bit lines, and when reading data, the transistors TR _IV-2 and TR _IV-4 are turned on,
When data is rewritten, the transistors TR _IV-1 , T
R _IV-3 may be turned on.

Although the switching transistor TR _S is provided in the example described above, a high resistance element R may be provided instead, as shown in the circuit diagram of FIG. Further, the structure of the gain cell type non-volatile memory described above can also be applied to the non-volatile memories according to the other embodiments of the present invention.

Further, for example, as shown in FIG. 59, as a modification of the nonvolatile memory of the sixth or seventh embodiment, the first electrodes 21 'and 31' are upper electrodes,
The second electrodes 23 'and 33' can also be used as lower electrodes. Such a structure can also be applied to the nonvolatile memory according to the other embodiments of the invention. Incidentally, FIG.
A switching transistor or a high resistance element is not shown in FIG.

[0165]

According to the present invention, a circuit for short-circuiting the plate line and the common first electrode is provided, or a circuit for grounding the common first electrode is provided. When the ferroelectric non-volatile semiconductor memory is inoperative (standby), the common first electrode is not in a floating state, and as a result, the potential fluctuation of the common first electrode can be suppressed. Therefore, even if the polarization attenuation phenomenon called relaxation occurs in the ferroelectric layer, it is possible to reliably prevent the data stored in the memory cell from being destroyed. Even if a switching transistor or a high resistance element is provided, there is almost no area overhead. Furthermore, since the switching transistor can be formed simultaneously with the formation of the selection transistor and the like, there is no increase in the manufacturing process of the ferroelectric non-volatile semiconductor memory, and even in the formation of the high resistance element, The increase in the manufacturing process of the ferroelectric non-volatile semiconductor memory is slight.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a ferroelectric non-volatile semiconductor memory according to a first embodiment of the invention when cut along a virtual vertical plane parallel to a direction in which a bit line extends.

FIG. 2 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory according to the first embodiment of the invention.

FIG. 3 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.

FIG. 4 is a schematic partial cross-sectional view when the ferroelectric non-volatile semiconductor memory according to the second embodiment of the invention is cut along a virtual vertical plane parallel to the extending direction of bit lines.

FIG. 5 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory according to a second embodiment of the invention.

6 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 5;

FIG. 7 is a schematic partial cross-sectional view of the ferroelectric non-volatile semiconductor memory according to the third embodiment of the invention, taken along a virtual vertical plane parallel to the extending direction of bit lines.

FIG. 8 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory according to a third embodiment of the invention.

9 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 8;

FIG. 10 is a schematic partial cross-sectional view of a modification of the ferroelectric non-volatile semiconductor memory according to the third embodiment of the present invention, taken along a virtual vertical plane parallel to the extending direction of bit lines. .

FIG. 11 is a conceptual circuit diagram of a modification of the ferroelectric non-volatile semiconductor memory according to the third embodiment of the invention.

FIG. 12 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 11.

FIG. 13 is a schematic partial cross-sectional view of another modification of the ferroelectric non-volatile semiconductor memory according to the third embodiment of the present invention, taken along a virtual vertical plane parallel to the extending direction of the bit lines. Is.

FIG. 14 is a conceptual circuit diagram of another modification of the ferroelectric non-volatile semiconductor memory according to the third embodiment of the invention.

FIG. 15 is a conceptual circuit diagram of another modification of the ferroelectric non-volatile semiconductor memory according to the third embodiment of the invention.

16 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 14;

FIG. 17 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 15.

FIG. 18 is a schematic partial cross section of yet another modification of the ferroelectric non-volatile semiconductor memory according to the third embodiment of the present invention, taken along a virtual vertical plane parallel to the extending direction of the bit lines. It is a figure.

FIG. 19 is a conceptual circuit diagram of still another modification of the ferroelectric non-volatile semiconductor memory according to the third embodiment of the invention.

FIG. 20 is a conceptual circuit diagram of still another modification of the ferroelectric non-volatile semiconductor memory according to the third embodiment of the invention.

FIG. 21 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 19;

22 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 20.

FIG. 23 is a schematic partial cross-sectional view when the ferroelectric non-volatile semiconductor memory according to the fourth embodiment of the present invention is cut along an imaginary vertical plane parallel to the extending direction of bit lines.

24A and 24B are conceptual circuit diagrams of a ferroelectric non-volatile semiconductor memory according to a fourth embodiment of the invention, respectively.

FIG. 25 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.

FIG. 26 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.

FIG. 27 is a schematic partial cross-sectional view when the ferroelectric non-volatile semiconductor memory according to the fifth embodiment of the present invention is cut along a virtual vertical plane parallel to the extending direction of bit lines.

28A and 28B are conceptual circuit diagrams of a ferroelectric non-volatile semiconductor memory according to a fifth embodiment of the invention, respectively.

FIG. 29 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.

FIG. 30 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 28 (B).

FIG. 31 is a schematic partial cross-sectional view when the ferroelectric non-volatile semiconductor memory according to the sixth embodiment of the present invention is cut along an imaginary vertical plane parallel to the extending direction of bit lines.

FIG. 32 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory according to a sixth embodiment of the invention.

FIG. 33 is a conceptual circuit diagram of a modified example of the ferroelectric non-volatile semiconductor memory according to the sixth embodiment of the invention.

FIG. 34 is a conceptual circuit diagram of another modification of the ferroelectric non-volatile semiconductor memory according to the sixth embodiment of the invention.

FIG. 35 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 32.

FIG. 36 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 34.

FIG. 37 is a schematic partial cross-sectional view of the ferroelectric non-volatile semiconductor memory according to the seventh embodiment of the present invention, taken along a virtual vertical plane parallel to the extending direction of bit lines.

FIG. 38 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory according to a seventh embodiment of the invention.

FIG. 39 is a conceptual circuit diagram of a modified example of the ferroelectric non-volatile semiconductor memory according to the seventh embodiment of the invention.

FIG. 40 is a conceptual circuit diagram of another modification of the ferroelectric non-volatile semiconductor memory according to the seventh embodiment of the invention.

FIG. 41 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 38.

FIG. 42 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 40.

FIG. 43 is a schematic partial cross-sectional view when the ferroelectric non-volatile semiconductor memory according to the eighth embodiment of the invention is cut along an imaginary vertical plane parallel to the extending direction of bit lines.

FIG. 44 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory according to an eighth embodiment of the invention.

FIG. 45 is a conceptual circuit diagram of a modification of the ferroelectric non-volatile semiconductor memory according to the eighth embodiment of the invention.

FIG. 46 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 44 or FIG. 45.

FIG. 47 is a schematic partial cross-sectional view when the ferroelectric non-volatile semiconductor memory according to the ninth embodiment of the present invention is cut along an imaginary vertical plane parallel to the extending direction of bit lines.

FIG. 48 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory according to a ninth embodiment of the invention.

FIG. 49 is a conceptual circuit diagram of a modification of the ferroelectric non-volatile semiconductor memory according to the eighth embodiment of the invention.

FIG. 50 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 48 or FIG. 49.

FIG. 51 is a schematic partial cross-sectional view showing a modified example of the ferroelectric non-volatile semiconductor memory described in the sixth embodiment of the invention or the seventh embodiment of the invention.

52 is a circuit diagram of the ferroelectric non-volatile semiconductor memory shown in FIG. 51.

FIG. 53 is a circuit diagram of a gain cell type ferroelectric non-volatile semiconductor memory.

54 is a layout diagram of the ferroelectric non-volatile semiconductor memory shown in FIG. 53. FIG.

FIG. 55 is a schematic partial cross-sectional view of the ferroelectric non-volatile semiconductor memory shown in FIG. 53.

56 is a schematic partial cross-sectional view of the ferroelectric non-volatile semiconductor memory shown in FIG. 53, as viewed in a cross section different from FIG. 55.

FIG. 57 is a circuit diagram showing a kind of switch circuit arranged between bit lines when a predetermined potential of a wiring connected to one end of a detection transistor is 0 volt.

FIG. 58 is a circuit diagram of a modification of the gain cell type ferroelectric non-volatile semiconductor memory.

FIG. 59 is a schematic partial cross-sectional view of another modification of the ferroelectric non-volatile semiconductor memory according to the fourth embodiment of the invention.

FIG. 60 is a PE (V) hysteresis loop diagram of a ferroelectric substance.

FIG. 61 is a circuit diagram of a ferroelectric non-volatile semiconductor memory disclosed in US Pat. No. 4,873,664.

FIG. 62 is a circuit diagram of a ferroelectric non-volatile semiconductor memory disclosed in Japanese Patent Laid-Open No. 9-121032.

63A and 63B are schematic diagrams of charge distribution due to a polarization attenuation phenomenon, and FIG. 63C is a diagram schematically showing a change in potential of a lower electrode. is there.

[Explanation of symbols]

10 ... Silicon semiconductor substrate, 11 ... Element isolation region, 12 ... Gate insulating film, 13 ... Gate electrode,
14A, 14B, 14C ... Source / drain regions,
14D ... Ground wire, 15 ... Connection hole (contact hole), 16 ... Insulating layer, 17, 27 ... Opening part,
18, 28 ... Connection holes 21, 21A, 21B, 2
1 ', 31, 31A, 31B, 31' ... 1st electrode, 22, 22A, 22B, 32, 32A, 32B ...
.Ferroelectric layer, 23, 23 ', 33, 33' ... second
Electrode, 25 ... Pad portion, 26 ... Insulating layer (interlayer insulating layer), 26A, 36A ... Insulating film, TR ... Selection transistor, TR _S ... Switching transistor, R. ..High resistance elements, WL ... Word lines, B
L ... bit line, PL ... plate line, WD ...
Word line decoder / driver, SA ... Sense amplifier, PD ... Plate line decoder / driver, CN
..Common node, TR _W ... Writing transistor, T
_R R ··· readout transistor, TR _D ··· detection transistor

Claims (16)

[Claims] 1. (A) A bit line, (B) a selection transistor, (C) a memory unit composed of M (where M ≧ 2) memory cells, and (D) M plates. Line, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, and in the memory unit, the first electrode of the memory cell is common and the common first The electrode is connected to the bit line via the selection transistor, and in the memory unit, the m-th electrode (where m = 1, 2 is used).
, M) is a ferroelectric non-volatile semiconductor memory in which the second electrode of the memory cell is connected to the m-th plate line, and the common first electrode is grounded, or , A ferroelectric non-volatile semiconductor memory further comprising a circuit for short-circuiting the M plate lines and the common first electrode. 2. The ferroelectric non-volatile semiconductor memory according to claim 1, wherein the circuit comprises a switching transistor. 3. The ferroelectric non-volatile semiconductor memory according to claim 1, wherein the circuit comprises a high resistance element. 4. The resistance value of the high resistance element is 1 × 10 ⁶ Ω to 1
The ferroelectric non-volatile semiconductor memory according to claim 3, wherein the ferroelectric non-volatile semiconductor memory is × 10 ¹² Ω. 5. (A) a bit line, (B) a selection transistor, and (C) each consisting of M (where M ≧ 2) memory cells, N (where N ≧ 2). ) And (D) M × N plate lines, N memory units are stacked with an insulating layer in between, and each memory cell has a first electrode and a ferroelectric material. A first electrode of the memory cell is common in each memory unit, and the common first electrode is connected to the bit line through the selection transistor, In the memory unit of the layer (n = 1, 2, ..., N), the m-th (however, m = 1, 2 ..., N)
The second electrode of the M) th memory cell is the [(n-1) M +
a ferroelectric non-volatile semiconductor memory connected to the (m) th plate line, for grounding a common first electrode, or for connecting M × N plate lines and a common first electrode. A ferroelectric non-volatile semiconductor memory further comprising a circuit for short-circuiting. 6. The ferroelectric non-volatile semiconductor memory according to claim 5, wherein the circuit comprises a switching transistor. 7. The ferroelectric non-volatile semiconductor memory according to claim 5, wherein the circuit comprises a high resistance element. 8. The resistance value of the high resistance element is 1 × 10 ⁶ Ω to 1
The ferroelectric non-volatile semiconductor memory according to claim 7, wherein the ferroelectric non-volatile semiconductor memory is × 10 ¹² Ω. 9. An (A) bit line, (B) N (where N ≧ 2) selection transistors, and (C) each consisting of M (where M ≧ 2) memory cells. In addition, each memory cell includes N memory units and (D) M plate lines. Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. The first electrode of the cell is common, and the common first electrode in the n-th (where n = 1, 2, ..., N) memory unit is connected via the n-th selection transistor. It is connected to the bit line, and is the m-th (however, in the n-th memory unit
The second electrode of the memory cell of m = 1, 2 ..., M) is
A ferroelectric non-volatile semiconductor memory connected to a common m-th plate line between memory units, for grounding a common first electrode or common to M plate lines A ferroelectric non-volatile semiconductor memory, further comprising a circuit for short-circuiting the first electrode of the. 10. The ferroelectric non-volatile semiconductor memory according to claim 9, wherein the circuit comprises a switching transistor. 11. The ferroelectric non-volatile semiconductor memory according to claim 9, wherein the circuit comprises a high resistance element. 12. The ferroelectric non-volatile semiconductor memory according to claim 11, wherein the resistance value of the high resistance element is 1 × 10 ⁶ Ω to 1 × 10 ¹² Ω. 13. (A) N (where N ≧ 2) bit lines, (B) N selection transistors, and (C) M number of memory cells (where M ≧ 2). And (D) M plate lines, each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. , The first electrode of the memory cell is common, and the common first electrode in the n-th (where n = 1, 2, ..., N) memory unit is the n-th selection transistor. Connected to the n-th bit line via the, and in the n-th memory unit, the m-th (however,
The second electrode of the memory cell of m = 1, 2 ..., M) is
A ferroelectric non-volatile semiconductor memory connected to a common m-th plate line between memory units, for grounding a common first electrode or common to M plate lines A ferroelectric non-volatile semiconductor memory, further comprising a circuit for short-circuiting the first electrode of the. 14. The ferroelectric non-volatile semiconductor memory according to claim 13, wherein the circuit comprises a switching transistor. 15. The ferroelectric non-volatile semiconductor memory according to claim 13, wherein the circuit comprises a high resistance element. 16. The ferroelectric non-volatile semiconductor memory according to claim 15, wherein the resistance value of the high resistance element is 1 × 10 ⁶ Ω to 1 × 10 ¹² Ω.