JP2003174257A - Wiring plate and manufacturing method thereof, semiconductor mounting substrate and manufacturing method thereof, semiconductor package and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring plate excellent in a wiring density, and a semiconductor mounting substrate as well as a semiconductor package which are employing the wiring plate, and the manufacturing method of the wiring plate, the manufacturing method of the semiconductor mounting substrate as well as the manufacturing method of the semiconductor package, which are simplified in a process, low in a cost and high in a connecting reliability. <P>SOLUTION: The wiring plate is provided with an in-layer substrate on which an in-layer wiring is formed, a thin film built-up layer having an adhesive layer and an insulation resin layer at least on one side of the in-layer substrate, and a wiring formed on the insulation resin layer while the wiring and at least the in-layer wiring are connected through via holes. The wiring, formed on the insulation resin layer, is constituted of a spatter metallic layer and a pattern electric plating layer utilizing the spatter metallic layer as a substrate metal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board and a manufacturing method thereof, a semiconductor mounting substrate and a manufacturing method thereof, a semiconductor package and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, electronic devices have become smaller, lighter, and more multifunctional, and with this, the wiring boards have become highly integrated and miniaturized rapidly, and wiring layers have become multilayered and miniaturized. It is progressing. A ceramic substrate has been used as a semiconductor mounting substrate, but in recent years, an organic resin substrate has come to be used because of its price and ease of processing, and many wiring board technologies have been adopted.

In a semiconductor package using such a semiconductor mounting substrate, as the degree of integration of semiconductors increases,
The number of input / output terminals is increasing. Therefore, a semiconductor package having a large number of input / output terminals has been required. Generally, there are two types of I / O terminals, which are arranged in a row around the periphery of the package and an array type in which not only the periphery but also the inside are arranged in multiple rows. The former is QFP (Quad Flat P).
is typical. When the number of terminals is increased, it is necessary to reduce the terminal pitch.
In the area of 5 mm pitch or less, high technology is required for connection with the wiring board. The latter array type is suitable for increasing the number of pins because the terminals can be arranged at a relatively large pitch. Conventionally, the array type has a PGA (P
In Grid Array) is generally used, but the connection with a wiring board is an insertion type and is not suitable for surface mounting. Therefore, surface mountable BGA (Ball Gr)
A package called id Array) has been developed.

On the other hand, along with the miniaturization of electronic equipment, there is an increasing demand for further miniaturization of the package size. To cope with this miniaturization, a so-called chip size package (CS
P; Chip Size Package) has been proposed. This is a package having a connection portion with an external wiring substrate (wiring board) in the mounting area, not in the peripheral portion of the semiconductor chip. As a specific example, a polyimide film with bumps is adhered to the surface of a semiconductor chip, electrical connection is made with the chip and a gold lead wire, and then epoxy resin or the like is potted and sealed (NIKKEI MA
TERIALS & TECHNOLOGY 94.
4, No. 140, p18-19), or metal bumps are formed on the temporary substrate at positions corresponding to the connection portions of the semiconductor chip and the external wiring substrate, the semiconductor chip is face-down bonded, and then transfer molded on the temporary substrate ( Smallest Flip-Chip-Lik
e Package CSP; The Second
VLSI Packaging Workshop
Japan, p. 46-50, 1994) and the like.

What is common to these wiring boards, semiconductor mounting substrates, and semiconductor packages is that there has been an increasing demand for higher density wiring patterns in order to improve the mounting density. In order to satisfy the requirements, thinning of layers, miniaturization of wiring, and reduction of the diameter of interlayer connection holes are performed,
In addition, interstitial via holes (hereinafter referred to as IVH) that connect only conductors between adjacent layers and belly via holes (hereinafter referred to as BVH) have come to be used, and these IVH and BVH have even smaller diameters. It is being converted.

Also in the formation of fine wiring, the wiring which can be formed with a good yield by the subtract method of forming wiring by etching is conductor width / conductor spacing = 50 μm / 50.
It is about μm. Finer conductor width / conductor spacing = 35μ
When the wiring has a thickness of about m / 35 μm, the conductor can be formed to have a uniform thickness by electroplating. Therefore, a relatively thin plating layer is formed on the surface of the base material, and a plating resist is formed on the plating layer to form an electrical conductor. The semi-additive method of forming a conductor to a required thickness by plating and then removing the relatively thin plating by soft etching has begun to be used. When the wiring has a finer conductor width / conductor spacing = 25 μm / less than 25 μm, the roughened shape of the copper foil roughening plating or chemical roughening is 1 to
Since it is about 3 μm, it is necessary to excessively etch it in order to etch the roughened layer, so that the wiring becomes thin and the variation of the wiring width becomes large. Wiring is formed by a semi-additive method in which a plating resist is formed on the conductor, a conductor is formed to a required thickness by electroplating, and then a relatively thin plating is removed by soft etching.

[0007]

By the way, when a wiring having a fine conductor width / conductor spacing = 25 μm / less than 25 μm is formed, the characteristic impedance, which is one of the electrical characteristics, becomes 5
In order to adjust to 0Ω, the insulating resin layer also needs to be uniformly thin. Up to now, the insulating resin layer has been formed by a printing method, a spin coating method, or the like, but it is difficult to control the film thickness of the thin insulating resin layer, and the unevenness of the surface becomes large, making it difficult to form fine wiring. Further, in order to eliminate surface irregularities, a technique used in semiconductors called CMP (Chemical Mechanical Polishing) is used to flatten the surface, but this causes a cost increase.

The present invention provides a wiring board excellent in wiring density, a semiconductor mounting substrate and a semiconductor package using the wiring board, and
An object of the present invention is to provide a method for manufacturing a wiring board, a method for manufacturing a semiconductor mounting substrate, and a method for manufacturing a semiconductor package, which can simplify the process, have low cost, and have high connection reliability.

[0009]

The present invention is characterized by the following. That is, the first feature of the present invention is
An inner layer substrate on which inner layer wiring is formed, an adhesive layer, an insulating resin layer, and a wiring formed on the insulating resin layer on at least one side of the inner layer substrate, and the wiring and at least the inner layer wiring. And a thin film build-up layer connected by via holes, and the wiring formed on the insulating resin layer,
A wiring board comprising a sputtered metal layer and a pattern electroplating layer using the sputtered metal layer as a base metal.

The second feature of the present invention is that a. Forming inner layer wiring on the inner layer substrate; b. A step of forming an adhesive layer on the inner layer substrate, arranging an insulating resin layer having a sputtered metal formed on one side so that the insulating resin layer is in contact with the adhesive, and heating and pressing to laminate the layers; c. Forming a hole for interlayer connection from the sputtered metal layer to the inner layer wiring, d. And a step of forming a conductor circuit of an outer layer by performing a plating for electrically connecting the sputtered metal layer and the inner layer circuit to each other.

A third feature of the present invention is that an inner layer substrate on which inner layer wiring is formed, an adhesive layer, an insulating resin layer, and an insulating resin layer are formed on at least one side of the inner layer substrate. A thin film build-up layer in which the wiring and at least the inner layer wiring are connected by a via hole, the wiring formed on the insulating resin layer is a sputtered metal layer and the sputtered metal layer. Is a pattern electroplating layer using as a base metal, the outermost conductor circuit, which is a wiring formed on the insulating resin layer, is an external connection terminal connected to at least another wiring board, and a semiconductor chip terminal. A semiconductor mounting substrate having an internal connection terminal to be connected.

The fourth feature of the present invention is that a. Forming inner layer wiring on the inner layer substrate; b. A step of forming an adhesive layer on the inner layer substrate, arranging an insulating resin layer having a sputtered metal formed on one side so that the insulating resin layer is in contact with the adhesive, and heating and pressing to laminate the layers; c. Forming a hole for interlayer connection from the sputtered metal layer to the inner layer wiring, d. A step of forming a conductor circuit of an outer layer by performing plating for electrically connecting the sputtered metal layer and the inner layer circuit, and d-2. A method for manufacturing a semiconductor mounting substrate, comprising the step of forming at least an external connection terminal connected to another wiring board and an internal connection terminal connected to a terminal of a semiconductor chip in a conductor circuit of the outermost layer. . In the wiring board and the semiconductor mounting substrate, the thickness of the thin film buildup layer is less than 25 μm, and the thickness of the insulating resin layer is 1 μm.
It is preferable that it is less than 0 μm and the tensile elastic modulus is 5 GPa or more. Further, in the method for manufacturing a wiring board and the method for manufacturing a semiconductor mounting substrate, the holes in step c are opened by laser irradiation, and step d
Then, after forming a plating layer on the surface of the sputtered metal layer, the inner wall of the hole, and the bottom of the hole, and then forming a plating resist on the plating layer, the plating layer is thicker than the plating layer at a portion where the plating resist is not formed. It is preferable to form a plating layer and to form a conductor circuit on the outer layer of the thin film buildup layer by etching, particularly by using an etching solution containing sulfuric acid and hydrogen peroxide as main components.

A fifth feature of the present invention is the semiconductor mounting substrate including any one of the above features including the third feature or the semiconductor mounting substrate including any one of the above features including the fourth feature. It is a semiconductor package characterized by including. The sixth feature of the present invention is that a. On the inner layer substrate,
Forming an inner layer wiring; b. A step of forming an adhesive layer on the inner layer substrate, arranging an insulating resin layer having a sputtered metal formed on one side so that the insulating resin layer is in contact with the adhesive, and heating and pressing to laminate the layers; c. Forming a hole for interlayer connection from the sputtered metal layer to the inner layer wiring, d. A step of forming a conductor circuit of an outer layer by performing plating for electrically connecting the sputtered metal layer and the inner layer circuit, and d-2. A step of forming at least an external connection terminal connected to another wiring board and an internal connection terminal connected to a terminal of the semiconductor chip on the outermost conductor circuit; e. A method of manufacturing a semiconductor package, comprising: mounting a semiconductor chip; and connecting a terminal of the semiconductor chip and an internal connection terminal of a conductor circuit of an outermost layer.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION (Wiring Board) FIG. 1 is a sectional view of an embodiment of the wiring board of the present invention. The wiring board of the present invention is, for example, as shown in FIG. 1, an inner layer substrate 1 on which inner layer wiring 2 is formed.
And an adhesive layer 3, an insulating resin layer 4, and an outer layer wiring 8 formed on the insulating resin layer 4 outside the inner layer substrate 1, and the outer layer wiring 8 and the inner layer wiring 2 are Has a thin film build-up layer connected by a via hole 7, and the outer layer wiring 8 formed on the insulating resin layer 4 is a sputtered metal layer, that is, a thin film copper layer 50, a base metal 51, and the sputtered metal layer. An example of the wiring board is a pattern electroplating layer having a metal layer as a base metal. In FIG. 1, the inner layer substrate 1 on which the inner layer wiring 2 is formed is laminated with an insulating resin layer 4 and an adhesive layer 3. The via hole 7 for interlayer connection connecting the outer layer wiring 8 and at least the inner layer wiring 2 has a layer of thin copper plating 6. Wirings other than the inner layer wiring 2 are called outer layer wirings.

(Thickness of Thin-Film Build-Up Layer) In FIG. 1, the thin-film build-up layer is composed of an adhesive layer 3, an insulating resin layer 4, and a base metal 51 which is a sputtered metal layer on the insulating resin layer. It has a thin film copper layer 50 and an outer layer wiring 8 formed on the thin film copper layer 50, and further, a via hole 7 that connects the outer layer wiring and the inner layer wiring 2 is formed.
The thickness of the thin film buildup layer (hereinafter referred to as the buildup layer) in the present invention means the adhesive layer 3 to the outer layer wiring 8.
Up to 25 μm, preferably 5 μm or more. If the thickness is less than 5 μm, it becomes difficult to embed a wiring conductor or the surface irregularities become large, so that fine wiring cannot be formed. A more preferable thickness range is 15 μm to 10 μm. When the thickness is used within this range, it is possible to control the characteristic impedance, which is an electric characteristic when a fine wiring is formed. When the thickness is 25 μm or more or less than 5 μm, it is difficult to control the characteristic impedance. Base metal 51
, Cr, Ni, Co, Pd, Zr, Ni / Cr,
Metals such as Ni / Cu are preferable, and the thickness is preferably 5 to 50 nm. The thickness of the thin film copper layer 50 on the base metal 51 is 2
It is preferably from 0 to 500 nm.

(Thickness of Insulating Resin Layer) As described in the section of the thickness of the build-up layer, it is preferable to set the thickness of the build-up layer to 5 μm or more and less than 25 μm in consideration of various characteristics from the viewpoint of electrical characteristics. preferable. The thickness of the insulating resin layer 4 is 1
The thickness is preferably less than 0 μm, and more preferably 3 μm or more. A more preferable thickness range is 7μ.
It is preferably m to 4 μm. If the thickness is 10 μm or more, the thickness of the adhesive used for multilayering is 15 μm
When the thickness is less than m, the surface irregularities of the substrate when laminated in multiple layers become large and it becomes difficult to form fine wiring. If the thickness of the insulating resin layer is less than 3 μm, the handleability is poor and wrinkles are generated, which leads to a decrease in substrate yield and wiring formability.

(Elastic Modulus of Insulating Resin Layer) The elastic modulus of the insulating resin layer 4 is preferably 5 GPa or more and 15 GPa or less. A more preferable range is 8 GPa or more and 12 GPa or less. If the elastic modulus is less than 5 GPa, the film has poor handleability and wrinkles tend to occur, resulting in 15 GPa.
If it exceeds, the film becomes hard and cracks may occur during handling.

(Insulating Resin Layer) As the insulating resin layer 4, a thermosetting resin or a thermoplastic resin can be used. Examples of the thermosetting resin are phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, Saturated polyester resin, diallyl phthalate resin, epoxy resin, silicone resin, resin synthesized from cyclopentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, A resin containing triallyltrimetallate, a furan resin, a ketone resin, a xylene resin, a thermosetting resin containing a condensed polycyclic aromatic compound, or the like can be used. Among them, a phenol resin, in particular, a resol-type phenol resin,
As the solvent, an organic solvent such as butyl carbitol, ethyl lactate, ethyl carbitol, and butyl cellosolve acetate can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, and aramid resin.

(Adhesive Layer) As the adhesive layer 3, it is preferable to use a thermosetting resin, and it is preferable to use an epoxy resin, or a polyamideimide resin and an epoxy resin, among them. May be any as long as it has an epoxy group in the molecule, and is bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, alicyclic epoxy resin, aliphatic chain epoxy resin. , Phenol novolac type epoxy resin, cresol novolak type epoxy resin, bisphenol A novolac type epoxy resin, biphenol diglycidyl ether compound, naphthalene diol diglycidyl ether compound, phenol diglycidyl ether compound, alcohol diglycic acid Ethers halides, and alkyl substituted derivatives thereof, halides, hydrogenated product and the like. Two or more of these may be used in combination, and components other than the epoxy resin may be contained as impurities.

The curing agent for the epoxy resin used in the present invention can be used without limitation as long as it cures the epoxy resin, and examples thereof include polyfunctional phenols, amines, imidazole compounds, acid anhydrides and organic compounds. Examples thereof include phosphorus compounds and their halides.

Examples of polyfunctional phenols are monocyclic bifunctional phenols such as hydroquinone, resorcinol and catechol, polycyclic bifunctional phenols such as bisphenol A, bisphenol F, naphthalenediols, biphenols, and halides thereof. Examples thereof include alkyl group-substituted compounds, and further examples include novolac and resol which are polycondensates of these phenols and aldehydes.

Examples of amines include aliphatic or aromatic primary amines, secondary amines, tertiary amines, quaternary ammonium salts and aliphatic cyclic amines, guanidines, urea derivatives and the like. Can be mentioned.

Examples of these compounds include N, N-benzyldimethylamine and 2- (dimethylaminomethyl).
Phenol, 2,4,6-tris (dimethylaminomethyl) phenol, tetramethylguanidine, triethanolamine, N, N'-dimethylpiperazine, 1,4-
Diazabicyclo [2,2,2] octane, 1,8-diazabicyclo [5,4,0] -7-undecene, 1,5-
Diazabicyclo [4,4,0] -5-nonene, hexamethylenetetramine, pyridine, picoline, piperidine,
Pyrrolidine, dimethylcyclohexylamine, dimethylhexylamine, cyclohexylamine, diisobutylamine, di-n-butylamine, diphenylamine, N
-Methylaniline, tri-n-propylamine, tri-
n-octylamine, tri-n-butylamine, triphenylamine, tetramethylammonium chloride,
Examples thereof include tetramethylammonium bromide, tetramethylammonium iodide, triethylenetetramine, diaminodiphenylmethane, diaminodiphenyl ether, dicyandiamide, tolbiguanide, guanylurea and dimethylurea.

Examples of the imidazole compound are imidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-methylimidazole, 2-phenylimidazole, 2-undecylimidazole, 1-
Benzyl-2-methylimidazole, 2-heptadecylimidazole, 4,5-diphenylimidazole, 2-
Methyl imidazoline, 2-phenyl imidazoline, 2-
Undecyl imidazoline, 2-heptadecyl imidazoline, 2-isopropyl imidazole, 2,4-dimethyl imidazole, 2-phenyl-4-methyl imidazole, 2-ethyl imidazoline, 2-phenyl-4-methyl imidazoline, benz imidazole, 1- Examples thereof include cyanoethylimidazole.

Examples of acid anhydrides include phthalic anhydride, hexahydrophthalic anhydride, pyromellitic dianhydride, benzophenonetetracarboxylic dianhydride and the like.

As the organic phosphorus compound, any phosphorus compound having an organic group can be used without particular limitation.
Hexamethylphosphoric triamide, tri (dichloropropyl) phosphate, tri (chloropropyl) phosphate, triphenyl phosphite, trimethyl phosphate, phenylphosphonic acid, triphenylphosphine, tri-n-butylphosphine, Examples thereof include diphenylphosphine.

These curing agents may be used alone or in combination of two or more. The compounding amount of these epoxy resin curing agents is not particularly limited as long as the curing reaction of the epoxy group can be progressed, but it is preferably 0.01 mole per 1 mole of the epoxy group.
To 5.0 equivalents, particularly preferably 0.8 to 1.2
Use within the equivalent range.

If necessary, a curing accelerator may be added to the thermosetting epoxy resin composition of the present invention. Typical curing accelerators include, but are not limited to, tertiary amines, imidazoles, quaternary ammonium salts and the like.

(Polyamideimide resin) Further, it is preferable to use a silicone-modified polyamideimide resin as the polyamideimide resin, and this silicone-modified polyamideimide is a polymer having a siloxane bond, an imide bond and an imide bond. There are the following three manufacturing methods. (1) Method of reacting diimidedicarboxylic acid (1-1) containing diimidedicarboxylic acid having siloxane bond with diisocyanate compound (1-2), (2) Diamine compound containing diamine having siloxane bond (2-2) And tricarboxylic acid chloride (2-
It can be produced by a method of reacting 3), a method of reacting a diisocyanate compound (3-1) containing a diisocyanate having a siloxane bond with a tricarboxylic acid anhydride (3-2), or the like.

The silicone-modified polyamideimide obtained by the above method (1) will be described in detail below.
1) Examples of the diimidedicarboxylic acid containing the diimidedicarboxylic acid having a siloxane bond include compounds represented by the following general formula (I).

[Chemical 1]

Further, as an example of the diimidedicarboxylic acid having a siloxane bond, in the general formula (I), R1 is 2
There are some valent aliphatic groups (which may contain oxygen). Examples of the divalent aliphatic group include an alkylene group such as a propylene group, a hexamethylene group, an octamethylene group, a decamethylene group, and an octadecamethylene group, and a group in which oxygen is bound to both ends of the alkylene group.

Among the diimidedicarboxylic acids other than the diimidedicarboxylic acid having a siloxane bond, as an example of the aromatic diimidedicarboxylic acid in which the divalent residue connecting the imide groups is an aromatic diimidedicarboxylic acid, a compound represented by the following general formula (II) is used. Can be mentioned.

[Chemical 2] Examples of the divalent organic group include an alkylene group such as a propylene group, a phenylene group, and an alkyl group-substituted phenylene group.

As the (1-2) diisocyanate compound, as the aromatic diisocyanate compound, compounds represented by the following general formula (III) can be given.

[Chemical 3] Examples of R ₉ include an aliphatic diisocyanate compound or an alicyclic diisocyanate compound having a divalent aliphatic group such as an alkylene group or a divalent alicyclic group such as a cycloalkylene group.

The diimidedicarboxylic acid having a siloxane bond and the other diimidedicarboxylic acid can be obtained by reacting a diamine compound having a siloxane bond and a diamine (1-1a) other than this with trimellitic anhydride. . The diimidedicarboxylic acid having a siloxane bond and the other diimidedicarboxylic acids are preferably used as a mixture. Diamine compound having siloxane bond and other diamine (1
It is particularly preferable to use a diimidedicarboxylic acid mixture obtained by reacting the mixture of -1a) with trimellitic anhydride.

As the diamine other than the diamine compound having a siloxane bond, an aromatic diamine is preferable, and a diamine having three or more aromatic rings is particularly preferable. It is preferable to use aromatic diamine in an amount of 50 to 100 mol% among diamines other than the diamine compound having a siloxane bond.

The diamine compounds other than the (A) siloxane bond-containing diamine compound and the (B) siloxane bond-containing diamine compound have (A) / (B) of 99.9 /
It is preferable to use it so as to have a molar ratio of 0.1 to 0.1 / 99.9). In addition, (A) a diamine other than a diamine compound having a siloxane bond, and (B) a diamine compound having a siloxane bond and trimellitic anhydride, 2 parts of trimellitic anhydride per 1 mol of (A) + (B) in total. It is preferable to react at a ratio of 0.05 to 2.20.

As the (1-2) diisocyanate compound, an aromatic diisocyanate compound is preferable, and it is preferable to use 50 to 100 mol% of the aromatic diisocyanate compound in the diisocyanate compound. It is preferable that the whole diimidedicarboxylic acid and the diisocyanate compound are reacted so that the amount of the former is 1.05 to 1.50 mol per mol of the former.

The diamine compound and trimellitic anhydride are reacted at 50 to 90 ° C. in the presence of an aprotic polar solvent, and an aromatic hydrocarbon which can be azeotroped with water is added to the aprotic polar solvent of 0%. 1 to 0.5 mass ratio, 1
The reaction is performed at 20 to 180 ° C. to produce a mixture containing imidodicarboxylic acid and siloxanediimidedicarboxylic acid,
It is preferable to react this with a diisocyanate compound. After producing the diimidedicarboxylic acid, it is preferable to remove the aromatic hydrocarbons from the solution.

When the reaction temperature of the imidodicarboxylic acid and the diisocyanate compound is low, the reaction time becomes long, and when it is too high, the isocyanates react with each other. Therefore, in order to prevent them, it is preferable to carry out the reaction at 100 to 200 ° C. .

Examples of aromatic diamines include phenylenediamine, bis (4-aminophenyl) methane, 2,2-bis (4-aminophenyl) propane, bis (4-aminophenyl) carbonyl and bis (4-aminophenyl). There are sulfone, bis (4-aminophenyl) ether, and the like, and particularly, as a diamine having three or more aromatic rings, 2,2-bis [4- (4-aminophenoxy) phenyl] propane (hereinafter referred to as BAPP and Abbreviated), screw [4-
(3-aminophenoxy) phenyl] sulfone, bis [4- (4-aminophenoxy) phenyl] sulfone,
2,2-bis [4- (4-aminophenoxy) phenyl] hexafluoropropane, bis [4- (4-aminophenoxy) phenyl] methane, 4,4′-bis (4-
Aminophenoxy) biphenyl, bis [4- (4-aminophenoxy) phenyl] ether, bis [4- (4-
Aminophenoxy) phenyl] ketone, 1,3-bis (4-aminophenoxy) benzene and the like.

Examples of the aliphatic diamine include hexamethylene diamine, octamethylene diamine, decamethylene diamine, octadecamethylene diamine, terminal aminated propylene glycol and the like. The alicyclic diamine includes 1,4-diaminocyclohexane and the like.

As the diamine compound having a siloxane bond (hereinafter referred to as siloxane diamine), a compound represented by the following general formula (IV) is used.

[Chemical 4] Examples of such a siloxane diamine include those represented by the following general formula (V). Among these, amino-modified reactive silicone oil X-22-161AS (amine equivalent 45
0), X-22-161A (amine equivalent 840), X-
22-161B (amine equivalent weight 1500) (all trade names manufactured by Shin-Etsu Chemical Co., Ltd.), BY16-853 (amine equivalent weight 650), BY16-853B (amine equivalent weight 220)
0) (these are product names manufactured by Toray Dow Corning Silicone Co., Ltd.) and the like are commercially available products.

[Chemical 5]

Specific examples of the aromatic diisocyanate include 4,4'-diphenylmethane diisocyanate (hereinafter abbreviated as MDI), 2,4-tolylene diisocyanate, 2,6-tolylene diisocyanate and naphthalene-.
Examples include 1,5-diisocyanate and 2,4-tolylene dimer. In particular, MDI is preferable because the isocyanate groups are separated from each other in the molecular structure, the concentration of the amide group and the imide group in the molecule of the polyamideimide is relatively low, and the solubility is improved.

Examples of the aliphatic or alicyclic diisocyanate include hexamethylene diisocyanate, isophorone diisocyanate and methylenebis (cyclohexyl diisocyanate).

Examples of the aprotic polar solvent include dimethylacetamide, dimethylformamide, dimethylsulfoxide, N-methyl-2-pyrrolidone, 4-butyrolactone, sulfolane and cyclohexanone. Since the imidization reaction requires a high temperature, N-methyl-2-methylpyrrolidone (hereinafter abbreviated as NMP) has a high boiling point.
Are particularly preferable. The amount of water contained in these mixed solvents depends on trimellitic acid generated by hydration of TMA,
Since the reaction does not proceed sufficiently and causes a decrease in the molecular weight of the polymer, it is preferably controlled at 0.2% by mass or less. In addition, the aprotic polar solvent is not particularly limited, but if the mass ratio of the diamine having three or more aromatic rings, the siloxane diamine and trimellitic anhydride is large, the solubility of trimellitic anhydride decreases. However, it is not possible to carry out a sufficient reaction, and if it is low, it is disadvantageous as an industrial production method, so that it is preferably in the range of 10% by mass to 70% by mass.

Examples of aromatic hydrocarbons that can be azeotroped with water include aromatic hydrocarbons such as benzene, xylene, ethylbenzene, and toluene. Particularly, toluene having a relatively low boiling point and less harmful to the working environment is preferable. The amount used is 0.1 to 0.5 mass ratio (10 to 5) of the aprotic polar solvent.
0 mass%) is preferable.

Next, the silicone-modified polyamideimide obtained by the method (2) will be explained.
As the diamine compound (2-2) containing a diamine having a siloxane bond, a diamine having a siloxane bond,
There is a compound represented by the above general formula (V). As the other diamine, those mentioned above can be used. Tricarboxylic acid chloride (2-3) includes trimellitic acid chloride and the like, which can be produced by a well-known acid chloride method.

Next, the silicone-modified polyamideimide obtained by the method (3) will be explained.
(3-1) As a diisocyanate compound containing a diisocyanate having a siloxane bond, a diisocyanate compound having a siloxane bond, a diisocyanate compound corresponding to the siloxane diamine represented by the general formula (IV), and other diisocyanate compounds described above are used. Can be used. Tricarboxylic acid anhydride (3-2) includes trimellitic anhydride and the like, which can be produced by the reaction of a well-known diamine compound and a diisocyanate compound.

The amount of the silicone-modified polyamide-imide resin mixed with the epoxy resin is 1 to 150 parts by weight of the epoxy resin with respect to 100 parts by weight of the silicone-modified polyamide-imide resin.
It is preferably in the range of parts by weight, and the epoxy resin is 1
If it is less than 1 part by weight, the solvent resistance is lowered,
When it exceeds the weight part, Tg is lowered due to unreacted thermosetting resin, heat resistance becomes insufficient, and flexibility is lowered.

(Method for manufacturing wiring board) (a) to FIG.
(G) is sectional drawing of each process which shows one Embodiment of the manufacturing method of the above-mentioned wiring board of this invention. The wiring board can be manufactured as follows.

(Step a) Step a is a step of producing the inner layer substrate 1 on which the inner layer wiring 2 is formed as shown in FIG. 2A. The inner layer substrate 1 to be used is glass cloth impregnated with epoxy resin. The FR-4 substrate, the BT substrate impregnated with the bismaleimide-triazine resin, and the polyimide film substrate using a polyimide film as a base material can be used. In addition, for circuit formation, the subtract method, the semi-additive method, which are generally used,
A full additive method or the like can be used.

(Step b) In step b, as shown in FIG. 2B, first, the B-stage adhesive layer 3 is formed on the inner layer substrate 1 on which the inner layer wiring 2 is formed in the step (a). Then, the base metal 51 and the thin film copper layer 5 are formed by sputtering in advance.
0 is a step of arranging the insulating resin layer 4 formed on one side so that the insulating resin layer 4 is in contact with the adhesive layer 3, and heating and pressing to laminate. The sputtering device used for forming the thin film copper layer 50 on the insulating resin layer 4 may be a two-pole sputter, a three-pole sputter, a four-pole sputter, a magnetron sputter, a mirrortron sputter, or the like. The target used for sputtering is C in order to ensure close contact.
r, Ni, Co, Pd, Zr, Ni / Cr, Ni / Cu
It is preferable to sputter 5 to 50 nm by using a metal such as the above as the base metal 51. Then, sputtering is performed using copper as a target to form the thin film copper layer 50. The thickness of the thin film copper layer 50 is preferably 200 to 500 nm. In the laminating step, heating and pressurization can be carried out by a general press such as roll laminating or batch type flat laminating to integrally laminate the layers.

(Step c) Step c is a step of forming a hole for interlayer connection, that is, a via hole 7 reaching the inner layer wiring 2 from above the thin film copper layer 50 as shown in FIG. 2C.
A general NC drill machine and a laser drilling device can be used for drilling, and it is preferable to drill by laser irradiation. The type of laser used in the laser drilling machine may be a CO ₂ laser, a YAG laser, an excimer laser, or the like, but the CO ₂ laser is preferable in terms of productivity and hole quality. In order to perform drilling by using a laser, a method of etching and removing the metal in a portion to be a via hole of the thin film copper layer 50 in advance, and a method of directly removing the thin film copper layer 50
There is a method of irradiating a laser from above. Drilling conditions are
It is adjusted according to the thickness of the thin film copper layer 50, the type of adhesive, and the thickness of the adhesive layer 3. When the number of shots (pulses) is less than 1 shot, no holes are made, and when the number of shots exceeds 20,
Waveform duty ratio of 1 shot pulse is 1/100
Even if it is close to 0, the hole diameter becomes large and it may not be practical, but the number that allows the adhesive in the hole to evaporate up to the point where it reaches the inner layer circuit may be experimentally obtained.

After the via hole 7 is formed in this way, a desmear process is performed to remove the adhesive residue of the adhesive layer 3 in the via hole. For this desmear treatment, a general acidic oxidizing roughening liquid or an alkaline oxidizing roughening liquid can be used. For example, a chromium / sulfuric acid roughening solution may be used as the acidic oxidizing roughening solution, and a potassium permanganate roughening solution may be used as the alkaline oxidizing roughening solution. After roughening the adhesive with an oxidizing roughening liquid,
Although it is necessary to chemically neutralize the oxidizing roughening liquid on the surface of the insulating resin layer 4, a general method can also be adopted. For example, when using a chromium / sulfuric acid roughening solution,
Treatment with sodium bisulfite 10 g / l for 5 minutes at room temperature, and when using potassium permanganate roughening solution, dipping in an aqueous solution of sulfuric acid 150 ml / l and hydrogen peroxide water 15 ml / l for 5 minutes at room temperature. To complete the neutralization.

(Step d) Step d is as shown in FIGS.
In the step of forming the outer layer wiring 8 by plating in order to electrically connect the thin film copper layer 50 and the inner layer wiring 2 as shown in FIG. 2, for example, the thin film copper layer 50 and the inner layer wiring 2 are electrically connected. A layer of patterned electroplating 11 is obtained. To form the outer layer wiring 8, it is preferable to include two steps,
In the first step, a catalyst for forming a copper foil layer, which is a thin copper plating 6 serving as a base for forming a circuit conductor, by electroless plating is applied. This plating catalyst uses the same technique as the through-hole plating of a normal wiring board. That is, it is possible to use a substance which becomes a nucleus of plating such as a tin colloidal palladium catalyst or an alkali ion catalyst.

As a next step, the substrate having the catalyst attached to the resin layer is contacted with an electroless copper plating solution containing an ionized plating metal, a complexing agent for the plating metal, and a reducing agent for the plating metal. Then, a layer of thin copper plating 6 is deposited on the entire substrate (see FIG. 2D). The plating thickness is preferably 0.3 to 1.0 μm, and if it is less than 0.3 μm, a uniform plating film may not be obtained, and subsequently electroplating causes variation in film thickness. In addition, 1.0 μm
If it exceeds, swelling occurs in the electroless plating film of the thin copper plating 6, and a good circuit cannot be formed.

Further, a plating layer is formed on the surface of the sputtered metal layer, the inner wall of the hole and the bottom of the hole, and then a plating resist is formed on the plating layer, and then the plating is applied to a portion where the plating resist is not formed. A plating layer thicker than the layer is formed. For example, on the thin copper plating 6 layer,
After the plating resist 10 is formed, a layer of the pattern electroplating 11 is formed by electroplating at a portion where the plating resist is not formed (see FIG. 2E). At this time, the plating resist 10 may be in the form of a film or a liquid, and a negative type or a positive type may be used. In particular, when forming a resist pattern of less than 20 μm, it is preferable to use a liquid positive type from the viewpoint of wiring formability and resist adhesion. In electroplating, it is preferable to perform 3 to 10 μm plating on the entire substrate by using a general electrocopper plating technique. The most suitable electroplating solution is copper sulfate plating, which is easy to manage and efficient. This pattern electroplating 1
When the thickness of the electrolytic plating of No. 1 is less than 3 μm, there is a problem that the thermal cycle characteristics of the interlayer connection part deteriorates.
If it exceeds 0 μm, the characteristic impedance cannot be matched, and the electric signal noise increases, which is not preferable.

Next, the plating resist 10 is peeled off (see FIG. 2).
(See (f)). As a stripping solution for the negative type plating resist, a general sodium hydroxide aqueous solution or an amine stripping solution can be used, and an amine series having excellent strippability is preferable. Further, in a positive type liquid resist, it is possible to dissolve and remove it by using an organic solvent, so that peeling residue does not occur, which is preferable. After that, the thin copper plating 6, the thin film copper layer 50 and the base metal 51 are removed to form the outer layer wiring 8 (FIG. 2).
(See (g)). This removal is preferably by etching. Thin copper plating 6, thin film copper layer 50 and base metal 5
Any solution that can etch copper and a base metal can be used as the solution for etching No. 1, but an etching solution containing sulfuric acid and hydrogen peroxide as main components, such as a sulfuric acid / hydrogen peroxide-based etching solution. It is preferable because the etching rate is slow. Furthermore, after this, a solder resist that insulates and coats the outermost wiring of the outer layer wiring 8 can be provided, as in the case of a normal wiring board.

(Multilayering) When the required wiring density cannot be obtained, steps b to d may be repeated to form a multilayer. The outermost layer refers to a wiring or conductor circuit layer formed on the outermost side at the time of completion. When the buildup layer is one layer, the outer layer wiring is the outermost wiring.

(Semiconductor Mounting Substrate) FIG. 3 is a sectional view showing an embodiment of the semiconductor mounting substrate of the present invention. The semiconductor mounting substrate of the present invention, the conductor circuit which is the outermost wiring of the wiring board as described above, at least the external connection terminal to connect to another wiring board and the internal connection terminal to connect to the terminal of the semiconductor chip. I have. This method for manufacturing a semiconductor mounting substrate is the same as the method for manufacturing a wiring board as described above. A step of forming a conductor circuit of an outer layer by performing plating for electrically connecting the sputtered metal layer and the inner layer circuit, and d-2. It is characterized by including a step of forming at least an external connection terminal connected to another wiring board and an internal connection terminal connected to a terminal of the semiconductor chip in the outermost conductor circuit. For example, as shown in FIG. 3, the outermost wiring or via hole 7 of the wiring board produced above is insulation-coated with a solder resist 71, and at least an external connection pad 82 and a semiconductor chip connected to another wiring board, as shown in FIG. By forming the internal connection pads 83 connected to the terminals of, the semiconductor mounting substrate is obtained. The external connection pad 82 can be connected to, for example, a connector, a passive component (resistor, capacitor), or the like in addition to another wiring board. In this external connection pad 82,
As shown in FIG. 5, which will be described later, solder balls 86 may be formed to serve as external connection terminals.

(Semiconductor Package) The semiconductor package of the present invention includes the above-mentioned semiconductor mounting substrate of the present invention, and the semiconductor package manufacturing method of the present invention is the above-mentioned semiconductor mounting substrate of the present invention. And e.
The method is characterized by including a step of mounting a semiconductor chip and connecting a terminal of the semiconductor chip and an internal connection terminal of a conductor circuit of the outermost layer. FIG. 4 is a sectional view showing an embodiment of the semiconductor package of the present invention, and FIG. 5 is a sectional view showing another embodiment. A semiconductor chip 90 is further mounted on the semiconductor mounting substrate as described above, and the semiconductor chip 90 is
By electrically connecting the internal connection pad 83 and the internal connection pad 83 with a bonding wire 84, a semiconductor package as shown in FIG. 4 can be obtained. Further, when the semiconductor chip 90 and the internal connection pad 83 are electrically connected by flip-chip connection using the bump 85, the structure shown in FIG.
A semiconductor package as shown in FIG. Further, in each of these semiconductor packages, it is preferable to seal the semiconductor chip 90 with a sealing resin 91 as shown in the drawing. In addition, the semiconductor package is preferably obtained by repeating the above steps b to d to form a multilayer.

[0062]

[Example] (Example 1) Step a: 12 μ of surface of double-sided copper-clad laminate E-679F
An etching resist was formed on a portion of the copper foil to be a circuit, and was then etched using a ferric chloride etching solution to produce an inner layer substrate 1 having inner layer wirings 2.

Step b: In order to form the first buildup layer, the sputtered film thickness of the underlying copper layer and the thin film copper layer is 0.25 μm.
m, a copper sputtered aramid film having a film thickness of 4.4 μm (insulating resin layer 4 having a sputtered metal layer), Miktron (trade name, manufactured by Toray Industries, Inc.), and a silicone-modified polyamide-imide film having a thickness of 15 μm (adhesive layer 3 ),
Arranged so that the sputtered surface is on the outside, the silicone-modified polyamide-imide film is arranged between the inner layer substrate 1 and the insulating resin layer and overlapped, and 200 ° C., 1 hour, 2.0M
It was heated and pressed under the condition of Pa to be laminated and integrated.

Step c: Next, in order to form a via hole, a laser beam machine ML605LDX (trade name, manufactured by Mitsubishi Electric Corporation) is used, and frequency is 5 kHz, 50 shots, mask diameter is 0.4 mm, pulse energy is 11 μJ /
IVH having a diameter of 50 μm was formed under the condition of cm ² from above the thin film copper layer 50 to reach the inner wiring 2.

Step d: Next, 7
After removing the smear by immersing at 0 ° C for 10 minutes,
In order to form the outer layer wiring, first, the electroless copper plating catalyst HS-202B (trade name, manufactured by Hitachi Chemical Co., Ltd.)
It was immersed in the solution at room temperature for 15 minutes to apply the plating catalyst. Electroless copper plating CUST-2 on the substrate with plating catalyst
01 (manufactured by Hitachi Chemical Co., Ltd., trade name) at room temperature for 15
It was dipped for 3 minutes to form an underlying thin copper plating layer 6 having a thickness of 0.3 μm. Next, PMER P-LA900PM
(Tokyo Ohka Kogyo Co., Ltd., trade name) was used to form a plating resist layer 10 having a film thickness of 20 μm by a spin coating method. Exposure under the condition of 1000 mJ / cm ² and PMER
Immerse using developer P-7G for 6 minutes at 23 ° C and shake L
A resist pattern of / S = 10 μm / 10 μm was formed. After that, the patterned copper plating layer 11 was formed to about 7 μm using a copper sulfate plating solution. Then, the plating resist was removed by immersion for 1 minute at room temperature using methyl ethyl ketone. Furthermore, for quick etching of copper sputtered film, 5 of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Inc.)
The base metal 51, the copper sputtered film of the thin film copper layer 50, and the thin copper plating layer 6 were removed by etching using a double dilution solution by immersing and shaking at 30 ° C. for 30 seconds to form wiring.

Multi-layering process: After that, the processes b to d are repeated twice to form two build-up layers and 40 m.
A BGA substrate having a size of m × 40 mm was manufactured.

(Comparative Example 1) In step b, a liquid bisphenol A type epoxy resin having a thickness of 2 is used as an insulating resin layer.
A BGA substrate was manufactured in the same manner as in Example 1 except that the inner layer substrate was directly printed with a thickness of 0 μm, the insulating resin was heated and cured, and then the thin film copper layer was formed by sputtering.

(Comparative Example 2) In step b, a liquid polyimide resin as an insulating resin layer was directly applied to the inner layer substrate by spin coating to a thickness of 15 μm, the insulating resin was heat-cured, and then a thin film copper layer was formed by sputtering. A BGA substrate was prepared in the same manner as in Example 1 except for the above.

(Test) Gas phase thermal shock test: B prepared in Example 1 and Comparative Examples 1 and 2
The GA board is mounted on the mother board, and the thermal shock tester Therma Shock Chamber TSR-103 (TABAI,
30 minutes at -65 ° C and 30 minutes at 125 ° C
The change in connection resistance was measured under the condition of 1 minute and 1 cycle. The connection resistance was measured using a multimeter 3457A manufactured by Hewlett Packard. Flatness: Mitutoyo Surface Roughness Meter SV-2000
Was measured using. Characteristic impedance: Hewlett-Packard digital oscilloscope 54121T (Time Domain Re
The characteristic impedance was measured by using flectmetry). The results of these measurements are shown in Table 1.

[0070]

[Table 1]

[0071] Gas-phase thermal shock test: ○; 1000 cycles or more, conductivity change less than 10%                       X: Less than 1000 cycles Conduction resistance change rate 10% or more Flatness: Good; surface irregularities less than 2 μm                       ×: Surface unevenness of 2 μm or more   Wiring formability: Good; conductor width / conductor spacing (L / S) = 10 μm / 10 μm Can be formed                       X: L / S = 10 μm / 10 μm cannot be formed   Characteristic impedance: ○; Impedance accuracy less than ± 5%                       ×: Impedance accuracy ± 5% or more

[0072]

As described above, according to the present invention, there are provided a wiring board, a semiconductor mounting substrate, a semiconductor package and a manufacturing method thereof which are excellent in flatness of the substrate, miniaturization of wiring, electrical characteristics and productivity. can do.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an embodiment of a wiring board of the present invention.

2A to 2G are cross-sectional views for explaining each step of one embodiment of the method for manufacturing a wiring board of the present invention.

FIG. 3 is a sectional view showing an embodiment of a semiconductor mounting substrate of the present invention.

FIG. 4 is a sectional view showing an embodiment of a semiconductor package of the present invention.

FIG. 5 is a sectional view showing another embodiment of the semiconductor package of the present invention.

[Explanation of symbols]

1. Inner layer substrate 2. Inner layer wiring 3. Adhesive layer 4. Insulating resin layer 50. Thin film copper layer 51. Base metal 6. Thin copper plating 7. Via hole 8. Outer layer wiring 82. External connection pad 83. Internal connection pad 84. Bonding wire 85. Bump 86. Solder ball 90. Semiconductor chip 91. Sealing resin 10. Plating resist 11. Pattern electroplating

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H05K 3/00 H05K 3/00 N 3/42 620 3/42 620B (72) Inventor Kenji Takai Shimodate, Ibaraki Prefecture City Oita 1500 Ogawa Hitachi Chemical Co., Ltd. Research Institute (72) Inventor Toyoki Ito Shimodate, Ibaraki Prefecture Ogata 1500 Ogawa Hitachi Chemical Research Institute (72) Inventor Shigeharu Ariya Shimodate, Ibaraki Ogawa Ogawa 1500, Hitachi Chemical Co., Ltd., Research Institute (72) Inventor Akashi Nakaso 1500 Ogawa, Shimodate City, Ibaraki Prefecture F-Term (Reference), Hitachi Chemical Co., Ltd., Research Institute 5E317 AA24 BB01 BB12 CC31 CC44 CC51 CD15 CD18 CD25 CD25 CD32 GG11 GG14 5E346 AA05 AA06 AA12 AA15 AA16 AA32 AA35 AA38 AA43 BB01 BB15 CC02 CC08 CC31 CC41 CC52 CC58 DD02 DD17 DD22 DD33 DD47 EE33 FF04 GG17 GG22 GG23 GG28 HH03 HH24

Claims (25)

[Claims] 1. An inner layer substrate on which inner layer wiring is formed, an adhesive layer, an insulating resin layer, and a wiring formed on the insulating resin layer on at least one side of the inner layer substrate, The wiring formed on the insulating resin layer has a sputtered metal layer and a pattern electric layer using the sputtered metal layer as a base metal, and a thin film buildup layer in which the wiring and at least the inner layer wiring are connected by via holes. A wiring board, which is a plated layer. 2. The wiring board according to claim 1, wherein the thickness of the thin film buildup layer is less than 25 μm. 3. The wiring board according to claim 1, wherein the insulating resin layer has a thickness of less than 10 μm. 4. The wiring board according to claim 1, wherein the tensile elastic modulus of the insulating resin layer is 5 GPa or more. 5. A. Forming inner layer wiring on the inner layer substrate; b. A step of forming an adhesive layer on the inner layer substrate, arranging an insulating resin layer having a sputtered metal formed on one side so that the insulating resin layer is in contact with the adhesive, and heating and pressing to laminate the layers; c. Forming a hole for interlayer connection from the sputtered metal layer to the inner layer wiring, d. And a step of forming a conductor circuit of an outer layer by performing plating for electrically connecting the sputtered metal layer and the inner layer circuit. 6. The method for manufacturing a wiring board according to claim 5, wherein the holes in step c are opened by laser irradiation. 7. In step d, a plating layer is formed on the surface of the sputtered metal layer, the inner wall of the hole and the bottom of the hole, and then a plating resist is formed on the plating layer, and the plating resist is not formed. 7. The method for manufacturing a wiring board according to claim 5, wherein a plating layer that is thicker than the plating layer is formed at a location. 8. The method for manufacturing a wiring board according to claim 5, wherein the conductor circuit of the outer layer is formed by etching. 9. The method for manufacturing a wiring board according to claim 8, wherein the conductor circuit of the outer layer is etched with an etching solution containing sulfuric acid and hydrogen peroxide as main components. 10. An inner layer substrate on which inner layer wiring is formed, an adhesive layer, an insulating resin layer, and a wiring formed on the insulating resin layer on at least one side of the inner layer substrate, The wiring formed on the insulating resin layer has a sputtered metal layer and a pattern electric layer using the sputtered metal layer as a base metal, and a thin film buildup layer in which the wiring and at least the inner layer wiring are connected by via holes. The outermost conductor circuit, which is a plating layer and is a wiring formed on the insulating resin layer, has an external connection terminal connected to at least another wiring board, and an internal connection terminal connected to a terminal of the semiconductor chip. A substrate for mounting a semiconductor, comprising: 11. The thin film buildup layer has a thickness of 25 μm.
The semiconductor mounting substrate according to claim 10, which is less than 10. 12. The semiconductor mounting substrate according to claim 10, wherein the insulating resin layer has a thickness of less than 10 μm. 13. The tensile elastic modulus of the insulating resin layer is 5 GPa.
It is above, The semiconductor mounting substrate in any one of Claims 10-12. 14. A. Forming inner layer wiring on the inner layer substrate; b. A step of forming an adhesive layer on the inner layer substrate, arranging an insulating resin layer having a sputtered metal formed on one side so that the insulating resin layer is in contact with the adhesive, and heating and pressing to laminate the layers; c. Forming a hole for interlayer connection from the sputtered metal layer to the inner layer wiring, d. A step of forming a conductor circuit of an outer layer by performing plating for electrically connecting the sputtered metal layer and the inner layer circuit, and d-2. A method for manufacturing a semiconductor mounting substrate, which comprises the step of forming at least an external connection terminal connected to another wiring board and an internal connection terminal connected to a terminal of a semiconductor chip in the outermost conductor circuit. 15. The method for manufacturing a semiconductor mounting substrate according to claim 14, wherein the holes in step c are opened by laser irradiation. 16. A plating layer is formed on the surface of the sputtered metal layer, the inner wall of the hole, and the bottom of the hole, a plating resist is formed on the plating layer, and then the plating is applied to a portion where the plating resist is not formed. The method for manufacturing a semiconductor mounting substrate according to claim 14 or 15, wherein a plating layer thicker than the layer is formed. 17. The method for manufacturing a semiconductor mounting substrate according to claim 14, wherein the conductor circuit of the outer layer is formed by etching. 18. The method for manufacturing a semiconductor mounting substrate according to claim 17, wherein the conductor circuit of the outer layer is etched with an etching solution containing sulfuric acid and hydrogen peroxide as main components. 19. A semiconductor package comprising the semiconductor mounting substrate according to any one of claims 10 to 13 or the semiconductor mounting substrate manufactured by the manufacturing method according to any one of claims 14 to 18. 20. a. Forming inner layer wiring on the inner layer substrate; b. A step of forming an adhesive layer on the inner layer substrate, arranging an insulating resin layer having sputtered metal formed on one side so that the insulating resin layer is in contact with the adhesive, and laminating by heating and pressing; c. Forming a hole for interlayer connection from the sputtered metal layer to the inner layer wiring, d. A step of forming a conductor circuit of an outer layer by performing plating for electrically connecting the sputtered metal layer and the inner layer circuit, and d-2. A step of forming at least an external connection terminal connected to another wiring board and an internal connection terminal connected to a terminal of the semiconductor chip on the outermost conductor circuit; e. A method of manufacturing a semiconductor package, comprising: mounting a semiconductor chip; and connecting a terminal of the semiconductor chip and an internal connection terminal of a conductor circuit of an outermost layer. 21. The method of manufacturing a semiconductor package according to claim 20, wherein steps b to d are repeated. 22. The method of manufacturing a semiconductor package according to claim 20, wherein the hole in step c is opened by laser irradiation. 23. In step d, a plating layer is formed on the surface of the sputtered metal layer, the inner wall of the hole and the bottom of the hole, and then a plating resist is formed on the plating layer, and the plating resist is not formed. 23. The method of manufacturing a semiconductor package according to claim 20, wherein a plating layer that is thicker than the plating layer is formed at a location. 24. The method of manufacturing a semiconductor package according to claim 20, wherein the outer conductor circuit is formed by etching. 25. The method of manufacturing a semiconductor package according to claim 20, further comprising a step of sealing a semiconductor chip with a resin after step e.