JP2003158146A - Semiconductor element and semiconductor element mounted substrate as well as semiconductor element mounting method employing the semiconductor element or the semiconductor element mounted substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element and a semiconductor element mounted substrate, which are capable of contriving conduction between a bump and an electrode pad even when a parallelism between the semiconductor element and the semiconductor element mounted substrate is low, as well as a mounting method capable of providing the parallelism with a margin by employing the semiconductor element or the semiconductor element mounted substrate. SOLUTION: The bump B of the semiconductor element IC is constituted of two layers (B1, B2), or the electrode pad P of the semiconductor element mounted substrate 1 is constituted of two layers (P1, P2), while the second layer bump (B2) or the second layer electrode pad (B2) is made readily flattened. The semiconductor element IC is adhered to the semiconductor element mounting substrate 1 with pressure through an adhesive 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element having a plurality of bumps which are projecting electrodes, a semiconductor element mounting substrate having a plurality of electrode pads, and a semiconductor element or a semiconductor element using the semiconductor element mounting substrate. Regarding the implementation method.

[0002]

2. Description of the Related Art In recent years, in order to meet the demand for miniaturization of electronic equipment, higher density mounting of semiconductor elements is required.
A face-down mounting method is generally used as a method for this high-density mounting. FIG. 8 shows a face-down mounting method. As shown in FIG. 8A, in the face-down mounting, the bump B of the semiconductor element IC and the electrode pad P of the semiconductor element mounting substrate 1 are opposed to each other, and
As shown in (b), the pressure bonding tool 3 is used to heat and pressurize the semiconductor element IC from above, and the semiconductor element IC is fixed to the semiconductor element mounting substrate 1 with the adhesive 2. Of the semiconductor element mounting substrate 1 and the electrode pad P of the semiconductor element mounting substrate 1 are electrically connected.
Is mounted on the semiconductor element mounting substrate 1. According to this mounting method, there is an advantage that the semiconductor element ICs can be mounted at high density as compared with a normal mounting method such as wire bonding.

[0003]

However, in the above-mentioned conventional structure, as shown in FIG.
When C and the semiconductor element mounting substrate 1 are not parallel to each other, that is, when the semiconductor element IC is inclined, one (right side in the figure) bump BR and one (right side in the figure) electrode pad PR
However, there is a problem regarding the parallelism that the bump BL on the other side (the left side in the drawing) and the electrode pad PL on the other side (the left side in the drawing) cannot be connected to each other. In other words, when the parallelism between the semiconductor element IC and the semiconductor element mounting substrate 1 is high (when the semiconductor element IC is mounted in parallel), the bump B and the electrode pad P have good conduction, but the parallelism is high. When the value is low (when the semiconductor element IC is mounted at an angle)
However, there is a problem that the bump B and the electrode pad P have poor electrical continuity.

In the step of mounting the semiconductor element IC on the semiconductor element mounting substrate 1, it is required to mount the semiconductor element IC with extremely high parallelism in order to prevent the conduction failure. Although it was necessary to strictly control the parallelism with the substrate 1, it has become difficult to keep the parallelism of the semiconductor element IC high as the semiconductor element IC becomes smaller and has a higher density.

Further, the problem regarding the parallelism between the semiconductor element IC and the semiconductor element mounting substrate 1 also arises due to the relationship with the adhesive 2 interposed therebetween. That is, there are various methods for mounting the semiconductor element IC with bumps on the semiconductor element mounting substrate 1 face down. Instead of the conventional so-called solder bump, an anisotropic conductive film (Anis
It is becoming possible to realize high-density mounting by interposing an otropic conductive film (ACF) between the connection terminals (fine pitch). The anisotropic conductive film is a paste or film having conductive particles 2a dispersed in an insulating adhesive, having conductivity in the thickness direction (connection direction), and insulating in the plane direction (lateral direction). This is adhesive 2. However, as shown in FIG.
When the adhesive 2 such as ACF which is an adhesive containing a is interposed, the parallelism between the semiconductor element IC and the semiconductor element mounting substrate 1 is lowered. That is, the conductive particles are present only between the bump BR on one side (the right side in the figure) and the electrode pad PR, and the bump B on the other side (the left side in the figure).
When the conductive particles are not present between L and the electrode pad PL, the semiconductor element IC tilts and the surface of the bump BL in contact with the electrode pad PL becomes small, which causes a problem of poor conduction.

In mounting a semiconductor element on a liquid crystal panel, a COG (chip on) is used to directly connect the semiconductor element to an electrode terminal (connection electrode or electrode pad) on a glass substrate.
Glass) mounting has become mainstream, but in COG mounting and the like, it is usual to mount a semiconductor element having bumps by using the anisotropic conductive film (ACF).

Therefore, an object of the present invention is to achieve electrical continuity between bumps and electrode pads when mounting a semiconductor element on a semiconductor element mounting substrate even when the parallelism between the semiconductor element and the semiconductor element mounting substrate is low. An object of the present invention is to provide a semiconductor element and a semiconductor element mounting substrate that can be used, and a mounting method that can provide a margin in parallelism by using the semiconductor element or the semiconductor element mounting substrate.

[0008]

In order to solve the above problems and achieve the above object, a semiconductor element according to claim 1 is a semiconductor element having a plurality of bumps which are projecting electrodes, As the layer bump, a second layer bump is formed thereon, and the second layer bump is more easily crushed than the first layer bump.

According to this invention, the semiconductor element of the present invention is placed on an electronic element mounting substrate having electrode pads connected to the second layer bumps of the semiconductor element, and pressure is applied from above the semiconductor element. Then, the second-layer bump is crushed. Therefore, even when the electronic element is mounted with an inclination, all the second layer bumps come into contact with the electrode pads by crushing the second layer bumps in accordance with the inclination.

A semiconductor element according to a second aspect is based on the semiconductor element according to the first aspect, and the second layer bump has a columnar shape in a direction perpendicular to the bottom surface with a connection surface to the first layer bump as a bottom surface. The bottom surface is formed in a pyramid shape, and the size of the bottom surface is smaller than the connecting surface of the first layer bump to the second layer bump.

According to the present invention, since the pressure applied to the second layer bump is increased, the second layer bump can be easily crushed from the viewpoint of the shape.

The semiconductor element according to claim 3 is based on the semiconductor element according to claim 1 or 2, and the second layer bump is formed of a material softer than the first layer bump. And

According to the present invention, the second layer bump can be more easily crushed from the viewpoint of the material.

According to a fourth aspect of the present invention, there is provided a semiconductor element mounting method, wherein the semiconductor element according to any one of the first to third aspects is mounted on a semiconductor element mounting substrate having an electrode pad connected to the second layer bump. It is characterized in that the semiconductor element is mounted by pressure bonding to the semiconductor element mounting substrate via an adhesive.

According to the present invention, even when the semiconductor element is pressure-bonded to the semiconductor element mounting substrate with an adhesive, and the second layer bump is crushed by the pressure, the parallelism of the semiconductor element is lowered. Continuity is achieved.
Therefore, in the mounting process, it is not necessary to perform strict control in order to increase the parallelism, and some inclination can be allowed. That is, it is possible to allow a certain degree of parallelism.

The semiconductor element mounting substrate according to claim 5 is
In a semiconductor element mounting substrate having a plurality of electrode pads, the electrode pad is used as a first layer electrode pad, and a second layer electrode pad is formed thereon, and the second layer electrode pad is the first layer electrode. It is characterized by being crushed more easily than a pad.

According to this invention, when the semiconductor element having the bumps connected to the electrode pads is placed on the semiconductor element mounting substrate of the present invention and pressure is applied from above the semiconductor element, the second layer electrode pad is formed. Is crushed. Therefore, even when the semiconductor element is mounted with an inclination, all the second layer electrode pads come into contact with the bumps by crushing the second layer electrode pads according to the inclination.

A substrate for mounting a semiconductor element according to claim 6 is
On the premise of the semiconductor element mounting substrate according to claim 5, the second layer electrode pad is formed in a columnar shape or a pyramid shape in a direction perpendicular to the bottom surface with the connection surface to the first layer electrode pad as the bottom surface, and the bottom surface. Is smaller than the connecting surface of the first layer electrode pad with the second layer electrode pad.

According to the present invention, since the pressure applied to the second layer electrode pad is increased, the second layer electrode pad can be easily crushed from the viewpoint of the shape.

The semiconductor element mounting substrate according to claim 7 is
Based on the semiconductor element mounting substrate according to claim 5 or 6, the second layer electrode pad is formed of a material softer than the first layer electrode pad.

According to the present invention, the second layer electrode pad can be more easily crushed from the viewpoint of the material.

According to the semiconductor element mounting method of claim 8, when mounting the semiconductor element having the bumps connected to the second layer electrode pads on the semiconductor element mounting substrate of claim 5 to claim 7, bonding is performed. It is characterized in that the semiconductor element is pressure-bonded to the semiconductor element mounting substrate via the agent.

According to the present invention, since the semiconductor element is pressure-bonded to the semiconductor element mounting substrate via the adhesive, the second-layer electrode pad is crushed by the pressure and comes into contact with the bump. Conduction is achieved even when the degree decreases. Therefore, in the mounting process, it is not necessary to perform strict control in order to increase the parallelism, and the parallelism can have a margin.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) In the present embodiment,
A semiconductor element IC having a second layer bump and a mounting method using the semiconductor element IC will be described. FIG. 1 is a diagram showing a semiconductor device IC of the present embodiment. On the back surface (upper side in FIG. 1) of the semiconductor element IC, a large number of bumps, which are protruding electrodes, are formed along the outer periphery. Each bump is 2
It has a layer (two-stage) structure, and a rectangular parallelepiped first-layer bump B1 is formed on the lower stage (lower side in the drawing) of the two-layer structure. It should be noted that the bumps of the conventional semiconductor element are arranged such that the input side and the output side face each other (opposite along the outer periphery), or the bumps are arranged in a staggered pattern.

Above the first layer bump B1 (upper layer of the two-layer structure)
Is provided with a second-layer bump B2. The second layer bump B2 is easier to be crushed than the first layer bump B1 from the viewpoint of shape and material. Specifically, from the viewpoint of the shape, the second-layer bump B2 has a rectangular column shape in the direction perpendicular to the bottom surface with the connection surface B2a of the second-layer bump B2 to the first-layer bump B1 as the bottom surface. The size of the bottom surface (that is, the connection surface B2a) is smaller than the size of the connection surface B1a of the first layer bump B1 with the second layer bump B2. By having such a shape, the first layer bump B1
Compared with, the second layer bump B2 can be easily crushed from the viewpoint of the shape. The shape of the second-layer bump B2 is not limited to the quadrangular prism, and may be a polygonal prism, a cylindrical column, or the like.

From the viewpoint of material, the second layer bump B
2 uses a softer material than the first layer bump B1. Specifically, low purity gold in which copper and nickel are mixed in a high ratio to gold is used as the material of the first layer bump B1, and high purity gold is used as the material of the second layer bump B2. . Since high-purity gold is softer than low-purity gold, the second-layer bump B2 is more easily crushed than the first-layer bump B1. The material of the second layer bump B2 is not limited to the gold, and may be any material that is softer than the material of the first layer bump B1.

Next, a method of manufacturing the second layer bump B2 will be described with reference to FIG. Generally, as a method of forming bumps on a semiconductor wafer, many methods such as a method using photolithography and plating are known. Here, an example in which the second layer bump B2 is manufactured by a method using photolithography and plating will be described. First, a resist film having an opening is formed on the connection surface B1a of the first layer bump B1 by photolithography (a). The opening of this resist film is formed in conformity with the shape of the second layer bump B2. That is, since the connection surface B2a of the second layer bump B2 is smaller than the connection surface B1a of the first layer bump B1, the connection surface B1 of the first layer bump B1 is included in the resist film.
An opening that is one size smaller than a is formed in a quadrangular prism shape. Next, the opening of the resist film is washed with acid or the like. Then, after gold (Au) plating is formed on the opening by performing a film forming process using a gold plating liquid with low purity (b), the film resist is removed (c), and the second layer bump B2 is formed. Form. Then, finally, an annealing process is performed. If you want to change the shape of the second layer bump B2,
The shape of the opening is changed. The first layer bump B1
Are usually formed by photolithography and plating.

Next, a method of mounting the semiconductor element IC of this embodiment on the semiconductor element mounting substrate 1 will be described. As shown in FIG. 3A, the semiconductor element mounting substrate 1
Is the second layer bump B2 of the semiconductor element IC of the present embodiment.
There is an electrode pad P that is connected to, and an adhesive 2 is arranged. The semiconductor element IC is aligned such that the second layer bump B2 of the semiconductor element IC corresponds to the electrode pad P of the semiconductor element mounting substrate 1, and then the semiconductor element IC is heated and pressed from above the semiconductor element IC to form a semiconductor. It is pressure-bonded and fixed to the element mounting substrate 1. Since the second layer bump B2 is easily crushed from the viewpoint of shape and material, the semiconductor element IC is pressure-bonded to the semiconductor element mounting substrate 1 with the adhesive 2 at the same time by the pressure at the time of pressure bonding the semiconductor element IC. The second layer bump B2 is crushed by the pressure.

FIG. 3B shows a state in which the semiconductor element IC according to the present embodiment is mounted on the semiconductor element mounting substrate 1 with an inclination, that is, a state in which parallelism is low. Semiconductor element IC
Has a lower one side (right side in the drawing) and a higher inclination on the other side (left side in the drawing). The second layer bump B2 (B2R) is crushed on one side (right side in the figure), and the first layer bump B1 (B1R) and the electrode pad P (PR) are separated from each other by the second layer bump B2 (B2R).
Will be conducted through. On the other hand, the first layer bump B1 (B1L) and the electrode pad P (P
L) has a wide gap, but the second layer bump B2 (B2R) on the one side (the right side in the drawing) is crushed, so that the second layer bump B2 (the left side in the drawing) on the other side (the left side in the drawing) is formed. B2
L) contacts the electrode pad P (PL), and the first layer bump B
1 (B1L) and the electrode pad P (PL) are electrically connected via the second layer bump B2 (B2L).

Therefore, the semiconductor element I of this embodiment is
By using C, the electrical connection between the bump B and the electrode pad P can be achieved even when the semiconductor element IC is mounted at an inclination with respect to the semiconductor element mounting substrate 1 (when parallelism is low). In the mounting process, the semiconductor element IC and the semiconductor element mounting substrate 1 do not need to be strictly parallel to each other (that is, the parallelism does not need to be strictly controlled), and a slight inclination can be allowed ( In other words, you can give a margin to the parallelism).

(Application example of the first embodiment) FIG. 4 shows a first example.
An application example of the embodiment will be described. Second layer bump B2 of FIG.
The shape of is a quadrangular pyramid, and like the first embodiment,
The size of the bottom surface (that is, the connecting surface B2a) of the second-layer electrode pad is the connecting surface B of the first-layer bump B1 to the second-layer bump B2.
It is smaller than 1a. When the semiconductor element IC is pressure-bonded to the semiconductor element mounting substrate 1 by using the quadrangular pyramid, a high pressure is applied to the tip portion of the second layer bump B2, so that the tip portion is more easily crushed. Therefore, the same effect as that of the first embodiment can be obtained. The second-layer bump B2 is not limited to a quadrangular pyramid, and may have a conical shape such as a cone or a polygonal pyramid.

(Second Embodiment) FIG. 5 is a diagram showing a semiconductor element mounting substrate 1 of the present embodiment and a semiconductor element IC mounted on the semiconductor element mounting substrate 1 of the present embodiment. In the semiconductor element mounting substrate 1 of the present embodiment, the square columnar second layer electrode pad P2 is provided as the first layer electrode pad P1.
Is provided above. However, the second layer electrode pad P2
Bottom surface (that is, the connection surface P2 with the first layer electrode pad P1)
The size of a) is smaller than the size of the connection surface P1a of the first layer electrode pad P1 with the second layer electrode pad P2. With such a shape, the pressure applied to the second layer electrode pad is increased, and the second layer electrode pad P2 is more likely to be crushed than the first layer electrode pad P1. The material of the second layer electrode pad P2 is the same as in the first embodiment.
It is gold with a higher purity than the first layer electrode pad P1. Since the second layer electrode pad P2 is more easily crushed than the first layer electrode pad P1 in terms of shape and material, when the semiconductor element IC and the semiconductor element mounting substrate 1 are pressure-bonded via the adhesive 2,
The second layer electrode pad P2 according to the inclination of the semiconductor element IC
Is crushed, and all the second-layer electrode pads P2 come into contact with the bumps B. Therefore, similarly to the first embodiment, even if the parallelism between the semiconductor element IC and the semiconductor element mounting substrate 1 is low, the conduction between the bump B and the electrode pad P can be achieved, and in the semiconductor mounting step. Can allow for parallelism. Note that the shape and material of the second-layer bump B2 are not limited to the square pole and high-purity gold, as in the first embodiment.

Also, in the method of manufacturing the second layer electrode pad P2, the second layer electrode pad P2 is formed on the connection surface P1a of the first layer electrode pad P1 by the method of photolithography and plating. Since the bottom surface of P2 (that is, the connection surface P2a) is smaller than the connection surface P2a of the first layer electrode pad P1, the resist film has the first layer electrode pad P1.
An opening portion that is slightly smaller than the connection surface P1a is provided. When a plurality of semiconductor element ICs are mounted on one semiconductor element mounting substrate 1, the second layer bumps B2 are simultaneously formed on the first layer electrode pads P1 corresponding to the bumps B of all the semiconductor element ICs. To do.

(Application Example of Second Embodiment) FIG. 6 shows a second example.
An application example of the embodiment will be described. Semiconductor element mounting substrate 1
The shape of the second layer electrode pad P2 formed on the first layer electrode pad P1 is a quadrangular pyramid, and like the second embodiment, the bottom surface of the second layer electrode pad P2 (that is, the connection surface P2).
The size of a) is smaller than the connecting surface P1a of the first layer electrode pad P1 with the second layer electrode pad P2. When the semiconductor element IC is pressure-bonded to the semiconductor element mounting substrate 1 by forming the second-layer electrode pad P2 into a quadrangular pyramid, a high pressure is applied to the tip end portion of the second-layer electrode pad P2, so that the second-layer electrode pad P2 is easily crushed. The second-layer electrode pad P2 is not limited to a quadrangular pyramid, and may have another pyramidal shape such as a cone or a polygonal pyramid.

(Application Example to Liquid Crystal Display Device) As a specific example, a case where the semiconductor element IC or the semiconductor element mounting substrate 1 of the present invention is applied to a COG-mounted liquid crystal display device LCD will be described below. FIG. 7 shows a COG-mounted liquid crystal display device L.
It is a figure which shows CD. The liquid crystal display device LCD is a reflection type liquid crystal display device LCD using a TFT which is a typical active element currently used. For the COG-mounted liquid crystal display device LCD, one of the semiconductor element IC and the semiconductor element mounting substrate 1 of the present invention is used.

The first substrate (one substrate: also referred to as an AM substrate or an array substrate) 1 of the liquid crystal panel LCD is larger than the other substrate 4, and therefore when the both substrates 1 and 4 are superposed, the AM substrate 1 A mounting region 5 of the semiconductor element IC partially protruding is formed in the periphery of the. In the mounting area 5 of the first substrate 1, the wiring pattern 6 for semiconductor mounting is formed.
7 are formed. The AM substrate 1 may be a flexible substrate made of synthetic resin, instead of the glass substrate.

The semiconductor element IC of this embodiment is mounted on the mounting area 5 of the AM substrate 1 with the conductive particle adhesive 2 interposed therebetween. On the back surface side of the semiconductor element IC, a large number of bumps B are formed facing each other along the outer periphery.

Electrodes P connected to the semiconductor element IC are patterned on the ends of the wiring patterns 6 and 7. The electrode P on one side (left side in FIG. 6) is an input electrode, and the electrode P on the other side (right side in FIG. 6) is an output electrode. The semiconductor element IC that drives the liquid crystal panel LCD is mounted via the ACF 2 containing the conductive particles 2a in the adhesive.

When the semiconductor element IC of the present invention is applied to such a liquid crystal panel LCD, it is used as the semiconductor element IC arranged in the mounting region 5. That is, the conventional bumps of the semiconductor element IC arranged in the mounting area 5 are replaced with the first layer bumps B1.
Then, the second layer bump B2 is formed on the first layer bump B1. In this case, the second layer electrode pad is not provided on the electrode pad P to which the second layer bump B2 is connected. When the semiconductor element mounting substrate 1 of the present invention is applied, it is used as the AM substrate 1. That is, the conventional electrode pad P in the mounting area 5 is used as the first layer electrode pad P1, and the second layer electrode pad P2 is formed on the first layer electrode pad P1. In this case, the bump B connected to the second layer electrode pad is not provided with the second layer bump.

As described above, in each of the above-mentioned embodiments, both the shape and the material of the second layer bump B2 are easily crushed.
It is not limited to the case where both the shape and the material are easily crushed, and it is sufficient that the shape and the material are easily crushed comprehensively. For example, the second layer bump B
The bottom surface (connection surface B2a) of 2 may have the same size as the connection surface B1a of the first layer bump B1. In this case, by making the material of the second layer bump B2 easier to be crushed than the material of the first layer bump B1, the second layer bump B2 can be easily crushed as a whole. The material of the second layer bump B2 and the material of the first layer bump B1 may be the same, and in this case, the shape of the second layer bump B2 is the same as that of the first layer bump B1.
The second-layer bump B2 can be easily crushed comprehensively by making it more easily crushed than the shape of (2) (for example, a small square pillar or a square pyramid as in the above-described embodiment). This also applies to the second-layer electrode pad. Further, in the application example of the present invention, the COG-mounted liquid crystal display device has been described as an example, but the present invention can also be applied to a COF-mounted liquid crystal display device in which a semiconductor element is mounted on a flexible substrate via an adhesive, and other electronic devices. Is.

[0042]

As described above, according to the present invention, even when the parallelism between the semiconductor element IC and the semiconductor element mounting substrate 1 is low (that is, when the semiconductor element IC is mounted at an inclination),
By collapsing the second layer bumps or the second layer electrode pads according to the parallelism (inclination), all the second layer bump bumps and the electrode pads are electrically connected. Therefore,
By using the semiconductor element IC or the semiconductor element mounting substrate 1 of the present invention, the reliability of conduction between the bump and the electrode pad can be improved. Further, the semiconductor element IC of the present invention
Alternatively, in the mounting method using the semiconductor element mounting substrate 1,
Even if the parallelism between the semiconductor element IC and the semiconductor element mounting substrate 1 slightly decreases, this decrease can be tolerated, so that it is not necessary to perform strict control to increase the parallelism. .

[0043]

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a method of manufacturing the second-layer bump of the above-described embodiment.

FIG. 3 is a diagram showing a method for mounting the semiconductor element of the above embodiment.

FIG. 4 is a diagram showing an application example of the above embodiment.

FIG. 5 is a semiconductor element mounting substrate according to the second embodiment;
The figure which shows the semiconductor element mounted on the semiconductor element mounting substrate.

FIG. 6 is a diagram showing an application example of the above embodiment.

FIG. 7 is a diagram showing an example of application of the present invention to a liquid crystal display device.

FIG. 8 is a diagram showing a conventional face-down mounting method.

FIG. 9 is a diagram showing a state in which a semiconductor element is mounted on a semiconductor mounting substrate while being tilted.

[Explanation of symbols]

IC semiconductor element 1 semiconductor element mounting substrate (one substrate, AM substrate) 2 adhesive, ACF 2a conductive particles 3 pressure bonding tool 4 other substrate 5 mounting areas 6, 7 wiring pattern B electrode bump B1 first layer electrode bump B1a Connection surface of first layer electrode bump with second layer electrode bump B2 Second layer electrode bump B2a Connection surface of second layer electrode bump with first layer electrode bump P Electrode pad P1 First layer electrode pad P1a First Connection surface of layer electrode pad with second layer electrode pad P2 Second layer electrode pad P2a Connection surface of second layer electrode pad with first layer electrode pad

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hikaru Fujita             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Hideki Niimi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Takashi Ishikawa             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 5E319 AA03 AB05 AC01 AC03 AC15                       BB01 CD25 GG20                 5F033 HH07 HH11 HH13 MM05 MM17                       MM21 VV07                 5F044 KK06 KK18 LL07

Claims (8)

[Claims] 1. A semiconductor element having a plurality of bumps which are protrusion-shaped electrodes, wherein the bumps are used as first layer bumps, and second layer bumps are formed on the bumps, and the second layer bumps are the first layer bumps. A semiconductor device characterized by being more easily crushed than a layer bump. 2. The second-layer bump is formed in a columnar shape or a pyramid shape in a direction perpendicular to the bottom surface with a connection surface to the first-layer bump as a bottom surface, and the size of the bottom surface is the size of the first-layer bump. The semiconductor element according to claim 1, wherein the semiconductor element is smaller than the connection surface with the second layer bump. 3. The semiconductor element according to claim 1, wherein the second layer bump is made of a material softer than the first layer bump. 4. When mounting the semiconductor element according to any one of claims 1 to 3 on a semiconductor element mounting substrate having an electrode pad connected to the second layer bump, the semiconductor element is bonded to the semiconductor element via an adhesive. A method of mounting a semiconductor element, which comprises mounting the mounting substrate by pressure bonding. 5. A semiconductor device mounting substrate having a plurality of electrode pads, wherein the electrode pads are used as first layer electrode pads, and second layer electrode pads are formed on the electrode pads.
The semiconductor element mounting substrate, wherein the second layer electrode pad is more easily crushed than the first layer electrode pad. 6. The second layer electrode pad is formed in a columnar shape or a pyramid shape in a direction perpendicular to the bottom surface with a connection surface with the first layer electrode pad as the bottom surface, and the size of the bottom surface is the first layer electrode. The substrate for mounting a semiconductor element according to claim 5, wherein the pad is smaller than the connection surface with the second layer electrode pad. 7. The substrate for mounting a semiconductor element according to claim 5, wherein the second layer electrode pad is made of a material softer than the first layer electrode pad. 8. When mounting a semiconductor element having bumps connected to the second-layer electrode pads on the semiconductor element mounting substrate according to claim 5, the semiconductor element is bonded to the semiconductor element via an adhesive. A method for mounting a semiconductor device, which comprises mounting on a device mounting board.