JP2003150128A - Matrix type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a matrix type display device which is unnecessary to supply, from an external device, a scanning operation clock signal to be inputted to a scanning drive circuit for driving scanning signal lines. SOLUTION: In the matrix type display device, display elements 15, a plurality of data signal lines 13 and plurality of scanning signal lines 14 for driving the display elements 15, and a data driving circuit 11 and a scanning drive circuit 12 for driving the data signal lines 13 and the scanning signal lines 14, are respectively formed on the same substrate. On the substrate, a scanning clock generation circuit 40 for generating scanning operation clock signals GCK1A, GCK2A to be outputted to the scanning drive circuit 12 using a data driving start signal SSP to be inputted to the data driving circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type display device in which a display element and a drive circuit for driving the display element are formed on the same substrate. Specifically, the present invention relates to a matrix type display device that does not need to supply a scan operation clock signal input to a scan drive circuit that drives a scan signal line from the outside of the device.

[0002]

2. Description of the Related Art In a matrix type display device, a large number of signal lines are arranged in a row direction and a column direction with respect to a display element, and by driving the signal lines, characters, symbols,
This is a device for displaying images such as figures. As the display device, an FPD (flat panel display) such as an LCD (liquid crystal display), a PDP (plasma display panel), an EL (electroluminescence) display, and an FED (field emission display) is used. Since the FPD can be made thinner and lighter than a conventional CRT (cathode ray tube), it has recently been used in various display devices.

FIG. 8 is a block diagram showing a schematic structure of a conventional matrix type display device. In the matrix type display device 100, a large number of data signal lines 13 parallel to the column direction are arranged in the row direction and a large number of scanning signal lines 14 parallel to the row direction are arranged in the column direction with respect to the display element. The data signal line 13 is connected to the data driving circuit 11, and the scanning signal line 14 is connected to the scanning driving circuit 110.

The data drive circuit 11 includes a data signal Data which is image data for one line, and a data drive start signal SSP used for starting a drive operation of the circuit 11 to the data signal line 13. Data signals Data1 to Data obtained by dividing the data signal Data for each pixel.
Of the data operation clock signals SCK and SCKB used for sequentially driving the data signals to the respective data signal lines 13.
And are entered.

The scan drive circuit 110 is used to sequentially drive the scan signal lines 14 and the scan drive start signal GSP used to start the drive operation of the scan signal lines 14 of the circuit 110. Scan operation clock signal GCK1
・ GCK2 is input.

The matrix type display device 100 having the above structure.
The operation will be described based on the timing charts of FIGS. 9 and 11. First, as shown in FIG. 11, the drive operation of the scan drive circuit 110 is started based on the scan drive start signal GSP, and the scan operation clock signal GCK1.
The first scanning signal line 14 is driven based on GCK2.

Next, as shown in FIG. 9, the drive operation of the data drive circuit 11 is started based on the data drive start signal SSP, and the data operation clock signals SCK and SCKB.
Based on the above, the data signals Data1 to Data of one pixel are sequentially output to each data signal line 13.

When the output of the data signal Data for one line to the data signal line 13 is completed, the next scanning signal line 14 is generated based on the scanning operation clock signals GCK1 and GCK2.
Is driven, and thereafter, this operation is repeated up to the last scanning signal line 14, whereby an image of one frame is displayed on the display element.

[0009]

As described above, the conventional matrix type display device 100 has the data signal Dat.
It is necessary to input various timing signals such as a, the data drive start signal SSP, the data operation clock signals SCK / SCKB, the scan drive start signal GSP, and the scan operation clock signals GCK1 and GCK2 from a circuit external to the device.

Recently, in order to further reduce the size and weight of the FPD, it is required to reduce the number of parts of the external circuit for generating the signal. To solve this problem, there is a display device disclosed in Japanese Patent Laid-Open No. 11-194713.

In the display device, a timing generation circuit for generating the timing signal is provided in a source driver (data drive circuit), and the timing signal is transmitted from the timing generation circuit to the gate driver (scan drive circuit). I am trying. Since the display device generates the timing signal in the data driving circuit, it is possible to reduce the number of parts of the external circuit and reduce the number of wirings in the flexible substrate connecting the external circuit and the display device. be able to.

However, in the display device, the circuit scale is increased by providing the timing generation circuit in the source driver. Further, the above publication does not disclose a configuration for reducing the scale of the timing generation circuit.

[Object of the Invention] In view of the above problems, the inventor of the present application paid attention to the following points. That is, since the scanning operation clock signal is for timing the driving of each scanning signal line, as shown in FIG. 9, a certain scanning signal line is driven during the period of transferring an image of at least one line. The timing may be such that

It is an object of the present invention to provide a matrix type display device in which it is not necessary to supply a scanning operation clock signal input to a scanning drive circuit for driving a scanning signal line from outside the device.

[0015]

In order to solve the above-mentioned problems, a matrix type display device of the present invention comprises a display element,
A matrix type display device comprising a plurality of data signal lines and a plurality of scanning signal lines for driving the display element, and a data driving circuit and a scanning driving circuit for respectively driving the data signal lines and the scanning signal lines, A scan clock generation circuit that generates a scan operation clock signal to be output to a scan drive circuit by using a data drive start signal input to a data drive circuit to start transferring an image data signal for one line to a data signal line. It is characterized by having.

According to the above structure, the scan clock generation circuit generates the scan operation clock signal by using the data drive start signal input to the data drive circuit. The data driving start signal is used to start driving the data driving circuit, and the data driving circuit is
After inputting the data drive start signal, the image signal signal for one line is started to be output to the data signal line.

From this, the scanning operation clock signal generated by using the data drive start signal can be set to the timing before the output of the image data signal to the data signal line is started. By inputting to the scan drive circuit, the scan signal line can be driven before outputting the image data signal to the data signal line.

Therefore, in the matrix type display device of the present invention, since the scanning operation clock signal is generated by using the data drive start signal, it becomes unnecessary to supply the scanning operation clock signal from outside the device. As a result, the circuit for generating the scanning operation clock signal is not required for the external circuit, so that the number of parts of the external circuit can be reduced and the wiring for transmitting the scanning operation clock signal from the external circuit to the display device is unnecessary. Therefore, the number of connection wirings between the external circuit and the display device can be reduced.

Further, in the matrix type display device of the present invention, the scanning operation clock signal has the timing for starting the driving of the scanning signal line by using the data driving start signal. It is not necessary to newly provide a circuit for this, and as a result, it is possible to suppress an increase in the size and the number of parts of the display device.

Further, in the matrix type display device of the present invention, in the above structure, the data driving circuit includes a shift register group in which a plurality of shift registers are connected in series, and at least one of the plurality of shift registers. The section drives each data signal line,
The scan clock generation circuit generates a scan operation clock signal using the data drive start signal and the output signal of the shift register.

According to the above structure, the scanning clock generation circuit generates the scanning operation clock signal by using the data driving start signal and the output signal of the shift register. The signal level of the output signal from each shift register sequentially shifts based on the data operation clock signal. Therefore, by using the output signal from one of the shift registers and knowing the timing at which the output signal becomes active, the timing at which the sequential driving of the data signal lines by the shift register is stopped can be known.

From this, the scanning operation clock signal generated by using the output signal can be set to the timing at which the image data signal is output to the data signal line, and the scanning operation clock signal is used as the scanning driving circuit. By inputting to, the driving of the scanning signal line can be finished after the image data signal is outputted to the data signal line.

Therefore, in the matrix type display device of the present invention, the scanning operation clock signal uses the output signal of the shift register in the data driving circuit to set the timing for ending the driving of the scanning signal line. As a result, it is not necessary to newly provide a circuit for setting the timing, and as a result, it is possible to suppress an increase in the size of the display device and an increase in the number of parts.

The matrix type display device of the present invention is a matrix type display device comprising a display element, a plurality of the data signal lines and a plurality of the scanning signal lines, the data drive circuit and the scan drive circuit. There
The data drive circuit includes a shift register group in which a plurality of shift registers are connected in series, and at least a part of the plurality of shift registers drives each data signal line. It is characterized in that a scan clock generation circuit for generating a scan operation clock signal to be output to the scan drive circuit is provided by using the output signal.

According to the above structure, the scanning clock generation circuit generates the scanning operation clock signal by using the output signal of the shift register. The shift register is
The operation is started by the input of the data drive start signal, and the image data signals are sequentially output to the plurality of data signal lines based on the data operation clock signal.

At this time, when the data drive start signal and the data operation clock signal are not synchronized, the output signal of the first stage of the shift register is more than the output signals of the other stages during the period of driving the data signal line. May be shorter.

Therefore, the output signal of the first stage of the shift register is generally not used to drive the data signal line, and the output signals of the subsequent stages are used to drive the data signal line. That is, it can be said that the output signal of the first stage of the shift register indicates the timing immediately before the start of outputting the image data signal to the data signal line.

From this, the scanning operation clock signal generated by using the output signal of the shift register can be set to the timing before the output of the image data signal to the data signal line is started. Is inputted to the scan drive circuit, the scan signal line can be driven before the output of the image data signal to the data signal line is started.

As described above, the scanning operation clock signal generated by using the output signal can be set to the timing at which the image data signal is output to the data signal line. By inputting to the scan drive circuit, the drive of the scan signal line can be ended after the image data signal is output to the data signal line.

Therefore, in the matrix type display device of the present invention, since the scanning operation clock signal is generated by using the output signal of the shift register in the data driving circuit, the scanning operation clock signal is supplied from the outside of the device. Is unnecessary. As a result, the circuit for generating the scanning operation clock signal is not required for the external circuit, so that the number of parts of the external circuit can be reduced and the wiring for transmitting the scanning operation clock signal from the external circuit to the display device is unnecessary. Therefore, the number of connection wirings between the external circuit and the display device can be reduced.

Further, in the matrix type display device of the present invention, the scanning operation clock signal uses the output signal of the shift register in the data driving circuit to set the timing for ending the driving of the scanning signal line. As a result, it is not necessary to newly provide a circuit for setting the timing, and as a result, it is possible to suppress an increase in the size of the display device and an increase in the number of parts.

Further, the matrix type display device of the present invention is characterized in that, in the above-mentioned structure, the scanning clock generation circuit uses the output signal of the first-stage shift register provided in the data driving circuit.

According to the above configuration, the timing of the output signal of the first-stage shift register is almost the same as the timing of the data drive start signal. Therefore, by using this output signal, the image data signal is transferred to the data signal line. You can know the timing before output starts.

Therefore, the scanning operation clock signal generated by using the output signal of the first-stage shift register can be the timing before the output of the image data signal to the data signal line is started. Is inputted to the scan drive circuit, the scan signal line can be driven before the output of the image data signal to the data signal line is started.

Further, in the matrix type display device of the present invention, in the above structure, the display element, the plurality of data signal lines, the plurality of scanning signal lines, the data driving circuit, the scanning driving circuit and the scanning clock. It is characterized in that the generation circuit is formed on the same substrate.

According to the above configuration, the scan clock generation circuit can be manufactured in the same process as the data drive circuit and the scan drive circuit. Therefore, the manufacturing cost is suppressed as compared with the case where the scan clock generation circuit is provided outside the device. be able to.

Further, the matrix type display device of the present invention is characterized in that, in the above structure, the scan clock generation circuit generates the scan operation clock signal after the scan drive start signal is inputted.

In the conventional display device, when the scan drive start signal is input to the scan drive circuit, the scan operation clock signal is also input, and the scan drive start signal and the scan operation clock signal are synchronized. If not, the period for driving the first scanning signal line may be shortened. Therefore, it is necessary to provide a circuit for synchronizing the scan drive start signal and the scan operation clock signal before driving the first scan signal line.

On the other hand, in the matrix type display device of the present invention, after the scan drive start signal is input, the scan clock generation circuit generates the scan operation clock signal and outputs it to the scan drive circuit. It is not necessary to synchronize the start signal with the scanning operation clock signal. Therefore, the matrix type display device of the present invention can omit the circuit for synchronizing the scan drive start signal and the scan operation clock signal. As a result, the number of components in the scan drive circuit can be reduced and the circuit scale can be reduced.

Further, in the matrix type display device of the present invention, in the above structure, the scan driving circuit includes a shift register group in which a plurality of shift registers are connected in series, and at least a part of the plurality of shift registers. Is
Each of the scanning signal lines is driven, and the shift register that drives each of the scanning signal lines has a function of being reset by the input of a scanning driving start signal.

The matrix type display device of the present invention is suitable for displaying on a part of pixels. For example, when an image is displayed on only a part of the lines, the scan clock generation circuit does not generate the scan operation clock signal because the data drive start signal is not input after the image is displayed. In this case, when the next image signal is input, the display device is displayed after the previously displayed line.

Therefore, in the matrix type display device of the present invention, when the scan drive start signal is input to display the next image, the shift register is reset, so that the first operation is performed again based on the scan operation clock signal. The scanning signal lines can be sequentially driven.

Therefore, the matrix type display device of the present invention can operate normally even when the next image is displayed after being displayed on some pixels.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] An embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing a schematic configuration of the matrix type display device in this embodiment. In the display device 10, m data signal lines 13 parallel to the column direction are arranged in the row direction and m scan signal lines 14 parallel to the row direction are arranged in the column direction with respect to the display element. However, m and n are natural numbers).

Each data signal line 13 and each scanning signal line 1
At the intersection of 4, F that functions as a switching element
An ET (Field Effect Transistor) 16 is provided and the F
The ET 16 has a gate terminal connected to the scanning signal line 14, a source terminal connected to the data signal line 13, and a drain terminal connected to one pixel 15 of the display element. That is, the display device 10 is provided with m (row direction) × n (column direction) pixels 15. The display device 10
A liquid crystal is used as the display pixel 15.

The data signal line 13 is connected to the data driving circuit 11, and the scanning signal line 14 is connected to the scanning driving circuit 12. Hereinafter, the internal configurations of the data drive circuit 11 and the scan drive circuit 12 will be described with reference to FIGS.
It will be described based on.

First, the data drive circuit 11 will be described with reference to FIGS. 3 and 4. FIG. 3 is a block diagram showing a schematic configuration of the data driving circuit 11. The data drive circuit 11 includes a data signal Data, which is image data for one line, and a data drive start signal SS used to start a drive operation of the circuit 11 to the data signal line 13.
P and two data operation clock signals SCK and SCKB which are used for sequentially driving the data signals Data1 to Data obtained by dividing the data signal Data for each pixel to the respective data signal lines 13 are input.

The signal SCKB is an inverted signal of the signal SCK, and when distinguishing the signals SCK and SCKB, the signal SCK is referred to as a "data operation clock signal".
The signal SCKB will be referred to as a "data operation clock inversion signal".

The data driving circuit 11 is provided with a shift register group 20 composed of (m + 3) shift registers 21 connected in series. In addition, the shift register 21 of each connection stage is provided with symbols S0 to S (m +) from the upstream side.
It will be distinguished by adding 2). Here, the reference numeral of the shift register of the first stage is S0 because the shift register S0 of the first stage does not drive the output of the data signal Data to the data signal line 13 for the reason described later.

FIG. 4 is a block diagram showing a schematic structure of the shift register 21. The shift register 21 has an RS
An -FF (flip-flop) circuit 23 and an AND gate 24 are provided. In the shift register 21, the signals input from the set terminal S and the reset terminal R are input to the set terminal S ′ and the reset terminal R ′ of the RS-FF circuit 23, respectively, and output from the output terminal Q ′ of the RS-FF circuit 23. The output signal and the signal input from the clock terminal CK are input to the AND gate 24 and AN
The signal output from the D gate 24 is output from the output terminal Q.

When the pulse signal is input to the set terminal S, the shift register 21 having the above structure has the RS-FF circuit 2
The output signal of 3 becomes H level, and the signal input from the clock terminal CK is output from the output terminal Q. When a pulse signal is input to the reset terminal R, RS
The output signal of the -FF circuit 23 becomes L level, and the output signal from the output terminal Q is maintained at L level.

As the internal structure of the shift register 21, in addition to the RS-FF circuit 23 shown in FIG.
Various FF circuits such as a circuit can be used.

Referring again to FIG. 3, the shift register S0 at the first stage has a set terminal S to which a data drive start signal SSP is applied.
Of the output signal S of the FF circuit S1 at the next stage to the reset terminal R
The data operation clock inversion signal SCKB is input to the clock terminal CK of the Q1 and the output signal Q0 is output from the output terminal Q.

The second to (m + 2) th stage shift registers Si (1≤i≤m + 1, i is an integer) have output terminals SQ (i) of the preceding stage shift register S (i-1) at the set terminal S.
-1) is the shift register S of the next stage at the reset terminal R
The output signal SQ (i + 1) of (i + 1) is input, and the output signal SQi is output from the output terminal Q. The data operation clock signal SCK is input to the clock terminal CK of the shift register Si when the connection stage is an even stage, and the inverted signal SCKB thereof is input when the connection stage is an odd stage.

The (m + 3) th stage shift register S (m +
2) is a shift register S (m +
The output signal SQ (m + 1) of 1) is the output signal SQ (m + 2) of its own at the reset terminal R, and the data operation clock signal SCK or its inverted signal SCK at the clock terminal CK.
B (depending on whether it is an even stage or an odd stage) is input, and an output signal Q (m + 2) is output from an output terminal Q.

Further, the data driving circuit 11 includes the second stage
A switch element 22 for turning on / off the output of the data signal Data to the data signal line 13 based on the output signals SQ1 to SQm of the (m + 1) th stage shift registers S1 to Sm is provided. Here, it is assumed that the switch element 22 is turned on when the output signal input from the shift register 21 is at the H (high) level.

The data driving circuit 11 having the above structure has the same structure as the data driving circuit 11 in the conventional matrix type display device 100 shown in FIG. The operation of the data driving circuit 11 will be described with reference to FIG.

FIG. 9 shows the shift registers S0 to S (m + 2) of the data drive circuit 11 for the data drive start signal SSP and the data operation clock signals SCK and SCKB.
Output signals SQ0 to SQ (m + 2), data signal Data, and signal SL output to each data signal line 13.
It is a timing chart which shows the time change of 1-SLm. Here, the output signals SQ0 to SQ (m + 2) will be described, and the data signal Data and the signal SL1 will be described.
~ SLm will be described later.

First, in the data drive circuit 11, the shift register S0 at the first stage receives the data operation clock inversion signal SC input to the clock terminal CK when the data drive start signal SSP input to the set terminal S becomes H level.
KB is output from the output terminal Q as the output signal SQ0.

Output signal SQ of the first-stage shift register S0
0 becomes H level based on the data operation clock inversion signal SCKB, the second-stage shift register S1 to which the output signal SQ0 is input to the set terminal S is connected to the data operation clock signal SCK input to the clock terminal CK. Is output as the output signal SQ1.

Output signal S of the second stage shift register S1
When Q1 becomes H level based on the data operation clock signal SCK, the third stage shift register S2 to which the output signal SQ1 is input to the set terminal S is
The data operation clock inversion signal SCKB input to K is output as the output signal SQ2.

Further, in the first-stage shift register S0 to which the output signal SQ1 of the second-stage shift register S1 is input to the reset terminal R, the scanning drive start signal SSP input to the set terminal S is set to the H level again. Until the output signal S is inverted regardless of the data operation clock inversion signal SCKB.
Maintain Q0 at L level.

The output signal S of the third-stage shift register S2
When Q2 becomes H level based on the data operation clock inversion signal SCKB, the output signal SQ2 changes to the set terminal S.
The shift register S3 of the fourth stage, which is input to, outputs the data operation clock signal SCK input to the clock terminal CK as the output signal SQ3.

Further, in the second-stage shift register S1 whose output signal SQ2 from the third-stage shift register S2 is input to the reset terminal R, the output signal SQ0 from the first-stage shift register S0 input to the set terminal S is received. The output signal SQ1 is maintained at the L level regardless of the data operation clock signal SCK until it becomes the H level again.
The same process is performed up to the two-stage shift register S (m + 1).

Shift register S (m + 1) of the (m + 2) th stage
Output signal SQ (m + 1) of H level based on the data operation clock signal SCK, the output signal SQ
(M + 1) is input to the set terminal S at the final stage (m + th)
The shift register S (m + 2) of three stages has a data operation clock inversion signal SCKB input to the clock terminal CK.
Is output as an output signal SQ (m + 2).

When the output signal SQ (m + 2) of the final stage shift register S (m + 2) becomes H level based on the data operation clock inversion signal SCKB, the output signal SQ is output.
The (m + 2) th shift register S (m + 1) of the (m + 2) th stage input to the reset terminal R outputs the output signal SQm of the (m + 1) th stage shift register Sm of the set terminal S.
Until the signal goes high again, the data operation clock signal S
The output signal SQ (m + 1) is maintained at the L level regardless of CK.

Further, the final stage shift register S (m +
2), since the output signal SQ (m + 2) is input to its own reset terminal R, when the output signal SQ (m + 2) becomes H level based on the data operation clock inversion signal SCKB, it is input to the set terminal S. The output signal SQ (m + 1) of the (m + 2) th-stage shift register S (m + 1) becomes H again.
Data operation clock inversion signal SCK until level
The output signal SQ (m + 2) is maintained at the L level regardless of B.

From the above, in the data drive circuit 11, the output signal SQ0 of the first stage shift register S0 becomes H level when the data drive start signal SSP becomes H level, and thereafter, the data operation clock signals SCK and SCKB become H level. Each time the level shifts to the level, the shift register whose output signal becomes the H level shifts to the downstream stage, and the shift register S at the final stage
It can be seen that the output signal SQ (m + 2) of (m + 2) serves as a trigger signal and the operation of the shift register group 20 ends.

As is apparent from FIG. 9, the second stage ...
Output signals SQ1 to SQ of the (m + 2) th stage shift register
The period in which (m + 1) is at the H level is a half cycle of the data operation clock signals SCK and SCKB. On the other hand, since the data drive start signal SSP and the data operation clock inversion signal SCKB are not always synchronized during the period when the output signal SQ0 of the first stage shift register is at the H level,
As shown in FIG. 9, the data operation clock signal SCK · S
It may be shorter than the half cycle of CKB.

Therefore, the output signal SQ0 of the first-stage shift register is not used for controlling the transfer of the data signal Data to the data signal line 13. Similarly, the output signal SQ (m + 2) of the final-stage shift register has a trigger shape as shown in FIG. 9, and is not used for the transfer control.

Further, the data operation clock signal SCK.S
When the cycle of CKB is short, the trigger width of the output signal SQ (m + 2) of the shift register of the final stage is also short, and the shift register S (m + 1) of the m + 2th stage reset by the output signal SQ (m + 2) is normal. May not be reset to. Therefore, in the present embodiment, the last stage 1
The output signal SQ (m + 1) of the (m + 2) th stage shift register, which is the immediately preceding stage, is not used for the transfer control.

However, the final stage shift register S
By providing a delay circuit or the like at (m + 2) to lengthen the trigger width of the output signal SQ (m + 2) so that the shift register S (m + 1) at the (m + 2) th stage is accurately reset, Output signal SQ of shift register
(M + 1) can be used for the transfer control.

Next, the scan drive circuit 12 and the scan operation clock signals GCK1A · G input to the scan drive circuit 12
The scan clock generation circuit 40 for generating CK2A will be described with reference to FIGS. 2 and 5. FIG. 5 is a block diagram showing a schematic configuration of the scan drive circuit 12. The scan drive circuit 12 includes a scan drive start signal GS used to start a drive operation of the scan signal line 14 of the circuit 12.
P and the scanning operation clock signals GCK1A and GCK2A used for sequentially driving the scanning signal lines 14 are input.

The signal GCK2A is a signal obtained by delaying the signal GCK1A by a half cycle as shown in FIG. 6, and when the signals GCK1A and GCK2A are distinguished, the signal GCK2A is separated.
The CK1A will be referred to as a "first scanning operation clock signal" and the signal GCK2A will be referred to as a "second scanning operation clock signal".

As described above, the scanning operation clock signal is
The scan signal line 14 is driven to drive the data signal D for one line.
This is the timing at which ata is transferred to the pixel 15 via the data signal line 13.

At the timing of setting the scanning operation clock signal to the H level, that is, the timing of setting the scanning signal GL to the H level, the data signal Data1 of the first pixel of the data signals Data for one line is transferred to the data signal line 13. Before doing so. In addition, the timing of setting the scanning operation clock signal to the L level, that is, the timing of setting the scanning signal GL to the L level is the last pixel data signal D.
It is only necessary to transfer the tam to the data signal line 13.

Referring to the timing chart of FIG. 9,
For example, the timing at which the data driving start signal SSP becomes H level can be used as the timing at which the scanning operation clock signal becomes H level, and the m + 2th stage in the data driving circuit 11 can be used as the timing at which the scanning operation clock signal becomes L level. It can be seen that the output signal SQ (m + 1) from the shift register S (m + 1) can be used.

Therefore, in the present embodiment, the scan clock generation circuit 40 uses the data drive start signal SSP and the output signal SQ (m + 1) to scan the operation clock signal GC.
It shall generate K1A and GCK2A.

FIG. 2 is a block diagram showing the internal configuration of the scan clock generation circuit 40 in this embodiment. The scan clock generation circuit 40 includes an RS-FF circuit 41, DF
An F circuit 42, an inverter 43, and two NOR circuits 44 and 45 are provided.

In the RS-FF circuit 41, the data drive start signal SSP is input to the set terminal S and the reset terminal R
The output signal SQ (m + 1) is input to.

In the D-FF circuit 42, the inverted output signal from its own inverted output terminal Q / is input to the data terminal D,
The output signal SQ (m + 1) is input to the clock terminal CK via the inverter 43, and the scan drive start signal GSP is input to the reset terminal RES. When the H-level signal is input to the reset terminal RES, the D-FF circuit 42 changes the signal level of the output signal from the output terminal Q to L.
It is assumed that the level is set.

The first NOR circuit 44 has an inverted output signal from the inverted output terminal Q / of the RS-FF circuit 41 and a D-F signal.
The output signal from the output terminal Q of the F circuit 42 is input,
The first scanning operation clock signal GCK1A is output. In addition, the second NOR circuit 45 is the RS-FF circuit 4
1 inverted output signal from the inverted output terminal Q /, and D-FF
The inverted output signal from the inverted output terminal Q / of the circuit 42 is input, and is output as the second scanning operation clock signal GCK2A.

Next, the internal structure of the scan drive circuit 12 will be described with reference to FIG. The scan drive circuit 12 includes
A shift register group 30 composed of (n + 1) shift registers 31 connected in series is provided. The shift registers 31 at the respective connection stages will be distinguished from each other by adding the symbols G1 to G (n + 1) from the upstream side.

Since the internal structure of the shift register 31 of the scan drive circuit 12 is the same as the internal structure of the shift register 21 of the data drive circuit 11 shown in FIG. 4, the description thereof will be omitted. In addition to the RS-FF circuit 23 shown in FIG. 4, various FF circuits such as a D-FF circuit can be used as the internal configuration of the shift register 31.

In the first-stage shift register G1, the set drive terminal S receives the scan drive start signal GSP, the reset terminal R receives the output signal GQ1 of the next-stage shift register G1, and the clock terminal CK receives the second scan operation clock signal GCK2A. Each is input, and the output signal GQ1 is output from the output terminal Q.

The shift registers Gj (2
.Ltoreq.j.ltoreq.n, j is an integer), the output signal GQ (j-1) of the shift register G (j-1) in the previous stage is set to the set terminal S, and the output signal GQ (j-1) of the shift register G (j + 1) in the next stage is set to the reset terminal R The output signal GQ (j + 1) is input to each of the output terminals Q
To output an output signal GQj. The shift register G
The first scanning operation clock signal GCK1A is input to the clock terminal CK of j when the connection stage is an even number stage, and the second scanning operation clock signal GCK2A is input when the connection stage is an odd number stage.

The (n + 1) th stage shift register G (n +
In 1), the output signal GQn of the shift register Gn of the previous stage is set to the set terminal S and the output signal GQn of its own is set to the reset terminal R
(N + 1) receives the first or second scanning operation clock signals GCK1A and GCK2A (depending on whether it is an even stage or an odd stage) at the clock terminal CK, and outputs the output signal Q (n + 1) from the output terminal Q.

The operation of the matrix type display device 10 having the above structure will be described with reference to FIG. FIG. 6 shows the scanning operation clock signal G generated by the scanning clock generation circuit 40.
It is a timing chart which shows the time change of CK1A * GCK2A. The data operation clock signal SCK, the data operation clock inversion signal SCKB, the data drive start signal SSP, and the output signals SQ0 to SQ of the shift registers S0 to S (m + 1) in the data drive circuit 11 shown in FIG.
(M + 1) and the scan drive start signal GSP are the same as those of the conventional one shown in FIGS. 9 and 11.

First, the scan drive start signal GSP changes to D-FF.
By being input to the circuit 42, the output signal from the terminal Q of the D-FF circuit 42 becomes L level and the inverted output signal from the terminal Q / becomes H level. As a result, in the second scanning operation clock signal GCK2A output from the second NOR circuit 45, the output signal SQ (m + 1) is D-
The L level is maintained until it is input to the FF circuit 42.

At this time, since the inverted output signal from the terminal Q / of the RS-FF circuit 41 is at the H level, the first
The first scanning operation clock signal GCK1A output from the NOR circuit 44 remains at the L level.

Next, when the data drive start signal SSP becomes H level, the inverted output signal from the terminal Q / of the RS-FF circuit 41 becomes L level, so that the first scanning operation clock signal GCK1A becomes H level. Become.

As a result, the output signal GQ1 from the first-stage shift register G1 in the scan drive circuit 12 becomes H level, so that the scan drive circuit 12 outputs the first scan signal line 14
When the scanning signal GL1 output above goes to H level,
The FET 16 connected to the scanning signal line 14 is turned on. Then, the data operation clock signal SCK / SCK
Based on B, the data signals Data1 to Data divided for each pixel are data signal lines 13 and FE.
The image is transferred to the pixel 15 via T16, and an image of one line is displayed.

The m-th data signal Datam passes through the m-th data signal line 13 and the FET 16 and the pixel 1
5, the output signal SQ (m +) of the (m + 2) th stage shift register S (m + 1) in the data driving circuit 11 is transferred.
1) becomes H level based on the data operation clock signal SCK. At this time, R of the scan clock generation circuit 40
In the S-FF circuit 41, since the H-level signal is input to the reset terminal R, the inverted output signal from the terminal Q / becomes H-level. As a result, the first scanning operation clock signal GCK1A output from the first NOR circuit 44 becomes L
Become a level.

Next, when the output signal SQ (m + 1) becomes L level based on the data operation clock signal SCK, the D-FF circuit 42 of the scan clock generating circuit 40
Since an H level signal is input to the clock terminal CK,
The output signal from the output terminal Q becomes L level, and the inverted output signal from the inverted output terminal Q / becomes H level. As a result, the first scanning operation clock signal GCK1A output from the first NOR circuit 44 becomes the next output signal SQ.
The L level is maintained until (m + 1) is input to the D-FF circuit 42.

Hereinafter, the second scanning operation clock signal GCK
2 is H when the data drive start signal SSP becomes H level, like the first scanning operation clock signal GCK1 described above.
When the output signal SQ (m + 1) becomes H level, it becomes L level. And the output signal SQ
When (m + 1) becomes L level, the second scanning operation clock signal GCK2 maintains L level until the next output signal SQ (m + 1) is input to the D-FF circuit 42.

Thereafter, the above operation is repeated up to the last scanning signal line 14 to display an image of one frame on the display element. Then before you start displaying the next image,
There is a vertical blanking period. In the vertical blanking period, the above-described image display operation is unnecessary, so the data drive start signal SS
It is desirable to maintain P at L level. At this time, the scanning operation clock signals GCK1A and GCK2A generated from the scanning clock generation circuit 40 are also maintained at the L level.

Comparative Example Next, as a comparative example of the present embodiment, a conventional active matrix type display device will be described with reference to FIGS. 8 to 11. In addition, the configuration having the same function as the configuration described in the above-described embodiment,
The same reference numerals are given and the description thereof is omitted.

FIG. 8 is a block diagram showing a schematic structure of a conventional active matrix type display device. The conventional display device 100 is the display device 10 of the present embodiment shown in FIG.
In comparison with the above, the configuration of the scan clock generation circuit 40 is omitted, and a scan drive circuit having a configuration different from the scan drive circuit 12 in that a scan operation clock signal is input to the scan drive circuit from the outside of the apparatus is provided. Except for this point, the other configurations are the same.

FIG. 10 is a block diagram showing a schematic structure of the scan drive circuit 110. The scan driving circuit 110 is
Compared to the scan drive circuit 12 shown in FIG. 5, the shift register G0 is added on the upstream side of the shift register G1 that drives the first scan signal line 14, and other configurations are the same.

In the scan driving circuit 110, the scan operation clock signals GCK1 and GCK2 are input from the outside of the device 100. The signal GCK2 is a signal obtained by delaying the signal GCK1 by a half cycle as shown in FIG. 11, and when the signals GCK1 and GCK2 are distinguished, the signal GCK1 is used.
Is referred to as a "first scanning operation clock signal", and the signal GCK
2 will be referred to as a "second scanning operation clock signal".

FIG. 11 shows shift registers G0 to G (n + 1) of the scan drive circuit 110 in response to the scan drive start signal GSP and the scan operation clock signals GCK1 and GCK2.
3 is a timing chart showing the time change of the output signals GQ0 to GQ (n + 1) from the above. It should be noted that the second stage to the (n +
1) Output signals GQ from the stage shift registers G1 to Gn
1 to GQn are signals GL output to each scanning signal line 14.
1 to GLn. The period a during which the scanning operation clock signals GCK1 and GCK2 are at the H level is slightly longer than the image transfer period for one line shown in FIG.

Output signals GQ0 to GQ from the shift registers G0 to G (n + 1) of the scan drive circuit 110 shown in FIG.
The operation of Q (n + 1) is performed by the data driving circuit 11 shown in FIG.
Output signal S from the shift registers S0 to S (m + 2)
Since the operation is the same as Q0 to SQ (m + 2), detailed description thereof will be omitted.

Therefore, in the scan drive circuit 110, when the scan drive start signal GSP goes high, the output signal GQ0 of the first-stage shift register G0 goes high,
Hereinafter, each time the scanning operation clock signals GCK1 and GCK2 become H level, the shift register whose output signal becomes H level shifts to the downstream stage, and the shift register S (n
It can be seen that the output signal SQ (n + 1) of +1) becomes a trigger signal and the operation of the shift register group 111 ends.

For the same reason as in the case of the data driving circuit 11, the output signals GQ0 and GQ (n + 1) of the first-stage and last-stage shift registers are not used for driving control of the scanning signal line 14.

However, the scanning operation clock signal GCK1A.
GCK2A is a data operation clock signal SCK / SCK
Since the cycle is remarkably longer than that of B, the trigger width of the output signal GQ (n + 1) of the final stage shift register can be ensured to be long enough to normally reset the nth stage shift register Gn. Therefore, in the scan drive circuit 12, the output signal GQn of the shift register at the nth stage, which is one stage before the final stage, is used for drive control of the scan signal line 14.

In the display device 100 having the above structure, first, as shown in FIG. 11, after the second scanning operation clock signal GCK2 becomes H level, the scanning drive start signal G
When SP becomes H level, the output signal GQ0 of the first stage shift register G0 becomes H level. Next, when the second scanning operation clock signal GCK2 becomes L level, the output signal GQ0 of the first stage shift register G0 becomes L level.

Then, the first scanning operation clock signal GC
When K1 goes high, the second-stage shift register G1
Output signal GQ1 goes high and the scan signal GL1 output on the first scan signal line 14 goes high, so that the FET 16 connected to the first scan signal line 14 is turned on.

Next, as shown in FIG. 9, when the data drive start signal SSP goes to H level after the data operation clock inversion signal SCKB goes to H level, the data drive circuit 11 shifts the shift register S0 of the first stage. Output signal SQ0
Becomes H level.

Next, the data operation clock inversion signal SCK
When B becomes L level, the output signal SQ0 of the first stage shift register S0 becomes L level. At the same time, the data operation clock signal S input to the second-stage shift register S1
Since CK becomes H level, the second stage shift register S
The output signal SQ1 of 1 becomes H level, and the first switch element 22 connected to the shift register S1 of the second stage is turned on.

At this time, the data signal Data1 divided into pixel units is input to the data drive circuit 11, and the first
Output to the first data signal line 13 via the switch element 22 of the above, and to the pixel 15 in the first row and first column via the FET connected to the first scanning signal line 14, Reference numeral 15 provides a display according to the data signal Data1.

Next, the data operation clock signal SCK becomes L
When the level becomes the level, the output signal SQ1 of the second-stage shift register S1 becomes the L level, the first switch element 22 connected to the shift register S1 is turned off, and the first switch element 22 is turned off.
The scanning signal line 13 becomes the high impedance (Hi-Z) state, and the transfer of the data signal to the pixel 15 in the first row and the first column is completed.

At the same time, since the data operation clock inversion signal SCKB input to the shift register S2 of the third stage becomes the H level, the output signal SQ2 of the shift register S2 of the third stage becomes the H level and the third stage Shift register S
The second switch element 22 connected to 2 is turned on.

At this time, the data signal Data2 divided into pixel units is input to the data driving circuit 11, and the second signal
Is output to the second data signal line 13 via the switch element 22 and is output to the pixel 15 in the first row and second column via the FET connected to the first scanning signal line 14, Reference numeral 15 performs display according to the data signal Data2.

Hereinafter, the data operation clock signal SCK.S
A data signal is transferred to the pixel 15 in each column of the first row based on CKB. After the data signal is transferred to the pixel 15 in the first row and the m-th column, when the data operation clock inversion signal SCKB becomes L level, the output signal SQm of the (m + 1) th stage shift register Sm becomes L level and the shift register S
The m-th switch element 22 connected to the m-th switch is turned off, and the m-th scanning signal line 13 has a high impedance (Hi
In the −Z) state, the transfer of the data signal to the pixel 15 in the first row and the m-th column ends, and as a result, the transfer of the image data of one line to the pixel 15 in the first row ends.

When the transfer is completed, as shown in FIG. 11, the first scanning operation clock signal GCK1 becomes L level, the output signal GQ1 of the second-stage shift register G1 becomes L level, and the first scanning operation clock signal GCK1 becomes L level. Since the scanning signal GL1 output on the scanning signal line 14 is at the L level, the FET 16 connected to the first scanning signal line 14 is turned off.

Next, the second scanning operation clock signal GCK
When 2 becomes H level, the output signal GQ2 of the third-stage shift register G2 becomes H level, and the scanning signal GL2 output on the second scanning signal line 14 becomes H level. The FET 16 connected to the scanning signal line 14 is turned on, and the above operation is repeated up to the last scanning signal line 14 to display one frame image on the display element.

The matrix type display device 10 of the present embodiment.
And a conventional matrix type display device 100 shown in a comparative example.
By comparing with, it can be understood that the matrix type display device 10 of the present embodiment has the following effects.

The matrix type display device 10 of this embodiment.
Is the data drive start signal SSP and the data drive circuit 11
Of the output signals SQ (m +
1) and the scanning operation clock signal GCK1A
Since GCK2A is generated, it is not necessary to supply the scanning operation clock signals GCK1A and GCK2A from outside the device. As a result, the circuit for generating the scanning operation clock signal is not required for the external circuit, so that the number of parts of the external circuit can be reduced and the wiring for transmitting the scanning operation clock signal from the external circuit to the display device is unnecessary. Therefore, the number of connection wirings between the external circuit and the display device can be reduced.

After the image transfer for one line is completed,
Using the output signal SQ (m + 1), the scanning signal line 1
Since the timing for setting 4 to the L level is taken, it is not necessary to newly provide a circuit for taking this timing, and as a result, it is possible to prevent the display device 10 from increasing in size and increasing the number of parts.

By maintaining the data drive start signal SSP at the L level during the vertical blanking period, the scan clock generation circuit 40 does not perform the drive operation, so that the power consumption of the scan clock generation circuit 40 can be suppressed. it can.

In the scan clock generation circuit 40 of this embodiment, after the scan drive start signal GSP goes to H level, the scan operation clock signals GCK1A and GCK2A go to H level after the data drive start signal SSP goes to H level.
Since it becomes the level, the scanning operation clock signal GCK1A
There is no possibility that the period when GCK2A becomes H level becomes short.

Therefore, the scanning operation clock signal GCK1A
Since the period when GCK2A first becomes H level can be devoted to the period for driving the first scanning signal line 14,
The first stage shift register G0 in the scan driving circuit 110 shown in FIG. 10 can be omitted. As a result, the number of components in the scan drive circuit 110 can be reduced,
The circuit scale can be reduced.

In this embodiment, the scan operation clock signals GCK1A and GCK2A are generated by using the data drive start signal SSP and the output signal SQ (m + 1) of the (m + 2) th stage shift register in the data drive circuit 11. However, any signal can be used as long as the timing chart shown in FIG. 6 can be obtained.

For example, since the timing of the data drive start signal SSP and the timing of the output signal SQ0 of the first-stage shift register in the data drive circuit 11 are almost the same, instead of the data drive start signal SSP, Even if the output signal SQ0 is used, the same effect as that of the present embodiment can be obtained.

Further, in this embodiment, in order to shift the scanning operation clock signals GCK1A and GCK2A from H level to L level, the output signal SQ (m + 1) of the (m + 2) th stage shift register in the data driving circuit 11 is changed. However, by providing a counter circuit, a delay circuit, etc. in the scan drive circuit 12, the scan operation clock signal GCK1 is used.
If the A.GCK2A goes to H level and then goes to L level after a lapse of a predetermined period, the output signal SQ
There is no need to use (m + 1).

Further, in the matrix type display device 10 of the present embodiment, each constituent element can be formed on the same substrate. In this case, since the scan clock generation circuit 40 can be manufactured in the same process as the data drive circuit 11 and the scan drive circuit 12, the manufacturing cost can be suppressed more than when the scan clock generation circuit 40 is provided outside the device.

[Embodiment 2] Next, another embodiment of the present invention will be described with reference to FIG. It should be noted that configurations having the same functions as the configurations described in the related art and the embodiments described above are designated by the same reference numerals, and the description thereof will be omitted.

The display device of the present embodiment is provided with a shift register group having a configuration different from that of the shift register group in the scan drive circuit as compared with the display device of the embodiment shown in FIG. It is the same. FIG. 7 is a block diagram showing a schematic configuration of the scan drive circuit 12 in this embodiment. The shift register group 50 in the scan drive circuit 12 is different from the shift register group 30 in the scan drive circuit 12 shown in FIG. 5 in that the shift registers G1 to Gn other than the final shift register are provided with a reset function. However, other configurations are the same.

The display device 10 of the present embodiment is suitable for displaying only a part of the pixels 15. For example, 1
When displaying Y lines (Y is a natural number) from the second line, when the image of the Yth line is displayed, the data drive start signal SSP is not input. Therefore, in the display device 10 shown in FIGS. 1 to 3, the scanning operation clock signal GCK1A generated by the scanning clock generation circuit 40 is generated.
・ GCK2A is maintained at L level. At this time, in order to display the next image, when the scan drive start signal GSP and the data drive start signal SSP are input, the image is displayed from the (Y + 1) th line.

In the scan drive circuit 12 of this embodiment, the first-stage to n-th stage shift registers G1 to Gn (51) are provided.
Is provided with a new reset terminal RES, and the scan drive start signal GSP is input to the reset terminal RES.

As a result, the display device 10 of the present embodiment.
Even when the display is performed only on some of the pixels 15, the shift register 51 is reset when the scan drive start signal GSP is input to display the next image.
Based on the scanning operation clock signals GCK1A and GCK2A, it is possible to sequentially drive again from the first scanning signal line 14.

Since the shift register G (n + 1) at the final stage in the scan drive circuit 12 is reset by its own output signal, it is not necessary to provide a new reset terminal RES.

In the above embodiment, the scan drive circuit 12 uses the two scan operation clock signals GCK1A.GC.
The scanning signal lines 14 are sequentially driven based on K2A. However, the present invention can be applied to a configuration in which the scanning signal lines are sequentially driven based on one scanning operation clock signal. In this case, the output signal from the output terminal Q (not shown) in the RS-FF circuit 41 of the scan clock generation circuit 40 shown in FIG. 2 becomes the scan operation clock signal.

[0135]

As described above, in the matrix type display device of the present invention, the display element, the plurality of data signal lines and the plurality of scanning signal lines for driving the display element, the data signal line and the scanning signal are provided. A matrix type display device including a data drive circuit and a scan drive circuit for driving each line, wherein data drive start input to the data drive circuit in order to start transferring an image data signal for one line to a data signal line The configuration includes a scan clock generation circuit that generates a scan operation clock signal to be output to the scan drive circuit using the signal.

As a result, since the scanning operation clock signal is generated by using the data drive start signal, it becomes unnecessary to supply the scanning operation clock signal from outside the device. As a result, a circuit for generating the scanning operation clock signal is not required for the external circuit, which has the effect of reducing the number of parts of the external circuit and does not require wiring for transmitting the scanning operation clock signal from the external circuit to the display device. Therefore, the effect of reducing the number of connection wirings between the external circuit and the display device is obtained.

Further, since the scanning operation clock signal uses the data driving start signal to set the timing for starting the driving of the scanning signal line, it is necessary to newly provide a circuit for setting the timing. As a result, there is an effect of suppressing an increase in the size of the display device and an increase in the number of parts.

Further, as described above, in the matrix type display device of the present invention, in the above structure, the data driving circuit includes a shift register group in which a plurality of shift registers are connected in series, and a plurality of the shift register groups are provided. At least a part of the shift register drives each of the data signal lines, and the scan clock generation circuit uses the data drive start signal and the output signal of the shift register to generate a scan operation clock signal. This is the configuration to generate.

Accordingly, the scanning operation clock signal uses the output signal of the shift register in the data driving circuit to set the timing for ending the driving of the scanning signal line. It is not necessary to newly dispose, and as a result, it is possible to suppress an increase in the size and the number of parts of the display device.

As described above, the matrix type display device of the present invention includes the display element, the plurality of data signal lines and the plurality of scanning signal lines, the data driving circuit and the scanning driving circuit. In the matrix type display device, the data driving circuit includes a shift register group in which a plurality of shift registers are connected in series, and at least a part of the plurality of shift registers drives each data signal line. In this configuration, a scan clock generation circuit that generates a scan operation clock signal to be output to the scan drive circuit using the output signal of the shift register is provided.

As a result, since the scanning operation clock signal is generated by using the output signal of the shift register in the data driving circuit, it becomes unnecessary to supply the scanning operation clock signal from outside the device. As a result, the circuit for generating the scanning operation clock signal is not required in the external circuit,
In addition to the effect of reducing the number of parts of the external circuit, the effect of reducing the number of connecting wires between the external circuit and the display device is eliminated because the wiring for transmitting the scanning operation clock signal from the external circuit to the display device is unnecessary.

As the scanning operation clock signal, the output signal of the shift register in the data driving circuit is used,
Since the timing for ending the driving of the scanning signal line is set, it is not necessary to newly provide a circuit for setting the timing, and as a result, it is possible to suppress an increase in the size and the number of parts of the display device.

As described above, in the matrix type display device of the present invention, in the above structure, the scanning clock generation circuit uses the output signal of the first-stage shift register provided in the data driving circuit. .

As a result, the scanning operation clock signal generated by using the output signal of the first-stage shift register can be set to the timing before the output of the image data signal to the data signal line is started. By inputting the signal to the scan drive circuit, the scan signal line can be driven before the output of the image data signal to the data signal line is started.

As described above, in the matrix type display device of the present invention, in the above structure, the display element, the plurality of data signal lines, the plurality of scanning signal lines,
The data drive circuit, the scan drive circuit, and the scan clock generation circuit are formed on the same substrate.

With this, the scan clock generation circuit can be manufactured in the same process as the data drive circuit and the scan drive circuit, so that the manufacturing cost can be suppressed more than the case where the scan clock generation circuit is provided outside the apparatus.

As described above, the matrix-type display device of the present invention has the above-mentioned structure in which the scanning clock generation circuit generates the scanning operation clock signal after the scanning drive start signal is input.

As a result, the circuit for synchronizing the scan drive start signal and the scan operation clock signal can be omitted, and as a result, the number of components in the scan drive circuit can be reduced and the circuit scale can be reduced. It has the effect of being able to.

As described above, in the matrix type display device of the present invention, in the above structure, the scan drive circuit includes a shift register group in which a plurality of shift registers are connected in series, and the plurality of shift registers are provided. At least a part of the register drives each scanning signal line, and the shift register that drives each scanning signal line has a function of being reset by input of a scanning drive start signal.

Thus, after being displayed on some pixels,
Even when the next image is displayed, there is an effect that it operates normally.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a matrix type display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a scan clock generation circuit in this embodiment.

FIG. 3 is a block diagram showing an internal configuration of a data driving circuit shown in FIG.

4 is a block diagram showing an internal configuration of a shift register used in the data drive circuit and scan drive circuit shown in FIG. 1. FIG.

5 is a block diagram showing an internal configuration of the scan drive circuit shown in FIG. 1. FIG.

FIG. 6 is a timing chart showing a time change of a scanning operation clock signal generated by a scanning clock generation circuit in the present embodiment.

FIG. 7 is a block diagram showing an internal configuration of a scan drive circuit in a matrix type display device according to another embodiment of the present invention.

FIG. 8 is a block diagram showing a schematic configuration of a conventional matrix type display device.

9 is a timing chart showing a time change of a signal relating to the data driving circuit shown in FIG.

10 is a block diagram showing an internal configuration of the scan drive circuit shown in FIG.

FIG. 11 is a timing chart showing a time change of a signal regarding the scan driving circuit shown in FIG.

[Explanation of symbols]

10 matrix display device 11 data drive circuit 12 scan drive circuit 13 data signal line 14 scan signal line 20 shift register group 21 in data drive circuit shift register 30 in data drive circuit shift register group 31 in scan drive circuit 31 scan drive Shift register 40 in circuit Scan clock generation circuit 50 Shift register group 51 in scan drive circuit Shift register GCK1A in scan drive circuit Scan operation clock signal GCK2A Scan operation clock signal GSP Scan drive start signal SQ0 to SQ (m + 2) Data drive Output signal of shift register in circuit SSP Data drive start signal

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 622P 623 623H F term (reference) 2H093 NC16 NC22 NC34 ND49 ND54 5C006 AF42 AF51 AF53 AF72 BB16 BC03 BC11 BC20 BF03 BF06 BF26 EB04 EB05 FA42 5C080 AA05 AA06 AA10 BB05 DD23 DD27 DD28 FF11 JJ02 JJ03 JJ04

Claims (7)

[Claims] 1. A display element, a plurality of data signal lines and a plurality of scanning signal lines for driving the display element, and a data driving circuit and a scanning driving circuit for respectively driving the data signal line and the scanning signal line. A matrix type display device comprising: a scanning operation for outputting to a scan drive circuit by using a data drive start signal inputted to a data drive circuit to start transferring an image data signal for one line to a data signal line. A matrix type display device comprising a scanning clock generation circuit for generating a clock signal. 2. A data drive circuit includes a shift register group in which a plurality of shift registers are connected in series, and at least a part of the plurality of shift registers drives each data signal line. The matrix according to claim 1, wherein the scan clock generation circuit generates a scan operation clock signal by using a data drive start signal input to a data drive circuit and an output signal of the shift register. Type display device. 3. A display element, a plurality of data signal lines and a plurality of scanning signal lines for driving the display element, a data driving circuit and a scanning driving circuit for driving the data signal line and the scanning signal line, respectively. In the matrix type display device, the data driving circuit includes a shift register group in which a plurality of shift registers are connected in series, and at least a part of the plurality of shift registers drives each data signal line. A matrix-type display device comprising a scan clock generation circuit that generates a scan operation clock signal to be output to a scan drive circuit using an output signal of the shift register. 4. The matrix type display device according to claim 3, wherein the scan clock generation circuit uses an output signal of a first-stage shift register provided in a data driving circuit. 5. The display element, the plurality of data signal lines, the plurality of scanning signal lines, the data driving circuit, the scanning driving circuit and the scanning clock generating circuit are formed on the same substrate. The matrix type display device according to any one of 1. 6. The matrix type display device according to claim 1, wherein the scan clock generation circuit generates the scan operation clock signal after the scan drive start signal is input. . 7. A scan drive circuit includes a shift register group in which a plurality of shift registers are connected in series, and at least a part of the plurality of shift registers drives each scan signal line. 7. The matrix type display device according to claim 1, wherein the shift register that drives each scanning signal line has a function of being reset by inputting a scanning drive start signal.