JP2003031592A - Junction field effect transistor and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a junction field effect transistor which has high dielectric strength and low loss, and can operate at high frequencies, and to provide its manufacturing method. SOLUTION: This junction field effect transistor has a vertical type structure and on/off characteristics of a normally off type and uses silicon carbide as a semiconductor material as the main component. A channel layer 3 has a drift layer 21 of high impurity concentration and an intrinsic channel layer 23 with low impurity concentration. The intrinsic channel layer 23 is provided with a recessed part 25 for embedding a gate means, and a gate diffusion layer 5 is embedded in the intrinsic channel layer 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a junction field effect transistor having a vertical structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art In this type of junction field effect transistor, one of the problems is how to secure the breakdown voltage while suppressing the channel resistance.

[0003]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a junction field effect transistor which has a high breakdown voltage, low loss and is capable of high frequency operation, and a method of manufacturing the same.

[0004]

A technical means for achieving the above object is a junction type field effect transistor having a vertical structure in which a source electrode and a drain electrode are formed on the front surface side and the back surface side of a semiconductor chip. The impurity concentration of the channel layer is set so as to decrease from the back surface side toward the front surface side, which is the gate means formation side.

Preferably, the junction field effect transistor is formed of silicon, GaAs, silicon carbide, gallium nitride or diamond as a main component semiconductor material.

Further, preferably, the channel layer includes a first semiconductor layer in which the impurity concentration has a first concentration value,
A second semiconductor layer in which the impurity concentration is a second concentration value lower than the first concentration value, is formed above the first semiconductor layer, and is joined to the gate means. Is good.

Further, preferably, the gate means is
A gate diffusion layer formed in the second semiconductor layer and a gate electrode joined to the gate diffusion layer may be provided.

Preferably, the gate means is a gate diffusion layer formed below a recess for embedding formed in the second semiconductor layer from the surface side thereof, and the gate means is embedded in the recess. It is preferable to provide a gate wiring which is joined to the gate diffusion layer.

Further preferably, the gate electrode is
The gate diffusion layer is formed by introducing impurities from a predetermined semiconductor surface and is connected to the gate diffusion layer, or is embedded in a recess for embedding formed in the second semiconductor layer from the surface side thereof and the gate diffusion layer. Good to be connected.

Further, it is preferable that the gate wiring is formed of a refractory metal.

Further, preferably, the gate wiring is
A gate contact portion joined to the gate diffusion layer,
And a gate wiring portion connected to the gate contact portion, wherein the junction field effect transistor has a source wiring formed on the front surface side of the channel layer and a portion between the gate wiring and the source wiring. And a source contact portion that is joined to the channel layer via a source diffusion layer or without a source diffusion layer, and the source wiring is formed on the upper side of the gate wiring portion. And a planar source wiring portion connected to the source contact portion via the insulating layer.

Further, it is preferable that the gate means have a plan view shape and are provided in a scattered manner, and the channel layer is formed so as to surround each gate means. .

Further, the technical means for achieving the above-mentioned object is the method for manufacturing a junction field effect transistor according to claim 1, wherein the impurity concentration is reduced toward the upper side on the semiconductor substrate. The channel layer is formed by homoepitaxial growth so that

A technical means for achieving the above object is the method for manufacturing a junction field effect transistor according to claim 4, wherein the impurity concentration on the semiconductor substrate is the first concentration value. Forming the first semiconductor layer by homoepitaxial growth so that
Forming a second semiconductor layer on the semiconductor layer by homoepitaxial growth so that the impurity concentration has the second concentration value; and using a mask to partially gate the second semiconductor layer. And a step of forming the gate diffusion layer by introducing an impurity for forming a diffusion layer, and a step of forming the gate electrode by introducing an impurity from a predetermined semiconductor surface.

Further, a technical means for achieving the above object is the method for manufacturing a junction field effect transistor according to claim 5, wherein the impurity concentration on the semiconductor substrate is the first concentration value. And a step of forming the first semiconductor layer by homoepitaxial growth so that the second semiconductor layer is vertically divided into two on the first semiconductor layer, Is formed by homoepitaxial growth so that the impurity concentration becomes the second concentration value, and the impurity for forming the gate diffusion layer is partially introduced into the first division layer by using a mask. The step of forming the gate diffusion layer and the second part of the upper second division layer, which is the remaining part of the second semiconductor layer, are homoepitaxially grown so that the impurity concentration becomes the second concentration value. Forming a recess on the gate diffusion layer by partially removing the second division layer located on the gate diffusion layer, and forming the recess on the gate diffusion layer. Exposing at least a part of the upper surface of the gate, forming a side oxide film covering the inner surface of the recess, and forming the gate wiring on the exposed upper surface of the gate diffusion layer. It is characterized by

The technical means for achieving the above object is the method for manufacturing a junction field effect transistor according to claim 5, wherein the impurity concentration is the first concentration value on the semiconductor substrate. Forming the first semiconductor layer by homoepitaxial growth so that
Forming a second semiconductor layer on the semiconductor layer by homoepitaxial growth so that the impurity concentration becomes the second concentration value; and partially removing a part of the second semiconductor layer. To form the concave portion, a step of forming a side surface oxide film covering the inner side surface of the concave portion, and a gate diffusion layer forming portion at a portion of the second semiconductor layer forming the bottom portion of the concave portion using a mask. Partially introduced the impurities of
The method further comprises the steps of forming the gate diffusion layer and forming the gate wiring on the upper surface of the formed gate diffusion layer.

<Description of Terms> The “gate means” according to the present invention has a structure including a gate diffusion layer and a gate electrode (or a gate wiring), and a gate electrode (gate electrode not formed with the gate diffusion layer). Alternatively, a structure having only a gate wiring) is included.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION <First Embodiment> FIG. 1 is a view showing a sectional structure of a junction field effect transistor (hereinafter, simply referred to as “transistor”) according to a first embodiment of the present invention. 6 to 7 are views showing manufacturing steps of the transistor of FIG. 1, FIG. 7 is a plan view showing a configuration of a gate wiring and a source wiring of the transistor of FIG. 1, and FIG. 8 is a configuration of a main part of FIG. It is a fracture | rupture perspective view which shows schematically.

This transistor, as shown in FIG.
A junction-type field effect transistor, which has a vertical structure and a normally-off type on / off characteristic, and which uses silicon carbide as a main component semiconductor material.
+ A semiconductor substrate 1, an N-type channel layer 3 formed on the semiconductor substrate 1, a P + gate diffusion layer 5 embedded in the channel layer 3 corresponding to a predetermined gate pattern,
The gate wiring 7 that also functions as a gate electrode that is joined to the gate diffusion layer 5, and the N + source diffusion layer formed on the channel layer 3 in a region between the gate wirings 7 corresponding to a predetermined source pattern. 9, a source wiring 11 also serving as a source electrode bonded to the source diffusion layer 9, and a drain electrode 13 formed on the lower surface of the semiconductor substrate 1. Among these, the semiconductor substrate 1, the channel layer 3, the gate diffusion layer 5, and the source diffusion layer 9 are formed with silicon carbide as a main component. Further, the gate diffusion layer 5 and the gate wiring 7 correspond to the gate means of the present invention.

The channel layer 3 is formed on the semiconductor substrate 1, and is formed on the drift layer 21 and an N type drift layer (first semiconductor layer) 21 in which the impurity concentration is set to the first concentration value. , And an N-intrinsic channel layer (second semiconductor layer) 23 having an impurity concentration set to a second concentration value lower than the first concentration value. The drift layer 21 and the intrinsic channel layer 23 are formed of silicon carbide as a main component, and various kinds of impurities of a normal degree for achieving a predetermined performance of the transistor are mixed therein. Further, in the present embodiment, the intrinsic channel layer 23 is composed of first and second division layers 23a and 23b formed in two steps.

Here, the drift layer 21 mainly bears the withstand voltage characteristic of this transistor, is formed relatively thick so as to obtain a predetermined withstand voltage characteristic, and has a high impurity content for suppressing the channel resistance. It is set to the density value.

The intrinsic channel layer 23 is mainly responsible for the on / off characteristics of this transistor. When the gate is opened and the application of the control voltage to the gate wiring 7 is released so that this transistor is of the normally-off type, A low impurity concentration value is set so that the conductive path between the source wiring 11 and the drain electrode 13 is pinched off by the depletion layers formed around the left and right gate diffusion layers 5. Therefore, since the intrinsic channel layer 23 has a high resistance value, the thickness (channel length) of the intrinsic channel layer 23 is set to the minimum necessary minimum value.

Further, the intrinsic channel layer 23 is provided with a recess 25 for embedding the gate means. By forming the gate diffusion layer 5 below the recess 25, the gate wiring 7 of the gate diffusion layer 5 is formed. The upper surface 27 to be joined is located below the upper surface 29 of the intrinsic channel layer 23, and accordingly, the gate diffusion layer 5 is completely embedded in the intrinsic channel layer 23. A side surface oxide film 31 of SiO 2 is formed on the inner peripheral side surface of the recess 25 for insulation or the like.

The gate wiring 7 is made of tungsten, titanium,
It is formed of a refractory metal such as nickel (tungsten here). An interlayer insulating film (insulating layer) is provided between the gate wiring 7 and the source wiring 11 formed thereabove.
It is separated and insulated by 33.

Next, the manufacturing process of this transistor will be described. First, N + formed mainly of silicon carbide
The semiconductor substrate 1 is prepared, and surface treatment such as initial cleaning of the semiconductor substrate 1 is performed. Subsequently, as shown in FIG. 2, a drift layer 21 is formed on the semiconductor substrate 1. The drift layer 21 is formed by homoepitaxial growth while mixing a predetermined N-type impurity into silicon carbide so that the impurity concentration becomes the first concentration value. Then, the first dividing layer 23 a of the intrinsic channel layer 23 is formed on the drift 21.
To form. The first division layer 23a is made of silicon carbide with N
It is formed by homoepitaxial growth while mixing predetermined impurities of the mold so that the impurity concentration becomes the second concentration value.

Subsequently, as shown in FIG. 3, an oxide film 35 of SiO2 is formed on the first division layer 23a, and a metal mask layer (here, aluminum film) is formed on the oxide film 35 by sputtering, electron beam evaporation or the like. Forming a mask layer) 37,
By patterning using photoresist and etching (here dry etching (RIE or the like)), the metal mask layer 37 and the oxide film 3 corresponding to the gate pattern are formed.
5 is partially removed. Subsequently, using the patterned metal mask layer 37 and oxide film 35 as a mask, impurities (P-type ions (aluminum ions) here) for forming a gate diffusion layer are formed in the exposed portions of the first division layer 23a. And the gate diffusion layer 5 is formed at a plurality of locations (here, in a stripe shape).

Then, as shown in FIG. 4, the remaining metal mask layer 37 and oxide film 35 are removed, and the intrinsic channel layer 23 is formed on the exposed first division layer 23a and gate diffusion layer 5. The second division layer 23b is formed. The second division layer 23b is formed in the same manner as the above-mentioned first division layer 23a. Subsequently, the N + source diffusion layer 9 is formed on the second division layer 23b. Source diffusion layer 9 is formed by homoepitaxial growth while mixing a predetermined N-type impurity into silicon carbide so that the impurity concentration becomes a predetermined concentration value. Subsequently, an SiO 2 oxide film (field oxide film) 39 is formed on the source diffusion layer 9.
Is formed.

Then, as shown in FIG. 5, a metal mask layer (here, an aluminum metal mask layer) 41 is formed on the oxide film 39 by electron beam evaporation, sputtering or the like. Subsequently, by patterning using a photoresist and etching (dry etching), the metal mask layer 41 and the oxide film 3 located above each gate diffusion layer 5 are patterned.
9 is partially removed, and the remaining metal mask layer 41
And dry etching (R
The source diffusion layer 9 and the second division layer 23b located above each gate diffusion layer 5 are partially removed by IE or the like to form a trench 43, and the trench 43 is formed through the trench 43. A part (central portion) of the upper surface 27 is exposed. The lower end of the trench 43 constitutes the recess 25. Thus, by performing dry etching using metal mask layer 41 as a mask, patterning of hard source diffusion layer 9 and second division layer 23b containing silicon carbide as a main component can be easily performed.

Subsequently, as shown in FIG. 6, the metal mask layer 41 is removed, and an oxide film 45 of SiO 2 is formed on the inner peripheral surface of the trench 43 and the upper surface of the field oxide film 39 by CVD or the like. The portion of the oxide film 45 provided on the inner side surface of the trench 43 becomes the side surface oxide film 31. The step of forming the oxide film 45 includes a step of forming a sacrificial oxide film and a step of removing the sacrificial oxide film in order to remove a damaged portion such as the inner side surface of the trench 43. . Then, the oxide film 45 on the bottom surface of the trench 43 is formed.
Are removed by dry etching, and the gate wiring 7 is formed by selective CVD using tungsten as a wiring material.
In this embodiment, the gate wiring 7 is formed into a pattern of the gate wiring 7 by forming a wiring material layer on the entire surface so that the wiring material fits in the trench 43 and then patterning using photoresist and etching. Correspondingly, it is formed by partially removing the layer of the wiring material. Then, an interlayer insulating film 33 is formed by CVD so as to cover the gate wiring 7.

Then, as shown in FIG. 1, patterning using a photoresist and etching is performed to correspond to the pattern of the source contact hole 51 (here,
The interlayer insulating film 33, the oxide film 45, and the field oxide film 39 are partially removed so that the source contact 51 is formed and the source wiring 11 is formed so that the stripe-shaped gate wiring 7 is extended between the gate wirings 7. To do. The source wiring 11 is formed by forming a wiring material layer on the entire surface so that the wiring material fits into the source contact hole 51, and then patterning using a photoresist and etching.
It is formed by partially removing the layer of the wiring material corresponding to the pattern of the source wiring 11.

Next, a protective film 5 of SiO2 and SiN
After 3 is formed, the gate pad 55 and the source pad 57 shown in FIG. 7 are formed.

Next, referring to FIGS. 7 and 8, the structure of the gate wiring 7 and the source wiring 11 of this transistor will be briefly described. In the present embodiment, the gate wiring 7 is, as shown in FIGS. 7 and 8, generally, a branch line portion (gate wiring) formed in a stripe shape and joined to each gate diffusion layer 5 formed in a stripe shape. Part) 7a
Is provided in a rectangular ring shape so as to surround the main line portion 11b of the source wiring 11 described later on the outer edge portion of the transistor so as to be connected to each branch line portion 7a, and the branch line portions 7a are integrated to form the gate pad 55. Main line part (gate wiring part) connected to
And 7b. An end portion of the branch line portion 7a joined to the gate diffusion layer 5 is a gate contact portion.

The source wiring 11 is shown in FIG. 7 and FIG.
As shown in FIG. 2, the branch line portions 11a formed in stripes are joined to the source diffusion layers 9 formed in stripes, and the central portion of the transistor is connected to the branch line portions 11a. Each branch line portion 11a is formed in a planar shape.
And a main line portion (source wiring portion) 11b that integrates and connects to the source pad 57. Branch line 11
The end portion of the a that is joined to the source diffusion layer 9 is a source contact portion.

Here, the branch line portion 7a of the gate wiring 7 and the main line portion 11b of the source wiring 11 provided thereabove are insulated by the interlayer insulating film 33. Further, the gate pad 55 and the source pad 57 provided on the upper surface of the transistor are insulated from the main line portions 7b and 11b of the gate wiring 7 and the source wiring 11 provided below the gate pad 55 and the source pad 57 by the protective film 53.

The transistor thus constructed has a normally-off type on / off characteristic. That is,
In the gate free state in which the control signal (voltage) is not applied to the gate wiring 7, the depletion layer generated in the intrinsic channel layer 23 turns off the source and the drain, and a positive voltage is applied to the gate wiring 7. By doing so, the source and drain are turned on.

As described above, according to this embodiment, since silicon carbide is used as the semiconductor material, it is possible to improve the device performance (particularly the breakdown voltage performance) that cannot be achieved with silicon.

Further, since it has a normally-off type on / off characteristic, it is suitable for vehicle mounting.

Further, since the channel layer 3 is composed of the drift layer 21 and the intrinsic channel layer 23, the thickness of the high resistivity intrinsic channel layer 23 mainly responsible for the on / off characteristic of the device is reduced, It is possible to secure the thickness of the drift layer 21 mainly responsible for the breakdown voltage characteristics of the device,
This makes it possible to suppress the channel resistance while ensuring a predetermined breakdown voltage characteristic.

Further, since the upper surface 27 of the gate diffusion layer 5 is located below the position of the upper surface 29 of the intrinsic channel layer 23 and the gate diffusion layer 5 is embedded in the intrinsic channel layer 23, the gate diffusion layer 5 is formed. 5 and the source diffusion layer 9 formed on the upper surface of the intrinsic channel layer 23 can be increased in distance, and the electric field concentration of the gate diffusion layer 5 can be mitigated. The breakdown voltage can be improved.

The gate wiring 7 also serving as the gate electrode
However, since it is formed of a refractory metal (tungsten here), the resistance of the gate wiring 7 can be reduced, and it is suitable for high frequency operation. Also, tungsten is selected CV
D is applicable, suitable for fine processing, and the process is simplified. Further, tungsten has a higher melting point than aluminum, which allows the device to operate at high temperatures. In addition, the gate becomes a self-alignment gate, and the precision of fine processing is significantly improved.

Further, the main line portion 11b of the source wiring 11
Are formed on the upper side of the striped branch line portion 7a of the gate wiring 7 and are connected to the lower branch line portion 11a (source contact portion) through the interlayer insulating film 33. The current flowing through the transistor can be efficiently passed in the vertical direction, and the transistor can be made compact.

Further, according to the manufacturing method of this embodiment, the channel layer 3 including the drift layer 21 and the intrinsic channel layer 23, which are mainly composed of silicon carbide and have different impurity concentrations, and the intrinsic channel layer 23 thereof are provided. The embedded gate structure can be easily formed.

In this embodiment, the recess 25 for embedding is formed, and the gate wiring 7 made of a refractory metal is embedded in the recess 25 so as to be joined to the gate diffusion layer 5. The gate wiring 7 is formed by partially introducing from the surface of the second division layer 23b or the source diffusion layer 9 the same kind of impurities as those for forming the gate diffusion layer without using the predetermined mask. (In particular, a gate contact portion or the like) may be formed and the gate wiring 7 may be joined to the gate diffusion layer 5.

<Second Embodiment> FIG. 9 is a view showing a sectional structure of a junction field effect transistor (hereinafter, simply referred to as "transistor") according to a second embodiment of the present invention.
10 to 13 are views showing manufacturing steps of the transistor of FIG. The transistor according to the present embodiment is different from the transistor according to the first embodiment described above substantially only in the difference in the detailed configuration mainly caused by the difference in the manufacturing process, and the portions corresponding to each other are the same. The reference numerals are attached and the description is omitted.

As a difference in structure, in the first embodiment, as shown in FIG. 1, the left and right ends of the gate diffusion layer 5 are the gate wiring 7 (particularly the contact portion of the branch line portion 7a).
In contrast to the left and right ends of the gate diffusion layer 5 which greatly extend beyond the side surface oxide film 31, the left and right ends of the gate diffusion layer 5 stop at the position of the side surface oxide film 31 in the present embodiment, as shown in FIG. ing. In addition, the channel layer 23 is formed in one step rather than being formed in two steps as in the first embodiment.

In the manufacturing method according to the present embodiment, first, the N + semiconductor substrate 1 formed mainly of silicon carbide is prepared, and the semiconductor substrate 1 is subjected to surface treatment such as initial cleaning. Subsequently, as shown in FIG. 10, a drift layer 21, an intrinsic channel layer 23, and a source diffusion layer 9 are formed on the semiconductor substrate 1 in this order. The drift layer 21, the intrinsic channel layer 23, and the source diffusion layer 9 are formed in the same manner as in the first embodiment. However, in this embodiment, the intrinsic channel layer 23 is formed at once in one process.

Subsequently, as shown in FIG. 11, an oxide film 61 of SiO 2 is formed on the source diffusion layer 9, and the oxide film 6 is formed.
A metal mask layer (here, an aluminum mask layer) 63 is formed on the substrate 1 by sputtering, electron beam evaporation, or the like, and the metal mask layer 63 and the oxide film 61 are partially formed by patterning using photoresist and etching (dry etching). Remove to form a mask. By dry etching (RIE or the like) using the mask, the source diffusion layer 9 is partially removed corresponding to the gate pattern, and a part of the exposed upper portion of the intrinsic channel layer 23 is removed to form the trench 65. Form. This trench 65
The recess 25 is formed by the lower end of the. Thus, by performing dry etching using the metal mask layer 63 and the oxide film 61 as a mask, patterning of the hard source diffusion layer 9 and the intrinsic channel layer 23 whose main component is silicon carbide can be easily performed. it can.

Subsequently, as shown in FIG. 12, the patterned metal mask layer 63 and the oxide film 61 are used as a mask to form a gate diffusion layer in the portion exposed through the trench 65 of the intrinsic channel layer 23. The impurities (P-type ions (aluminum ions here)) are introduced to form the gate diffusion layer 5. Then, the remaining metal mask layer 63 is removed, and an oxide film 67 of SiO 2 is formed on the inner peripheral surface of the trench 65 and the upper surface of the oxide film 61 by CVD or the like.
Is formed. The portion of the oxide film 67 provided on the inner side surface of the trench 65 becomes the side surface oxide film 31. The step of forming the oxide film 67 includes a step of forming a sacrificial oxide film and a step of removing the sacrificial oxide film in order to remove a damaged portion such as an inner surface of the trench 65. . Subsequently, a high temperature annealing process for activating the gate diffusion layer 5 and a removal of the oxide film 67 located on the bottom surface of the trench 65 by dry etching are performed.

Subsequently, as shown in FIG. 13, a gate wiring 7 is formed by selective CVD using tungsten as a wiring material. In the present embodiment, the gate wiring 7 is formed into a pattern of the gate wiring 7 by forming a wiring material layer on the entire surface so that the wiring material fits in the trench 65, and then patterning using photoresist and etching. Correspondingly, it is formed by partially removing the layer of the wiring material. Then, an interlayer insulating film 33 is formed by CVD so as to cover the gate wiring 7.

Then, as shown in FIG. 9, the interlayer insulating film 33 and the oxide films 67 and 61 are partially removed corresponding to the pattern of the source contact hole 51 by patterning using photoresist and etching. As a result, the source contact 51 is formed and the source wiring 11 is formed.
In the source wiring 11, a wiring material layer is formed on the entire surface so that the wiring material fits into the source contact hole 51, and then patterning is performed using photoresist and etching so as to correspond to the pattern of the source wiring 11. It is formed by partially removing the wiring material layer.

Subsequently, the SiO 2 and SiN protective film 5 is formed.
After 3 is formed, the gate pad 55 and the source pad 57 shown in FIG. 7 are formed.

As described above, substantially the same effects as in the case of the first embodiment can be obtained by the transistor and the manufacturing method thereof according to the present embodiment.

<Modification> FIG. 14 is a diagram showing a modification of the gate arrangement of the transistors according to the first and second embodiments. In this modified example, as shown in FIG. 14, the gate diffusion layer 5 and the gate contact portion 7c of the gate wiring 7 joined to the gate diffusion layer 5 have a plan view shape and are scattered ( Here, the channel layer 3 and the source diffusion layer 9 (or the source diffusion layer 9) are formed in a matrix and surround the periphery of each gate diffusion layer 5 and each gate contact portion 7c.
At the same time, a source contact portion of the source wiring 11) is formed.

Further, according to this modification, the area of each gate diffusion layer 5 can be reduced, which can reduce the parasitic capacitance component of the device and make the structure suitable for high-speed operation.

Further, the ratio of the source region in the element formation surface can be increased, and the current value in the same area can be increased. As a result, the mutual conductance is increased and the high frequency characteristics are improved.

Further, by reducing the area of each gate diffusion layer 5, the forward current of the diode between the gate and the drain (or the source), which is the leakage current, can be reduced, and the drive current can be reduced. it can.

Further, in each of the above-mentioned embodiments, the transistor is formed by using silicon carbide as a main component semiconductor material, but silicon, GaAs, gallium nitride or diamond may be used instead of silicon carbide.

[0058]

According to the invention described in claims 1 to 9, since the channel layer is formed so that the impurity concentration decreases from the back surface side toward the front surface side where the gate means is formed, the channel layer is formed. A high-resistivity intrinsic channel region (a region where a depletion layer is formed so as to pinch off the conductive path between the source and drain when the gate is opened), which is located in the vicinity of the gate means in the layer and mainly plays a role in the on / off characteristics of the device. While reducing the thickness (channel length), the resistance value of the region (drift region) located below the intrinsic channel region and mainly responsible for the withstand voltage characteristic of the device can be suppressed, thereby ensuring the predetermined withstand voltage characteristic. In addition, it is possible to provide a junction field effect transistor which can suppress the channel resistance to a small value, has a high breakdown voltage, a low loss, and can operate at a high frequency.

According to the third aspect of the present invention, the channel layer is formed on the first semiconductor layer having a high impurity concentration and the first semiconductor layer formed on the first semiconductor layer and having a low impurity concentration joined to the gate means. 2 semiconductor layers and is joined to the gate means to reduce the thickness of the high-resistivity region in the channel layer mainly responsible for the on / off characteristics of the device, while mainly improving the withstand voltage characteristics of the device. It is possible to secure the thickness of the region (drift region) in the channel to be carried, and thus it is possible to suppress the channel resistance while securing a predetermined breakdown voltage characteristic.

According to the invention described in claim 5, since the gate diffusion layer is formed so as to be embedded in the second semiconductor layer forming the channel layer, the gate diffusion layer is formed above the gate diffusion layer and the channel layer. The distance between the formed source electrode and the like can be increased, the electric field concentration in the gate diffusion layer can be relaxed, and the breakdown voltage between the gate and the source can be improved.

According to the seventh aspect of the invention, since the gate wiring is formed of a refractory metal, the resistance of the gate wiring can be reduced and a high frequency operation can be performed.

According to the invention described in claim 8, the source wiring portion of the source wiring is formed in a planar shape on the upper side of the gate wiring portion and connected to the lower source contact portion via the insulating layer. Therefore, the current flowing through the transistor can be efficiently passed in the vertical direction, and the transistor can be made compact.

According to the invention described in claim 9, since the gate means has a plan view shape and is provided in a scattered manner, the area of each gate means can be reduced.
As a result, the parasitic capacitance component of the device can be reduced, and a configuration suitable for high speed operation can be obtained.

Further, since the channel layer is formed so as to surround the periphery of each gate means in a plan view, it is possible to form the source region so as to surround the gate means, and thus in the device formation surface. The ratio occupied by the source region can be increased, and the current value in the same area can be increased. As a result, the mutual conductance is increased and the high frequency characteristics are improved.

Furthermore, by reducing the area of each gate means, the forward current of the diode between the gate and the drain, which is the leakage current, can be reduced, and the drive current can be reduced.

According to the tenth aspect of the invention, it is possible to easily form the channel layer in which the impurity concentration changes so as to decrease toward the upper side.

According to the eleventh aspect of the present invention, the channel layer including the first and second semiconductor layers having different impurity concentrations can be easily formed.

According to the twelfth and thirteenth aspects of the present invention, a channel layer including first and second semiconductor layers having different impurity concentrations and a gate structure embedded in the second semiconductor layer can be easily formed. Can be formed.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a junction field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the transistor of FIG.

FIG. 3 is a diagram showing a manufacturing process of the transistor of FIG.

FIG. 4 is a diagram showing a manufacturing process of the transistor of FIG. 1;

FIG. 5 is a diagram showing a manufacturing process of the transistor of FIG. 1;

FIG. 6 is a diagram showing a manufacturing process of the transistor of FIG. 1;

7 is a plan view showing a configuration of a gate wiring, a source wiring and the like of the transistor of FIG.

8 is a cutaway perspective view schematically showing a configuration of a main part of FIG.

FIG. 9 is a diagram showing a cross-sectional structure of a junction field effect transistor according to a second embodiment of the present invention.

FIG. 10 is a diagram showing a manufacturing process of the transistor of FIG. 9;

FIG. 11 is a diagram showing a manufacturing process of the transistor of FIG. 9;

FIG. 12 is a diagram showing a manufacturing process of the transistor of FIG. 9;

FIG. 13 is a diagram showing a manufacturing process of the transistor of FIG. 9;

FIG. 14 is a diagram showing a modified example of the gate arrangement form of the transistors of FIGS. 1 and 2;

[Explanation of symbols]

1 Semiconductor substrate 3 channel layers 5 Gate diffusion layer 7 Gate wiring 9 Source diffusion layer 11 Source wiring 13 drain electrode 21 Drift layer 23 Intrinsic channel layer 23a First division layer 23b Second division layer 25 recess 31 Side oxide film 33 Interlaminar membrane 35 oxide film 37 Metal mask layer 39 Field oxide film 41 Metal mask layer 53 Protective film 55 gate pad 57 Source Pad 61 oxide film

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takashi Hoshino             1-7-10 Kikuzumi, Minami-ku, Nagoya-shi, Aichi             Auto Network Technical Laboratory Co., Ltd. (72) Inventor Kenichi Hirotsu             Sumitomo Electric Works 1-1-3 Shimaya, Konohana-ku, Osaka             Electric Power Systems Engineering Laboratory (72) Inventor Makoto Harada             Sumitomo Electric Works 1-1-3 Shimaya, Konohana-ku, Osaka             Electric Power Systems Engineering Laboratory F-term (reference) 4M104 AA01 AA03 AA05 AA10 BB05                       BB14 BB18 CC01 DD43 DD46                       FF02 FF27 GG11 GG18                 5F102 FA01 FA02 GB02 GB04 GC08                       GD04 GJ02 GJ03 GJ05 GL02                       GL07 GL08 GL15 GM02 GN02                       GR04 GR11 GS07 GT03 GV03                       HC01 HC07 HC11 HC15

Claims (13)

[Claims] 1. A junction type field effect transistor having a vertical structure in which a source electrode and a drain electrode are formed on a front surface side and a back surface side of a semiconductor chip, wherein an impurity concentration of a channel layer is from a back surface side to a gate means formation side. A junction-type field effect transistor, which is set so as to become smaller toward a certain surface side. 2. The junction field effect transistor according to claim 1, wherein the junction field effect transistor is formed by using silicon, GaAs, silicon carbide, gallium nitride or diamond as a main semiconductor material. Transistor. 3. The channel layer, wherein the impurity concentration is a first semiconductor layer having a first concentration value, the impurity concentration is a second concentration value lower than the first concentration value, The junction field effect transistor according to claim 1, further comprising a second semiconductor layer formed above the first semiconductor layer and joined to the gate means. 4. The gate means comprises a gate diffusion layer formed in the second semiconductor layer, and a gate electrode joined to the gate diffusion layer. A junction field effect transistor as described. 5. The gate means comprises a gate diffusion layer formed below a recess for embedding formed in the second semiconductor layer from the surface side thereof, and the gate diffusion layer embedded in the recess. The junction field effect transistor according to claim 3, further comprising: 6. The gate electrode is formed by introducing impurities from a predetermined semiconductor surface and connected to the gate diffusion layer, or is embedded in the second semiconductor layer from the surface side thereof for embedding. The junction field effect transistor according to claim 4, wherein the junction field effect transistor is embedded in the recess and connected to the gate diffusion layer. 7. The junction field effect transistor according to claim 5, wherein the gate wiring is formed of a refractory metal. 8. The gate wiring comprises a gate contact portion joined to the gate diffusion layer and a gate wiring portion connected to the gate contact portion, and the junction field effect transistor comprises the channel. A source wiring formed on the front surface side of the layer; and an insulating layer that insulates the gate wiring from the source wiring, wherein the source wiring has a source diffusion layer or a source diffusion layer. A source contact portion that is joined to the channel layer without any contact, and a planar source wiring portion that is formed above the gate wiring portion and that is connected to the source contact portion through the insulating layer. The junction field effect transistor according to claim 5, wherein 9. The gate means has a plan view shape, is provided in a scattered manner, and the channel layer is formed so as to surround the periphery of each gate means. Items 1 to 8
The junction field effect transistor according to any one of 1. 10. The method for manufacturing a junction field effect transistor according to claim 1, wherein the channel layer is formed on a semiconductor substrate by homoepitaxial growth so that the impurity concentration decreases upward. A method of manufacturing a junction field effect transistor, comprising: 11. The method for manufacturing a junction field effect transistor according to claim 4, wherein the first semiconductor is formed on the semiconductor substrate by homoepitaxial growth so that the impurity concentration becomes the first concentration value. A step of forming a layer, a step of forming the second semiconductor layer on the first semiconductor layer by homoepitaxial growth so that the impurity concentration becomes the second concentration value, and A step of partially introducing an impurity for forming a gate diffusion layer into the second semiconductor layer to form the gate diffusion layer; and a step of forming the gate electrode by introducing an impurity from a predetermined semiconductor surface. A method of manufacturing a junction field effect transistor, comprising: 12. The method for manufacturing a junction field effect transistor according to claim 5, wherein the first semiconductor is formed on a semiconductor substrate by homoepitaxial growth so that the impurity concentration becomes the first concentration value. A step of forming a layer, and forming a layer on the first semiconductor layer, wherein the lower first divided layer obtained by vertically dividing the second semiconductor layer into two is provided with the impurity concentration of the second concentration value. And a step of forming a gate diffusion layer by partially introducing an impurity for forming a gate diffusion layer into the first division layer using a mask so as to form a gate diffusion layer. Of the remaining second semiconductor layer of the semiconductor layer on the first semiconductor layer and the formed gate expansion layer by homoepitaxial growth so that the impurity concentration becomes the second concentration value. Forming a recess on the gate diffusion layer by partially removing the second dividing layer located on the gate diffusion layer, and exposing at least a part of an upper surface of the gate diffusion layer. A step of forming a side surface oxide film covering an inner side surface of the recess, and a step of forming the gate wiring on the exposed upper surface of the gate diffusion layer. Production method. 13. The method for manufacturing a junction field effect transistor according to claim 5, wherein the first semiconductor is formed on the semiconductor substrate by homoepitaxial growth so that the impurity concentration becomes the first concentration value. A step of forming a layer, a step of forming the second semiconductor layer on the first semiconductor layer by homoepitaxial growth so that the impurity concentration becomes the second concentration value, and the second semiconductor A step of partially removing a part of the layer to form the concave portion; a step of forming a side surface oxide film covering an inner side surface of the concave portion; and a second step of forming a bottom portion of the concave portion using a mask. A step of partially introducing an impurity for forming a gate diffusion layer into a portion of the semiconductor layer to form the gate diffusion layer; and a step of forming the gate wiring on the upper surface of the formed gate diffusion layer. A method for manufacturing a junction field effect transistor, comprising: