JP2003087443A - Image processing integrated circuit and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image forming apparatus including a hardware configuration capable of high-speed image processing when a CPU whose interface is not open to public is used for a controller of the image forming apparatus. SOLUTION: In the case that the interface of a CPU 102 is not open to public, an NB (North Bridge) 103 and an ASIC (Application Specific IC) 108 being a part of a chip set are connected by using an AGP (Accelerated Graphic Port) 106 being an exclusive port for graphic display so as to apply switching control to image data sent/received between the chip set of the CPU 102 and an engine section 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing integrated circuit connected to an engine section and a CPU, and an image forming apparatus including the image processing integrated circuit. The present invention relates to an image processing integrated circuit and an image forming apparatus having a hardware configuration capable of performing image forming processing at high speed when used for a controller of the forming apparatus.

[0002]

2. Description of the Related Art Conventionally, in an image forming apparatus such as a printer or a copying machine, an ASIC (Application Spec
In many cases, a controller including a smart IC) and a CPU is connected to the engine unit, and this controller is used to perform image forming processing.

For example, in the case of a copying machine, an ASIC having a plurality of hardware elements for image processing is mounted on a controller, the ASIC and the engine section are connected by a PCI interface, and they are arranged on the same controller. CP by connecting the CPU and ASIC
The copy process will be performed under the control of U.

When a new image forming apparatus having excellent performance is made, the controller for controlling the drawing and control is replaced with a high-speed controller for each unit.

[0005]

However, although the interface of the previous CPU was open to the public, the recent RISC general-purpose CPU does not open the interface of the CPU itself, so that the ASIC via the chip set is used. Since there is no choice but to connect the CPU to the CPU, there is a problem that performance is restricted.

[0006] Specifically, when connecting to an external device via a chip set, usually a PCI (Peripheral Compo
Although a PCI bus via a chipset has low performance, it is not suitable for configuring an image forming apparatus such as a printer or a copying machine.

Therefore, when a CPU whose interface is not open to the public is used as the controller of the image forming apparatus, how to appropriately exchange data between the CPU chip set and the engine section, and how to achieve high-speed image processing. Whether or not to perform the forming process is a very important issue.

Particularly in some recent multifunction peripherals, instead of assigning copy processing, printer processing, and FAX processing to separate CPUs mounted on separate boards as in the past, all of these processings are performed by the same CPU. Since the person in charge has appeared, how to solve the above performance degradation is a very important issue.

The present invention has been made to solve the above-mentioned problems of the prior art. When a CPU whose interface is not open to the public is used as a controller of an image forming apparatus, the chip set and engine portion of the CPU are used. It is an object of the present invention to provide an image processing integrated circuit and an image forming apparatus capable of appropriately performing data exchange with the image forming apparatus and performing image forming processing at high speed.

[0010]

[Means for Solving the Problems]
In order to achieve the object, an image processing integrated circuit according to the invention of claim 1 includes: an engine interface unit for connecting an engine unit having a scanner and a plotter; a chipset interface unit for connecting a chipset unit of a CPU; Whether to output the scanner image data input from the engine interface unit and read by the scanner to the engine interface unit as plotter data for the plotter, or to output the scanner image data to the chipset interface unit,
And a switching control unit that controls switching of whether to output the image data input from the chipset interface unit to the engine interface unit as plotter data for the plotter.

According to the first aspect of the present invention, the scanner image data input from the engine interface unit and read by the scanner is output to the engine interface unit as plotter data for the plotter, or the scanner image data is chipset. Since it is decided to switch whether to output to the interface section or output the image data input from the chipset interface section to the engine interface section as plotter data for the plotter, the CPU whose interface is not open is used for image formation. When used as a controller of the device, it is possible to appropriately exchange data between the CPU and the engine unit by smooth switching control.

An image processing integrated circuit according to a second aspect of the present invention further comprises a memory interface section for connecting a storage section for storing image data and the like, wherein the switching control section is The image data input from the engine interface unit or the chipset interface unit is temporarily output to the memory interface unit, and then the image data is input from the memory interface unit to the engine interface unit or the chipset interface unit. It is characterized by outputting to.

According to the second aspect of the present invention, the image data input from the engine interface section or the chipset interface section is temporarily output to the memory interface section, and then the image data is input from the memory interface section to output the engine data. Since the data is output to the interface unit or the chipset interface unit, the data transfer rates of the engine interface unit and the chipset interface unit can be adjusted.

The image processing integrated circuit according to a third aspect of the present invention is the image processing integrated circuit according to the second aspect, wherein the memory interface unit has a RAM interface and a hard disk interface.
When inputting / outputting image data using the memory interface unit, the input / output destination is switched to the RAM interface or the hard disk interface.

According to the third aspect of the present invention, when the image data is input / output using the memory interface unit, the input / output destination is switched to the RAM interface or the hard disk interface. That is, it is possible to handle applications with different data flows such as a net file application.

The image processing integrated circuit according to a fourth aspect of the present invention is the image processing integrated circuit according to the third aspect, wherein lossless compression processing is performed when image data is output to the memory interface section, and the image is output from the memory interface section. The feature is that decompression processing is performed when data is input.

According to the invention of claim 4, the lossless compression process is performed when the image data is output to the memory interface unit, and the decompression process is performed when the image data is input from the memory interface unit.
More image data can be stored in the storage unit.

According to a fifth aspect of the present invention, in the image processing integrated circuit according to the first to fourth aspects, the chipset interface section is an accelerated graphic port, and a chipset of the CPU. The north bridge forming part is connected to the accelerated graphic port.

According to the invention of claim 5, the chipset interface unit is an accelerated graphic port (AGP), and the north bridge forming a part of the chipset of the CPU is connected to the accelerated graphic port. Since it is decided to do so, high-speed data exchange can be performed via the AGP.

According to a sixth aspect of the present invention, in the image processing integrated circuit according to the first to fifth aspects, the engine interface section is a PCI interface that accommodates a PCI bus, and the engine section is the PCI interface. It is characterized by connecting to the interface.

According to the invention of claim 6, the engine interface unit is a PCI interface for accommodating a PCI bus, and the engine unit is connected to this PCI interface. Therefore, the connection form of the engine unit is changed. You can eliminate the need to

The image processing integrated circuit according to a seventh aspect of the present invention is the image processing integrated circuit according to the first to sixth aspects, wherein the engine section is a monochrome plotter having the PCI interface, a one-color color plotter, and a four-drum color plotter. It is characterized by having a color plotter, a copier engine or a fax unit.

According to the invention of claim 7, the engine unit has a black and white plotter having a PCI interface, and
Drum color plotter, 4 drum color plotter,
Since it has a copier engine or a fax unit, it can meet various needs such as monochrome printing, color printing, image reading, copying, and faxing.

Further, in the image forming apparatus according to the invention of claim 8, an engine section having a scanner and a plotter and a CPU are connected to a controller having an integrated circuit for image processing, and the image forming processing is performed under the control of the CPU. In the image forming apparatus, the controller is an engine interface unit for connecting the engine unit, a chipset interface unit for connecting the chipset unit of the CPU, and the scanner read by the engine interface unit. Output the scanned image data to the engine interface unit as plotter data to the plotter, output the scanner image data to the chipset interface unit, or input image data from the chipset interface unit. Characterized by comprising a switching control unit which controls switching whether to output to the engine interface as plotters data to the plotter.

According to the invention of claim 8, the scanner image data input from the engine interface unit and read by the scanner is output to the engine interface unit as plotter data for the plotter, or the scanner image data is output to the chip set. Since it is decided to switch whether to output to the interface section or output the image data input from the chipset interface section to the engine interface section as plotter data for the plotter, the CPU whose interface is not open is used for image formation. When used as a controller of the apparatus, smooth switching control enables efficient data exchange between the CPU and the engine section.

The image forming apparatus according to a ninth aspect of the present invention is the image forming apparatus according to the eighth aspect, wherein the controller further comprises a memory interface section for connecting a storage section for storing image data and the like, and the switching control section. Outputs the image data input from the engine interface unit or the chipset interface unit to the memory interface unit, and then inputs the image data from the memory interface unit to input the image data to the engine interface unit or the chipset. It is characterized by outputting to the interface section.

According to the ninth aspect of the present invention, the image data input from the engine interface section or the chipset interface section is once output to the memory interface section, and then the image data is input from the memory interface section. Since the data is output to the interface unit or the chipset interface unit, the data transfer rates of the engine interface unit and the chipset interface unit can be adjusted.

According to a tenth aspect of the present invention, in the image forming apparatus according to the ninth aspect, the memory interface section has a RAM interface and a hard disk interface, and the switching control section has the memory interface section. When inputting and outputting the used image data, the input / output destination is switched to the RAM interface or the hard disk interface.

According to the tenth aspect of the present invention, when the image data is input / output using the memory interface section, the input / output destination is switched to the RAM interface or the hard disk interface. That is, it is possible to handle applications with different data flows such as a net file application.

According to the invention of claim 11, in the image forming apparatus of claim 10, the image data is output from the memory interface section by performing a reversible compression process when outputting the image data to the memory interface section. The feature is that decompression processing is performed when inputting.

According to the eleventh aspect of the invention, the lossless compression process is performed when the image data is output to the memory interface unit, and the decompression process is performed when the image data is input from the memory interface unit. More image data can be stored in the storage unit.

According to a twelfth aspect of the present invention, in the image forming apparatus according to the eighth to eleventh aspects, the chipset interface section is an accelerated graphic port, and a part of a chipset of the CPU is provided. The eggplant north bridge is connected to the accelerated graphic port.

According to the twelfth aspect of the present invention, the chipset interface section is an accelerated graphic port (AGP), and the north bridge forming a part of the CPU chipset is connected to the accelerated graphic port. I decided to do so, so AGP
It is possible to exchange data at high speed via.

According to a thirteenth aspect of the present invention, in the image forming apparatus according to the eighth aspect, the engine interface unit is a PCI interface that accommodates a PCI bus, and the engine unit is the PCI interface. It is characterized by connecting.

According to the thirteenth aspect of the present invention, the engine interface unit is the PCI interface that accommodates the PCI bus, and the engine unit is connected to this PCI interface. Therefore, the connection form of the engine unit is changed. You can eliminate the need to

According to a fourteenth aspect of the present invention, in the image forming apparatus according to the eighth aspect, the engine section is a monochrome plotter having the PCI interface, a one-drum color plotter, a four-drum color plotter, and a copy machine. It is characterized by having a machine engine or a fax unit.

According to the fourteenth aspect of the present invention, the engine section has a black and white plotter having a PCI interface,
Since it has a one-drum color plotter, a four-drum color plotter, a copier engine or a fax unit, it can meet various needs such as monochrome printing, color printing, image reading, copying, and fax.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an image processing integrated circuit and an image forming apparatus according to the present invention will be described in detail below with reference to the accompanying drawings. The first embodiment
A case where the present invention is applied to a printer is shown, and a case where the present invention is applied to a multifunction machine is shown in the second embodiment.

(First Embodiment) FIG. 1 shows the first embodiment.
It is a diagram showing the overall configuration of a printer according to. As shown in the figure, this printer has a configuration in which a controller 101 and an engine unit 110 are connected by a PCI 109. The controller 101 is a controller that controls the entire printer and controls drawing, communication, and input from the operation unit 111. The engine unit 110 is a printer engine or the like that can be connected to the PCI bus.
For example, a drum color plotter, a 4-drum color plotter, a scanner or a fax unit. The engine section 110 includes an image processing section such as error diffusion and gamma conversion in addition to a so-called engine section such as a plotter.

The controller 101 includes a CPU 102,
North bridge (NB) 103 and system memory (M
EM-P) 104 and South Bridge (SB) 105
, Local memory (MEM-C) 107, and ASIC
108, an operation unit 111, and a hard disk drive (HDD) 112, the north bridge (NB) 1
03 and ASIC108 between AGP (Accelerated Gr
The configuration is such that an aphics port) 106 is used for connection.

The CPU 102 controls the entire printer, and has a chip set consisting of the NB 103, the MEM-P 104 and the SB 105. here,
The interface of this CPU is not open to the public, and other devices are to be connected via a chipset.

The NB 103 has a CPU 102 and a MEM-P.
104, SB 105, AGP 106, and MEM-P 104 is a system memory used as a drawing memory of the printer, SB
Reference numeral 105 is a bridge for connecting the NB 103 to the ROM, PCI device, and peripheral device.

The MEM-C 107 is a local memory used as a copy image buffer and a code buffer,
The ASIC 108 is an IC for image processing applications having a hardware element for image processing.
It also has a role of a bridge that connects the CI 109, the HDD 112, and the MEM-C 107, respectively.

The operation unit 111 is an operation unit that receives an input operation from the user and performs a display for the user, and the HDD 112 stores image data, programs, font data, and forms. For storage.

The AGP 106 is a bus interface for a graphics accelerator card proposed for speeding up graphics processing, and by directly accessing the system memory with high throughput,
It speeds up graphics accelerator cards.

The AGP 106 is originally used to smoothly display a 3D (three-dimensional) image on the display, but in the present embodiment, the AGP 1 is used.
The NB 103 and the ASIC 108 are connected via 06.

That is, since the interface of the CPU 102 is not open to the public, the ASIC 108 is connected here via the NB 103 which is a part of the chip set. At this time, if the two are connected using the PCI bus, the performance will decrease.
Extended use of P106.

Next, the configuration of the ASIC 108 shown in FIG. 1 will be described. FIG. 2 shows the ASIC 10 shown in FIG.
8 is a block diagram showing a configuration of No. 8. As shown in the figure,
This ASIC 108 includes an AGP unit 201, a CONFIG register 202, and a master (MASTER).
Unit 203 and target (TARGET) unit 20
4, the internal register 205, the DMA controller (DM
AC) 206, RAM controller (RAMC) 207,
CONFIG register 209 and master (MAST
It has an ER) unit 210, a target (TARGET) unit 211, and a PCI unit 212.

The AGP unit 201 is a unit (chipset interface section) that executes the bus protocol of the AGP bus 106 connected to the NB 103, and is a CO
The NFIG 202 is a PCI configuration register for the AGP bus 106. MASTER203 is AGP bus 1
The unit that executes the 06 bus master function, TARG
The ET 204 is a unit included in the AGP bus 106 that executes a PCI target function.

The internal register 205 is a register that is required when each part of the ASIC 108 exerts its function.
The DMAC 206 is a DMA controller for performing a DMA transfer to the local memory MEM-C107.

The RAMC 207 is a local memory MEM-C.
A RAM controller for controlling 107, and CONFIG2
Reference numeral 09 is a PCI configuration register for the PCI bus 109, MASTER 210 is a unit that executes the bus master function of the PCI 109, and TARGET204
Is a unit that executes a PCI target function included in the PCI 109. The PCI unit 212 is
It is a unit (engine interface unit) that executes the bus protocol of the PCI 109.

Next, the internal structure of the CONFIG 202 shown in FIG. 2 will be described. FIG. 3 shows the CONFIG 20 shown in FIG.
It is explanatory drawing for demonstrating the internal structure of 2. As shown in the figure, the AGP bus 10 that the ASIC 108 has
CONFIG202, which is the configuration register on the 6 side, is
It has two base address registers, R202a and BAR202b.

The BAR 202a is a local memory MEM.
-A base address register for mapping C107, the BAR 202b is an internal register 205,
It is a base address register for mapping the PCI memory space and PCI I / O space.

Next, the space base register for the DMAC provided on the internal register 205 shown in FIG. 2 will be described. FIG. 4 is an explanatory diagram for explaining the space base register for DMAC provided on the internal register 205 shown in FIG.

As shown in the figure, the internal register 20
5 includes AGPMEMBASE register 205a and LOCALMEM
There is a BASE register 205b. The AGPMEMBASE register 205a is a register for setting a base address to which the AGP space of the NB 103 is mapped, and is provided to notify the DMAC 206 of the access destination. The LOCALMEMBASE register 205b is the ASIC1
A register for setting a base address to which 08 memory space is mapped is provided to notify the DMAC 206 of the access destination.

Next, the mutual relationship of the memory maps of the PCI 109, ASIC 108 and CPU 102 will be described. FIG. 5 shows PCI 109, ASIC 108 and C.
FIG. 6 is an explanatory diagram for explaining a mutual relationship of memory maps of PU 102.

The PCI I / O space 501 shown in FIG.
The PUII / O space of the ASIC 108 visible to the PU 102, the PCIMEM space 502 is the PCIMEM space of the ASIC 108 visible to the CPU 102, and the internal register space 503 is the ASIC1 visible to the CPU 102.
08 internal register space. In addition, AGP504
Is a memory space that can be accessed by the AGP bus protocol managed in the NB 103, and is a MEM-P50.
Reference numeral 5 is a memory space managed by the NB 103.

The PCI I / O space 506 has an ASI
PCIIIO space of C108, PCIMEM space 507 is PCIMEM space of ASIC108,
The internal register space 508 is an internal register space of the ASIC 108. In addition, AGP509 is ASIC10
8 is a memory space accessible from the AGP bus protocol, and the MEM-C 510 is a memory space managed by the ASIC 108. The base 511 is M
The start address of the EM-C510 and the base 512
Is the start address of the AGP space.

Further, the MEM-C 513 is a memory space of the MEM-C 107 accessible from the engine unit 110, the AGP 514 is an AGP space accessible from the engine unit 110, and the PCIMEM space 515.
Is a PCIMEM space actually accessed by the CPU 102 via the ASIC 108, and a PCI I / O space 516 is a PCI II / O space actually accessed by the CPU 102 via the ASIC 108.

As shown in the figure, the PCI I / O space 51
6, PCI I / O space 506 and PCI I / O space 5
01 is associated with each other, and PCIMEM space 515,
The PCIMEM space 507 and the PCIMEM space 502 are associated with each other. Further, the internal register space 508 and the internal register space 503 are associated with each other.

Furthermore, AGP514, AGP509, A
GP504 is associated with each other, MEM-C513,
The MEM-C510 and the MEM-P505 are associated with each other. A detailed description of mapping will be given later.

Next, the operation of the printer shown in FIG. 1 will be described. When this printer is powered on,
The CPU 102 is a BIOS ahead of the SB 105 (not shown).
Start the boot from the NB103 initialization and SB1
05 initialization. Then, during this initialization, the CONFIG 202 of the ASIC 108 is accessed via the AGP 106, and the BAR 202a and BAR shown in FIG. 3 are accessed.
202b is set, and the initialization of the ASIC 108 as an AGP device is completed.

In this way, the AGP of the ASIC 108 is
When initialization as a device is completed, the ASIC 108
The internal register 205 of can be accessed. Specifically, the AGPMEMBASE register 2 of this internal register 205
05a is set to which address in the ASIC 108 the AGP space is mapped, and the LOCALMEMBASE register 205b is set to where the local memory MEM-C107 directly managed by the ASIC 108 is mapped.

That is, the address of the base 512 shown in FIG. 6 is set in the AGPMEMBASE register 205a shown in FIG. 4, and the base 511 is set in the LOCALMEMBASE register 205b.
Address is set. Then, when the mapping is performed, the memory map shown in FIG. 5 is obtained.

As a result, when viewed from the CPU 102,
The system memory exists at the location of the MEM-P 505, and the AGP space 504 is mapped thereon. The setting of the AGP space 504 is set in the register of the NB 103. Therefore, the register mapped in the PCI space can be seen at the upper address.

The internal register space 503, PCIMEM space 502 and PCI I / O space 501 are the CO of PCI.
It is set by the BAR 202a of the NFIG202. ASIC1
08 memory under control MEM-C107BAR20
2b and can be accessed from the CPU 102 via PCI.

The base address set in the BAR 202a means the beginning of the internal register 508, and the PCI address
The MEM space 507 and the PCI I / O space 506 are fixedly defined by an offset with respect to the base address.

When the CPU 102 accesses the PCIMEM space 507, the write access is posted, and the CP
U102 will be released and ready for the next task. The write access is written in the PCIMEM space 515 at the same address of the PCI 109. PCII /
Similarly, the write access to the O space 506 is PCI1.
It is written to the PCI I / O space 16 of 09.

Further, the CPU 102 uses the PCIMEM space 5
When 02 is read access, the access is NB10
Converted to AGP access in 3 and PC of ASIC108
Read access to the IMEM space 507.

The ASIC 108 is a PCI of the PCI 109.
Accessing the MEM space 515 takes time until the data is read, so a retry is once returned to the AGP access from the CPU 102. NB1
Upon receiving the retry signal, 03 repeats the read access. When the ASIC 108 reads the data from the PCI 109 and prepares the data, the data is transferred to the NB 10
Return to 3. The NB 103 transfers data with the CPU 102, and the transaction is completed.

Engine unit 11 connected to PCI 109
0 has a CONFIG register, and by mapping its base address to somewhere in the PCIMEM space 515, the engine PCI register 602 of the engine unit 110 shown in FIG. 6 can be accessed. In the PCIMEM space 601 shown in FIG.
It is a PCIMEM space that can be accessed via the IC 108, and the engine PCI 602 is
Engine PCI registers mapped in PCIMEM space accessible via IC.

A CONFIG register 209 also exists on the PCI 109 side of the ASIC 108 for access from the engine unit 110. Specifically, the AGP of NB103
AS a base register for accessing the space 504
A base register for accessing the memory MEM-C510 under the control of the IC 108, a base register for setting the input address of the image input DMAC of the ASIC 108, and a base register for setting the output address of the image output DMAC of the ASIC 108. and so on. All such work is performed in the initialization process.

When the mapping is completed, the memory map is as shown in FIG. 5, and the CPU 102 can access according to this memory map. Further, the engine unit 110 can access the memory according to the memory map as shown in FIG. The engine unit 110 also performs self-diagnosis after power-on and waits for mapping by the CPU 102. Therefore, when the initialization is completed, the engine unit 11
0 can also communicate with the CPU 102.

When the initialization of the software is completed, the controller 101 notifies the operation unit 111 of a message indicating that printing is possible, and enters a standby state in preparation for receiving data from the host.

The ASIC 108 is a network, IEEE
It has an interface for connecting to a host such as E1394, USB, etc. When data reception starts, the transmission data is sequentially interpreted and drawing is started on the MEM-P 104. Then, when the drawing is completed, a command is transmitted to the engine unit 110 to instruct the drawing of the drawn picture.

The CPU 102 operates the internal register of the NB 103 to make the data of the MEM-P 104 look like the space of the AGP 504, rewrites the table on the memory, and sets it so that it can be seen from the engine unit 110 in the AGP space 514. The engine unit 110 receives the start address of the buffer with the drawn picture, activates the DMAC inside the engine unit 110, and executes the MEM through the AGP 514.
-Read out the picture on P505. At this time, the ASIC 108
Performs target operation for PCI109, and AG
For P106, it operates as a master. The engine unit 110 reads out a picture according to the internally generated timing.

Next, the engine section 110 shown in FIG. 1 will be described. FIG. 7 shows the engine unit 110 shown in FIG.
6 is an explanatory diagram for explaining the operation timing of FIG. A paper size 701 shown in the figure is a paper size determined by main scanning and sub-scanning, FGATE 702 is a signal indicating the effective range of paper sub-scanning, and LGATE 703 is
This is a signal indicating the effective range of the main scanning of the paper, and is LSYNC.
Reference numeral 704 is a synchronization signal that is asserted at the beginning of main scanning.

As described above, the engine section 110 determines the effective area F in the sub-scanning direction according to the output paper size 701.
GATE 702 and effective area LGATE7 in the main scanning direction
03 and an LSYNC 704 that represents the start of each main scanning line.

When the engine section 110 receives a print command, the sheet is conveyed and at the same time an FGATE 702 is produced, and the number LS at which the FGATE 702 is asserted.
Start transfer to read the picture into the internal buffer 704 hours before YNC.

FIG. 8 is an explanatory diagram for explaining the basic timing signal for PCI transfer. In the figure, LSY
The NC 801 is a line sync, the DREQ 802 is a data request, the DATA 803 is a data transfer for one line, the XREQ 804 is a bus request signal of the PCI bus, the XGNT 805 is a bus grant signal of the PCI bus, and the TRANZ 806 is a PCI. It is a bus transaction for a bus.

PCICLK807 is the basic clock of PCI, XFRAME808 is the FRA of PCI.
ME signal, XDEVSEL809 is PCI DE
VIR signal, XIRDY810 is the IR of PCI
DY signal, XTRDY811 is PCI TRDY
AD [31: 0] 812 is a PCI address / data bus signal, and CBE [3: 0] 813 is a PCI command / byte enable signal.

As shown in the figure, a data transfer request DREQ 802 is generated at the rising edge of LSYNC 801.
Is asserted, and the transfer of DATA 803 for one line is completed. Data for one line is transferred in synchronization with each LSYNC 801.

XREQ 804 is asserted on the PCI 109, XGNT 805 is asserted when the use of the bus is permitted, and one PCI transaction 806 is performed. Repeat the PCI transaction 1
The data transfer for the line is completed. The PCI transaction 806 is a burst transfer.

The PCI signal is synchronized with the rising edge of PCICLK807. When the bus use permission is obtained, the engine unit 110, which is the bus master, is XFRAME80.
8 is asserted, and at the same time, the address AD [31: 0] 81
2 and the command CBE [3: 0] 813. AS
The IC 108 uses the address AD [31: 0] issued by the engine unit 110 in the base address register of its own CONFIG.
When 812 hits, XDEVSEL 809 is asserted.

If the engine unit 110 can receive the data, after confirming the assertion of the XDEVSEL 809, the XIRDY 810 is asserted, and the target of receiving the data is ASI.
Teach C108. The ASIC 108 uses the command CBE
If data is prepared for [3: 0] 813,
Assert XTRDY811 to put data on the bus.

Then, in synchronization with PCICLK807,
If there is data, one data is continuously transferred per clock. One clock before the last data, the engine unit 110, which is the bus master, negates the XFRAME 808, indicating that the next data is the last data of this transaction. After data transfer is completed, ASIC108
Negates XDEVSEL 809 and XTRDY811. The engine unit 110 negates XTRDY811 to complete the transaction.

Next, a specific example of the engine section 110 shown in FIG. 1 will be described. FIG. 9 is a diagram showing the configuration of a color one-drum plotter as the engine unit 110 shown in FIG. The engine section 900 shown in the figure comprises a PCI unit 902 and an LDB 903. The PCI unit 902 is a unit that executes transfer by the PCI 901 bus protocol and DMA and command communication with the controller, and the LDB 903 is a unit that draws on a drum with a laser.

As shown in the figure, this engine section 900
Is a color one-drum plotter, so a full-color image is color-separated into YMCK and one full-color output is completed by passing the paper through one drum four times.
Inside the engine unit 900, the toner corresponding to the color is selected and transferred.

Next, a color four-drum plotter used as the engine section 110 shown in FIG. 1 will be described.
FIG. 10 is a block diagram showing the configuration of a color four-drum plotter used as the engine unit 110 shown in FIG. Each drum unit has a toner corresponding to each color, and a command in the memory space of the ASIC 108 which is a target for the necessary image data is provided a few line cycle time before each unit outputs a picture corresponding to a physical position. Read to the address specified by. In addition, here, a laser drive unit LDB1001, an image processing unit 1002, an image shift processing unit (SFT) 1003, a drum relation and D
The MAC is collectively called a drum unit.

The image processing unit 1002 converts the obtained analog signal into a digital signal, performs shading correction, M
The SFT 1003 is an image processing unit that performs TF correction, γ correction, and the like, and the SFT 1003 is an image shift unit that performs image shifting and clipping.

Each drum unit is in charge of each color and outputs the YMCK image plane. If transfer is performed in the order of YMCK from the drum on the side closer to the paper transport tray, the Y-color DMAC reads the data for one line of main scanning to the address specified by the ASIC 108. .

This DMAC is a PCI block 1004 in the figure.
Exist for each color, are arbitrated when necessary, and the image data for each color is transferred in order. The transfer unit of each color is a burst unit and is transferred at the timing shown in FIG. However, the YMCAs are not synchronized with each other and generate transfer requests at necessary timings. FIG. 8 shows the transfer timing of a single color, and the actual PCI
When the bus is the busiest, YMCA burst transfer is alternately performed.

Next, a color scanner used as the engine section 110 shown in FIG. 1 will be described. FIG. 11 shows
FIG. 2 is a block diagram showing a configuration of a color scanner used as an engine unit 110 shown in FIG. 1. CCD shown in FIG.
Reference numeral 1101 denotes a color reading element capable of simultaneously reading three colors, and the image processing unit 1102 is a CCD.
An image processing unit that converts an analog signal read from 1101 into a digital signal and performs shading correction, MTF correction, γ correction, and the like.

The SFT 1103 is an image shift unit for shifting or clipping an image, the scaling unit 1104 is a unit for enlarging / reducing, and the color separation unit 1105 is for separating three RGB colors into four YMCK colors. Units, ENC 1106-1108
Is a unit for converting a multi-valued image into a code.

The PCI unit 1110 comprises a part that executes the PCI bus protocol and DMAC, and transfers an image to the controller. In addition, it is a unit that transmits a command from the controller to the engine unit.

When receiving an instruction from the host or an instruction from the operation unit 111 from the user, the scanner 110
0 reads an image and transfers it to the memory of the controller 101. The memory is MEM-C107 or MEM
-P104 can be selected. The controller 101 delivers the image read through the network I / F to the operator.

Next, the flow of images will be described. CCD 11
The RGB image data read in 01 is converted from an analog signal to a digital signal in the image processing unit 1102, and then MTF correction, shading correction, and γ correction are performed, and the image shift unit corresponds to the designated area of the reading area. The image is shifted and cut out in 1103, and then converted in the scaling unit 1104 according to the designated magnification or resolution.

In the color separation unit 1105, when the read request is RGB, the read request remains YMC and the read request is YMC.
If it is K, it is decomposed into YMCA, and if a code is requested by a command, it is converted into a code by the encoder, and PC
It is passed to the I unit 911. A DMAC corresponding to each color exists in the PCI unit 911, and image data is transferred to the controller 101 via the PCI bus 1111 in synchronization with the reading timing. The controller 101 can receive data for each color.

As described above, in the first embodiment, when the interface of the CPU 102 is not open to the public, the NB 103 and the AS that form a part of the chip set are connected.
Since the IC 108 is configured to be connected using the AGP 106, high-speed print processing can be performed.

(Second Embodiment) By the way, in the above-mentioned first embodiment, the case where the present invention is applied to the printer is shown, but here, the case where the present invention is applied to the multi-function peripheral will be shown. FIG. 12 is a functional block diagram showing the configuration of the multi-function peripheral according to the second embodiment.

As shown in FIG.
Has a monochrome line printer (B & W LP) 1201, a color line printer (Color LP) 1202, and other hardware resources 1203, and the software group 1210 includes a platform 1220 and an application 1230.

The platform 1220 interprets the processing request from the application 1230 and manages one or a plurality of hardware resources and the control service described below for generating a hardware resource acquisition request, and controls from the control service. System resource manager (SRM) that arbitrates acquisition requests
Ource Manager) 1223) and a general-purpose OS 1221.

This control service is formed by a plurality of service modules. Specifically, the SCS
(System Control Service) 1222 and ECS (Engi
ne Control Service) 1224 and MCS (Memory Con
trol service) 1225 and OCS (Operation panel)
Control Service) 1226 and FCS (FAX Control S)
ervice) 1227 and NCS (Network Control Servic
e) There is 1228. In addition, this platform 12
Reference numeral 20 has an application program interface capable of receiving a processing request from the application by a predefined function.

The general-purpose OS 1221 is a general-purpose operating system such as UNIX (registered trademark), and executes each software of the platform 1220 and the application 1230 as processes in parallel. By using the open source UNIX, the security of the program can be secured, the network can be supported, and the source code can be easily obtained. Further, royalties of OS and TCP / IP are not required, and outsourcing becomes easy.

The SRM 1223 controls the system and manages resources together with the SCS 1222. The SRM 1222 includes an engine unit such as a scanner and a plotter, a memory, an HDD file, a host I / O (Centro I / F,
Network I / F, IEEE1394 I / F, RS2
32C I / F, etc.) performs arbitration according to a request from an upper layer that uses a hardware resource, and controls execution.

Specifically, this SRM 1223 determines whether the requested hardware resource is available (whether it is not used by another request), and if it is available, the requested hardware resource is available. Tell upper layers that wear resources are available. In addition, hardware resource utilization scheduling may be performed in response to a request from an upper layer, and the request content (for example, paper conveyance and image forming operation by the printer engine, memory reservation, file generation, etc.) may be directly executed. .

The SCS1222 includes (1) application management,
(2) Operation unit control, (3) system screen display (job list screen, counter display screen, etc.), (4) LED display, (5) resource management, and (6) interrupt application control. Specifically, in (1) application management, processing of registering an application and notifying other applications of the information is performed. With respect to the registered application, the state of the engine unit is notified according to the system setting and the request setting from the application. In addition, the registered applications are inquired as to whether or not the system is in a state transition such as a power mode transition inquiry and an interrupt mode.

Further, in (2) operation unit control, exclusive control of the operation unit use right of the application is performed. Then, the key information from the operation unit driver (OCS) is exclusively notified to the application having the right to use the operation unit. This key information performs mask control for temporarily stopping the notification in response to a system state transition such as application switching.

Further, in (3) system screen display, a warning screen corresponding to the state of the engine section is displayed in accordance with the content of the request from the application having the operation section usage right. Among these, there is one that turns on / off the warning display according to the state of the application such as the user restriction screen. In addition to the state of the engine section, display control of a job list screen for displaying the reservation / execution status of jobs, a counter screen for displaying total counters, and a screen indicating that CSS is being notified is performed. Regarding these system screen displays,
Drawing is performed as a system screen that covers the application screen without requesting the application to release the right to use the operation unit.

In addition, (4) LED display shows a warning LE.
It controls the display of system LEDs such as D and application keys. The LED unique to the application is directly controlled by the application using the display driver.

In the resource management (5), the application (ECS) provides a service for exclusive control of engine resources (scanner, staple, etc.) that must be excluded when executing a job, and (6)
In the interrupt application control, control and service are performed to prioritize the operation of a specific application.

The ECS 1224 is a monochrome line printer (B & W LP) 1201 and a color line printer (Color L).
P) 1202 and other hardware resources 1203 for controlling the engine unit, and performs image reading and printing operations, status notification, jam recovery, and the like.

Specifically, a series of copy / scan / print operations are realized by sequentially issuing print requests to the SRM 1223 in accordance with the job mode designation received from the application 1230. This ECS12
The job to be handled by 24 is assumed to have a scanner (SCANNER) specified for the image input device or a plotter (PLOTTER) specified for the image output device.

For example, in the case of a copy operation, "SCANNE
"R → PLOTTER" is specified, "SCANNER → MEMORY" is specified for file accumulation, and "SCANNER → FAX_IN" is specified for facsimile transmission. When printing a stored file or printing from the printer application 1211, “MEMORY → PLOTTER” is designated, and when receiving a facsimile, “FAX_OUT → PLOTTE” is specified.
R "is designated.

Although the definition of the job differs depending on the application, the processing operation for one set of images handled by the user is defined as one job here. For example, in the case of the copy ADF (Automatic Document Feeder) mode, one job is to read one set of documents placed on the platen, and the platen mode is one job to read the final document. . In the case of the copy application 1212, the operation of copying a bundle of documents is one job, and in the case of the fax application 1213, the operation of sending one document or the operation of receiving one document is one job, and the operation of the printer application is In this case, one document print operation is one job.

The MCS 1225 performs memory control, and specifically, performs acquisition and release of an image memory, use of a hard disk device (HDD), compression and expansion of image data, and the like.

Here, the functions necessary for managing the information required as an image data file stored in the hard disk drive are (1) file access (generation / generation
Delete / Open / Close) function (including exclusive processing),
(2) File name / ID management (file / user) /
Various file attribute management such as password management / accumulation time management / page number / data format (compression method etc.) / Access restriction / creating application / printing condition management (management of image data file of physical page unit)
(3) Join / insert / on a file basis and page basis
Disconnection function, (4) file sorting function (accumulation time order / user ID order, etc.), (5) notification of all file information (for display / search), (6) recovery function (corrupted file / page discard), (7) There is an automatic file deletion function.

The functions for holding and accessing the image data to the memory such as RAM are (1) the function of acquiring the file and page / band attribute information from the application 1230, and (2) the application 1
Secure, release, and read (Re
ad), write (Write) function.

The OCS 1226 is a module for controlling the operation panel which is a means for transmitting information between the operator and the main body control, and is a process for notifying the main body control of an operator's key operation event, a library function for each application to construct a GUI. Is provided, processing for managing the constructed GUI information for each application, display reflection processing on the operation panel, and the like are performed.

This OCS 1226 is provided with (1) a library providing function for constructing a GUI, (2) operation unit hardware resource management function, (3) VRAM drawing / LCD display function (hardware display, display application switching, display) Language switching, window dark display, message / icon blink display, message concatenation display), (4) hard key input detection function, (5) touch panel key input detection function,
(6) LED output function and (7) buzzer output function.

The FCS 1227 is used for facsimile transmission / reception from each application layer of the system controller using the PSTN / ISDN network, registration / quotation of various facsimile data managed by BKM (backup SRAM), facsimile reading, facsimile reception printing, fusion transmission / reception. It provides an API for performing.

Specifically, this FCS 1227 is
(1) PS the document requested to be sent from the application layer
Sending function to send to a facsimile receiver using TN / ISDN network, (2) Fax receiving screen received from PSTN / ISDN network, receiving function to transfer and print various reports to each application layer, (3) Phonebook quotation / registration function for quoting and registering fax management items such as phonebook and group information stored in the fax board, (4) Transmission / reception result history information stored in the BKM mounted on the fax board It has a fax log notification function for notifying an application that requires such information, and (5) an event notification function for notifying an event of an application registered in the FCS when the status of the fax board changes.

The NCS 1228 is a module group for providing services that can be commonly used for applications that require network I / O. The NCS 1228 distributes data received from each protocol from the network side to each application, and Mediates when data is transmitted from the network to the network side. Specifically, ftpd, httpd, lpd, snmpd, telnetd,
It has a server daemon such as smtpd and a client function of the same protocol.

Application 1230 includes page description language (PDL), PCL and postscript (P
A printer application 1211, which is a printer application having S), a copy application 1212 which is a copying application, a fax application 1213 which is a facsimile application, a scanner application 1214 which is a scanner application, and a net file application. It has a certain net file application 1215 and a process inspection application 1216 which is a process inspection application. Since each application 1211 to 1216 can operate and execute using each process on the platform 1220, screen control,
A screen display control program that performs key operation control and job generation is the main component. Note that NCS122
A new application can also be installed via the network via the network connected by 8. Further, each application can be added or deleted for each application.

As described above, this multifunction peripheral 1200 does not have a controller board for each function such as printer, copy, and facsimile, unlike the conventional multifunction peripheral, but simply shares the printer application, copy application, and facsimile application. It does not run on the OS. That is, the multifunction peripheral 1200 centrally processes the processing commonly required by each application on the platform 1220, thereby improving the development efficiency of each application and increasing the productivity of the entire apparatus. .

Next, the hardware configuration of the multifunction peripheral 1200 shown in FIG. 12 will be described. FIG. 13 is a block diagram showing the hardware configuration of the multifunction peripheral 1200 shown in FIG. As shown in FIG.
Is an operation panel 1310, fax control unit (FCU) 1320, USB 1330,
The configuration is such that the IEEE13941340 and the engine unit 1350 are connected to the ASIC 1301 of the controller 1300 by a PCI bus or the like.

The controller 1300 uses the ASIC 130.
1 is connected to the MEM-C 1302, HD 1303, etc., and the ASIC 1301 and the CPU 1304 are connected via the NB 1305 of the CPU chip set. In this way, the reason for connecting via the NB 1305 is that the interface of the CPU 1304 itself is not open to the public.

Here, the ASIC 1301 and the NB 13
05 is not connected simply via PCI, but is connected via AGP 1308 in terms of hardware configuration. Thus AGP1308
The reason why we decided to connect via
0 controls the execution of a plurality of processes forming the platform 1220 and the application 1230 shown in FIG.
This is because the performance will decrease.

The CPU 1304 controls the entire complex machine 1200. Specifically, the general-purpose OS 12
SCS12 forming platform 1220 on 21
22, SRM1223, ECS1224, MCS122
5, OCS1226, FCS1227, NCS1228
And the printer application 1211, which forms the application 1230, the copy application 1212, the fax application 1213, the scanner application 1214, the net file application 1215, and the process inspection application 1216.

The NB 1305 has a CPU 1304 and a MEM.
-P1306, SB1307, is a bridge for connecting the ASIC1301, MEM-P1306,
The SB 1307 is a system memory used as a drawing memory of the multi-function peripheral.
It is a bridge for connecting I devices and peripheral devices.

The MEM-C 1302 is a local memory used as a copy image buffer and a code buffer, and the ASIC 1301 is an IC for image processing use having a hardware element for image processing. Specifically, the ASIC 1301 is
It is connected to the NB 1305 which is a part of the chipset of the CPU 1304 via the P port 1400. In addition, AS
Since the specific configuration of the IC 1301 has already been described with reference to FIG. 2, detailed description thereof will be omitted here.

The HDD 1310 is a storage for accumulating image data, programs, font data, and forms, and the operation panel 1310 receives an input operation from the user and displays it to the user. It is an operation unit for performing.

Therefore, the ASIC 1301 has a ME
A RAM interface for connecting the M-C1302 and a hard disk interface for connecting the HDD 1310 are provided. When inputting / outputting image data to / from these storage units, the input / output destination is R.
It can be switched to AM interface or hard disk interface. As in the case of a graphic board, if the image is simply displayed on the display device at high speed, it is not necessary to switch to the hard disk in this part. In other words, in this multifunction machine 1200,
The memory interface is switched in order to handle not only the copying operation but also an application having a completely different data flow such as an operation as a net file application.

As described in the first embodiment, the AGP 1308 is a bus interface for a graphics accelerator card that has been proposed for speeding up graphics processing, and enables direct access to system memory with high throughput. , Is intended to speed up graphics accelerator cards.

Also in the second embodiment, 3D is originally used.
The NB 1305 and the ASIC 1301 are connected via the AGP 1308 used for smoothly displaying a (three-dimensional) image on the display. That is, in the multifunction peripheral 1200 according to the second embodiment, the CPU 130
Since 4 has the characteristic of activating a very large number of processes, they are connected via the AGP 1308 instead of the low-speed PCI that deteriorates the performance.

Next, the switching control of image data via the ASIC 1301 shown in FIG. 13 will be described.
The patterns for this switching include (1) "pattern 1" for outputting the scanner image data read by the scanner 1352 of the engine 1350 to the plotter 1351 of the engine 1350, and (2) outputting this scanner image data to the AGP 1308. "Pattern 2"
(3) There is a "pattern 3" in which the image data input from the AGP 1308 is output as plotter data to the plotter 1351.

More specifically, in the pattern 2, the multifunction machine 1200 has a PC FAX, a net file application, a CPU.
This is a pattern when operating as image processing, and PCI
The scanner image data input from the bus is transferred to the AGP 130.
8 is output. Further, pattern 3 is a pattern when the multifunction peripheral 1200 operates as a printer,
The image data input from the AGP 1308 is output to the PCI bus.

Hereinafter, these three patterns will be described in more detail with reference to the drawings. First, the pattern 1 will be described. FIG. 15 is an explanatory diagram for explaining the flow of image data in the case of pattern 1. As shown in the figure, this pattern 1 is a pattern when the multifunction peripheral 1200 operates as a copying machine, and returns image data (scanner image data) input from the PCI bus to the same PCI bus side. .

Specifically, the ASIC 1301 uses the scanner image data read by the scanner 1520 as a PC.
When received via the I-bus, this image data is sent to the MEM-C13 via a memory interface section (not shown).
02 is temporarily stored. After that, this MEM-C130
The scanner image data temporarily stored in 2 is output to the plotter 1510 via the PCI bus and printed on the printing paper. Although the image data does not pass through the AGP 1308, a control signal such as paper feeding is transmitted from the CPU 1304 to the plotter 1510 when printing is performed by the plotter 1510.

Next, the pattern 2 will be described. Figure 1
FIG. 6 is an explanatory diagram for explaining the flow of image data in the case of pattern 2. Originally, since the fax unit 1530 that performs fax transmission is added to the engine unit 1350 side, when performing normal fax transmission processing, the image data is output to the FCU 1320 via the PCI bus and the image data is output to the AGP 1308. It is not output.

However, in PC FAX that directly transmits FAX data to a computer, FAX data is transmitted to the computer via the network I / F unit 1500. Therefore, in such a case, in FIG.
, The scanner image data read by the scanner 1510 is compression-encoded by the ASIC 1301, and the compression-encoded FAX data is converted into ASICs 1301 to AGP.
It is transmitted to the network I / F unit 1500 via 1308 to NB1305.

Similarly, when the scanning process is performed, the read image data is stored in the MEM-C 1302, so that the image data does not pass through the AGP 1308. However, when the computer on the network is used as a network scanner, the image data captured by the scanner 1520 is transmitted to the external computer via the network I / F unit 1500.

When data transfer processing is performed by the net file application 1215, the scanner 151
The scanner image data read by 0 is the HDD 1303
It is stored in the
When the image data stored in the DD 1303 is requested, the image data stored in the HDD 1303 is ASI.
It is transmitted to an external computer via the network I / F unit 1500 via the C1301 to AGP1308 to NB1305.

In the pattern 2, the image data is temporarily stored in the MEM-C 1302 or the HDD 1303, but the reason is mainly to make it possible to adjust the data transfer rates of the PCI interface and the AGP interface.

Next, the pattern 3 will be described. Figure 1
FIG. 5 is an explanatory diagram for explaining the flow of image data in the case of pattern 3. As shown in FIG.
When 0 performs a print operation, print data described in, for example, page description language (PDL) is received by the network I / F unit 1500. And this P
The DL data is expanded into bitmap data (image data) on the MEM-P 1306, and this bitmap data is transmitted via the NB 1305 to AGP 1308 to the ASIC 130.
Input to 1. After that, this bitmap data is
Once stored in the MEM-C1302, this MEM-C1
The bitmap data stored in 302 is output to the plotter 1510 via the PCI bus. At this time, a control signal such as paper feeding can be transmitted from the CPU 1304 to the printer 1510.

It is also possible to perform lossless compression processing on the image data when temporarily storing the image data in the MEM-C 1302 or HDD 1303, and perform decompression processing when reading the temporarily stored image data. As a result, the size of the image data is compressed, and the MEM-C1302 or H
This is because more image data can be stored in the DD 1303.

Further, the CPU 1304 and the ASIC 1301
Since the mutual relations of the memory maps, etc. are similar to those described in the first embodiment, detailed description thereof will be omitted here.

As described above, according to the second embodiment, the platform 12 that is the base of the multifunction machine 1200 is used.
20 and a CPU 1304 and an ASIC that start and execute a plurality of processes that form an application 1230
Since it is configured to be connected to 1301 via the AGP 1308, even if the interface of the CPU 1304 is not open to the public, it is possible to provide a function as a multifunction peripheral at high speed without degrading performance.

In the second embodiment, SCS1222, SRM1223, ECS1224, M are used for convenience of explanation.
CS1225, OCS1226, FCS1227, NC
The case where the platform 1220 is formed by S1228 and the application 1230 is formed by the printer application 1211, the copy application 1212, the fax application 1213, the scanner application 1214, the net file application 1215, and the process inspection application 1216 has been shown. The present invention is not limited to this, and can be applied when other software elements are added to the platform 1220 or the application 1230.

[0150]

As described above, according to the first aspect of the present invention, the scanner image data read by the scanner input from the engine interface unit is output to the engine interface unit as plotter data for the plotter, or Since the scanner image data is output to the chipset interface unit or the image data input from the chipset interface unit is output to the engine interface unit as plotter data for the plotter, the interface is disclosed. When a CPU which is not provided is used as a controller of the image forming apparatus, an effect is obtained that an image processing integrated circuit capable of efficiently exchanging data between the CPU and the engine section can be obtained by smooth switching control.

According to the invention of claim 2, the image data input from the engine interface section or the chipset interface section is once output to the memory interface section, and then the image data is input from the memory interface section. Since it is configured to output to the engine interface unit or the chipset interface unit, it is possible to obtain an image processing integrated circuit capable of adjusting the data transfer speed of the engine interface unit and the chipset interface unit.

According to the third aspect of the invention, since the input / output destination is switched to the RAM interface or the hard disk interface when the image data is input / output using the memory interface section, the copying operation is of course performed. Therefore, it is possible to obtain an image processing integrated circuit capable of handling an application having a different data flow such as a net file application.

According to the invention of claim 4, the lossless compression process is performed when the image data is output to the memory interface unit, and the decompression process is performed when the image data is input from the memory interface unit. Thus, an effect that an image processing integrated circuit capable of storing a larger amount of image data in the storage unit can be obtained.

According to the invention of claim 5, the chipset interface section is an accelerated graphic port (AGP), and the north bridge forming a part of the CPU chipset is connected to this accelerated graphic port. Since it is configured to connect, AG
An effect is obtained that an image processing integrated circuit capable of performing high-speed data transfer via P can be obtained.

Further, according to the invention of claim 6, the engine interface unit is a PCI interface for accommodating a PCI bus, and the engine unit is configured to be connected to this PCI interface. It is possible to obtain an image processing integrated circuit that can eliminate the need for modification.

According to the invention of claim 7, the engine section is a monochrome plotter having a PCI interface,
Since it is configured to have a 1-drum color plotter, 4-drum color plotter, copier engine or fax unit, image processing that can meet various needs such as monochrome printing, color printing, image reading, copying and faxing. The integrated circuit for use is obtained.

According to the invention of claim 8, the scanner image data input from the engine interface unit and read by the scanner is output to the engine interface unit as plotter data for the plotter, or the scanner image data is output to the chip. Since it is configured to control whether to output to the set interface section or output the image data input from the chipset interface section to the engine interface section as plotter data to the plotter, the CPU whose interface is not exposed When used in the controller of the forming apparatus, an effect is obtained that an image forming apparatus capable of efficiently exchanging data between the CPU and the engine section can be obtained by smooth switching control.

According to the ninth aspect of the invention, the image data input from the engine interface section or the chipset interface section is once output to the memory interface section, and then the image data is input from the memory interface section. Since the image is output to the engine interface unit or the chipset interface unit, it is possible to obtain an image forming apparatus capable of adjusting the data transfer rate of the engine interface unit and the chipset interface unit.

According to the tenth aspect of the invention, when inputting / outputting the image data using the memory interface section, the input / output destination is switched to the RAM interface or the hard disk interface. Therefore, it is possible to obtain an image forming apparatus capable of handling an application having a different data flow such as a net file application.

According to the eleventh aspect of the invention, the lossless compression process is performed when the image data is output to the memory interface unit, and the decompression process is performed when the image data is input from the memory interface unit. Therefore, it is possible to obtain an image forming apparatus capable of storing a larger amount of image data in the storage unit.

According to the twelfth aspect of the present invention, the chipset interface section is an accelerated graphic port (AGP), and the north bridge forming a part of the CPU chipset is connected to the accelerated graphic port. Since it is configured to connect, A
There is an effect that it is possible to obtain an image forming apparatus capable of performing high-speed data transfer via GP.

Further, according to the invention of claim 13, the engine interface unit is a PCI for accommodating a PCI bus.
Since this is an interface and the engine unit is configured to be connected to this PCI interface, there is an effect that it is possible to obtain an image forming apparatus capable of eliminating the need to change the connection form of the engine unit.

According to the fourteenth aspect of the present invention, the engine unit is configured to have a monochrome plotter having a PCI interface, a one-drum color plotter, a four-drum color plotter, a copier engine or a fax unit. It is possible to obtain an image forming apparatus capable of meeting various needs such as monochrome printing, color printing, image reading, copying, and fax.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of a printer according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of the ASIC shown in FIG.

FIG. 3 is an explanatory diagram for explaining an internal structure of CONFIG shown in FIG.

FIG. 4 is a DMA provided on the internal register shown in FIG.
It is an explanatory view for explaining a space base register for C.

FIG. 5 is an explanatory diagram for explaining a mutual relationship of memory maps of PCI, ASIC, and CPU.

FIG. 6 is an explanatory diagram for explaining a PCIMEM space of an engine unit.

FIG. 7 is an explanatory diagram for explaining an operation timing of the engine unit shown in FIG.

FIG. 8 is an explanatory diagram for explaining a basic timing signal of PCI transfer.

9 is a diagram showing the configuration of a color one-drum plotter as the engine unit shown in FIG.

10 is a block diagram showing a configuration of a color four-drum plotter used as the engine unit shown in FIG.

11 is a block diagram showing the configuration of a color scanner used as the engine unit shown in FIG.

FIG. 12 is a functional block diagram showing a configuration of a multi-function peripheral according to the second embodiment.

13 is a block diagram showing a hardware configuration of the multi-function peripheral shown in FIG.

14 is a block diagram showing the configuration of the ASIC shown in FIG.

FIG. 15 is an explanatory diagram illustrating a flow of image data in the case of pattern 1.

FIG. 16 is an explanatory diagram illustrating a flow of image data in the case of pattern 2.

FIG. 17 is an explanatory diagram illustrating a flow of image data in the case of pattern 3.

[Explanation of symbols]

101 controller 102 CPU 103 NB (Northbridge) 104 MEM-P (system memory) 105 SB (South Bridge) 106 AGP 107 MEM-C (local memory) 108 ASIC 109 PCI 110 engine 1300 controller 1301 ASIC 1302 MEM-C 1303 HDD 1304 CPU 1305 NB 1306 MEM-P 1307 SB 1308 AGP 1310 Operation panel 1320 Fax control unit 1330 USB 1340 IEEE 1394 1350 engine 1500 Network I / F part 1510 printer 1520 scanner 1530 FAX unit

Claims (14)

[Claims] 1. An engine interface unit for connecting an engine unit having a scanner and a plotter, a chipset interface unit for connecting a chipset unit of a CPU, and a scanner image input from the engine interface unit and read by the scanner. The data is output to the engine interface unit as plotter data for the plotter, the scanner image data is output to the chipset interface unit, or the image data input from the chipset interface unit is plotted to the plotter. An image processing integrated circuit, comprising: a switching control unit that controls whether to output as data to the engine interface unit. 2. A memory interface unit for connecting a storage unit for storing image data and the like, wherein the switching control unit stores the image data input from the engine interface unit or the chipset interface unit in the memory interface unit. 2. The integrated circuit for image processing according to claim 1, wherein the image data is output once to the engine interface unit or the chipset interface unit by inputting the image data from the memory interface unit. 3. The memory interface unit is an RA
The switching control unit has an M interface and a hard disk interface, and when inputting / outputting image data using the memory interface unit,
The integrated circuit for image processing according to claim 2, wherein an input / output destination is switched to the RAM interface or the hard disk interface. 4. The reversible compression process is performed when the image data is output to the memory interface unit, and the decompression process is performed when the image data is input from the memory interface unit. Image processing integrated circuit. 5. The chipset interface unit is an accelerated graphic port, and a north bridge forming a part of the chipset of the CPU is connected to the accelerated graphic port. 4. The image processing integrated circuit described in any one of 4 to 4. 6. The engine interface unit is P
6. The image processing integrated circuit according to claim 1, wherein the image processing integrated circuit is a PCI interface that accommodates a CI bus, and the engine unit is connected to the PCI interface. 7. The engine section includes a black-and-white plotter having the PCI interface, a one-drum color plotter, a four-drum color plotter, a copier engine, or a fax unit. An integrated circuit for image processing according to any one of the above. 8. An image forming apparatus for connecting an engine unit having a scanner and a plotter and a CPU to a controller having an integrated circuit for image processing, and performing image forming processing under the control of the CPU, wherein the controller comprises: An engine interface unit for connecting the engine unit, a chipset interface unit for connecting the chipset unit of the CPU, and scanner image data read by the scanner input from the engine interface unit to plotter data for the plotter. Or output the scanner image data to the chipset interface unit, or the image data input from the chipset interface unit as plotter data to the plotter. An image forming apparatus characterized by comprising a switching control unit which controls switching whether to output to the serial engine interface. 9. The controller further includes a memory interface unit that connects a storage unit that stores image data and the like, and the switching control unit stores the image data input from the engine interface unit or the chipset interface unit. 9. The image forming apparatus according to claim 8, wherein the image data is output to the memory interface unit once, and then the image data is input from the memory interface unit and output to the engine interface unit or the chipset interface unit. . 10. The memory interface unit is R
The switching control unit has an AM interface and a hard disk interface, and switches the input / output destination to the RAM interface or the hard disk interface when inputting / outputting image data using the memory interface unit. The image forming apparatus according to claim 9. 11. The method according to claim 10, wherein lossless compression processing is performed when image data is output to the memory interface unit, and decompression processing is performed when image data is input from the memory interface unit. Image forming apparatus. 12. The chipset interface unit is an accelerated graphic port, and a north bridge forming a part of a chipset of the CPU is connected to the accelerated graphic port. The image forming apparatus according to any one of 1 to 11. 13. The engine interface unit comprises:
A PCI interface that accommodates a PCI bus,
The image forming apparatus according to any one of claims 8 to 12, wherein the engine unit is connected to the PCI interface. 14. The engine section includes a black-and-white plotter having the PCI interface, a one-drum color plotter, a four-drum color plotter, a copier engine, or a fax unit. The image forming apparatus according to any one of the above.