JP2003085995A - Semiconductor memory integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory integrated circuit in which optimum defect relieving efficiency can be set by only change of connection of wirings. SOLUTION: This circuit is provided with a memory cell array comprising redundant elements used for replacement of a defective element, a decoder circuit performing row and column selection of this memory cell array, and a replacement control circuit storing defective address, performing detection of coincidence between an inputted address and a defective address and controlling the decoder circuit so that the defective element is replaced by a redundant element. The memory cell array is constituted of a plurality of cell blocks, while a plurality of banks are defined by combination of cell blocks, and page length determined by the number of bands activated simultaneously is set by only connection change of wirings. Combination of magnitude of a relieving region defined as a range in which replacement of defective elements are permitted by one redundant element in a memory cell array and the number of redundant elements used for replacing a defective element in one relieving region is set by only connection change of wirings.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory integrated circuit having a redundant circuit for repairing defects.

[0002]

2. Description of the Related Art In recent years, semiconductor memory integrated circuits, especially multi-bank products, have a small page length, for example, by optimizing the page length without specializing in one application because of uncertain market trends. It is becoming increasingly common to manufacture chips that can be used for low-end machines and large page lengths for high-performance high-end machines. Incorporating such an option into one chip may sacrifice defective relief efficiency depending on the application. If specialized for a product with a large page length, a large relief area could be secured, but since a small page length can be dealt with, the relief area must be made small and efficiency is reduced.

[0003]

[Problems to be Solved by the Invention] For example, a multi-bank DR
Consider the AM page length option. This type of DRAM
In, a plurality of banks are defined with a cell block, which is a range where word lines and bit lines are continuous, as a unit. The page length is determined by the number of simultaneously activated cell blocks, and thus the page length is basically set by allocating addresses to the cell blocks. In order to realize a DRAM chip with a different page length without changing the basic configuration such as the cell array configuration of the chip or the number of data lines, for example, instead of the highest address assigned to a cell block, the column address Try to use the highest level.
This makes it possible to obtain a DRAM chip in which the page length is doubled because the highest cell block address is not used. Since the number of data lines does not change, cell data having a double page length is sequentially transferred by column access.

Despite such a change in page length, if the redundant circuit system for defect relief is not treated, the relief efficiency when the page length is increased is sacrificed. For example,
It is assumed that one redundant column element (for example, a spare column selection line) is arranged for a plurality of column elements (for example, a column selection line) across a plurality of cell blocks. At this time, in the relief area defined as a range in which one redundant column element can be relieved of a defect, when the page length is doubled, the number of simultaneously activated cell blocks is doubled, so that it is substantially halved. It will be.

An object of the present invention is to provide a semiconductor memory integrated circuit in which the optimum defect relief efficiency can be set only by changing the connection of wiring. It is another object of the present invention to provide a semiconductor memory integrated circuit capable of giving optimum defect relief efficiency to each of the cases where one chip has a plurality of page length options.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a memory cell array including a redundant element used for replacing a defective element, a decoder circuit for selecting a matrix of the memory cell array, a defective address stored and an input address. And a replacement control circuit for controlling the decoding circuit so as to replace the defective element with a redundant element by performing coincidence detection of the defective address and replacing the defective element with the redundant element. In the semiconductor memory integrated circuit, the defective element is replaced by one redundant element in the memory cell array. The size of the relief area defined as the allowable range and the number of redundant elements used for defective element replacement in the one relief area are set only by changing the wiring connection. It is characterized by that.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 shows a DRAM chip structure according to an embodiment of the present invention. The capacity is 256 Mbit, and each has four memory cell arrays MCA1 to MCA4 of 64 Mbits. A row decoder ROWD that selects a word line for each cell array
Column decoder COLDE for selecting EC and bit line
C is placed.

Each cell array MCA1, MCA2, MCA
3, MCA4 respectively include upper and lower sub cell arrays MCA1a, MCA1b, and MCA1b sandwiching the row decoder ROWDEC.
MCA2a, MCA2b, MCA3a, MCA3b, M
It is composed of CA 4a and MCA 4b. Focusing on one sub cell array, it has a non-independent 2 × 16 bank configuration in which two sets of 16 non-independent banks are provided. Specifically, the banks BANK0 to BAN are provided in the cell array MCA1 on the upper left of the chip and the cell array MCA2 on the lower right.
There are four sets of K15, and the lower left cell array MCA2
In the upper right cell array MCA4, the bank BANK16
~ There are 4 sets of BANK31 each.

FIG. 2 shows the configuration in one bank by taking the BANK 9 of the cell array MCA1 as an example. One bank includes 2K bit line pairs BL0 to 2047,
bBL0 to 2047 and 512 word lines WL0 to 5
11 are crossed and arranged, and one cell block having a capacity of 1 Mbit is formed by arranging memory cells MC at the crossing portions. A sense amplifier (SA) column 20 which is shared between adjacent cell blocks is arranged. That is, in the cell array MCA1 of FIG. 1, within one set of 16 consecutive banks BANK0 to 15, there is a constraint that adjacent banks cannot be activated at the same time, and this is called a non-independent bank. In the example of FIG. 1, the banks BANK0 to BANK0 of each set are arranged in the cell array MCA1.
Within the range of 15, there is this restriction between adjacent banks, but if they belong to different sets, the adjacent banks BANK0 and BANK15 can be independently activated without sharing a sense amplifier.

Although not shown in FIG. 2, 32 pairs of spare bit lines for replacing defective bit line pairs are arranged in one cell block. When BANK9 is active, the sense amplifier SA is set to BANK8 or BANK.
Gate FYT of transistors 21 and 22 connected to 10
8b and FYT10a become "L", while the gate FYT9 of the transistors 23 and 24 at the connection with BANK9.
a and FYT9b become "H".

In the region of the sense amplifier row 20 between the cell blocks, two pairs of local data lines LDQ (LDQ0 <n>, 2 <n> are provided for each segment obtained by dividing the cell block into eight in the word line direction. Or LDQ1 <n>, 3
Each <n>(<n> is a segment number) is provided. A column select line CSL, which will be described later, controls the connection between the bit line pair BL, bBL and the local data line pair LDQ, bLDQ.

FIG. 3 shows the allocation of bank addresses, focusing on one cell array MCA1. Cell array MCA1 on the upper left of the chip and cell array MCA on the lower right of the chip
The highest bank address BA <4> = “0” is assigned to 2, and BA <4> = “1” is assigned to the lower left cell array MCA3 and the upper right cell array MCA4. Bank addresses BA <0> to <3> are BAN
It is used to select one of K0-15.
Among the cell arrays MCA2,4, BANK16-3
Bank address BA to select one of the
<0> to <3> are used.

The DRAM chip of this embodiment is 1K.
It has different page lengths of Byte and 2K Byte as options. Hereinafter, "KB" is simply referred to as "KB". The page length of 1 KB means an operation mode in which 1 KB of cell data is simultaneously activated in the cell array by a certain row address input. Specifically, in the case of this embodiment, with 1 KB page length, two cell arrays MCA1 and MCA2 (or MCA3 and MCA) are used.
In 4), two cell blocks (given the same bank number) are activated at the same time, and 4 (cell block) × 2K (bit line pair) = 1 KB of cell data is transferred to the bit lines. Is output. In case of 2KB page length,
Two cell arrays MCA1 and MCA2 (or MCA
3, MCA 4), four cell blocks are activated at the same time, and 8 (cell block) × 2
Cell data of K (bit line pair) = 2 KB is output to the bit line.

In FIG. 3, in the case of 1 KB page, the shaded cell block of BANK 5 (total of 2 cell blocks in one cell array) is activated, and in the case of 2 KB page length, the shaded area is added. At the same time as the cell block of BANK5 that was created, the same bank number BANK5 shown in the shaded area
The cell blocks (total of 4 cell blocks in one cell array) are activated.

In the case of 1 KB page length, the highest row address RA <9> is allocated to the left half and right half of one cell array. That is, RA <9> = "0" selects 16 banks in the right half of the cell array,
By A <9> = “1”, 16 banks in the left half of the cell array are selected. As a result, BA <0: 3> activates one bank (BANK5 in the example of FIG. 3) from the right half or the left half of one cell array. On the other hand, if the page length is 2 KB, the highest row address RA <
Instead of 9>, the highest column address CA <6> is assigned to the selection of the left and right halves of the cell array. That is, R
Since A <9> is not used, BA <0: 3> simultaneously activates the corresponding banks (BANK5 in the example of FIG. 3) on both the left and right sides of the cell array, and when these columns are accessed, the column address CA < By 6>, either the left side or the right side is selected.

FIG. 4 shows the address allocation for the 1/4 part of one cell array. As described above, there are 16 cell blocks each having a capacity of 1 Mbit, and the row address RA <0: 8> is assigned to 512 word lines WL of each cell block. Also,
The 32 cell block of the sub cell array on one side of the row decoder is horizontally divided into eight segment columns SEG0 to SEG7. Each segment column has a column address CA <
The 64 column selection lines CSL defined by 0: 5> run in the horizontal direction. At the time of column access, one column selection line CSL is selected in each segment column. Since one column selection line CSL transfers data of 4 bits, a total of 128 bits of 64 bits from the upper half of the chip and 64 bits from the lower half of the chip can be obtained by one column access. One spare column selection line SCSL is prepared for each segment column, and the defective column selection line corresponding to the defective bit line in the segment column can be replaced.

FIG. 5 shows the upper left cell array MCA1 of the chip.
Of 32 sub-cell arrays MCA1a above the row decoder ROWDEC are extracted to show the data transfer for a page length of 1 KB.
In this area, main data lines MDQ and bMDQ run in a horizontal direction of 32 pairs for data transfer of 32 bits, and the column selection line CSL is 64 × 8 (segment) in parallel therewith.
512 of them are running. Although not shown in the figure, a total of eight spare column selection lines SCSL, one for every 64 column selection lines CSL, are arranged.

At the time of column access, the column selection line CSL selected by the CBSL selector 51 in which the bank address BA <0: 3> enters is complemented by the column selection line CSL which does not include bank information. It is placed in parallel with. Column bank selection line CB
The SL exists in a one-to-one correspondence with the sense amplifier region between the cell blocks. As shown in FIG. 2, the sense amplifier row 20 is basically shared between the blocks, but between the left and right middle BANK0 and BANK15, in order to make these two banks independent, The configuration is such that two sense amplifier rows dedicated to the block are arranged side by side, and the total number of sense amplifier rows is 34. Corresponding to this, 34
A column bank selection line CBSL of the book is arranged.

FIG. 5 shows the case of a 1 KB page length, and of the two left and right cell blocks CBL and CBR to which the same bank number BANK5 is attached, the shaded right side defined by RA <9> = 0. The cell block CBR is shown in an activated state. At this time, the cell block CBR
The sense amplifier activation signal SAA that activates the sense amplifiers SA on both sides of is set to "H", but the sense amplifier activation signal SAA is set to "L" for the sense amplifiers SA on both sides of the left cell block CBL. It is.

On the other hand, at the time of column access, there is no way to distinguish the left and right cell blocks, so the bank address BA
Both cell blocks CBL, CB based on <0: 3>
The four column bank selection signal lines CBSL corresponding to R simultaneously become "H". The multiplexer MUX connects the bit line BL and the local data line LDQ and the local data line LDQ and the main data line MDQ. The multiplexer MUX outputs the column bank selection signal C
AND of BSL and sense amplifier activation signal SAA is "
When the page length is 1 KB, the bit of only one of the left and right cell blocks CBL and CBR (only CBR in the example of FIG. 5) to which the same bank number "BANK5" is given is activated. The line data is transferred to the main data line MDQ.However, although only one bit line BL, local data line LDQ, and main data line MDQ are shown in the figure, they actually make a pair.

Similar to FIG. 5, FIG. 6 shows data transfer in the case where the page length is 2 KB by extracting 32 cell blocks of the sub cell array MCA1a above the row decoder ROWDEC in the inner half of the chip upper left cell array MCA1. There is. Here, the CBSL selector 51 has not only the bank address BA <0: 3> but also the column address CA <
6> is input. When "BANK5" is active, the left and right cell blocks CBL and CBR belonging thereto are both active as indicated by the hatched lines, and the sense amplifier activation signal SAA is "H". However, at the time of column access, based on the information of the column address CA <6>, only two column bank selection signals CBSL corresponding to a desired cell block are raised.

Specifically, in FIG. 6, the column address CA
Due to <6> = "0", the two column bank selection signals CBSL for the cell block CBR on the right side are "H".
2 shows a case where the two column bank selection signals CBSL for the left cell block CBL are "L". At this time, for the right cell block CBR in which both the sense amplifier activation signal SAA and the column bank selection signal CBSL are “H”, the bit line data passes through the multiplexer MUX, the local data line LDQ, and the main data line MDQ. Transferred to. When the column address CA <6> = "1", the cell block C on the left side
The bit line data of BL is transferred to the main data line MDQ.

The above 1 KB page length and 2 KB page length are realized by switching the address signal lines.
That is, as described with reference to FIG. 3, the row address RA <9> is used (in the case of 1 KB) or the column address CA <6> is used (2 KB) in selecting the right and left of the cell array MCA.
Or in the case of using only the bank address BA <0: 3> for the selector 51 of the column bank selection signal line CBSL (in the case of 1 KB), as described in FIGS.
Column address C with bank address BA <0: 3>
The difference between using A <6) (in the case of 2 KB) is that the basic configurations of the cell array and the data lines are the same, and switching is possible only by switching the address signal lines. This wiring switching is
Specifically, it can be realized by a wiring mask option, a bonding option, program control of a fuse (laser fuse or electric fuse), and the like.

FIG. 7 shows an example of switching the address signal wiring between the 1 KB page length and the 2 KB page length. NAND gates G11 and G12 for generating internal row address signals RA <9> and bRA <9> which are complementary signals by the row address signal RADR <9>, and internal columns which are complementary signals by the column address signal CADR <6>. N for generating the address signals CA <6> and bCA <6>
One of the input terminals of the AND gates G21 and G22 can be selectively connected to Vcc or Vss by switching the wiring as shown by the solid line and the broken line. In the case of the 1 KB page, the inputs of G21 and G22 are connected to Vss, and CA <6 is set regardless of the value of CADR <6>.
> And bCA <6> both become “H”. As a result, as shown in FIG. 5, two sets of CBSLs are selected. 2K
In the case of page B, the inputs of G11 and G12 are connected to Vss, regardless of the value of RADR <9>, RA <9
> And bRA <9> both become “H”. As a result, as shown in FIG. 6, all the sense amplifier activation signals SAA for the same bank number become "H".

To electrically switch the wiring connection according to the page length, for example, as shown in FIG. 8, two transfer gates TG are provided as an electrical wiring switching circuit.
The wiring switching circuit 10 using 1 and TG2 can be used. The transfer gates TG1 and TG2 provided between the signal paths A and B and the signal path C are selectively turned on by the control signals X and / X. Thereby, the signal paths A and B can be selectively connected to the signal path C.

FIG. 9 shows a control signal X = “H” or X = “L” for switching the wiring according to the two page length configurations.
2 is a configuration example of a control signal generation circuit 11 that outputs a fixed signal. Here, a fuse circuit is used as the control signal generation circuit 11. PMOS transistors QP1 and NM
The OS transistor QN1 and the laser fusing type fuse F are connected in series between the power supply VCC and the ground VSS, and the fuse F is cut according to the page length configuration. Specifically, this fuse programming is performed at the wafer stage. PMOS
The transistor QP1 is a transistor that precharges the node N, and the NMOS transistor QN1 is a fuse data selection transistor.

When the power is turned on, first the NMOS transistor Q
After N1 is turned off and the PMOS transistor QP1 is turned on to precharge the node N to VCC, the PMOS transistor QP1 is turned off and the NMOS transistor QN1 is turned on.
So that the initialization operation is performed, that is, is turned on. As a result, if the fuse F is cut off, the control signal X = “H” is output, and if the fuse F is not cut off, the control signal X = “L” is output. Therefore, the transfer gate circuit shown in FIG. 8 is arranged in the wiring change portion associated with the page length configuration change, and for example, the fuse F is cut in the case of the 1 KB page length configuration, and the fuse F is not cut in the case of the 2 KB page length configuration. The fuse programming is performed by the laser. Thereby, the wiring corresponding to the page length can be set.

The control signal generation circuit 11 shown in FIG. 10 is an example in which the control signals X and / X are generated by a bonding option. A resistor R0 having a large resistance value is connected between the pad PAD and the ground terminal VSS, and the pad PAD and the power supply terminal VCC are connected by bonding according to the page length configuration. This bonding connection is made before packaging the chip. Upon bonding connection, the pad PAD becomes high potential, and the control signal X = “L” is obtained. When the bonding connection is not made, the pad PAD becomes low potential and the control signal X = "H" is obtained. Therefore, the wiring corresponding to the page length configuration can be set by combining with the transfer gate circuit of FIG.

The control signal generating circuit 11 shown in FIG. 11 is an example in which the function similar to that of FIG. 9 is realized by using an antifuse AF which is an electric fuse. Antifuse AF
Has one end connected to the ground VSS and the other end connected to the voltage application terminal VAF via the resistor R1. The node on the resistance R1 side of the antifuse AF is connected to the gate of the read NMOS transistor QN3 via a buffer BF including, for example, a two-stage inverter. NMOS
The source of the transistor QN3 is grounded, and the drain is
It is connected to the output node N via the selection NMOS transistor QN2. A precharge PMOS transistor QP2 is provided between the output node and the power supply terminal VCC.

The fuse programming can be performed by applying a high voltage to the voltage application terminal VAF after packaging the chip. As a result, the antifuse AF is destroyed and becomes conductive. Voltage application terminal VAF
Then becomes the power terminal. When the antifuse AF is conductive, the NMOS transistor QN3 is turned off. When the antifuse AF is not cut off and is nonconductive, N is turned on.
The MOS transistor QN3 is turned on. Therefore, when the power is turned on, the precharge PMOS transistor QP2 and the selection NMOS transistor QN2 are set to QP in the case of FIG.
By operating in the same manner as 1 and QN1, the control signal X = “H” is obtained when the antifuse AF is in the conducting state, and the control signal X = “L” is obtained in the non-conducting state. Therefore, the wiring corresponding to the page length configuration can be set by combining with the transfer gate circuit of FIG.

Next, the mode of defective column replacement in this embodiment will be described. FIG. 12 shows a column selection line CSL and a spare column selection line SC for the upper half sub cell array MCA1a of the memory cell array MCA1 in the upper left part of the chip.
The arrangement of SL is shown. A total of 512 column selection lines CSL, 64 in each segment column, and a total of 8 spare column selection lines SCSL in each segment column, are arranged. There is no difference in the arrangement of the column selection line CSL and the spare column selection line SCSL between the options of 1 KB page length and 2 KB page length.

When accessing a column, a defective column selection line C
In order to activate the spare column selection line SCSL instead of SL, a plurality of fuse sets FS, which are programmed with defective addresses and are capable of flexible mapping, are prepared. As the output line of the fuse set FS,
Eight spare column select line enable signal lines SCSLE
0-7 are provided in one-to-one correspondence with the spare column selection line SCSL. Then, when a certain spare column selection line enable signal line SCSLEm becomes "H" corresponding to the input defective address, the segment column SEGm
The column decoder COLDEC is controlled so that the column selection line CSL selected in 1 is deactivated and the spare column selection line SCSL is activated instead.

As described above, one cell block is activated from one sub cell array MCA1a in the case of 1 KB page length, and two cell blocks from the left and right of one sub cell array MCA1a in the case of 2 KB page length. It is activated at the same time. In case of 1KB page length,
It is the row address RA <9> that distinguishes the cell blocks belonging to the same bank number on the left and right of the cell array, and there is no information for distinguishing at the time of column access. If the above-described column replacement operation does not distinguish right and left of the cell array, the column replacement is performed in the same manner in the case of 1 KB page length and the case of 2 KB page length.
In the case of the B page length, the defect repair efficiency is the same as in the case of the 1 KB page length. That is, one sub cell array MCA1a
When one bank on the left side of the segment column SEGi, for example, is activated and the defective column selection line CSL is replaced with the spare column selection line SCSL, the same bank number of the same segment column SEGi on the right side When paying attention to the bank of, the column selection line that may not be defective (the same wiring as the above-mentioned defective column selection line) is similarly linked and replaced. Therefore, it is not possible to distinguish right and left of the cell array for column replacement.
Due to the limitation peculiar to B, the relief efficiency in the case of the page length of 2 KB remains the same as that of 1 KB.

On the other hand, in this embodiment, a fuse element corresponding to the column address CA <6> for distinguishing the left and right of the cell array at the time of column access is added to the fuse set FS to repair the column of 2 KB page length. I try to improve efficiency. Specifically, 1 KB
In the case of page length, the fuse element corresponding to the column address CA <6> is not used, and in the case of 2 KB page length, it is used. Although the structure of such a fuse set FS will be described later, the column replacement mode in the case of such treatment is shown in FIGS. 13 and 14 for the case of 1 KB page length and the case of 2 KB page length, respectively. In these figures, one segment SEGi in the sub cell array MCA1a shown in FIG. 1 is focused and shown.

In the case of 1 KB page length, as shown in FIG. 13, one of two cell blocks CBL and CBR to which the same bank number BANKn on the left and right of the cell array is attached,
For example, only the shaded cell block CBL is activated. Then, as described above, the bit line data on the cell block CBL side is transferred to the main data line MDQ via the local data line LDQ. In FIG. 13, the state of this data transfer is indicated by the mark ◯ indicating that the cell block CBL side is turned on at the intersection of the local data line pair and the main data line pair. Since this bank selection is based on the row address RA <9> as described above, this distinction is not made at the time of column access.

Therefore, for example, there is a defective column indicated by x in the cell block CBL and its column selection line CSL
Is replaced by the spare column selection line SCSL,
Cell block C of the corresponding bank number BANKn on the right side
When BR is selected, the column select line CSL having the same column address as the mark X is replaced as defective regardless of whether or not the column is actually defective.

On the other hand, when the page length is 2 KB, as shown in FIG. 14, the same bank number BAN on the left and right of the cell array is used.
Both of the two cell blocks CBL and CBR marked with Kn are activated at the same time as shaded. Then, one of the bit line data of these cell blocks CBL and CBR is selected by the column address CA <6> and transferred to the main data line. In FIG. 14, CA
<6> = cell block C on the left selected by "1"
The case where data is being transferred on the BL side is shown. C
When A <6> = "0", the right cell block CBR
Data transfer is performed.

At this time, in this embodiment, the left and right cell blocks CBL and CB according to the column address CA <6> are used.
Similar to the selection of R, the column address CA <6> is also used for the column replacement control. As a result, the cell block CB
Different defective column replacement can be performed for each selection of L and CBR. That is, as shown in FIG. 14, even if there is a defective column indicated by x in the cell block CBL, the corresponding column selection line CSL is treated as normal when the cell block CBR on the right side is selected. The spare column selection line can replace another defective column selection line.

As described above, according to the mode of defective column replacement in this embodiment, according to the page length, when the page length is 1 KB, two segments SEG in the cell block are used.
There is one spare column selection line SCSL per cell (1SCSL / 2SEG), and when the page length is 2 KB, there is one spare column selection line SCSL per segment SEG in the cell block (1SCS).
L / 1SEG). That is, the optimum defect relief efficiency can be obtained by switching the combination of the defect relief region and the redundant element (the spare column selection line in this embodiment) according to the page length.

FIG. 15 shows the structure of one fuse set FS in this embodiment which performs the above-described column replacement replacement control. f11 is an enable fuse for storing whether or not this set is used, and f1
2 to f14, which of the eight segment columns SEG0 to 7 is to be replaced, that is, the spare column selection line SC
This is a fuse for determining which of SL0 to SL7 should be set. F0 of the fuses for designating defective addresses
.About.f5 are used to specify which of the 64 CSLs in the segment string corresponds, and f7 to f10 store address information for selecting one of the 16 banks. f6 corresponds to the column address CA <6> in the case of 2 KB page. These are programmed based on the test results.

All fuses are PM for precharge.
OS transistor QP and selection NMOS transistor Q
Together with N, it is connected in series between the power supply VCC and the ground VSS. The fuse data is precharged by turning on the PMOS transistor QP and turning off the NMOS transistor QN, and then turning off the PMOS transistor QP and NMO.
The S transistor QN is turned on and read. If the fuse is blown, the "H" level is output, and if it is not blown, the "L" level is output.

These defective address designating fuses f0
The outputs of .about.f10 are subjected to match detection with the column addresses CA <0> to CA <6> and the bank addresses BA <0> to BA <3> by the comparison circuit CMP. When they match, the output of the comparison circuit CMP becomes "H",
Further, the output is AND gates for all 10 comparison circuits C.
The product of the output of MP and the output of the enable fuse f11 is taken. As a result, the AND gate outputs a signal which becomes "H" only when the input address coincides with the fuse data and further the fuse set is to be used. This output is input to the decoder DEC as an activation signal. Decoder DE only when it becomes "H"
C is activated to set only one of the eight outputs to "H" depending on the states of the fuses f12 to f14. Decoder D
If the EC is inactive, all eight outputs are "L".

The eight outputs of the decoder DEC are also output from other fuse sets in the same manner, and their logical sums are taken by the OR gate. As a result, spare column select line enable signals SCSLE0 to SCSLE7 are output. When the replacement is required, one or more of the spare column selection line enable signals SCSLE0 to 7 becomes "H" to inactivate the defective column selection line and activate the spare column selection line. .

In this fuse set, the fuse data of the column address CA <6> is used only when the page length is 2 KB. That is, when the page length is 2 KB,
The fuse data comparison circuit CMP output of the column address CA <6> is wired so as to enter the AND gate. 1
In the case of the KB page length, the wiring is switched so that the output of "H" (specifically, VCC) is always applied to the AND gate instead of the fuse data of the column address CA <6>. Similar to the page length switching, this wiring switching is also performed by the wiring mask option, the bonding option, the fuse circuit programming, and the like.

As a result, as described above, the relief efficiency is not sacrificed even when the option having a large page length is selected. That is, in the high-speed and large-capacity DRAM, the demand for larger page length products for servers is increasing in the market, and it is possible to prevent the cost demerit even when the page length becomes 2 KB.

[Embodiment 2] Next, a description will be given of a DRAM according to an embodiment in which the size of the column relief region is switched according to options having different page lengths. Also in the previous embodiment, it is substantially equivalent to that the size of the column relief area by one spare column selection line is switched according to the page length, but in this embodiment, the column address is more positively addressed. The combination of the column relief area and the spare column selection line is changed by changing the allocation.

The cell array configuration and bank address allocation are assumed to be the same as those in the previous embodiments described with reference to FIGS. In this embodiment, the column address allocation for 1/4 of one cell array is shown in FIG. 16 in correspondence with FIG. 4 of the previous embodiment. Although row address allocation is omitted in FIG. 16, it is the same as in FIG.
<0> to <8> are assigned to 512 word lines in the cell block.

When the page length is 1 KB, the row address RA <9> is used to distinguish the left and right halves of the cell array, and the column addresses CA <0> to <5 are the same as in the previous embodiment. > Is allocated to the 64 column selection signal lines CSL in one segment column. In the case of the previous embodiment, when the page length is 2 KB, the column address CA <6> is used to distinguish the left and right cell blocks of the cell array. On the other hand, in the case of this embodiment, as shown in FIG.
0> to <6> are used to select 128 column selection lines CSL in the adjacent two segment columns. That is, the column address CA <6> is used not for selecting the cell block but for selecting the column selection line.

Therefore, one column selection line CSL in one of the two adjacent segment columns is selected and stands up during column access (one in 128 columns). This is 1KB
It is half of the case of page length. Therefore, the data transfer handled by one column selection line CSL is 8 bits, which is double that in the case of 1 KB page length. Such a change in address allocation can also be realized by a wiring mask option or wiring switching by program control.

FIG. 17 is similar to FIG. 6 and has a page length of 2 KB.
The data transfer in this case is shown for the upper half sub cell array MCA1a of the cell array MCA1.
The case of 1 KB page length is the same as in FIG. In this embodiment, the column bank select line CBSL is selected only by the bank address BA <0: 3> even if the page length is 2 KB. Therefore, as in the case of FIG. 5, all the four column bank selection signal lines CBSL corresponding to the two activated cell blocks belonging to the same bank number become “H”. That is, in the case of FIG. 17, the bank BANK
The two cell blocks CBL and CBR of n are simultaneously activated, the sense amplifier activation signals SAA for them are both set to "H", and the four column bank selection signal lines CBSL are set to "H".

On the other hand, the two cell blocks CBL and CBR which are activated at the same time are different from those of the previous embodiment in FIG.
As shown in FIG. 7, since they are respectively connected to different main data lines MDQ and perform data transfer simultaneously, both cell data of 8 bits are transferred by one column selection line CSL as described above. Further, in the case of a 2 KB page length, 128 column selection lines CSL in the range of two consecutive segment columns are selected by the column address CA <0: 6>, and this range is selected as two spare columns. The line SCSL serves as a relief area for relieving a defective column.

FIG. 18 shows a case where the page length is 2 KB and the local data line LDQ and the main data line MDQ are within the range of two adjacent segment columns SEG0 and SEG1.
And the spare replacement of the column selection line CSL. The case of 1 KB page length is the same as that in FIG. 13 of the previous embodiment. In the case of a 2 KB page length, as described above, only one column selection line CSL is selected by the two segment columns at the time of column access. By doubling, the connectable portion between the local data line LDQ and the main data line MDQ is halved. In FIG. 18, two cell blocks CB belonging to BANKn are included.
The fact that data is transferred from both L and CBR is shown by a circle surrounding the intersection of the local data line LDQ and the main data line MDQ.

FIG. 19 further shows how the spare column select line SCSL is activated in the case of a 2 KB page length, in correspondence with FIG. The case of 1 KB page length is the same as in FIG. The specific structure of the fuse set FS is the same as that of the previous embodiment shown in FIG. Figure 1
In 9, the adjacent spare column select line enable signal S
The OR of CSLE is taken. This corresponds to the range of two segments connecting the column relief region,
For example, either SCSLE0 or SCSLE1 is "H"
Becomes two segments SEG0, SEG1
This is because the defective column can be replaced within the range.

Also in this embodiment, the length of the local data line LDQ is doubled, and the local data line LDQ is doubled.
Content peculiar to the 2 KB page product such as reducing the number of connection points between the main data line MDQ and the main data line MD and ORing the spare column selection line enable signal is implemented by a wiring mask option or wiring switching by program control. This 2 KB page product has a larger repair domain than the 1 KB page product, although there is a limitation that both blocks in the same bank are linked and replaced at the time of spare replacement. That is, 2 of the previous embodiment
In the case of the KB page, as shown in FIG. 14, the column repair mode is 1SCSL / 1SEG, whereas in this embodiment, it is 2SCSL / 4SEGs. This is the same as the density of the spare column selection line in the case of the 1 KB page, but since the spare area where one spare column selection line can repair defects is large, substantially high repair efficiency can be obtained. It is also possible to deal with major defects.

[Third Embodiment] Next, the page length is set to 2 KB.
With regard to the DRAM specialized for the above, an embodiment having options having different column relief formats will be described. 20 and 21 show data transfer and column replacement in the two types of DRAMs. The cell array configuration and block address allocation are shown in FIGS. 1 to 3 described in the first embodiment.
Is the same as. FIG. 20 shows two segment columns, but FIG. 14 shows a case of a 2 KB page length in the first embodiment.
The same as the above, and the range of one segment is set as a relief area for relieving defects by one spare column selection line SCSL (1SCS
L / 1SEG). FIG. 21 is the same as FIG. 18 in the case of the 2 KB page length in the second embodiment, and substantially sets the range of 4 segments as the relief area where the 2 spare column selection line SCSL repairs the defect (2SCSLs / 4SEGs). .

Which of the two is better for the repair efficiency depends on the nature of the defect, but the latter is advantageous when there are many large defects. Both of these are made optional by a wiring mask option or wiring switching by program control. Since the 1 KB page product is no longer assumed here, there is no option in the fuse set in FIG. 15, and as shown in FIG. 22,
Information on the column address CA <6> is always used.

[0057]

As described above, according to the present invention, it is possible to provide a semiconductor memory integrated circuit in which the optimum defect relief efficiency can be set only by changing the connection of wiring.

[Brief description of drawings]

FIG. 1 is a diagram showing a cell array configuration of a DRAM according to an embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration of a cell block according to the same embodiment.

FIG. 3 is a diagram showing bank address allocation according to the same embodiment.

FIG. 4 is a diagram showing row address and column address allocation according to the first embodiment.

FIG. 5 is a diagram showing how data is transferred in the case of the 1 KB page length configuration according to the embodiment.

FIG. 6 is a diagram showing how data is transferred in the case of the 2 KB page length configuration of the same embodiment.

FIG. 7 is a diagram showing how address signal lines are switched for page length switching according to the first embodiment.

FIG. 8 is a diagram showing a configuration of an electrical switching circuit for wiring connection according to the same embodiment.

FIG. 9 is a diagram showing a configuration of a control circuit of the switching circuit.

FIG. 10 is a diagram showing a configuration of another control circuit of the switching circuit.

FIG. 11 is a diagram showing a configuration of another control circuit of the switching circuit.

FIG. 12 is a diagram showing a configuration of a defective column replacement circuit according to the same embodiment.

FIG. 13 is a diagram showing a mode of defective column replacement by the same defective column replacement circuit in the case of 1 KB page length.

FIG. 14 is a diagram showing an aspect of defective column replacement by the same defective column replacement circuit when the page length is 2 KB.

FIG. 15 is a diagram showing a configuration of a fuse set of the defective column replacement circuit.

FIG. 16 is a diagram showing column address allocation of a DRAM according to another embodiment.

FIG. 17 is a diagram showing how data is transferred in the case of a 2 KB page length according to the same embodiment.

FIG. 18 is a diagram showing a state of column replacement in the case of a 2 KB page length according to the same embodiment.

FIG. 19 is a diagram showing a configuration of a defective column replacement circuit according to the same embodiment.

FIG. 20 is a diagram showing an aspect of column replacement of a DRAM according to another embodiment.

FIG. 21 is a diagram showing another aspect of column replacement in the DRAM of the same embodiment.

FIG. 22 is a view showing a configuration of a fuse set according to the same embodiment.

[Explanation of symbols]

MCA1 to MCA4 ... Cell array, MCA1a, MCA
1b to MCA4a, MCA4b ... Sub cell array, BA
NK0-BANK31 ... Bank (cell block), RO
WDEC ... Row decoder, COLDEC ... Column decoder.

Claims (8)

[Claims] 1. A memory cell array including a redundant element used for replacing a defective element, a decoder circuit for selecting a matrix of the memory cell array, a defective address is stored, and a match between an input address and the defective address is detected. In a semiconductor memory integrated circuit having a replacement control circuit for controlling the decoding circuit to replace a defective element with a redundant element, the defective element replacement is defined as a range in which the redundant element replacement is allowed by one redundant element in the memory cell array. A semiconductor memory integrated device characterized in that a combination of the size of a relief region and the number of redundant elements used for replacing a defective element in one relief region is set only by changing the connection of wiring. circuit. 2. The memory cell array is composed of a plurality of cell blocks, a plurality of banks are defined by a combination of the cell blocks, and a page length determined by the number of simultaneously activated cell blocks is only a change in wiring connection. 2. The semiconductor memory circuit according to claim 1, wherein the semiconductor memory circuit is set by 3. The semiconductor memory integrated circuit according to claim 2, wherein the combination of the number of the relief area and the number of the redundant elements is optimally set according to the page length. 4. The replacement control circuit includes a fuse circuit using a plurality of fuses in which a defective address is programmed, and a coincidence detection circuit for performing coincidence detection of fuse data and an input address, and the relief area and the relief area. 4. The semiconductor memory integrated circuit according to claim 3, wherein the combination of the number of redundant elements is set only by changing the connection of wiring. 5. When the combination of the size of the relief area and the number of redundant elements used for the defective element replacement in one relief area is set by changing the wiring connection, the data line length is The semiconductor memory integrated circuit according to claim 2, wherein the semiconductor memory integrated circuit is switched. 6. The wiring switching circuit for changing the connection of the wiring, and a programmable control signal generating circuit for generating a control signal of the wiring switching circuit. Semiconductor memory integrated circuit. 7. The semiconductor memory integrated circuit according to claim 6, wherein the control signal generation circuit is a fuse circuit programmed by laser irradiation at a wafer stage. 8. The semiconductor memory integrated circuit according to claim 6, wherein the control signal generation circuit is an electric fuse circuit that can be programmed after packaging of the integrated circuit chip.