JP2003066930A - Device for processing image signal and image displaying device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processing technology outputting an input image signal as a digital image signal possible to display an image on the side of a display device. SOLUTION: The device is provided with a signal judging mean judging whether or not a clock of the input image signal can be displayed as image on the display, a clock selecting means selecting the clock possible to be displayed as image based on the result of the judgment and an output means outputting the digital image signal synchronized with the selected clock.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an input video signal,
The present invention relates to a video signal processing technique for processing as a digital video signal having a frequency that can be displayed on the display unit side.

[0002]

2. Description of the Related Art Conventionally, for example, the frequency and the number of pixels of a video signal of a personal computer are various. Therefore, the display (display device) also has various video signal frequencies and the number of pixels that can be displayed, depending on the respective applications. Generally, when a video signal having a frequency and a display pixel number different from the specifications is input to the display device for video display, the video signal frequency conversion and the display pixel number conversion (reduction processing or enlargement processing) are performed to meet the display device specifications. Process).

FIG. 2 is an explanatory diagram of a conventional video signal processing circuit. In the figure, 1 is an input terminal of a video signal A (input video signal), 2 is an input terminal of a horizontal synchronizing signal of the video signal A, and 4 is a PL for generating a dot clock of the video signal A.
L and 6 are input terminals for the vertical synchronizing signal of the video signal A, 7 is a synchronizing signal generating circuit for generating the horizontal synchronizing signal HB and the vertical synchronizing signal VB of the video signal B (output video signal), and 9 is a dot of the video signal B. PLL that generates a clock, 10 is a frequency conversion circuit, 11 is an A / D conversion circuit, 30 is a signal determination circuit, 31 is a frequency control circuit, 41 is an output terminal for the video signal B, and 42 is a horizontal synchronization signal for the video signal B. HA output terminal,
Reference numeral 43 is an output terminal for the vertical synchronizing signal VB of the video signal B. A display device (not shown) for displaying an image is connected to the output terminals 41, 42 and 43. In such a configuration, the video signal A from the input terminal 1 is converted into the A / D conversion circuit 11
Supply to. Further, the horizontal synchronizing signal HA of the video signal A is supplied from the input terminal 2 to the PLL 4, PLL 9, the signal discriminating circuit 30 and the frequency converting circuit 10, and the vertical synchronizing signal VA is fed from the input terminal 6 to the signal discriminating circuit 30, the frequency. Conversion circuit 1
Supply to 0. The signal discrimination circuit 30 sets in advance the frequency information (which matches the specifications of the display device) that can be input by the display device (not shown) in the built-in memory (not shown), and the input terminals 2, 6 The type of the input video signal A is determined from the frequency and polarity of the horizontal synchronization signal HA and the vertical synchronization signal VA of the input video signal A input from
The frequency information that can be input to the display device and the type of the input video signal A are supplied to the frequency control circuit 31. Frequency control circuit 3
1 generates a clock frequency control signal based on the signal discrimination result from the signal discrimination circuit 30, and PLL4 and PLL
Supply to 9. In the PLL 4, the multiplication number NA is set by the clock frequency control signal from the frequency control circuit 31,
A sampling clock (dot clock) CKA having a frequency NA times that of the horizontal synchronizing signal HA of the input video signal A is generated and supplied to the A / D conversion circuit 11 and the frequency conversion circuit 10. The A / D conversion circuit 11 converts the analog input video signal A from the input terminal 1 into a digital format by the sampling clock (dot clock) CKA from the PLL 4, and supplies the digital video signal A to the frequency conversion circuit 10. Further, in the PLL 9, the multiplication number NB is set by the clock frequency control signal from the frequency control circuit 31, a clock CKB having a frequency NB times the horizontal synchronization signal HA of the input video signal A is generated, and the frequency conversion circuit 10 and It is supplied to the synchronization signal generation circuit 7. In the synchronization signal generation circuit 7,
The horizontal synchronizing signal HB and the vertical synchronizing signal VB of the video signal B are generated from the clock CKB from the PLL 9 and supplied to the frequency conversion circuit 10 and the output terminals 42 and 43. In the frequency conversion circuit 10, the sampling clock (dot clock) CKA from the PLL 4 and the horizontal synchronizing signal HA and the vertical synchronizing signal VA from the input terminals 2 and 6 are synchronized to generate A /
Video signal A converted to digital format by the D conversion circuit 11
And outputs the video signal B in synchronism with the dot clock CKB from the PLL 9 and the horizontal sync signal HB and the vertical sync signal VB from the sync signal generation circuit 7 to output the frequency-converted video signal to the output terminal 41. Supply. The signals supplied to the output terminals 41, 42 and 43 are input to the display device. In this way, frequency conversion and pixel number conversion (reduction processing or enlargement processing) of the video signal are performed so as to match the frequency of the display device and the number of display pixels. Known examples include, for example, Japanese Patent Laid-Open No. 10-28256.

[0004]

In the above-mentioned prior art, since the dot clock CKB of the video signal B is generated by the PLL 9 from the horizontal sync signal HA of the video signal A, the horizontal sync signal HA is generated when there is no input signal. Is not input, the dot clock CKB cannot be generated. Further, when a signal having an unstable frequency such as a video signal is input as the video signal A, the dot clock CKB generated from the unstable horizontal synchronizing signal HA becomes unstable. If the dot clock CKB is absent or unstable, neither the horizontal synchronizing signal HB nor the vertical synchronizing signal VB is generated or it becomes unstable. In this case, the operation of the synchronizing signal generating circuit 7 and the frequency converting circuit 10 which receive the dot clock CKB is also unstable, and unstable signals are output to the output terminals 41, 42 and 43. For this reason, the display device connected to the output terminals 41, 42, 43 malfunctions and cannot display a normal image, or when there is no signal or the input signal is abnormal, the OSD (On Screen Disp.
lay) may not be able to display the specified display. Furthermore, C
When KA and CKB are different from each other, since clocks having two frequencies are present, beat interference due to the clock CKB is likely to occur in the analog format video signal before A / D conversion. In view of the situation of the above-mentioned prior art, the problem of the present invention is to provide a display device with a video signal capable of normal video display even when there is no input video signal or when the frequency of the input video signal is unstable. It is to be able to supply. An object of the present invention is to provide a technique capable of solving such a problem.

[0005]

In order to solve the above problems, the present invention basically discriminates a clock of an input video signal, and based on the discrimination result, a clock capable of displaying a video on a display device. Is selected, and a digital video signal synchronized with the selected clock is output. Specifically, (1) as a video signal processing device that processes an input video signal and outputs it as a video signal of a frequency that can be displayed on a display unit,
Signal determining means for determining whether or not the clock of the input video signal can be displayed on the display unit (corresponding embodiment: 3
0 ') and a clock selection means (corresponding embodiment: 2) for selecting the clock capable of displaying the image based on the discrimination result.
5, 25 ') and output means for outputting a digital video signal synchronized with the selected clock (corresponding embodiment: 10)
And a configuration including. (2) As a video signal processing device that samples an input video signal with a first clock having a predetermined frequency and digitizes it, and outputs a displayable video signal to the display unit side, a second sync signal from the input video signal is used. Second to generate the clock
A clock generating means (corresponding embodiment: 9), a signal discriminating means (corresponding embodiment: 30 ') for discriminating whether or not the second clock can display an image on the display portion, and the display portion. Third clock generating means (corresponding embodiment: 8) for generating a third clock capable of displaying an image, the second clock, the third clock, the second clock, and the third clock A clock switching means (corresponding embodiment: 22, 23) for switching between a fourth clock formed by spread spectrum of any one of the above, and the second and second clocks based on the discrimination result. Clock switching control means for selecting either the third clock or the fourth clock as a clock capable of displaying an image on the display unit (corresponding embodiment: 2
1) and an output means (corresponding embodiment: 10) for outputting a digital video signal synchronized with the selected clock. (3) As a video signal processing device for sampling an input video signal with a first clock having a predetermined frequency and digitizing it, and outputting a displayable video signal to a display unit side, a second signal from a synchronization signal of the input video signal is used. Second to generate the clock
The clock generating means (corresponding embodiment: 9), the signal discriminating means (corresponding embodiment: 30 ') for discriminating whether or not the second clock can display an image on the display portion, and the display portion. Third clock generating means (corresponding embodiment: 8) for generating a third clock capable of displaying an image, and first clock switching means (corresponding embodiment: for switching the second clock and the third clock). 22), fourth clock generation means (corresponding embodiment: 15) for spreading the spectrum of the second or third clock output from the first switching means to form a fourth clock, and Second clock switching means (corresponding embodiment: 23) for switching between the second or third clock and the fourth clock, and controlling the first and second clock switching means based on the discrimination result. , The second, the third , And a fourth clock, and a clock switching control means (corresponding embodiment: 21) for selecting a clock capable of displaying a video on the display unit, and an output means (corresponding to: a digital video signal synchronized with the selected clock). Example: 10). (4) In the above (3), when the signal determining means determines that the second clock has a frequency variation within a predetermined range and can be displayed as an image, the clock switching control means performs the above. The first clock switching means selects the second clock, and the second clock switching means also selects the second clock, while the second clock has a frequency fluctuation within a predetermined range. When it is determined that the image cannot be displayed, the clock switching control means selects the second clock by the first clock switching means and the fourth clock by the second clock switching means. Is selected. (5) In the above (3), when the signal determining means determines that the second clock has a frequency variation exceeding a predetermined range, the clock switching control means causes the first clock switching means. Then, the third clock is selected, and the fourth clock is selected by the second clock switching means. (6) As the video signal processing device for sampling the input video signal with the first clock having a predetermined frequency and digitizing the video signal, and outputting the displayable video signal to the display unit side,
Signal determining means (corresponding embodiment: 30 ') for determining whether or not the clock of FIG. 1 is video displayable on the display section, and a second clock for generating a plurality of second frequencies of video displayable on the display section. 2 clock generation means (corresponding embodiment: 45)
And a third clock generating means (corresponding embodiment: 15 ') that spreads the spectrum of the second clock to form and output a third clock, and switches the third clock and the first clock. Clock switching means (corresponding embodiment: 2
3 ') and the clock switching control means for controlling the clock switching means on the basis of the discrimination result and selecting one of the first and third clocks as a clock capable of displaying an image on the display section (corresponding implementation). Example: 21 ') and output means (corresponding embodiment: 10') for outputting a digital video signal synchronized with the selected clock. (7) In the above (6), when the signal determination means determines that the first clock has a frequency variation within a predetermined range and can be displayed as an image, the clock switching control means causes the clock switching control means to operate. When the clock switching means is switched and the first clock is selected, while it is determined that the first clock has a frequency fluctuation exceeding a predetermined range or cannot display an image, the clock switching means. Then, the third clock is selected. (8) As a video display device, the video signal processing device according to any one of (1) to (7) above, and a display unit for displaying video based on a video signal from the video signal processing device. To do.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. In FIG. 1, 1 is an input terminal for the input video signal A, 2
Is an input terminal of the horizontal synchronizing signal HA of the input video signal A, 4 is a PLL for generating a dot clock (first clock) of the input video signal A, and 6 is a vertical synchronizing signal V of the input video signal A
An input terminal 7 of A is a synchronizing signal generating circuit for generating a horizontal synchronizing signal HB and a vertical synchronizing signal VB of the video signal B.
Is a frequency conversion circuit, 11 is an A / D conversion circuit, 25 is a clock selection circuit for selecting a clock for video display, and 8 is a dot clock (third clock) suitable for a display device (not shown). ) Is an oscillator as a third clock generating means, 9 is a PLL as a second clock generating means for generating a second clock from the horizontal synchronizing signal HA of the input video signal A, and 15 is the second clock. Alternatively, a spread spectrum circuit as a fourth clock generating means for spreading the spectrum of the third clock to form a fourth clock, 22 is a first clock for switching the second clock and the third clock A switch as a switching means, and 23 is a switch as a second clock switching means for switching between the second or third clock and the fourth clock. Reference numeral 21 denotes a clock switching control circuit as a clock switching control means for controlling switching of the switches 22 and 23, and 30 'determines whether or not the second clock can be displayed on the display unit. A signal discriminating circuit as a signal discriminating means for supplying the resulting signal to the clock switching control circuit 21, 31 is a frequency control circuit, 41 is an output terminal of the video signal B, and 42 is an output terminal of the horizontal synchronizing signal HB of the video signal B. , 43 are output terminals for the vertical synchronizing signal VB of the video signal B. The output terminals 41, 4
A display device for displaying an image is connected to 2 and 43. In such a configuration, the video signal A is supplied from the input terminal 1 to the A / D conversion circuit 11. Further, the horizontal synchronizing signal HA of the video signal A is fed from the input terminal 2 to the PLL4, PL
L9, the signal discriminating circuit 30 ', and the frequency converting circuit 10, and the vertical synchronizing signal VA from the input terminal 6 is supplied to the signal discriminating circuit 3.
0 ′ is supplied to the frequency conversion circuit 10. Signal discrimination circuit 3
At 0 ', frequency information (matching the specifications of the display device) that can be input to the display device (not shown) connected to the output terminals 41, 42, 43 is set in advance in the built-in memory (not shown). The frequency control circuit 31 determines the presence / absence, type, frequency stability, etc. of the input video signal A from the frequencies and polarities of the horizontal sync signal HA and the vertical sync signal VA of the video signal A from the input terminals 2 and 6. And clock switching control circuit 21
On the other hand, the frequency information that can be input to the display device and the determination result information of the input video signal A are supplied. Frequency control circuit 31
Generates a clock frequency control signal based on the signal discrimination result from the signal discrimination circuit 30 ′,
Supply to 9. In the PLL 4, the multiplication number NA is set by the clock frequency control signal from the frequency control circuit 31,
A sampling clock (dot clock) CKA having a frequency NA times that of the horizontal synchronizing signal HA of the input video signal A is generated and supplied to the A / D conversion circuit 11 and the frequency conversion circuit 10. In the A / D conversion circuit 11, the analog input video signal A from the input terminal 1 is converted into a digital form by the sampling clock (dot clock) (first clock) CKA from the PLL 4, and the frequency conversion circuit 10 is supplied. Supply. In the PLL 9, the frequency control circuit 31
The multiplication number NB is set by the clock frequency control signal from (1) to generate a clock (second clock) having a frequency NB times that of the horizontal synchronizing signal HA of the input video signal A. Further, in the clock switching control circuit 21, the signal discrimination circuit 3
The switch 2 in the clock selection circuit 25 is generated based on the signal discrimination result from 0 '.
Control 2 and 23. On the other hand, the clock (second clock) from the PLL 9 is applied to the terminal a of the switch 22 and the terminal b
Is supplied with a clock (third clock) synchronized with the video signal B generated by the oscillator 8. In the switch 22, the switch is switched according to the clock switching control signal from the clock switching control circuit 21, and the selected clock is supplied to the spread spectrum circuit 15 and the terminal a of the switch 23. The spread spectrum circuit 15 spreads the spectrum of the clock from the switch 22 and supplies it to the terminal b of the switch 23 as a fourth clock. Switch 23
Then, the switch is switched according to the clock switching control signal from the clock switching control circuit 21 so that the terminal a or the terminal b is connected, and the second clock, the third clock or the fourth clock is selected. Clock CKB
Generate as. The clock CKB is supplied to the frequency conversion circuit 10 and the synchronization signal generation circuit 7. The synchronization signal generation circuit 7 generates the horizontal synchronization signal HB and the vertical synchronization signal VB of the video signal B from the clock CKB from the PLL 9 and outputs them to the frequency conversion circuit 10 and the output terminals 42 and 43. In the frequency conversion circuit 10, the dot clock CKB
Then, the video signal B is output to the output terminal 41 as a frequency-converted video signal in synchronization with the horizontal sync signal HB and the vertical sync signal VB from the sync signal generation circuit 7. In the frequency conversion circuit 10, the number of pixels may be expanded or reduced. The signals output to the output terminals 41, 42, and 43 are input to the display device.

FIG. 3 shows a configuration example of the spread spectrum circuit 15 shown in FIG. In FIG. 3, 51 is an integrator,
52 is a limiter, 53 is a PLL, and 54 is a frequency divider.
S _C is a frequency control signal, which has a lower frequency than the input clock CK _IN and changes gently. Integrator 5
1 integrates the input clock CK _IN and outputs a clock CK _S having a sloped rising and falling. Limiter 52, the level of the integrated clock CK _S,
It is limited by the frequency control signal S _C whose level changes gently, and is input to the PLL 53 as an input signal S _IN whose pulse width (cycle) constantly changes, that is, whose frequency changes. The PLL 53 multiplies the clock S _IN input from the limiter 52 by N corresponding to the frequency division ratio N set by the frequency divider 54 and outputs a clock CK _OUT . In this way, by changing the output of the output clock CK _OUT of the PLL 53 with a minute fluctuation width in accordance with the frequency control signal S _C input to the limiter 52, the clock C
Spread the spectrum of K _OUT . Therefore, in a device that operates with the clock signal CK _OUT as the operating frequency, the spectrum of the operating clock is dispersed, beat interference is suppressed, and electromagnetic radiation is reduced.

FIG. 4 is an explanatory diagram of clock selection in the clock selection circuit 25. The result of the signal determination by the signal determination circuit 30 'is No. When the input video signal A is stable and the sampling clock (dot clock) CKA of the input video signal A matches the dot clock having the frequency information that can be input to the display device, as in the case of 1, the signal determination is performed. The circuit 30 'is a clock switching control circuit 21.
The switch 22 and the switch 23 are both made to select the terminal a via
The multiplication number NB of LL9 is set to the same value as the multiplication number NA of PLL4. As a result, the dot clock CKB of the video signal B displayed on the display device has the same frequency as the sampling clock (dot clock) CKA, and beat interference is suppressed. Next, according to the signal determination result by the signal determination circuit 30 ', No. When the input video signal A is stable as in the case of 2, but the sampling clock (dot clock) CKA of the input video signal A does not match the dot clock having frequency information that can be input to the display device, The signal discrimination circuit 30 'is the clock switching control circuit 2
Switch 22 to select terminal a, switch 23 to select terminal b, and frequency control circuit 31 to select P.
The multiplication number NB of LL9 is set to a value NB that is a frequency different from the multiplication number NA of PLL4 and can be input to a display device. As a result, the dot clock CKB of the video signal B displayed on the display device has a frequency that can be input to the display device, and further spread spectrum processing is performed, so beat interference is suppressed. In this case, a spread spectrum clock is output as the clock output CKB of the clock selection circuit 25, but in general, the display device (not shown) is configured so as to be able to follow a slight fluctuation of the clock. Has been done. Therefore, it may be controlled by the frequency control signal S _C so that the display device falls within the range that can be followed. Next, according to the signal determination result by the signal determination circuit 30 ', No. When the input video signal A is unstable or when it is determined that the input video signal A is not present, as in the case of No. 3, the signal determination circuit 30 ′ determines that the clock switching control circuit 2
Both the switch 22 and the switch 23 are caused to select the terminal b via 1. As a result, the dot clock CKB of the video signal B displayed on the display device is a clock (third clock) formed by further spread spectrum processing of the stable clock (third clock) generated by the oscillator 8 independent of the input video signal. 4), malfunction of the display device can be prevented, OSD display can be performed when there is no signal or an input signal is abnormal, and beat interference is suppressed. The above No. 2, No. When the spread spectrum processing is performed as in the case of 3, it is possible to adjust the fluctuation range of the spread spectrum by varying the frequency control signal S _C at the same time. Further, by spreading the spectrum of the clock, electromagnetic radiation is also reduced. In addition, the above No. In the case of 2, the switch 22 is set to the side a, but this is the case where the input video signal does not match the display device (not shown), so that the switch 22 is used to select the side b.
The multiplication number NB of the PLL 9 may be set to a value different from the multiplication number NA of the PLL 4. A display device (display) is connected to the output terminals 41, 42, and 43 to configure the entire video display device.

According to the first embodiment, when the sampling clock (dot clock) CKA of the input video signal A has a frequency that cannot be input to the display device, or the input video signal A is unstable or does not exist. In this case, as the dot clock CKB, one that is further spread spectrum based on the frequency that can be input to the display device with the multiplication number NB of the PLL 9 is used, or a stable clock generated by the oscillator 8 that does not depend on the input signal is used. A clock that has a frequency that can be input to the display device is further spread spectrum is used. Therefore, malfunction of the display device can be prevented, and OSD display can be performed when there is no signal or when the input signal is abnormal. Further, since the spectrum of the clock is spread, electromagnetic wave radiation is also reduced.

FIG. 5 shows a second embodiment of the present invention. The second embodiment is a configuration example in which the number of clock switching means in the clock selection circuit is one. In FIG. 5, 25 'is a clock selection circuit, 45 is a clock generation circuit for generating a clock having a frequency capable of displaying an image on a display device, 15' is a spread spectrum circuit, 23 'is a switch as a clock switching means, and 21'. Is a clock switching control circuit as clock switching control means for controlling switching of the switch 23 '. The clock generation circuit 45 has a configuration for generating clocks of a plurality of frequencies, and the frequency control circuit 31 ′ controls the PLL 4 and the clock generation circuit 45. Other parts having the same configurations as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals as those in FIG. 1, and the description thereof will be omitted. The clock generation circuit 45 is
For example, a plurality of oscillators that generate different frequencies are provided,
It is configured to switch these with a switch,
A clock (second clock) having a predetermined frequency is selected by the clock frequency control signal from the frequency control circuit 31 ′ and supplied to the spread spectrum circuit 15. The spread spectrum circuit 15 spreads the supplied clock (second clock) and supplies the spread spectrum clock (third clock) to the terminal b of the switch 23 '. On the other hand, the terminal a of the switch 23 'has P
Sampling clock (dot clock) from LL4
(First clock) CKA is supplied. The clock selection in the clock selection circuit 25 'is as follows. That is, as a result of the signal determination by the signal determination circuit 30 ', the input video signal A is stable, and the sampling clock (dot clock) CKA of the input video signal A matches the dot clock having frequency information that can be input to the display device. In this case, the signal discrimination circuit 30 'causes the switch 23 to select the terminal a through the clock switching control circuit 21'.
Thus, by supplying the sampling clock (dot clock) CKA from the PLL 4 as the dot clock CKB of the video signal B, the dot clock CKB of the video signal B displayed on the display device becomes the sampling clock (dot clock) CKA. Will be the same. Therefore, beat interference is also suppressed. According to the signal determination result by the signal determination circuit 30 ', the input video signal A is stable,
When the sampling clock (dot clock) CKA of the input video signal A does not match the dot clock having frequency information that can be input to the display device, the signal determination circuit 3
0'causes the switch 23 'to select the terminal b via the clock switching control circuit 21', and the frequency control circuit 31 '.
The clock generation circuit 45 is caused to set the clock frequency to a frequency that can be input to the display device via the (second clock). The clock for which the frequency is set (second clock)
Is spread spectrum and is supplied to the terminal b of the switch 23 'as a third clock. As a result, the dot clock (third clock) CKB of the video signal B displayed on the display device can be input to the display device. Furthermore, since this clock is spread spectrum processed, beat interference is also suppressed. Further, when it is determined from the signal determination result by the signal determination circuit 30 ′ that the input video signal A is unstable or the input video signal A is not present, the signal determination circuit 30 ′ outputs the signal via the clock switching control circuit 21 ′. Switch 23 'to select the terminal b, and the frequency control circuit 3
The clock frequency is set to a frequency that can be input to the display device by the clock generation circuit 45 via 1 '(second clock). The frequency-set clock (second clock) is spread spectrum and is supplied to the terminal b of the switch 23 'as a third clock. As a result, the dot clock (third clock) CKB of the video signal B displayed on the display device can be input to the display device. Furthermore, since this clock is spread spectrum processed, beat interference is also suppressed. Output terminals 41, 42, 4
A display device (display) is connected to 3 to configure the entire video display device.

According to the second embodiment, when the sampling clock (dot clock) CKA of the input video signal A has a frequency that cannot be input to the display device, or the input video signal A is unstable or does not exist. In this case, the dot clock CKB is formed based on the stable clock generated by the clock generation circuit 45 that does not depend on the input signal. Therefore, malfunction of the display device can be prevented, and OSD display can be performed when there is no signal or when the input signal is abnormal. Furthermore, by spreading the spectrum of the clock,
Electromagnetic radiation is also reduced.

[0012]

According to the present invention, malfunction of the display device can be prevented. In addition, it is possible to display an OSD indicating an input abnormality. Beat interference due to the clock is also suppressed. Furthermore, electromagnetic radiation can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a conventional video signal processing device.

FIG. 3 is a diagram showing a configuration example of a spread spectrum circuit in the configuration of FIG.

FIG. 4 is a diagram showing a clock selection method in a clock selection circuit.

FIG. 5 is a diagram showing a second embodiment of the present invention.

[Explanation of symbols]

1, 2, 6 ... Input terminals, 4, 9, 53 ... PLL, 7
Synchronous signal generation circuit, 8 ... Oscillator, 10 ... Frequency conversion circuit, 11 ... A / D conversion circuit, 15, 15 '... Spread spectrum circuit, 21, 21' ... Clock switching control circuit, 22, 23, 23 '... Switch, 25, 2
5 '... Clock selection circuit, 30, 30' ... Signal discrimination circuit, 31, 31 '... Frequency control circuit, 41, 42,
43 ... Output terminal, 45 ... Clock generation circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 5/391 G09G 5/36 520E H04N 5/66 G06F 1/04 310A 7/01 (72) Inventor Hasegawa Honorable: 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Within Hitachi Eitech Co., Ltd. (72) Inventor Ryo Hasegawa 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa F-Term (Hitachi Eitech Co., Ltd.) 5B079 AA07 BA01 BC03 DD02 DD03 5C058 BA04 BA12 BB04 BB06 BB17 5C063 AA01 AB01 AC01 BA01 BA04 CA23 5C082 AA01 BA12 BA34 BA35 BC19 BD09 CA32 CB01 DA76 MM09 MM10

Claims (8)

[Claims] 1. A video signal processing device for processing an input video signal and outputting it as a video signal of a frequency displayable on a display unit, wherein it is determined whether or not the clock of the input video signal can be displayed on the display unit. And a clock selecting means for selecting the video displayable clock based on the determination result, and an output means for outputting a digital video signal synchronized with the selected clock. Video signal processing device. 2. A video signal processing device for sampling an input video signal with a first clock having a predetermined frequency and digitizing the input video signal, and outputting a displayable video signal to a display section side. Second clock generating means for generating a second clock, signal determining means for determining whether or not the second clock can display an image on the display section, and third signal capable of displaying an image on the display section. Third clock generating means for generating the second clock, the second clock, the third clock, and the fourth clock formed by spectrum spreading any one of the second clock and the third clock. Clock switching means for switching between clocks and the clock switching means is controlled based on the discrimination result, and any one of the second, third, and fourth clocks can be displayed on the display unit as an image. A clock switching control means for selecting as the clock, a video signal processing apparatus characterized and output means for outputting a digital video signal synchronized with clock the selected configuration having a. 3. A video signal processing apparatus for sampling an input video signal with a first clock having a predetermined frequency, digitizing the input video signal, and outputting a displayable video signal to a display unit side. Second clock generating means for generating a second clock, signal determining means for determining whether or not the second clock can display an image on the display section, and third signal capable of displaying an image on the display section. Clock generating means for generating the clock, the first clock switching means for switching the second clock and the third clock, and the second or third clock output from the first switching means.
Clock generating means for spreading the spectrum of the clock of 4 to form a fourth clock, second clock switching means for switching the second or third clock and the fourth clock, and the determination result. Clock switching control means for controlling the first and second clock switching means and selecting a clock that can be displayed on the display unit from the second, third, and fourth clocks based on the above. An image signal processing device characterized by comprising: an output unit that outputs a digital image signal synchronized with a selected clock. 4. The clock switching control means, when the signal determination means determines that the second clock has a frequency variation within a predetermined range and can be image-displayed, the clock switching control means determines the first clock. The switching means selects the second clock, and the second clock switching means also selects the second clock.
If it is determined that the second clock is one in which the frequency fluctuation is within the predetermined range and the image cannot be displayed, the clock switching control means determines the first clock switching means. 4. The video signal processing device according to claim 3, wherein said second clock is selected by, and said fourth clock is selected by said second clock switching means. 5. When the signal discriminating means discriminates the second clock so that the frequency fluctuation exceeds a predetermined range, the clock switching control means uses the first clock switching means for the third clock. Select the clock of the second and above
4. The video signal processing device according to claim 3, wherein the clock switching means selects the fourth clock. 6. A video signal processing device for sampling an input video signal with a first clock having a predetermined frequency and digitizing the input video signal and outputting a displayable video signal to a display section side, wherein the first clock is the display. Signal discriminating means for discriminating whether or not the image can be displayed on the display section, second clock generating means for generating a second clock of a plurality of frequencies capable of displaying the image on the display section, and spectrum of the second clock And a clock switching means for switching between the third clock and the first clock, and controlling the clock switching means based on the discrimination result. And a clock switching control means for selecting one of the first and third clocks as a clock capable of displaying an image on the display unit, and the selected clock. A video signal processing apparatus for an output means for outputting a digital video signal synchronized, the configuration with the features. 7. The clock switching control means controls the clock switching means when the signal determining means determines that the first clock has a frequency variation within a predetermined range and can be displayed as an image. When the first clock is switched, the first clock is selected, and when it is determined that the first clock has a frequency variation exceeding a predetermined range or a video cannot be displayed, the clock switching means selects the third clock. 7. The video signal processing device according to claim 6, wherein the clock is selected. 8. A video comprising the video signal processing device according to any one of claims 1 to 7 and a display section for displaying a video based on a video signal from the video signal processing device. Display device.