JP2003050739A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller for exact read of data recorded in a DRAM by high speed clocks at all times. SOLUTION: The memory controller is provided with a delay quantity retrieval mode and a delay quantity establishment mode, with no read request of the data in the DRAM and in the delay quantity retrieval mode. A delay quantity control part successively outputs a plurality of first delay values, a delay quantity adjusting part generates a fetch clock which is delayed by the first delay value, a read data register fetches the data in the DRAM in accordance with the fetch clock, the delay quantity control part determines the first optimal delay value, based on whether or not the data fetched by the read data register is proper, stores the first optimal delay value as a second delay value and the delay quantity adjusting part generates a fetch clock delayed by a second delay value, when the read request of the data of the DRAM exists or in the delay quantity establishment mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device.

[0002]

2. Description of the Related Art Conventionally, as a memory control device relating to the timing of loading data recorded in a DRAM into a read register, a device described in Japanese Patent Application No. 2000-193464 is known.

A conventional memory control device and an example of determining read data storage timing in the memory control device will be described with reference to FIGS. 5 and 6. In FIG. 5, 501 is a memory control device, 102 is a DRAM, and 10
An external device 3 accesses the DRAM 102. The memory control device 501 includes a reference clock generation unit 511, a read data register 512, an input / output unit 513, and a comparison unit 5.
14, comparison data register 515, delay amount control unit 51
6. It has a delay amount adjusting unit 517. Delay amount adjustment unit 517
Has a multistage delay unit 541 and a selector 542.

The memory controller 501 will be described. The reference clock generation unit 511 outputs the reference clock having the delay value of 0 to the multi-stage delay unit 541. The DRAM 102 outputs read data according to the reference clock. The read data register 512 sets the DRAM 10 according to the fetch clock.
The read data is read from No. 2 and output to the input / output unit 513. The input / output unit 513 inputs the data sent from the external device 103, transmits the data to a write data register (a register for writing to DRAM, not shown), inputs the data output from the read data register 512, and outputs the data to the outside. Transmit to device. In the delay amount search mode described later,
The input / output unit 513 does not output read data. Comparison unit 5
Reference numeral 14 compares the test value read from the DRAM 102 at the time of the read test with the test value stored in the comparison data register 515, determines whether or not the data is correctly read, and determines the determination result (comparison result) by the delay amount. It is transmitted to the control unit 516. The comparison data register 515 stores the test value for the read test. Delay amount control unit 5
16 receives the comparison result from the comparison unit 514 and outputs it to the selector 542 of the delay amount adjustment unit 517. Multi-stage delay unit 5
Reference numeral 41 inputs the reference clock and outputs a plurality of fetched clocks having different delay values to the selector 542. The selector 542 selects a capture clock having the delay value output by the delay amount control unit 516 from the plurality of input capture clocks and outputs it to the read data register 512.

The operation of the conventional memory control device configured as described above will be described below. The memory control device 501 has a delay amount search mode for searching an optimum delay amount and a delay amount search mode for delaying a reference clock with a fixed delay amount (optimal delay amount). The operation of will be described. First, a test value is written in the DRAM 102, and the same test value is stored in the comparison data register 515. The delay amount control unit 516 is set to 0 as the first delay value, and outputs the delay value 0 to the selector 542 of the delay amount adjusting unit 517. The multi-stage delay unit 541 includes the reference clock generation unit 5
The reference clock is input from 11 to generate a plurality of fetched clocks having different delay values and output to the selector 542. The selector 542 selects a fetch clock having a delay value of 0 from the plurality of input fetch clocks and outputs it to the read data register 512. The read data register 512 reads the written test value from the DRAM 102 in accordance with the fetch clock of the delay value 0.

The comparison unit 514 compares the read value with the test value stored in the comparison data register 515. If the capture clock is set within the period when the read data is confirmed, a correct value is read into the read data register 512, and if the capture clock is set during the period when the read data is not confirmed, the read data is read. The wrong value is read into the register 512. The comparison unit 514 sends the comparison result to the delay amount control unit 516 after confirming whether the two match. The delay amount control unit 516 increases the delay value by one step and outputs the delay value 1 to the selector 542 of the delay amount adjusting unit 517. The selector 542 selects a fetch clock having a delay value of 1 from a plurality of fetch clocks input from the multi-stage delay unit 541 and outputs it to the read data register 512.

Thereafter, the same operation is performed to test whether or not the read data can be correctly read for each delay value. The delay amount control device of the conventional memory control device sequentially transmits the delay values 0 to 7 to the delay amount adjusting unit 517. FIG. 6 is a timing chart showing the relationship between the read data output timing from the DRAM and the fetch clock timing (the read data register 512 reads the read data at the rising edge of the fetch clock). Figure 6
In 601 and 602, the read data is confirmed, and in the other periods, the read data is not confirmed. As a result, the delay value when correctly read, that is, the delay value of the capture clock having the rising edge in the period when the read data in FIG. 6 is fixed has a certain range (the delay value 2 in the example of FIG. 6).
To 6). The delay amount control unit 516 sets a delay value (4 in the example of FIG. 6) that is the center of the range as the optimum delay value.

Next, the operation of the memory control device 501 in the delay amount fixing mode will be described. In the delay amount confirmation mode, the delay amount control unit 516 outputs the set optimum delay value. The delay amount adjusting unit 517 generates a fetched clock by delaying the reference clock by an optimum delay value.
The read data register 512 reads the read data from the DRAM 102 at the fetch clock. As a result, the read data can be reliably captured even before or after the period when the read data is settled to some extent due to wiring delay or the like. This delay amount adjustment processing is performed when the power is turned on or DRA
It can be executed when M is not used, or the CPU or the like can be started at any timing. DRAM
When reading the data recorded in 102, DRAM or synchronous D that supports the high-speed page mode
If an attempt is made to increase the data transfer rate by using a RAM or the like, the time during which the read data is fixed on the data bus becomes shorter. The read data must be fetched at the fixed time. If the read data fetching timing is fixed, wiring delay may occur due to temperature change or the like, and the fetch timing may be set during the period when the read data is not fixed on the data bus.
Therefore, the memory control device uses a delay amount controller 516 and a delay amount adjuster 517 to adjust the read data fetch timing.

[0009]

The memory control device must always perform the delay amount adjustment process when the power is turned on, but after that, the delay amount adjustment process is performed at an arbitrary timing. However, when the external device makes a read access to the DRAM during the delay amount adjusting process, in the conventional memory control device, any one of the delay amounts during the delay amount searching process (in FIG. The read data register 112 fetches the read data from the DRAM 102. If the delay value is set to 0, 7 or the like at the timing of the read access, the read data register 112 has an acquisition error. Alternatively, it is necessary to delay the acceptance of the read access request to the DRAM of the external device until the delay amount adjusting process is completed and the optimum delay value is determined.
An object of the present invention is to provide a memory control device that surely reads and outputs correct data even when the AM is read-accessed. If the time during which the read data is fixed in the delay amount adjustment processing is short, it is necessary to finely adjust the delay value that can be set. When it is confirmed whether the data can be correctly read from the DRAM for each delay value from the leading end to the trailing end of a certain range, it takes some time to search and determine the optimum delay value. I will end up. It is an object of the present invention to provide a memory control device that searches and determines an optimum delay value in a short time.

[0010]

In order to solve the above problems, the present invention has the following constitution. According to the present invention of claim 1, a reference clock generation unit that generates a reference clock, a delay amount control unit that outputs a delay value of a fetched clock, the reference clock and the delay value are input, and the reference clock is delayed. A delay amount adjusting unit for generating a capture clock delayed by a value, and D according to the capture clock.
A read data register for reading the data in the RAM, an input / output unit for outputting the data in the read data register to the outside, a comparison data register for storing the data for the read test, and a read data register for the read test. Data is compared with the data stored in the comparison data register, and a comparison unit that outputs the comparison result is provided, and a delay amount search mode and a delay amount confirmation mode are provided. The delay amount control unit selects one delay value from a plurality of delay values and outputs the selected first delay value, and an optimum delay amount search unit and a second delay that is a confirmed delay value. An optimum delay amount storage unit that stores a value; and a selector that selects one from the first delay value and the second delay value and outputs the value to the delay amount adjustment unit. In an in the absence RAM read request for data and the delay search mode,
The optimum delay amount searching unit sequentially outputs a plurality of the first delay values, the selector selects and outputs the first delay value, and the delay amount adjusting unit delays by the first delay value. The read data register fetches the data of the DRAM in accordance with the fetch clock, and the comparator compares the data fetched by the read data register with the data stored in the comparison data register. The comparison result is output, the delay amount control unit determines the optimum first delay value from the plurality of the first delay values based on the comparison result, and the optimum delay amount storage unit determines the optimum first delay value. The first delay value of is stored as the second delay value, and when there is an external DRAM data read request or in the delay amount confirmation mode, the selector Select the serial second delay value output, is a memory control device according to claim.

According to a second aspect of the present invention, a reference clock generation section for generating a reference clock, a delay amount control section for outputting a delay value of a fetched clock, the reference clock and the delay value are input, and the reference clock is input. A delay amount adjustment unit that generates a captured clock that is delayed by the delay value,
A read data register that reads the data of the DRAM in accordance with the fetch clock, an input / output unit that outputs the data of the read data register to the outside, a comparison data register that stores the data for the read test, and the read data register during the read test. A comparison unit that compares the data read in the data register with the data stored in the comparison data register and outputs a comparison result, and provides a delay amount search mode and a delay amount confirmation mode. The delay amount control unit selects one delay value from a plurality of delay values and outputs the selected first delay value, and an optimum delay amount search unit and a second delay value that is a confirmed delay value. Of the optimum delay amount storing unit for storing the delay value of No. 1, and one of the first delay value and the second delay value, and a select for outputting to the delay amount adjusting unit. In the delay amount search mode, the optimum delay amount search unit sequentially outputs the plurality of first delay values, and the selector selects and outputs the first delay value, The delay amount adjusting unit generates a fetch clock delayed by the first delay value, and the read data register follows the DRA according to the fetch clock.
The data of M is taken in, the comparison unit compares the data taken in by the read data register with the data stored in the comparison data register, and outputs the comparison result, and the delay amount control unit makes the comparison result. The optimum first delay value is determined from a plurality of the first delay values based on the above, and the optimum delay amount storage unit stores the optimum first delay value as the second delay value. However, in the delay amount confirmation mode, the selector selects and outputs the second delay value, and in the delay amount search mode, D selects from the outside.
When there is a request to read the data in the RAM, after the delay amount search mode ends and the delay amount confirmation mode is entered, the data in the DRAM is read and output in response to the data read request in the DRAM. And a memory control device.

The present invention according to claim 3 operates the memory control device as the memory control device according to claim 1,
The memory control device according to claim 2 can be selectively set from the outside to operate as the memory control device.

The present invention according to claim 4 is characterized in that, during the process of writing data to the DRAM, the delay amount search mode is set to search for the optimum delay value.
Alternatively, the memory control device according to claim 2.

The memory storage device according to any one of claims 1 to 4 of the present invention stores the current optimum delay value before performing the delay amount adjusting process and performs the delay amount adjusting process. When the block requests read access to the DRAM during the processing, the read processing from the DRAM is performed using the determined delay value instead of the delay value during the delay amount search processing.
When the access is completed, the delay value is returned to the setting value that was being subjected to the delay amount adjustment processing, and the delay amount adjustment processing is restarted. The new delay value is used for read access after the delay amount adjustment processing is completed.

According to a fifth aspect of the present invention, a reference clock generator for generating a reference clock, a coarse adjustment delay value, and a fine adjustment delay value that can be set more finely than the coarse adjustment delay value. Inputting the reference clock, the coarse adjustment delay value and the fine adjustment delay value, and delaying the reference clock by the coarse adjustment delay value and the fine adjustment delay value. A delay amount adjusting section for generating a captured clock, and D according to the captured clock.
A read data register for reading the data in the RAM, an input / output unit for outputting the data in the read data register to the outside, a comparison data register for storing the data for the read test, and a read data register for the read test. The data stored in the comparison data register and outputs a comparison result, and a delay amount search mode and a delay amount confirmation mode. The delay amount control unit selects one delay value from the plurality of coarse adjustment delay values, selects one delay value from the plurality of fine adjustment delay values, and selects the selected first coarse adjustment delay value. And an optimum delay amount search unit that outputs a first fine adjustment delay value, a second coarse adjustment delay value and a second fine adjustment delay that are the determined coarse adjustment delay value and fine adjustment delay value. Write the value And an optimum delay amount storage unit that, the first
Of the coarse adjustment delay value and the first fine adjustment delay value, and the second coarse adjustment delay value and the second fine adjustment delay value, the delay amount adjustment In the delay amount search mode, the optimum delay amount search unit sequentially outputs a plurality of the first coarse adjustment delay values and a constant first fine adjustment delay value. Then, the selector selects and outputs the first coarse adjustment delay value and the first fine adjustment delay value, and the delay amount adjusting unit outputs the first coarse adjustment delay value and the first coarse adjustment delay value. Generates a fetch clock delayed by the fine adjustment delay value, the read data register fetches DRAM data according to the fetch clock, and the comparator stores the fetched data in the read data register and the comparison data register. Data It compares and outputs the comparison result,
The delay amount control unit determines an optimum first coarse adjustment delay value from a plurality of the first coarse adjustment delay values based on the comparison result, and then the optimum delay amount search unit The optimum first coarse adjustment delay value and a plurality of first fine adjustment delay values are sequentially output, and the selector outputs the first coarse adjustment delay value and the first fine adjustment delay value. The delay amount adjusting section selects and outputs the fetch clock delayed by the first coarse adjustment delay value and the first fine adjustment delay value, and the read data register DRAM according to the fetch clock. Of the data, the comparison unit compares the data received by the read data register with the data stored in the comparison data register and outputs the comparison result, and the delay amount control unit outputs the comparison result. Based on Of the first fine adjustment delay values, the optimum first fine adjustment delay value is determined, and the optimum delay amount storage unit outputs the optimum first coarse adjustment delay value to the second Stored as a delay value for coarse adjustment of
The fine adjustment delay value is stored as the second fine adjustment delay value, and in the delay amount confirmation mode, the selector is configured to cause the selector to select the second coarse adjustment delay value and the second fine adjustment delay value. Is selected and output.

According to a sixth aspect of the present invention, in the delay amount search mode, the optimum delay amount search section sequentially outputs a plurality of the first coarse adjustment delay values and a constant first fine adjustment delay value. However, when the optimum first coarse adjustment delay value is determined from among the plurality of first coarse adjustment delay values, the optimum first coarse adjustment delay value and the constant first coarse adjustment delay value are determined. When it is determined that the read data register stably reads the data of the DRAM in accordance with the fetch clock delayed by the fine adjustment delay value, the optimum delay amount storage unit stores the optimum first coarse adjustment delay value. The second coarse adjustment delay value is stored as the second coarse adjustment delay value, the constant first fine adjustment delay value is stored as the second fine adjustment delay value, and the optimum first coarse adjustment delay value and The removal delayed by a constant first fine adjustment delay value. When it is determined that the read data register cannot stably read the data of the DRAM according to the clock, the optimum delay amount search unit then determines the optimum first rough adjustment delay value and a plurality of first coarse adjustment delay values. The fine adjustment delay value is sequentially output, the selector selects and outputs the first coarse adjustment delay value and the first fine adjustment delay value, and the delay amount adjusting unit outputs the first coarse adjustment delay value. A capture clock delayed by the adjustment delay value and the first fine adjustment delay value is generated, the read data register captures DRAM data in accordance with the capture clock, and the comparison unit captures the data captured by the read data register. And the data stored in the comparison data register are compared, and the comparison result is output, and the delay amount control unit is configured to output a plurality of the first delay signals based on the comparison result. The optimum first fine adjustment delay value is determined from among the adjustment delay values, and the optimum delay amount storage unit converts the optimum first coarse adjustment delay value into the second coarse adjustment delay value. Memorized as the best said first
6. The memory control device according to claim 5, wherein the fine adjustment delay value is stored as the second fine adjustment delay value.

In the memory storage device according to the fifth and sixth aspects of the present invention, the delay amount adjusting unit is provided in two stages, and the delay amount adjusting unit which can be finely set in the second stage is provided, and the first stage is larger than that. The delay amount adjusting unit is capable of adjusting the delay amount. That is, first, the delay amount adjusting unit of the first stage performs the delay amount adjusting process, and a point at which data can be almost certainly read from the DRAM is searched for. A delay amount adjustment process is performed before and after that point.
This makes it possible to perform the delay amount adjustment processing (in a short time), and as a result, since the delay amount adjustment processing is performed, the time during which the external device cannot read data from the DRAM can be shortened.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments specifically showing the best mode for carrying out the present invention will be described below with reference to the drawings.

<< Embodiment 1 >> A memory controller according to Embodiment 1 of the present invention will be described with reference to FIGS. In FIG. 1, 101 is a memory control device, 102 is a DRAM, and 10
An external device 3 accesses the DRAM 102. The memory control device 101 includes a reference clock generation unit 111, a read data register 112, an input / output unit 113, and a comparison unit 1.
14, comparison data register 115, delay amount control unit 11
6. A delay amount adjusting unit 117 is included. Delay amount control unit 116
Is the optimum delay amount search unit 141 and the optimum delay amount storage unit 14
2. It has a selector 143. The delay amount adjustment unit 117
It has a multistage delay unit 151 and a selector 152.

The memory control device 101 will be described. The reference clock generation unit 111 outputs the reference clock having the delay value of 0 to the multi-stage delay unit 151. The DRAM 102 outputs read data according to the reference clock. The read data register 112 stores the DRAM 10 in accordance with the fetch clock.
The read data is read from No. 2 and output to the input / output unit 113. The input / output unit 113 inputs the data sent from the external device 103, transmits the data to a write data register (a register for writing to DRAM, not shown), inputs the data output from the read data register 112, and outputs the external data. Transmit to device. In the delay amount search mode described later,
The input / output unit 113 does not output read data. Comparison section 1
Reference numeral 14 compares the test value read from the DRAM 102 at the time of the read test with the test value stored in the comparison data register 115, determines whether or not the data is correctly read, and determines the determination result (comparison result) by the delay amount. It is transmitted to the control unit 116. The comparison data register 115 stores a test value for a read test. The optimum delay amount search unit 141 stores a plurality of delay values, and the comparison unit 114
The comparison result is input from and the delay value is output to the selector 143. The optimum delay amount search unit 141 registers the delay value in the optimum delay amount storage unit 142 when the delay amount search mode (described later) is finished and the optimum delay value for data reading is confirmed. . The optimum delay amount storage unit 142 stores the optimum delay value obtained in the previous delay amount search mode, and outputs the delay value to the selector 143. The selector 143 selects one of the two delay values input from the optimum delay amount search unit 141 and the optimum delay amount storage unit 142, and outputs it to the selector 152 of the delay amount adjusting unit 117. The multi-stage delay unit 151 inputs the reference clock and selects a plurality of fetch clocks having different delay values from the selector 152.
Output to. The selector 152 selects a capture clock having the delay value output by the selector 143 from the plurality of input capture clocks and outputs it to the read data register 112.

The operation of the memory control device of this embodiment constructed as described above will be described below. The memory control device 101 has a delay amount search mode for searching for the optimum delay amount and a delay amount fixing mode for delaying the reference clock by the fixed delay amount (optimal delay amount). The operation of the memory control device 101 in the delay amount search mode (assuming that there is no DRAM device read request from an external device) will be described. First, the test value is written in the DRAM 102, and the test value having the same value is stored in the comparison data register 115. The multistage delay unit 151 receives the reference clock from the reference clock generation unit 111, generates a plurality of fetched clocks having different delay values, and selects the selector 152.
Output to. The initial value of the delay value is set to 0, and the optimum delay amount search unit 141 sets the delay value 0 to the selector 1
Output to 43. The selector 143 is the optimum delay amount search unit 1
41 is set to select the delay value output by
The delay value 0 output from the optimum delay amount searching unit 141 is output to the selector 152 of the delay amount adjusting unit 117.

The selector 152 selects a fetch clock with a delay value of 0 from a plurality of input fetch clocks and outputs it to the read data register 112. The read data register 112 reads the test value written in the DRAM 102 according to the delay value 0 fetch clock. The comparison unit 114 compares the fetched value with the test value stored in the comparison data register 115. When the read clock is set within the time when the read data is fixed, the read data register 11
If the correct value is read into 2 and the fetch clock is set during the period when the read data is not fixed, the wrong value is read into the read data register 112. The comparison unit 114, after confirming whether the two match, sends the comparison result to the optimum delay amount search unit 141. The optimum delay amount search unit 141 increases the delay value by one step and sends the delay value 1 to the selector 143. The selector 143 selects the delay value 1 output by the optimum delay amount searching unit 141 and outputs it to the selector 152 of the delay amount adjusting unit 117.
The selector 152 selects a fetch clock having a delay value of 1 from a plurality of fetch clocks input from the multi-stage delay unit 151 and outputs it to the read data register 112.

Thereafter, the delay value is increased by one and the same processing is performed. In the first embodiment, the delay amount control unit 116 sequentially sends the delay values 0 to 4 to the delay amount adjustment unit 117. Figure 2 is DR
5 is a timing chart showing the relationship between the output timing of read data from the AM 102 and the timing of the fetch clock at each delay value. The read data register 112 reads the read data at the rising edge of the fetch clock. If it is set to the capture clock (delay value 1 to 3) of FIG. 2, the period during which the read data is fixed (the period between 201 and 202)
Therefore, correct data can be stored in the read data register 112 within this period. The delay amount control unit 116 determines the delay value (delay value 2 in this case) that is the center of the range as the optimum delay value. The optimum delay amount storage unit 142 stores the optimum delay value (delay value 2 in FIG. 2).

Next, the operation of the memory control device 101 in the delay amount fixing mode will be described. In the delay amount confirmation mode, the selector 143 of the delay amount control unit 116 selects the confirmed delay value (optimal delay value) output from the optimum delay amount storage unit 142, and the selector 152 of the delay amount adjustment unit 117.
To transmit. The selector 152 selects and outputs the fetched clock obtained by delaying the reference clock by the optimum delay value. The read data register 112 reads the read data from the DRAM 102 according to the fetch clock. As a result, the read data can be reliably captured even before or after the time when the read data is settled to some extent due to wiring delay or the like. When the external device 103 having the access right to the DRAM 102 requests read access during the delay amount adjustment processing in the delay amount search mode, the delay value output by the optimum delay amount search unit 141 is the read data. It may be set outside the fixed period (for example, the state of the capture clock (delay value 4) in FIG. 2). When the read data register 112 fetches the data from the DRAM 102 with this delay value, the read data cannot be correctly read from the DRAM 102.

Therefore, in the memory control device 101 of the first embodiment, the external device 103 requests read access during the delay amount adjustment processing in the delay amount search mode, and the external device 103
When the access request is permitted, the selector 143 switches the delay value output from the delay value output by the optimum delay amount search unit 141 to the delay value output by the optimum delay amount storage unit 142. At the same time, the delay amount adjustment processing is interrupted, and the external device 10
3 reads the data of the DRAM 102 requested and transmits it to the external device 103. Here, the optimum delay amount storage unit 142
It is assumed that, for example, information that the delay value before the delay amount adjustment processing of FIG. 2 is 1 is stored. The delay value set in the optimum delay amount storage unit 142 is a value determined in the delay amount adjusting process in the previous delay amount search mode.

Normally, the delay amount adjusting process is performed in order to prevent the read data from being abnormally taken in due to a change in the wiring delay of the read data due to a temperature change or the like. By setting the delay amount search mode at an appropriate timing, the delay value fixed in the previous delay amount search mode is set to the read data fixed period (201 and 20 in FIG. 2).
2)). Correct data can be read using the delay value determined in the previous delay amount search mode. Therefore, as described above, the delay amount adjustment processing of this time is temporarily interrupted, and the memory control device 101 reads data from the DRAM 102 using the delay value determined by the previous delay amount adjustment. After that, when the read access of the external device 103 is completed, the delay value received by the selector 152 by switching the selector 143 again is set to the delay value output by the optimum delay amount search unit 141 (before the external device 103 performs the read access. The value is returned to the delay value during the delay amount adjustment processing being performed), and the delay amount adjustment processing is restarted. With the conventional technique, the memory control device 101 may read erroneous data when a read access request is issued from the external device 103 during the delay amount search mode. Alternatively, it is necessary to delay the acceptance of the read access request to the DRAM of the external device until the delay amount adjustment processing is completed and the optimum delay value is determined. According to the present invention, even in the delay amount search mode, the memory control device 101 can read correct data from the DRAM 102 in response to a data read request from the external device 103.

When the power is turned on, the optimum delay amount storage section (having a volatile memory) does not store the correct optimum delay value. Therefore, in the first delay amount search mode after the power is turned on, even if a read access request from the external device 103 is issued during the delay amount search mode, the delay amount adjustment process is given priority and the delay search mode ends. After that, the external device 103 read access is permitted. When it is found that the data in the DRAM 102 cannot be read correctly during the operation in the delay amount fixing mode, the delay amount searching mode is forcibly set. In this case, the read data register 112 is set to the delay value stored in the optimum delay amount storage unit 142.
Cannot store correct read data, so the read access request from the external device 103 is not permitted during the delay amount search mode, and after the delay amount search mode ends, the external device 10
The read access request of No. 3 is permitted.

In the delay amount search mode, the memory control device of this embodiment selectively externally determines whether the read access is prioritized or the delay adjustment node process is prioritized when the external device requests the read access. Can be set.

For example, writing the image data in the DRAM,
Memory controller to read (eg VGA of computer)
In the controller), an external device (eg CPU)
Includes a software language (eg, Dire
A data write command described in ctX (registered trademark of Microsoft Corporation) may be sent. The memory control device converts a data write command written in a software language into hardware level write data,
Write the converted data to the DRAM. In the above write processing, it takes some time to convert the data write instruction written in the software language into the write data of the hardware level. At this time (DR
(AM is not operating) The memory control device of the first embodiment can shift to the delay amount search mode and search for the optimum delay value. In addition, the memory control device of the present embodiment is
During the process of writing data to M, the delay amount adjustment process can be performed by setting the delay amount search mode to obtain the optimum delay value. As a result, the memory control device can always take in the read data from the DRAM with the optimum delay value without causing any trouble in accessing the DRAM from the external device.

<Embodiment 2> A memory control apparatus according to Embodiment 2 of the present invention will be described with reference to FIGS. In FIG. 3, 301 is a memory control device, 102 is a DRAM, and 10
An external device 3 accesses the DRAM 302. The memory control device 301 includes a reference clock generation unit 311, a read data register 312, an input / output unit 313, and a comparison unit 3.
14, comparison data register 315, delay amount control unit 31
6. It has a delay amount adjusting unit 317. Delay amount control unit 316
Is the optimum delay amount search unit 341 and the optimum delay amount storage unit 34.
2. It has a selector 343. The delay amount adjusting unit 317
It has a coarse adjustment multi-stage delay unit 351, a selector 352, a fine adjustment multi-stage delay unit 353, and a selector 354.

The memory controller 301 will be described. The reference clock generation unit 311 outputs the reference clock having the delay value of 0 to the coarse adjustment multi-stage delay unit 351 and the DRAM 102. The DRAM 102 outputs read data according to the reference clock. The read data register 312 reads the read data from the DRAM 102 according to the fetch clock and outputs the read data to the input / output unit 313. The input / output unit 313 inputs the data sent from the external device 103, transmits the data to a write data register (a register for writing to DRAM, not shown), inputs the data output from the read data register 312, and outputs the data to the outside. Transmit to device. In the delay amount search mode (described later), the input / output unit 313 does not output read data. The comparison unit 314 compares the test value read from the DRAM 102 at the time of the read test with the test value stored in the comparison data register 315, determines whether or not the data is correctly read, and determines the determination result (comparison result) delay amount. It is transmitted to the control unit 316. The comparison data register 315 stores a test value for a read test.

The optimum delay amount retrieval unit 341 inputs the comparison result from the comparison unit 314 and selects one coarse adjustment delay value from the stored coarse adjustment delay values and fine adjustment delay values. , And one fine adjustment delay value are selected and output to the selector 343. When the delay amount search mode ends and the optimum delay value for data reading is confirmed, the optimum delay amount searching unit 341 stores the determined coarse adjustment delay value and fine adjustment delay value in the optimum delay amount storage unit 342. Register to.
The optimum delay amount storage unit 342 stores the coarse adjustment delay value and the fine adjustment delay value obtained in the previous delay amount search mode, and stores the coarse adjustment delay value and the fine adjustment delay value in the selector 343. Output. The selector 343 inputs one set of each of the coarse adjustment delay value and the fine adjustment delay value from the optimum delay amount search unit 341 and the optimum delay amount storage unit 342, and selects one of the two input delay values. A set (consisting of a coarse adjustment delay value and a fine adjustment delay value) is selected, and the coarse adjustment delay value of the selected set of delay values is selected by the selector 3 of the delay amount adjusting unit 317.
52 and outputs the fine adjustment delay value to the selector 354.

The coarse adjustment multi-stage delay unit 351 receives the reference clock and outputs a plurality of fetched clocks having different coarse adjustment delay values to the selector 352. Selector 35
2 selects a capture clock having a coarse adjustment delay value output from the delay amount control unit 316 from a plurality of input capture clocks and outputs it to the fine adjustment multi-stage delay unit 353. When the fine adjustment multi-stage delay unit 353 receives a capture clock having a constant coarse adjustment delay value from the selector 352, it receives a plurality of capture clocks having different fine adjustment delay values with the coarse adjustment delay value as a reference. Selector 354
Output to. The selector 354 selects a capture clock corresponding to the fine adjustment delay value output from the delay amount control unit 316 when receiving a plurality of capture clocks having different fine adjustment delay values with reference to a constant coarse adjustment delay value. , To the read data register 312. Here, the fine adjustment delay value output from the delay amount control unit 316 can be set more finely than the coarse adjustment delay value. For example, if the delay value for coarse adjustment is increased by 1, the delay value of the fetched clock is increased by 1.
When the fine adjustment delay value is increased by 1, the delay value of the fetched data is increased by 0.1 ns. Further, in the fine adjustment multi-stage delay unit 353, for example, when the fine adjustment delay value can be set in 9 steps from 0 to 8, the initial state is set to the center value of
(The reason will be described later).

The operation of the memory control device of this embodiment constructed as described above will be described below. The memory control device 301 has a delay amount search mode for searching for an optimum delay value and a delay amount fixing mode for delaying a reference clock with a fixed delay amount (optimal delay amount). Memory control device 301 in delay amount search mode (assuming that there is no external request to read data from DRAM 102)
The operation of will be described. First, the test value is written in the DRAM 102, and at the same time, the same test value is stored in the comparison data register 315. The delay amount control unit 316 first sets the coarse adjustment delay value to 0 and the fine adjustment delay value to 4, and sets the coarse adjustment delay value 0 to the selector 352 through the selector 343.
To output the fine adjustment delay value 4 to the selector 354. The coarse adjustment multi-stage delay unit 351 includes a reference clock generation unit 311.
The reference clock is input from the selector 352 to generate a plurality of acquisition clocks having different coarse adjustment delay values.
Output to. The selector 352 selects a capture clock having a coarse adjustment delay value of 0 from a plurality of input capture clocks and outputs it to the fine adjustment multi-stage delay unit 353.
When the fine adjustment multi-stage delay unit 353 receives the capture clock having the coarse adjustment delay value 0 from the selector 352, the coarse adjustment delay value is 0, and a plurality of captures having different fine adjustment delay values are received. The clock is output to the selector 354. Based on the input coarse adjustment delay value of 0, the selector 354 selects the capture clock of the fine adjustment delay value 4 from a plurality of capture clocks having different fine adjustment delay values, and reads the read data register 312. Output to.

The read data register 312 reads the test value written in the DRAM 102 in accordance with the fetch clock of the coarse adjustment delay value 0 and the fine adjustment delay value 4.
The comparison unit 314 compares the fetched value with the test value stored in the comparison data register 315. If the capture clock is set within the period when the read data is confirmed, a correct value is read into the read data register 312, and if the capture clock is set during the period when the read data is not confirmed, the read data is read. A wrong value is read into the register 312. The comparison unit 314, after confirming whether the two match, sends the comparison result to the delay amount control unit 316. The delay amount control unit 316 increases the coarse adjustment delay value by one step, outputs the coarse adjustment delay value 1 to the selector 352, and outputs the fine adjustment delay value 4 (without change) to the selector 354. In this case, the delay amount adjusting unit 317 outputs the fetch clock of the coarse adjustment delay value 1 and the fine adjustment delay value 4 to the read data register 312.

Thereafter, the coarse adjustment delay value is increased by 1 and the same processing is performed. The delay value for fine adjustment remains fixed at 4,
It is checked whether the read data output from the DRAM 102 can be correctly stored in the read data register 312 for each coarse adjustment delay value from 0 to the maximum coarse adjustment delay value 2. FIG. 4 shows the delay amount control unit 316.
And the acquisition clock whose delay value is set by the coarse adjustment delay value and the fine adjustment delay value output from the DRAM 10.
3 is a timing chart showing the relationship with the read data read from No. 2. The read data register 312 is
Read the read data at the rising edge of the capture clock. For example, as shown in FIG. 4, the capture clock is set within the period in which the read data is fixed only when the coarse adjustment delay value is 1 (because the period in which the read data is fixed is short). And However, even when the delay value for coarse adjustment is 1, for example, as shown in FIG. 4B at this time, the read block is set to the front, not in the middle of the period when the read data is fixed. It may have been done. In this case, even if the delay value for coarse adjustment is 1, if the period in which the read data is fixed is delayed due to wiring delay or the like, the rising edge of the capture clock is outside the period in which the read data is fixed, Data may not be read correctly. In other words, under the coarse adjustment delay value 1 and the fine adjustment delay value 4, the DRAM data cannot be read stably. If the fetch clock is as centered as possible within the fixed time, it is possible to avoid setting the fetch clock outside the fixed period even if the wiring delay of the read data changes to some extent.

Therefore, next, the delay value for coarse adjustment is fixed to 1 which is the optimum value, and the delay value for fine adjustment is 4 from the present value of 4 to the maximum value (in this example, the delay value of 8 is set). ), And whether or not the read data of the DRAM 102 can be correctly stored in the read data register 312 is checked for each. The reason for setting the delay value for fine adjustment at the center of the range in which the delay value for fine adjustment can be set when performing the test for determining the delay value for coarse adjustment is to fix the delay value for coarse adjustment and then finely adjust the capture clock before and after that. This is so that it can be done. As a result of fixing the delay value for coarse adjustment to 1 and varying the delay value for fine adjustment, if the delay values for fine adjustment are 3 to 7 in FIG. Is set. That is, if the capture clock is set within that period, the DRAM 102 is normally operated.
It indicates that the read data can be read. The fine adjustment delay value is set to 5, which is the center of 3 to 7. After all, the optimum values of the coarse adjustment delay value input to the selector 352 and the fine adjustment delay value input to the selector 354 are 1 and 5, respectively. Determine the optimal delay value for coarse adjustment and delay value for fine adjustment, and use this value to stabilize DR
When it is determined that the AM data can be read, the optimum delay amount searching unit 341 stores the determined coarse adjustment delay value and fine adjustment delay value in the optimum delay amount storage unit 342.

Next, the operation of the memory control device 301 in the delay amount fixing mode will be described. In the delay amount confirmation mode, the selector 343 of the delay amount control unit 316 selects the confirmed coarse adjustment delay value and fine adjustment delay value output from the optimum delay amount storage unit 342, and the selector 352 of the delay amount adjustment unit 317. And 354 respectively. The selectors 352 and 354 select and output the fetched clock obtained by delaying the reference clock by the optimum delay value. The read data register 312 uses the DRA according to the capture clock.
Read the read data from M102. In the conventional memory control device, the optimum delay amount is searched for by changing the timing of the rising edge of the clock from the beginning to the end of the fixed period in units of a constant delay amount. In the memory control device of the present invention, a rough maximum value is obtained by the coarse adjustment multistage delay unit, and then an accurate optimum value is obtained by the fine adjustment multistage delay unit. As a result, the search time for the optimum delay amount in the delay amount search mode can be shortened. As a result of checking whether the read data register 312 can correctly read the data by changing the coarse adjustment delay value while keeping the fine adjustment delay value constant, the optimum delay value can be determined. If so, the step of changing the fine adjustment delay value and checking whether the read data register 312 can correctly read the data can be omitted. For example, as a result of changing the coarse adjustment delay value from 0 to 2, the read data register 31
2 can read the data correctly. In this case, by setting the coarse adjustment delay value to 1 and the fine adjustment delay value to a constant value (4 in the embodiment), the read data register 312 malfunctions due to the influence of the temperature change wiring delay or the like. Always correct data without
It can be read from RAM.

In the above embodiment, the read clock input to the DRAM is fixed and the read clock input to the read data register is variable. Alternatively, the read clock input to the read data register may be fixed and the read clock input to the DRAM may be variable. "The read data register reads the DRAM data according to the fetch clock" includes any of the above cases.

[0040]

The memory control device of the present invention has an optimum delay amount storage section for storing the delay value obtained in the previous delay amount search mode. When the external device requests a read access during the delay amount adjustment processing, the delay value obtained in the previous delay amount search mode is temporarily returned, and the read processing of the accessed block is performed. When the access is completed, the delay value is returned to the setting value that was being adjusted for the delay amount,
Restart the delay amount adjustment processing. The new delay value is used in the read process after the end of the delay amount search mode. In addition, the memory control device of the present invention does not permit the data read during the delay amount search mode when the external device requests to read the data of the DRAM during the delay amount search mode, and enters the delay amount confirmation mode. After that, data reading is permitted. According to the present invention, it is possible to obtain an advantageous effect that a memory control device that always reads correct data from a DRAM can be realized. Further, according to the present invention, the delay amount adjusting unit is provided in two stages, that is, the coarse adjusting multistage delay unit and the fine adjusting unit. And a multistage delay unit for adjustment. First, the rough adjustment delay value is changed to roughly obtain an optimum delay amount, and then the fine adjustment delay value is changed to obtain an accurate and optimum delay value. According to the present invention, it is possible to obtain an advantageous effect of realizing a memory control device that obtains an optimum delay value in a short time.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory control device according to a first embodiment of the present invention.

FIG. 2 DR in the memory control device according to the first embodiment
Storage timing chart of read data from AM

FIG. 3 is a configuration diagram of a memory control device according to a second embodiment of the present invention.

FIG. 4 DR in the memory control device according to the second embodiment
Storage timing chart of read data from AM

FIG. 5 is a block diagram of a memory control device according to a conventional technique.

FIG. 6 is a storage timing chart of read data from a DRAM in a conventional memory control device.

[Explanation of symbols]

101, 301, 501 Memory control device 102 DRAM 103 External device 111, 311, 511 Reference clock generation unit 112, 312, 512 Read data register 113, 313, 513 Input / output unit 114, 314, 514 Comparison unit 115, 315, 515 Comparison data registers 116, 316, 516 Delay amount control units 117, 317, 517 Delay amount adjusting units 141, 341 Optimal delay amount searching units 142, 342 Optimal delay amount storage units 143, 152, 343, 352, 354, 542
Selectors 151, 541 Multistage delay unit 351 Coarse adjustment multistage delay unit 353 Fine adjustment multistage delay unit

Claims (6)

[Claims] 1. A reference clock generation unit that generates a reference clock, a delay amount control unit that outputs a delay value of a fetched clock, the reference clock and the delay value are input, and the reference clock is delayed by the delay value. A delay amount adjusting section for generating the fetched clock, a read data register for reading the data of the DRAM in accordance with the fetched clock, an output section for outputting the data of the read data register to the outside, and storing the read test data. A comparison data register, and a comparison unit that compares the data read into the read data register with the data stored in the comparison data register during a read test and outputs the comparison result. A delay amount search mode and a delay amount confirmation mode, wherein the delay amount control unit is Optimal delay amount search unit that selects one delay value from the number of delay values and outputs the selected first delay value, and optimum delay amount storage that stores the second delay value that is the confirmed delay value Section and a selector that selects one from the first delay value and the second delay value and outputs the selected delay value to the delay amount adjusting section, and there is no external request to read data from the DRAM. At the same time and in the delay amount search mode, the optimum delay amount search unit sequentially outputs the plurality of first delay values, and the selector selects and outputs the first delay value, The delay amount adjusting unit generates a fetch clock delayed by the first delay value, and the read data register fetches DRAM data according to the fetch clock.
The comparison unit compares the data received by the read data register with the data stored in the comparison data register and outputs a comparison result, and the delay amount control unit determines a plurality of the delay units based on the comparison result. The optimum first delay value is determined from the first delay values, and the optimum delay amount storage unit stores the optimum first delay value as the second delay value, and externally stores the DRAM delay value. The memory control device, wherein the selector selects and outputs the second delay value when there is a data read request or in the delay amount fixing mode. 2. A reference clock generation unit that generates a reference clock, a delay amount control unit that outputs a delay value of a fetched clock, the reference clock and the delay value are input, and the reference clock is delayed by the delay value. A delay amount adjusting section for generating the fetched clock, a read data register for reading the data of the DRAM in accordance with the fetched clock, an output section for outputting the data of the read data register to the outside, and storing the read test data. A comparison data register, and a comparison unit that compares the data read in the read data register with the data stored in the comparison data register at the time of the read test and outputs the comparison result. A delay amount determination mode and a delay amount confirmation mode. An optimum delay amount search unit that selects one delay value from the values and outputs the selected first delay value; and an optimum delay amount storage unit that stores the second delay value that is the confirmed delay value, A selector that selects one from the first delay value and the second delay value and outputs the selected delay value to the delay amount adjusting unit; in the delay amount search mode, the optimum delay amount search is performed. A unit sequentially outputs the plurality of first delay values, the selector selects and outputs the first delay value, and the delay amount adjusting unit generates a capture clock delayed by the first delay value. Then, the read data register fetches the DRAM data in accordance with the fetch clock, and the comparison unit compares the data fetched by the read data register with the data stored in the comparison data register and outputs the comparison result. The delay amount control unit determines the optimum first delay value from the plurality of first delay values based on the comparison result, and the optimum delay amount storage unit determines the optimum first delay value. Is stored as the second delay value. In the delay amount fixing mode, the selector selects and outputs the second delay value. When there is a read request, after the delay amount search mode is finished and the delay amount confirmation mode is entered, the DRA is responded to in response to the data read request of the DRAM.
A memory control device, wherein M data is read and output. 3. The memory control device can be selectively set from the outside to operate as the memory control device according to claim 1 and to operate as the memory control device according to claim 2. Memory controller. 4. The memory control device according to claim 1, wherein the delay amount search mode is set to search for the optimum delay value during the process of writing data to the DRAM. . 5. A reference clock generation unit that generates a reference clock, a delay value for coarse adjustment, and a delay amount control that outputs a fine adjustment delay value that can be set more finely than the coarse adjustment delay value. Section, and inputs the reference clock, the coarse adjustment delay value and the fine adjustment delay value, and generates a capture clock by delaying the reference clock by the coarse adjustment delay value and the fine adjustment delay value. A delay amount adjusting section, a read data register for reading the DRAM data according to the fetch clock, an output section for outputting the data of the read data register to the outside, a comparison data register for storing the read test data, and a read During the test, compare the data read in the read data register with the data stored in the comparison data register. And a comparison unit that outputs a comparison result, and a delay amount search mode and a delay amount confirmation mode, wherein the delay amount control unit includes one delay value from a plurality of coarse adjustment delay values. An optimum delay amount search unit that selects a value, selects one delay value from a plurality of fine adjustment delay values, and outputs the selected first coarse adjustment delay value and first fine adjustment delay value. And the determined coarse adjustment delay value and fine adjustment delay value
An optimal delay amount storage unit for storing the coarse adjustment delay value and the second fine adjustment delay value, the first coarse adjustment delay value, the first fine adjustment delay value, and the second coarse adjustment delay value. A selector that selects one from the adjustment delay value and the second fine adjustment delay value and outputs the selected one to the delay amount adjustment unit, and in the delay amount search mode, the optimum delay amount. The search unit sequentially outputs a plurality of the first coarse adjustment delay values and a constant first fine adjustment delay value, and the selector outputs the first coarse adjustment delay value.
The coarse adjustment delay value and the first fine adjustment delay value are selected and output, and the delay amount adjusting unit delays by the first coarse adjustment delay value and the first fine adjustment delay value. The read data register fetches the data of the DRAM in accordance with the fetch clock, and the comparator compares the data fetched by the read data register with the data stored in the comparison data register. The comparison result is output, and the delay amount control unit determines the optimum first coarse adjustment delay value from among the plurality of first coarse adjustment delay values based on the comparison result, and then, The optimum delay amount search unit sequentially outputs the optimum first coarse adjustment delay value and a plurality of first fine adjustment delay values, and the selector outputs the first coarse adjustment delay value and the first coarse adjustment delay value. Fine adjustment delay The delay amount adjusting section generates a capture clock delayed by the first coarse adjustment delay value and the first fine adjustment delay value, and the read data register follows the capture clock. The data of the DRAM is fetched, the comparison unit compares the data fetched by the read data register with the data stored in the comparison data register, and outputs the comparison result, and the delay amount control unit causes the comparison result. The optimum first fine adjustment delay value from a plurality of the first fine adjustment delay values, and the optimum delay amount storage section determines the optimum first coarse adjustment delay value. Is stored as the second coarse adjustment delay value, the optimal first fine adjustment delay value is stored as the second fine adjustment delay value, and in the delay amount confirmation mode, the selector The second coarse adjustment delay value and selects said second fine adjustment delay value output from the memory controller, characterized in that. 6. In the delay amount search mode, the optimum delay amount search unit sequentially outputs a plurality of the first coarse adjustment delay values and a constant first fine adjustment delay value, and a plurality of the plurality of the first fine adjustment delay values. When the optimum first coarse adjustment delay value is determined from among the first coarse adjustment delay values, only the optimum first coarse adjustment delay value and the constant first fine adjustment delay value When it is determined that the read data register stably reads the data of the DRAM according to the delayed capture clock, the optimum delay amount storage unit sets the optimum first coarse adjustment delay value to the second coarse adjustment. A fixed first fine adjustment delay value is stored as the second fine adjustment delay value, and an optimum first rough adjustment delay value and a constant first fine adjustment delay value are stored. According to the acquisition clock delayed by the delay value for fine adjustment If it is determined that the read data register cannot stably read the data in the DRAM, the optimum delay amount search unit then determines the optimum first rough adjustment delay value and a plurality of first fine adjustment delay values. The delay values are sequentially output, the selector selects and outputs the first coarse adjustment delay value and the first fine adjustment delay value, and the delay amount adjusting unit outputs the first coarse adjustment delay. Value and the first fine adjustment delay value, a capture clock delayed is generated, the read data register captures DRAM data in accordance with the capture clock, and the comparison unit compares the data captured by the read data register with the data. The data stored in the data register and outputs the comparison result, and the delay amount control unit selects one of the plurality of first fine adjustment delay values based on the comparison result. The optimum first fine adjustment delay value is determined from the above, and the optimum delay amount storage unit stores the optimum first coarse adjustment delay value as the second coarse adjustment delay value. The memory control device according to claim 5, wherein the first fine adjustment delay value is stored as the second fine adjustment delay value.