JP2002305291A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique which enhances the gattering capability of a semiconductor wafer, and to provide a technique which restrains crystal defects of the semiconductor wafer. SOLUTION: A base substrate 2A whose (100) plane is used as a main face and in which a notch 1A is formed in a <011> orientation inside its face and a bonding substrate 2B, whose (100) plane is used as a main face and in which a notch 1B is formed in a <010> orientation inside its face are pasted, in such a way that the notches are overlapped, and an SOI substrate is formed. In the semiconductor integrated circuit device formed by using the SOI substrate, the longitudinal direction of each element is formed in parallel or perpendicular to the <011> orientation of the base substrate 2A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly, to a method for manufacturing a bonded SOI (Silicon
The present invention relates to a technology which is effective when applied to the manufacture of a semiconductor integrated circuit device having a (n On Insulator) substrate.

[0002]

2. Description of the Related Art In a silicon (Si) wafer on which semiconductor elements and wirings are formed, the element formation surface is [100].
Plane is set. This is MOS (Metal-Oxide-Se
In the case of a device (semiconductor integrated circuit device) having a semiconductor structure, the interface order between silicon and an oxide film is [100]
Surface, the element forming surface is
A [100] plane is used.

In the silicon wafer, an orientation flat (hereinafter, abbreviated as OF) or a notch is set in the <011> direction. Usually, the device shape is rectangular, and the device is cut using the cleavage of the crystal. In the case of the (100) plane, the device can be easily cut by forming the device parallel or perpendicular to the OF or the notch.

In addition, a silicon active layer is formed on a substrate made of single crystal silicon with an insulating layer interposed therebetween, and a MISFET (Metal Insulator Semiconductor Device) is formed on a main surface of the active layer.
S for forming semiconductor elements such as d Effect Transistor)
There is OI technology. This SOI technology enables complete element isolation. (1) Since complete isolation between elements is possible, device miniaturization (high integration) and high reliability (insulation resistance, soft error and soft error) (Improvement of characteristics such as latch-up) is easy. (2) Since the parasitic capacitance between the element and the substrate can be reduced, the device operation can be sped up. (3) A three-dimensional structure is made possible, and higher integration and multifunction of the device can be achieved. It has such advantages.

[0005] A method of manufacturing an SOI substrate includes a single crystal silicon (SOI) as a bond substrate on which a semiconductor element is formed.
Layer) and single-crystal silicon serving as a base substrate are formed into an oxide film (B
After bonding via an OX (Buried Oxide) layer), the "bonding method" is formed by thinning the bond substrate, or oxygen is ion-implanted into the silicon substrate and a buried oxide layer is formed inside the substrate by heat treatment. "SIMO
X (Separation by Implanted Oxygen) method. However, the SIMOX method has problems such as the reliability of the buried oxide layer and the necessity of a crystallinity recovery heat treatment at 1350 ° C. or more. Have been.

The SOI substrate is described in, for example, Fumio Shimura, published by Maruzen Co., Ltd., “Semiconductor Silicon Engineering”, p. 217-p. 240.

[0007]

SUMMARY OF THE INVENTION As a semiconductor substrate, SO
When an I substrate is used, there is a problem of insufficient gettering ability against metal contamination.

In the process of forming a semiconductor element on a semiconductor substrate, a metal such as Fe (iron), Al (aluminum), C
There is a possibility that u (copper) or Ni (nickel) may be unexpectedly mixed into the semiconductor substrate (metal contamination). Metal contamination can degrade the electrical properties of the device. S
When an OI substrate is used, there is a possibility that the BOX layer, the interface between the BOX layer and the base substrate, or the interface between the BOX layer and the SOI layer may serve as a metal capture center (gettering site). However, it cannot be said that an effective gettering effect is actually obtained. In particular, metal introduced from the SOI side, that is, from the element formation surface (principal surface) tends to remain in the SOI layer. Therefore, it is desired that the SOI substrate has strong gettering ability.

A device having a normal MOS structure is
Using the [100] plane, there is an electric flow in the <100> direction. As a crystal, the mobility of carriers is larger in the <100> direction than in the <110> direction, and the device has higher electric performance when the rectangle of the semiconductor element is formed parallel or perpendicular to the <100> direction. Becomes However, actually, a rectangle of the semiconductor element is formed in the <110> direction. This is not due to the characteristics of the element, but because the device is cut using the cleavage of the semiconductor substrate.
Since a semiconductor substrate made of silicon has a slip direction in the <110> direction, forming a rectangle of a semiconductor element in the <110> direction facilitates cleavage. Also, <110
When the rectangle of the semiconductor element is formed in the orientation, there is a problem that dislocation due to thermal stress, dislocation due to stress received from the rectangular element, and cracks and chips during the manufacturing process are liable to occur.

An object of the present invention is to provide an SOI substrate having a high gettering ability, an electrically high performance, and suppressing generation of crystal defects.

Another object of the present invention is to provide a semiconductor integrated circuit device using the SOI substrate.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention provides a step of preparing a first single-crystal silicon wafer and a second single-crystal silicon wafer having a (100) plane as a main surface, and at least one surface of the second single-crystal silicon wafer. Forming a first insulating film, and bonding a main surface of the first single crystal silicon wafer and a first insulating film forming surface of the second single crystal silicon wafer to form an SOI substrate. The SOI substrate is formed by bonding the first orientation on the main surface of the first single-crystal silicon wafer and the second orientation on the main surface of the second single-crystal silicon wafer so as to overlap each other.

Further, the present invention provides a step of preparing a first single crystal silicon wafer and a second single crystal silicon wafer having a (100) plane as a main surface, and at least one surface of the second single crystal silicon wafer. Forming a first insulating film, bonding a main surface of the first single crystal silicon wafer and a first insulating film forming surface of the second single crystal silicon wafer to form an SOI substrate, Forming a first element isolation region and a gate electrode on a main surface of the single-crystal silicon wafer, wherein the SOI substrate has a first orientation on the main surface of the first single-crystal silicon wafer and the second orientation. The single crystal silicon wafer is formed by being bonded so as to overlap the second orientation on the main surface thereof and is parallel to one side of the gate electrode and one side of the gate electrode in the first element isolation region. Are those formed to be parallel or perpendicular to the second orientation of the second monocrystalline silicon wafer.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) As shown in FIG. 1, the SOI substrate of the present embodiment 1 has a crystal plane orientation of (10
0) plane, and the orientation in which the notch 1A is formed is <011.
> Direction (first direction), the thickness of which is approximately 500 μm
Base substrate 2A made of 800 μm single crystal silicon
(1st single-crystal silicon wafer) and single-crystal silicon having the same crystal plane orientation of the main surface as that of base substrate 2A, and the orientation in which notch 1B is formed is <010> orientation (second orientation). It is formed by bonding a bond substrate 2B (second single crystal silicon wafer). FIG.
The solid and dashed arrows in the middle indicate the directions.

After preparing the base substrate 2A and the bond substrate 2B shown in FIG. 1, as shown in FIG. 2, a silicon oxide film 3A (first
(Insulating film). Subsequently, the notch 1A formed on the base substrate 2A and the notch 1 formed on the bond substrate 2B are formed.
The main surface of the base substrate 2A and the back surface (the surface on which the first insulating film is formed) of the bond substrate 2B are bonded so that B overlaps. In other words, the <011> directions of the base substrate 2A and the bond substrate 2B are staggered by 45 ° and bonded together. This 45 ° includes a bonding error caused by a manufacturing apparatus used for bonding. Note that FIG.
FIG. 2B is a cross-sectional view of a main part along line AA in FIG.

Thereafter, as shown in FIG. 3, the bond substrate 2B is polished using, for example, a surface grinder, and then the bond substrate 2B is polished by a chemical mechanical polishing (CMP) method. SOI substrate 2 of Embodiment 1 can be obtained. At this time, the silicon oxide film 3A and the single crystal silicon included in the bond substrate 2B become the BOX layer 3 and the SOI layer 4 of the SOI substrate 2, respectively. By the above-mentioned polishing, the SOI layer 4
Can be formed in a desired thickness, and the first embodiment exemplifies that the thickness is about 1 to 2 μm.

On the (100) plane of the above-mentioned single crystal silicon, different strain stresses are generated between the base substrate 2A and the SOI layer 4 because the elastic modulus differs depending on the orientation. Therefore, the strain stress generated at the BOX layer 3 between the base substrate 2A and the SOI layer 4 and at the interface thereof can be increased. That is, the gettering ability of the BOX layer 3 can be improved as compared with a case where the <011> directions of the base substrate 2A and the bond substrate 2B are matched with each other. Thus, in the semiconductor integrated circuit device manufactured using the SOI substrate 2 of the first embodiment, it is possible to prevent deterioration of electric characteristics such as reduction of leak current.

If the <011> directions of the base substrate 2A and the bond substrate 2B are staggered by 45 °, the SOI substrate 2 has a symmetrical crystal structure. Here, when considering only increasing the strain stress generated in the BOX layer 3 between the base substrate 2A and the SOI layer 4, the <011> orientation of each of the base substrate 2A and the bond substrate 2B is shifted by several degrees. Even if they are bonded together, different strain stresses can be generated between the base substrate 2A and the SOI layer 4. That is, the gettering ability of the BOX layer 3 can be improved even if the <011> directions of the base substrate 2A and the bond substrate 2B are shifted by several degrees.

The semiconductor integrated circuit device of the first embodiment manufactured using the SOI substrate 2 is, for example, a CMOS logic LSI 10 as shown in FIG.

In the SOI layer 4 of the SOI substrate 2, a p-type well 11 and an n-type well 12 are formed. An element isolation groove 13 (first element isolation region) is formed in the element isolation region of the p-type well 11 and the n-type well 12. The p-type well 11 and the n-type well 12 are separated by a U-groove element isolation region 14 formed from a silicon oxide film.

In the active region of the p-type well 11, a plurality of n-channel MISFETs Qn are formed.
In the active region of the mold well 12, a plurality of p-channel MISFETs Qp are formed. n-channel type MI
The SFET Qn mainly includes a gate oxide film 15, a gate electrode 16, and an n-type semiconductor region (source, drain) 17
The p-channel MISFET Qp mainly has a gate oxide film 15, a gate electrode 16, and a p-type semiconductor region (source, drain) 18.

Above the n-channel MISFET Qn and the p-channel MISFET Qp, a first layer wiring 21, a second layer wiring 22 and a third layer wiring 23 are formed in order from the bottom. These wirings are made of metal such as Al (aluminum) alloy or W (tungsten).

The above-mentioned first layer wiring 21 to third layer wiring 23
Of the n-channel MISFET Qn or the p-channel MISFET Qn through a through hole 26 formed in an interlayer insulating film 25 made of silicon oxide or the like.
It is electrically connected to the SFET Qp. The first layer wiring 21 to the third layer wiring 23 are electrically connected to each other through a through hole 26 formed in the interlayer insulating film 25.

The CMOS logic LSI 10 shown in FIG.
As shown in FIG. 5A, the gate electrode 1 of the CMOS logic LSI 10 is formed on the SOI substrate 2.
6, a side parallel to one side of the gate electrode 16 of the element isolation trench 13 is parallel to the <010> direction of the SOI layer 4,
Alternatively, as shown in FIG.
> Formed perpendicular to the azimuth. The maximum stress of the element structure is <010> with respect to the crystal orientation <011>.
Since it occurs in the azimuth, the occurrence of crystal defects can be suppressed as compared with the case where the rectangle of the semiconductor element is formed in the <011> azimuth. In addition, since the semiconductor element is formed in the <010> direction, carrier mobility can be improved.

Here, one side of the gate electrode 16 and a side parallel to one side of the gate electrode 16 of the element isolation groove 13 are formed parallel or perpendicular to the <011> direction of the base substrate 2A. In addition, base substrate 2A made of single crystal silicon is easily scribed and cleaved along the <011> direction. Further, as described with reference to FIG. 3, the thickness of the base
Since the thickness of the SOI layer 4 is relatively larger than the combined thickness, the scribe and cleavage of the SOI substrate 2 are performed in the <011> direction of the base substrate 2A (<011 of the SOI layer 4).
> Azimuth). That is,
The longitudinal direction of the gate electrode 16 and the element isolation groove 1
The observation surface (cross section) perpendicular or parallel to the side parallel to one side of the third gate electrode 16 can be easily obtained.

Next, a method of manufacturing the CMOS logic LSI 10 configured as described above will be described with reference to FIGS.

First, as shown in FIG. 6, an element isolation groove 13 is formed on the main surface of the SOI substrate 2. This element isolation groove 13
Can be formed by embedding an insulating film such as silicon oxide in a groove formed by etching the SOI layer 4.

Next, the BOX layer 3 is formed on the main surface of the SOI substrate 2.
Is formed, and then, for example, a silicon oxide film is deposited, and then a CMP (Chemical Mechanical Polish)
ing) The excess silicon oxide film is removed using a method or the like, and the silicon oxide film is buried in the U-groove to form the U-groove element isolation region 14.

Subsequently, a p-type well 11 and an n-type well 12 are formed. The p-type well 11 is formed by ion-implanting P (phosphorus) into a part of the SOI layer 4 and n-type.
The mold well 12 can be formed by ion-implanting B (boron) into another part of the SOI layer 4.

Next, as shown in FIG. 7, a gate oxide film 15 is formed on the surfaces of the p-type well 11 and the n-type well 12 by subjecting the SOI substrate 2 to a heat treatment. A gate electrode 16 is formed. The gate electrode 16 is formed of, for example, a three-layer conductive film in which a P-doped low-resistance polycrystalline silicon film, a WN (tungsten nitride) film, and a W (tungsten) film are stacked in this order. Subsequently, P or As is added to the p-type well 11.
N-type semiconductor region 1 by ion implantation of (arsenic)
7 (source, drain) 17 are formed, and the n-type well 12 is formed.
B is ion-implanted to form a p-type semiconductor region (source, drain) 18. By the steps up to this point, the p-type well 11 has the n-channel MISFET Qn
Is formed, and a p-channel type MISFE is formed in the n-type well 12.
TQp is formed.

Next, as shown in FIG.
An n-type semiconductor region (source, drain) 1 is formed by forming an interlayer insulating film 25 over the ISFET Qn and the p-channel type MISFET Qp and then dry-etching the interlayer insulating film 25 using a photoresist film as a mask.
After a through-hole 26 is formed above the P-type semiconductor region 7 and the p-type semiconductor region (source and drain) 18, a first layer wiring 21 is formed above the interlayer insulating film 25. The interlayer insulating film 25
For example, it is formed by depositing a silicon oxide film by a CVD method. For the first layer wiring 21, for example, a metal film such as W or an Al alloy is deposited on the interlayer insulating film 25 by sputtering, and then the metal film is patterned by dry etching using a photoresist film as a mask. It forms by doing.

Subsequently, the process shown in FIG. 8 is repeated a plurality of times to obtain the second layer wiring 22 and the third layer wiring 2.
3 are sequentially formed to manufacture the CMOS logic LSI 10 of the first embodiment. The CMO of the first embodiment
Although the case where the S logic LSI 10 has three wiring layers has been described, the number of wiring layers is not limited to three.

(Embodiment 2) In Embodiment 2, the element formation surface (principal surface) of the bond substrate 2B described in Embodiment 1 with reference to FIG. 1 is inclined from the (100) plane. A bond substrate is used. Other members are the same as those in the first embodiment, and a description of those same members will be omitted.

FIG. 9 is a plan view and a sectional view showing a bond substrate 2C (second single crystal silicon wafer) included in the SOI substrate of the second embodiment.

FIG. 9B is a sectional view taken along line BB in FIG. 9A. (100) of the bond substrate 2B
Assuming that the normal on the surface is n, the bond substrate 2C of the second embodiment has a normal <n
> It is inclined about 4 ° to the azimuth. In addition, the bond substrate 2
In C, the orientation in which the notch 1C is formed is <010
> Azimuth. Here, the normal line n shown in FIG.
Is a component horizontal to the element formation surface of the bond substrate 2 at the normal line n shown in FIG. 9B. Further, in the second embodiment, the case where the normal n is inclined by about 4 ° in the <010> direction with respect to the normal of the element formation surface is illustrated, but the present invention is not limited to 4 °. Furthermore, the component of the normal line n that is horizontal to the element formation surface of the bond substrate 2 may be within an angle of about 35 ° around the <010> direction.

As shown in FIG. 9A, the bond substrate 2C
In, the orientation in which the notch 1C is formed is the <010> orientation. Therefore, the inclination of the normal line n is notch 1
It becomes symmetric about the <010> direction in which C is formed. That is, the four directions including the notch 1C ([011], [0-1]
1], [01-1] and [0-1-1]) are equivalent. However, for example, the notch 1C is oriented in the [011] direction,
When the normal n is formed so as to be inclined in the [0-11] direction or the [01-1] direction, there is the convenience that it is not necessary to distinguish between the front and back during the manufacturing. In addition, the above-mentioned -1 means being on the opposite side of the origin with respect to 1, and means the same symbol as the bar above the character which is a scientific code.

Next, referring to FIG.
A method for manufacturing an OI substrate will be described.

First, the bond substrate 2C is formed by the same steps as those described with reference to FIG.
After forming a silicon oxide film 3A (first insulating film) on the surface of the base substrate 2A and the bond substrate 2C, the notch 1A formed on the base substrate 2A and the notch 1C formed on the bond substrate 2C overlap. to paste together. That is, the <011> directions of the base substrate 2A and the bond substrate 2B are staggered by 45 ° and bonded together. Note that FIG. 10B is a diagram illustrating the AA in FIG.
It is principal part sectional drawing in a line.

Subsequently, the bond substrate 2C is formed by the same steps as those described with reference to FIG.
Is polished to obtain the SOI substrate of the second embodiment.

In the SOI substrate of the second embodiment formed as described above, the structure of FIG.
As in the case of the SOI substrate 2 described with reference to FIG.
Different strain stresses occur between A and the SOI layer composed of the bond substrate 2C. Therefore, the base substrate 2A and its SO
The strain stress generated in the BOX layer between the BOX layer and the I layer can be increased. That is, the gettering ability of the BOX layer can be improved as compared with the case where the <0-1-1> directions of the base substrate 2A and the bond substrate 2C are matched with each other. Thereby, in the semiconductor integrated circuit device manufactured using the SOI substrate of the second embodiment, it is possible to prevent the deterioration of the electrical characteristics.

In the SOI substrate of the second embodiment, the element formation surface of the bond substrate 2C is inclined by about 4 ° with respect to the (100) plane. Therefore, the stress applied to the single-crystal silicon forming the SOI layer from each element formed on the element formation surface of the SOI substrate can be reduced as compared with the SOI substrate 2 of the first embodiment. That is, in the SOI substrate according to the second embodiment, generation of crystal defects in the SOI substrate can be suppressed more effectively than in the SOI substrate 2 according to the first embodiment. Further, in the SOI substrate of the second embodiment, since the rectangle of the semiconductor element can be formed in the <100> direction, it is possible to improve the mobility of the carriers as compared with the SOI substrate 2 of the first embodiment. .

(Embodiment 3) FIG. 11 is a sectional view showing a main part of a semiconductor integrated circuit device according to Embodiment 3 of the present invention.

The semiconductor integrated circuit device of the third embodiment is
A DRAM (Dynamic Random Access Memory) is formed on the element formation surface (main surface) of the SOI substrate of the first and second embodiments.

In a part of the p-type well 11 formed in the SOI layer 4, a memory selection MISFET Qs constituting a memory cell of the DRAM is formed, and in another part, an n-channel MISFET Qn of a peripheral circuit is formed. Are formed. In the n-type well 12 formed in the SOI layer 4, a p-channel MISFET Qp of a peripheral circuit is formed. MISFET Qs for memory selection, n-channel type M
ISFET Qn and p-channel MISFET Qp
Are separated from each other by an element isolation groove 13 and a U-groove element isolation region 14.

The memory selection MISFET Qs and the n-channel MISFET Qn are mainly composed of a pair of n-type semiconductor regions (source, drain) formed in the p-type well 11.
17, a gate oxide film 15 formed on the surface of the p-type well 11, and a gate electrode 16 formed on the gate oxide film 15. p-channel type MISFE
TQp is mainly formed of a pair of p-type semiconductor regions (source and drain) 18 formed in n-type well 12, gate oxide film 15 formed on the surface of n-type well 12, and formed on gate oxide film 15. And the gate electrode 16 formed. The gate electrode 16 is composed of a polycide film in which a W (tungsten) silicide film is laminated on an n-type polycrystalline silicon film.

Bit lines BL1 and BL2 are formed above the memory cell selecting MISFET Qs, and the p-channel type MISFET Qp and the n-channel type
A first layer wiring 21 is formed above each of the SFETs Qn. An information storage capacitor C including a lower electrode 31, a capacitor insulating film 32, and an upper electrode 33 is formed above the bit lines BL1 and BL2.
A second layer wiring 23 is formed.

In the DRAM of the third embodiment, similarly to the CMOS logic LSI 10 described in the first embodiment with reference to FIGS. 4 and 5, the longitudinal direction of each element is the <010> direction of the SOI layer 4. Are formed in parallel or perpendicular to. Therefore, generation of crystal defects in the SOI substrate can be suppressed.

According to the third embodiment, the DRAM is formed by using the SOI substrate having the improved gettering ability shown in the first or second embodiment, so that the third embodiment has The leakage current of the DRAM can be suppressed. That is, since the leak current can be suppressed, the refresh characteristics of the DRAM of the third embodiment can be improved.

(Embodiment 4) FIG. 12 is a cross-sectional view showing a main part of a semiconductor integrated circuit device according to Embodiment 4 of the present invention.

The semiconductor integrated circuit device of the fourth embodiment is
A flash memory (EEPROM) is formed on the element formation surface (main surface) of the SOI substrate according to the first and second embodiments.

In a part of the p-type well 11 formed in the SOI layer 4, an n-channel MISFET Qm forming a memory cell of a flash memory (EEPROM) and an n-channel MISFET Qt forming a transfer MISFET are provided.
Are formed, and an n-channel MISFET Qn of a peripheral circuit is formed in another part. The memory cell is of an AND type, and its drain region is provided with a transfer MI.
Source of SFET (n-channel type MISFETQt),
It is electrically connected to the data line 21i via a drain path.

In the n-type well 12 formed in the SOI layer 4, a p-channel MISFET Qp of a peripheral circuit is formed. N-channel MISFET Qm, n-channel MISFET Qn and p-channel MISFE
TQp is applied to the surface of the SOI layer 4 by LOCOS (Local Oxid
field oxide film 35 formed by the ation of Silicon) method
(First element isolation region) and U-groove element isolation region 14.

Memory cell n-channel MISFET Q
m denotes a pair of n-type semiconductor regions (source and drain) 17 formed mainly in the p-type well 11 and the p-type well 1
1, a gate oxide film 15 formed on the gate oxide film 15, a second gate oxide film 36 formed on the gate electrode 16, and a second gate oxide film 36 formed on the gate electrode 16. It comprises a control gate 37 formed on the oxide film 36. The n-channel MISFET Qn of the peripheral circuit mainly includes a pair of n-type semiconductor regions (source and drain) 17 formed in the p-type well 11, a gate oxide film 15 formed on the surface of the p-type well 11, And a gate electrode 16 formed on the oxide film 15. p-channel type MI
The SFET Qp mainly includes a pair of p-type semiconductor regions (source and drain) 18 formed in the n-type well 12 and n
A gate oxide film 15 formed on the surface of the mold well 12;
And a gate electrode 16 formed on the gate oxide film 15.

Memory cell n-channel MISFET Q
A first layer wiring 21 is formed above m, and a second layer wiring 22 is further formed thereon. Peripheral circuit p-channel MISFET Qp and n-channel M
A first layer wiring 21 is formed on each of the ISFETs Qn, and a second layer wiring 22 is further formed thereon.
Are formed.

The flash memory according to the fourth embodiment (EE
PROM) in the first embodiment shown in FIG.
Logic LSI1 described with reference to FIG.
0, the longitudinal direction of each element is <010
> Formed parallel or perpendicular to the azimuth. Therefore, generation of crystal defects in the SOI substrate can be suppressed. That is, the reliability and yield of the flash memory (EEPROM) according to the fourth embodiment can be improved.

(Embodiment 5) FIG. 13 is a cross-sectional view showing a main part of a semiconductor integrated circuit device according to Embodiment 5 of the present invention.

The semiconductor integrated circuit device according to the fifth embodiment has
An SRAM (Static Random Access MRAM) is formed on the element formation surface (principal surface) of the SOI substrate according to the first or second embodiment.
emory). The memory cell of this SRAM is formed in an active region surrounded by a field insulating film 17 on the main surface of the SOI layer 4. Of the six MISFETs forming the memory cell, a pair of n-channel driving MISFETs and a pair of transfer MISFETs
The SFET is formed in an active region of the p-type well 11, and a pair of p-channel type load MISFETs is formed above the driving MISFET.

The pair of transfer MISFETs are p-type well 1
N ⁺ type semiconductor region 39 and n ⁻ type semiconductor region (source, drain) 40 (semiconductor element) formed in one active region, and gate oxide film 41 made of a silicon oxide film formed on the surface of this active region And the gate oxide film 41
And a gate electrode 42 (semiconductor element) made of polycide formed thereon. The gate electrode 42 of the transfer MISFET is formed integrally with the word line.

The pair of driving MISFETs includes an n ⁺ -type semiconductor region 39 and an n ⁻ -type semiconductor region (source, drain) 43 (semiconductor element) formed in the active region of the p-type well 11, and a surface of the active region. A gate oxide film 44 made of a silicon oxide film formed on
Gate electrode 4 made of polycrystalline silicon formed on 4
5 (semiconductor element).

The pair of load MISFETs includes a driving MI
A gate electrode 46 (semiconductor element) made of polycrystalline silicon formed on the SFET; a gate oxide film 47 formed on the gate electrode 46; and a polycrystalline silicon formed on the gate oxide film 47 And a p-type semiconductor region (source, drain) 48 (semiconductor element).

Reference numeral 49 denotes a p-type channel stopper layer, Vcc denotes a power supply line, Vss denotes a GND line, DL denotes a data line, and 50 to 52 denote first-layer metal wirings.

In the SRAM of the fifth embodiment, like the CMOS logic LSI 10 described in the first embodiment with reference to FIGS. 4 and 5, the longitudinal direction of each element is the <010> direction of the SOI layer 4. Are formed in parallel or perpendicular to. Therefore, generation of crystal defects in the SOI substrate can be suppressed. That is, the reliability and yield of the SRAM of the fifth embodiment can be improved.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

For example, in the above embodiment, S
Although the case where the notch is formed in the OI substrate has been illustrated, an orientation flat (OF) may be used instead of the notch.

[0068]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) With the (100) plane as the main surface, <011 of the base substrate
The BOX is formed by forming an SOI substrate bonded so that the> orientation and the <010> orientation of the bond substrate match.
Increases the strain generated at the layer and its interface. As a result, the gettering ability of the SOI substrate can be improved. (2) Since the gettering ability of the SOI substrate can be improved, deterioration of the electrical characteristics of the semiconductor integrated circuit device can be prevented. (3) By forming one side of each element of the semiconductor integrated circuit device parallel or perpendicular to the <010> direction of the SOI layer, generation of crystal defects in the SOI substrate can be suppressed.

[Brief description of the drawings]

FIG. 1 is a plan view of a main part of a base substrate and a bond substrate forming an SOI substrate of a semiconductor integrated circuit device according to an embodiment of the present invention.

2A is a plan view illustrating a method for manufacturing the SOI substrate in FIG. 1, and FIG. 2B is a cross-sectional view taken along line AA in FIG.

3 is a fragmentary cross-sectional view of the SOI substrate during a manufacturing step following that of FIG. 2;

FIG. 4 is a sectional view of a main part of a CMOS logic LSI according to an embodiment of the present invention;

FIGS. 5A and 5B are plan views showing the relationship between the crystal orientation of the base substrate and the SOI layer in the SOI substrate according to the embodiment of the present invention and the longitudinal orientation of the CMOS logic LSI; is there.

6 is a fragmentary cross-sectional view showing the method of manufacturing the CMOS logic LSI shown in FIG. 4;

7 is a fragmentary cross-sectional view of the CMOS logic LSI during a manufacturing step following that of FIG. 6;

8 is a fragmentary cross-sectional view of the CMOS logic LSI during a manufacturing step following that of FIG. 7;

9A is a plan view of a bond substrate included in an SOI substrate of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 9B is a cross-sectional view taken along line BB of FIG. It is.

FIG. 10A is a plan view illustrating a method for manufacturing an SOI substrate of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 10B is a cross-sectional view taken along line AA of FIG. It is.

FIG. 11 is a fragmentary cross-sectional view of a DRAM according to another embodiment of the present invention;

FIG. 12 is a sectional view of a main part of a flash memory (EEPROM) according to another embodiment of the present invention;

FIG. 13 shows an SRA according to still another embodiment of the present invention.
It is principal part sectional drawing of M.

[Explanation of symbols]

1A notch 1B notch 1C notch 2 SOI substrate 2A base substrate (first single crystal silicon wafer) 2B bond substrate (second single crystal silicon wafer) 2C bond substrate (second single crystal silicon wafer) 3 BOX layer 3A silicon oxide film ( 1st insulating film) 4 SOI layer 10 CMOS logic LSI 11 p-type well 12 n-type well 13 device isolation groove (first device isolation region) 14 U-groove device isolation region 15 gate oxide film 16 gate electrode (semiconductor device) 17 n Type semiconductor region (source, drain (semiconductor element)) 18 p-type semiconductor region (source, drain (semiconductor element)) 21 first layer wiring 21i data line 22 second layer wiring 23 third layer wiring 25 interlayer insulating film 26 through Hole 31 Lower electrode 32 Capacitive insulating film 33 Upper electrode 35 Field insulating film (first element) Isolation region) 36 second gate oxide film 39 n ⁺ -type semiconductor region 40 n ^- -type semiconductor region (source, drain (semiconductor device)) 41 gate oxide film 42 gate electrode (semiconductor element) 43 n ^- -type semiconductor region (source, Drain (semiconductor element) 44 Gate oxide film 45 Gate electrode (semiconductor element) 46 Gate electrode (semiconductor element) 47 Gate oxide film 48 p-type semiconductor region 48 (source, drain (semiconductor element)) 49 Channel stopper layer 50 to 52 Metal wiring BL1 Bit line BL2 Bit line C Information storage capacitor DL Data line n Normal Qm n-channel MISFET Qn n-channel MISFET Qp p-channel MISFET Qs MISFET for memory selection Qt n-channel MISFET Vcc Power supply line Vss GND line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/762 H01L 27/10 621B 21/8242 671C 21/8244 381 21/8247 434 27/08 331 29 / 78 371 27/108 627D 27/11 21/76 D 27/115 29/786 29/788 29/792 (72) Inventor: Kazuyuki Parkawa 1-280, Higashi-Koigabo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. 72) Inventor Naoyuki Kawai 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5F032 AA06 BA08 BB01 CA17 DA22 DA71 DA78 5F048 AC03 BA16 BB06 BB09 BC06 BE03 BF02 BF12 BG01 BG13 DA24 5F083 AD48 AD56 BS05 BS29 EP02 EP23 EP33 EP79 HA02 JA35 JA36 JA39 JA53 NA01 PR40 5F101 BA07 BB05 BD34 5F110 AA01 AA06 BB04 BB06 BB07 BB08 CC02 DD05 DD13 EE0 1 EE04 EE05 EE09 EE15 FF02 FF23 GG02 GG12 GG17 GG32 GG52 HJ01 HJ13 HL04 HL23 NN03 NN23 NN35 NN62 NN65 NN72 QQ11 QQ28

Claims (5)

[Claims] 1. A step of preparing a first single crystal silicon wafer and a second single crystal silicon wafer having a (100) plane as a main surface, and (b) at least one of the second single crystal silicon wafers. Forming a first insulating film on the surface; and (c) bonding the main surface of the first single crystal silicon wafer and the first insulating film forming surface of the second single crystal silicon wafer to form an SOI substrate. In the step (c), the first orientation on the main surface of the first single-crystal silicon wafer and the second orientation on the main surface of the second single-crystal silicon wafer are overlapped. Of manufacturing a semiconductor integrated circuit device. 2. A step of preparing a first single-crystal silicon wafer and a second single-crystal silicon wafer having a (100) plane as a main surface, and (b) at least one of the second single-crystal silicon wafers. Forming a first insulating film on the surface; and (c) bonding the main surface of the first single crystal silicon wafer and the first insulating film forming surface of the second single crystal silicon wafer to form an SOI substrate. In the step (c), the first orientation on the main surface of the first single-crystal silicon wafer and the first orientation on the main surface of the second single-crystal silicon wafer are staggered by a predetermined angle. A method for manufacturing a semiconductor integrated circuit device. 3. (a) a step of preparing a first single crystal silicon wafer having a (100) plane as a main surface, (b) (100)
Preparing a second single-crystal silicon wafer whose main surface is a surface inclined at a predetermined angle from the surface; (c) forming a first insulating film on at least one surface of the second single-crystal silicon wafer; (D) bonding a main surface of the first single-crystal silicon wafer to a first insulating film forming surface of the second single-crystal silicon wafer to form an SOI substrate; The normal in the (100) plane is inclined at a predetermined angle to an azimuth within a predetermined angle centered on the second azimuth with respect to the normal to the main surface of the second single crystal silicon wafer; In the above, the first
A method for manufacturing a semiconductor integrated circuit device, wherein a first orientation on a main surface of a single crystal silicon wafer and a second orientation on a main surface of the second single crystal silicon wafer are overlapped. 4. A step of preparing a first single-crystal silicon wafer and a second single-crystal silicon wafer having a (100) plane as a main surface, and (b) at least one of the second single-crystal silicon wafers. Forming a first insulating film on the surface; and (c) bonding the main surface of the first single crystal silicon wafer and the first insulating film forming surface of the second single crystal silicon wafer to form an SOI substrate. (D) forming a first element isolation region and a gate electrode on a main surface of the second single-crystal silicon wafer; The first direction in the plane and the second direction in the main surface of the second single crystal silicon wafer overlap each other, and one side of the gate electrode and a side parallel to one side of the gate electrode in the first element isolation region are: Previous A method of manufacturing a semiconductor integrated circuit device, wherein the second single crystal silicon wafer is formed so as to be parallel or perpendicular to the second orientation. 5. A step (a) of preparing a first single crystal silicon wafer having a (100) plane as a main surface, and (b) (100).
A step of preparing a second single-crystal silicon wafer whose main surface is a surface inclined at a predetermined angle from the surface; (c) a step of forming a first insulating film on at least the back surface of the second single-crystal silicon wafer; d) bonding the main surface of the first single-crystal silicon wafer to the back surface of the second single-crystal silicon wafer to form an SOI substrate; (e) forming a SOI substrate on the main surface of the second single-crystal silicon wafer; Forming a first element isolation region and a gate electrode, wherein the normal to the (100) plane of the second single crystal silicon wafer is the second
With respect to the normal to the main surface of the single-crystal silicon wafer, it is inclined at a predetermined angle to an azimuth within a predetermined angle around the second azimuth, and in the step (d), the main surface of the first single-crystal silicon wafer is The first direction in the plane and the second direction in the main surface of the second single crystal silicon wafer overlap each other, and one side of the gate electrode and a side parallel to one side of the gate electrode in the first element isolation region are: A method for manufacturing a semiconductor integrated circuit device, wherein the second single crystal silicon wafer is formed so as to be parallel or perpendicular to the second orientation.