JP2002369520A - Power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent overvoltage from being applied to a switching element and to attain high power conversion efficiency. SOLUTION: An excitation current, passed through the primary winding 15p of a transformer 15, is subjected to switching control using a switching element 20 for obtaining a desired output voltage on the secondary winding 15s side of the transformer. If an excitation current induced voltage produced at the transformer is superposed on an input direct-current voltage Vin and applied, it is detected, using a comparator 52 as to whether the voltage between the terminals of the switching element 20 exceeds a specified voltage. A switching element 42, comprising a snubber circuit, is brought into conduction to perform clamp operation on the voltage between terminals, only during the period when the voltage between terminals is detected as exceeding the specified voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a power converter. More specifically, the clamp operation of the terminal voltage is performed only when the terminal voltage of the switch element that controls the switching of the exciting current flowing through the primary winding of the transformer exceeds a predetermined voltage.

[0002]

2. Description of the Related Art In a power converter for performing power conversion by performing a switching operation of a switching element, for example, a switching converter, switching is performed to suppress noise generated by the switching element and to eliminate a limit to a higher frequency due to an increase in switching loss. The development of a switching converter using a resonance mode by an inductor and a capacitor during a transition period is in progress.

FIG. 8 shows a configuration of a conventional voltage resonance type switching converter. The AC voltage from the commercial AC power supply 10 is rectified by the diode bridge 11 and converted into a DC voltage, and is also smoothed by the capacitor 12, and is input to one terminal 15p1 of the primary winding 15p of the transformer 15 as the input DC voltage Vin. Supplied. Primary winding 1
The other terminal 15p2 of 5p is connected to the drain of the field effect transistor 20 as a switch element and the resonance capacitor 21, and the source of the field effect transistor 20 and the other end of the resonance capacitor 21 are grounded. In the field effect transistor 20, a parasitic diode is formed between the drain and the source.

[0004] One terminal 15s1 of the secondary winding 15s of the transformer 15 is connected to the anode of the rectifying diode 31, and the other terminal 15s2 is grounded. A smoothing capacitor 32 and a load 35 are connected to the cathode of the diode 31, and a secondary winding 15 s
Is rectified and smoothed and applied to the load 35, whereby power is supplied to the load 35.

An error amplifier 36 is connected to the cathode of the diode 31 and the error amplifier 3
Reference numeral 6 is connected to a reference voltage generator 37 for setting a DC voltage level of power supplied to the load 35. The error amplifier 36 generates an error signal EV indicating a voltage difference between the DC voltage Va of the power supplied to the load 35 and the reference voltage Vrf supplied from the reference voltage generation unit 37, and via the photocoupler 38. The error signal EV is supplied to the main drive unit 25.

The main drive unit 25 generates a drive signal DR for switchingly driving the field effect transistor 20 and supplies the drive signal DR to the gate of the field effect transistor 20. The error switching operation frequency is varied while keeping the off-period Toff of the field-effect transistor 20 substantially constant so that the voltage difference from Vrf is eliminated.

As described above, when the field effect transistor 20 is switched, the primary winding 1 of the transformer 15 is driven.
A pulse voltage, which is an exciting current induced voltage, is generated at 5p, and a pulse voltage is also induced in the secondary winding 15s by the transformer coupling. The pulse voltage induced in the secondary winding 15s is rectified by the diode 31 as described above, is smoothed by the capacitor 32, and is supplied to the load 35 as a DC voltage.

FIG. 9 shows a signal waveform in the field-effect transistor 20. When the drive signal DR shown in FIG. 9A is supplied to the gate, a pulse voltage which is an exciting current induced voltage is superimposed on the input DC voltage Vin. A voltage is supplied to the field effect transistor 20 and the field effect transistor 2
Since the resonance capacitor 21 is connected in parallel to 0, the drain-source voltage Vds becomes a half-sine smooth waveform of a sine wave as shown in FIG. 9B. Therefore, generation of noise due to the switching operation of the field effect transistor 20 can be suppressed. Also, the drain current Id is as shown in FIG. 9C, and since the voltage of the drain-source voltage Vds at the time of switching of the field effect transistor 13 is small, the overlap between the voltage waveform and the current waveform is reduced, so that the switching loss is also large. Can be suppressed.

However, the voltage V between the train and the source is
The peak value Lm of ds is expressed by the equation (1). If the voltage level of the input DC voltage Vin is high or the on-period Ton of the field-effect transistor 20 is long, that is, the load 35 , The peak value Lm increases. Lm = 2π (1 + Ton / Toff) Vin (1)

As described above, since the peak value Lm increases, the field effect transistor 20 needs to have a high breakdown voltage. However, field-effect transistors with a high breakdown voltage are few and expensive. Further, when a bipolar transistor is used as the switch element, the switching time of the bipolar transistor having a high withstand voltage becomes slow, and the frequency cannot be increased.

Therefore, as shown in FIG. 10, a capacitor 41 is connected in parallel with the primary winding 15p of the transformer 15.
A so-called switch snubber circuit is provided which provides a field effect transistor 42 which is a sub-switch element connected in series with the circuit, and performs overvoltage protection by switching the field effect transistor 42.

FIG. 11 shows a signal waveform of the field effect transistor 20 and a signal waveform of the field effect transistor 42 constituting the switch snubber circuit. The main drive unit 25a not only generates the drive signal DR shown in FIG. 11A supplied to the gate of the field-effect transistor 20, but also supplies a reference signal SR synchronized with the drive signal DR to the sub-drive unit 40. In the sub-drive unit 40, based on the reference signal SR,
FIG. 1 in which the phase is shifted by a predetermined time with respect to the drive signal DR
The driving signal DS shown in FIG.
And the switching of the field effect transistor 42 is performed. At this time, the field effect transistor 2
As shown in FIG. 11B, the drain-source voltage Vds of 0 can be limited to the voltage level Lsw when the field-effect transistor 42 is turned off. That is, since the voltage level when the field effect transistor 42 is turned off by the capacitor 41 is held, the voltage Vds between the drain and the source of the field effect transistor 20 becomes the voltage when the field effect transistor 42 is turned off. When the level becomes higher than the level Lsw, the capacitor 41 is charged through the parasitic diode of the field effect transistor 42. Therefore, the drain-source voltage Vds of the field effect transistor 20 is limited to the voltage level Lsw when the field effect transistor 42 is turned off. 11C shows the drain current Id of the field-effect transistor 20, and FIGS. 11E and 11F show the drain-source voltage Vdsb and the drain current Idb of the field-effect transistor 42.

[0013]

In the case where the peak value Lm of the drain-source voltage Vds of the field-effect transistor 20 is reduced by always performing the switching operation of the field-effect transistor 42, An invalid switching loss always occurs in the field effect transistor 42 when is turned on, turned off, and conducted.

When the load current is increased while the input DC voltage Vin is kept constant when the above-described snubber circuit is provided, the on-period Ton of the field-effect transistor 20 becomes longer. The number of operations is reduced and the field effect transistor 2
The current flowing to 0 increases. Therefore, as shown in FIG. 12A, as the load current increases, the loss caused by the switching operation of the field-effect transistor 20 (hereinafter, referred to as “main switch loss”) increases, and the relationship between the load current and the switching loss increases. The loss caused by the switching operation of the effect transistor 42 (hereinafter referred to as “sub-switch loss”) is reduced.

On the other hand, when no snubber circuit is provided,
When the load current is increased while the input DC voltage Vin is kept constant, the ON period Ton of the field effect transistor 20 becomes longer, so that the current flowing through the field effect transistor 20 increases. In addition, since the voltage between the drain and the source of the field effect transistor 20 is not suppressed, the relationship between the load current and the switching loss is such that as the load current increases, the switching loss in the field effect transistor 20 increases as shown in FIG. 12B. Further, when a snubber circuit is not provided, a high withstand voltage product is used as the field-effect transistor 20, but the high withstand voltage product has a larger saturation voltage than a non-high withstand voltage element having the same current capacity, and has poor switching characteristics. The main switch loss of FIG.
Is greater than the main switch loss.

Here, when the load current is small, FIG.
When the sum of the main switch loss and the sub switch loss shown in FIG. 2A is larger than the main switch loss shown in FIG. 12B and the load current is large, the sum of the main switch loss and the sub switch loss shown in FIG. Is smaller than the main switch loss shown in FIG. That is, when the snubber circuit as described above is provided, invalid switching loss always occurs in the field effect transistor 42, and when the load current is small, the switching loss in the field effect transistor 42 is large. High power conversion efficiency cannot be obtained unlike a voltage resonance type switching converter that does not use a snubber circuit. Accordingly, the present invention provides a power converter that can prevent an overvoltage from being applied to a switch element and can obtain high power conversion efficiency.

[0017]

A power converter according to the present invention performs switching control of an exciting current flowing through a primary winding of a transformer using a switching element, so that a desired current is supplied from a secondary winding side of the transformer. An output voltage is obtained, and between the terminals of the switch element, in a power converter in which an exciting current induced voltage generated by a transformer is superimposed on the input DC voltage and applied, the voltage between the terminals of the switch element exceeds a predetermined voltage. And a voltage suppressing means for performing a clamp operation of the inter-terminal voltage during a period in which the inter-terminal voltage is detected to exceed the predetermined voltage by the detecting means.

According to the present invention, the exciting current flowing through the primary winding of the transformer is controlled by determining whether the voltage between the terminals of the switching element for switching control exceeds a predetermined voltage, or the voltage generated in the winding wound around the transformer. Is used to detect whether or not the voltage between the terminals of the switch element has exceeded a predetermined voltage.During a period in which the voltage between the terminals is detected to exceed the predetermined voltage, for example, a capacitor and a capacitor are connected in series. By making the sub-switch element of the snubber circuit formed of the sub-switch element conductive, the clamp operation of the inter-terminal voltage is performed.

[0019]

Next, an embodiment of a power converter according to the present invention will be described in detail. FIG. 1 shows a configuration of, for example, a voltage resonance type switching converter as a power converter. An AC voltage from a commercial AC power supply 10 is rectified by a diode bridge 11 and converted into a DC voltage, and is also smoothed by a capacitor 12 to be connected to one terminal 15p1 of a primary winding 15p of a transformer 15.
Supplied to The other terminal 15p2 of the primary winding 15p is connected to the drain of the field-effect transistor 20 as a switch element and to the resonance capacitor 21. The source of the field effect transistor 20 and the other end of the resonance capacitor 21 are grounded. Further, a terminal 15p2 of the primary winding 15p is connected via a resistor 51 to a non-inverting input terminal of a comparator 52 constituting detection means. The detecting means includes a comparator 52, a suppression start level setting unit 54 and a sub-driving unit 55 which will be described later. Further, a snubber circuit as a voltage suppressing means is provided in parallel with the primary winding 15p of the transformer 15. This snubber circuit is configured by connecting, for example, a capacitor 41 and a field-effect transistor 42 as a sub-switch element to the capacitor 41 in series.

The non-inverting input terminal of the comparator 52 is grounded via a resistor 53, and the suppression input level setting section 54 is connected to the inverting input terminal. The output terminal of the comparator 52 is connected to the sub-drive unit 55. In the suppression start level setting unit 54, the field-effect transistor 20
Start voltage Vrc for setting the level at which the clamp operation is started for the drain-source voltage Vds of
And supplies the clamp start voltage Vrc to the comparator 52. In the comparator 52, the resistors 51,
At 53, the voltage Vds between the drain and the source is divided and the voltage Vk supplied to the non-inverting input terminal and the clamp start voltage Vrc
Then, an output signal Sc indicating the result of the comparison is generated and supplied to the sub-drive unit 55. In the sub-drive unit 55, the comparator 52
The drive signal DT is generated based on the output signal Sc from the controller and supplied to the gate of the field effect transistor 42, whereby the field effect transistor 42 performs a switching operation in accordance with the drain-source voltage Vds.

One terminal 15s1 of the secondary winding 15s of the transformer 15 is connected to the anode of the rectifying diode 31, and the other terminal 15s2 is grounded. The cathode of the diode 31 has a smoothing capacitor 32 and a load 3
5 is connected, and the voltage induced in the secondary winding 15s of the transformer 15 is rectified and smoothed and applied to the load 35, so that power is supplied to the load 35.

An error amplifier 36 is connected to the cathode of the diode 31 and the error amplifier 3
Reference numeral 6 is connected to a reference voltage generator 37 for setting a DC voltage level of power supplied to the load 35. The error amplifier 36 generates an error signal EV indicating a voltage difference between the DC voltage Va of the power supplied to the load 35 and the reference voltage Vrf supplied from the reference voltage generation unit 37, and via the photocoupler 38. The error signal EV is supplied to the main drive unit 25. In the error amplifier 36, the load 3
An error signal EV indicating a voltage difference between a reference voltage Vrf and a voltage obtained by dividing the DC voltage Va of the power supplied to the power supply 5 is also generated.

The main drive section 25 generates a drive signal DR for switchingly driving the field effect transistor 20 and supplies the drive signal DR to the gate of the field effect transistor 20. The error switching operation frequency is varied while keeping the off-period Toff of the field-effect transistor 20 substantially constant so that the voltage difference from Vrf is eliminated.

In the thus-configured voltage-resonant type switching converter, when the field-effect transistor 20 is switched and driven, the primary winding 1 of the transformer 15
A pulse voltage which is an exciting current induced voltage is generated by the exciting current flowing through 5p. Also, a pulse voltage is induced in the secondary winding 15s by the transformer coupling, and this secondary winding 1
The pulse voltage induced at 5 s is rectified by the diode 31 and smoothed by the capacitor 32 and supplied to the load 35 as the DC voltage Va. Here, when the load current supplied to the load 35 increases,
The on-period Ton of the field-effect transistor 20 is increased so that the DC voltage Va does not decrease, and the above equation (1) is used.
As is clear from FIG. 7, the peak value Lm increases.

After the field effect transistor 20, which is a switching element, is turned off, the drain-source voltage Vds increases, and the voltage Vk supplied to the non-inverting input terminal of the comparator 52 becomes higher than the clamp start voltage Vrc. When it becomes larger, the output signal Sc becomes high level “H”. At this time, the sub drive unit 55 turns on the field effect transistor 42 by the drive signal DT.

Thereafter, the voltage applied between the drain and the source of the field effect transistor 20 is a frequency determined by the exciting inductance (not shown) of the transformer 15 and the capacitor 41 of the snubber circuit. Resonant until the voltage drops to Vrc, and the voltage V
When k decreases to the clamp start voltage Vrc, the sub-driving unit 55 based on the output signal Sc from the comparator 52
Transistor 42 according to drive signal DT from
Is turned off. When the field effect transistor 42 is turned off, the drain-source voltage Vds attenuates to a zero level with a time constant determined by the exciting inductance of the transformer 15 and the resonance capacitor 21.

Next, the operation when the load current is small and when the load current is large will be described with reference to FIGS. When the load current is small, the on-period Ton in the drive signal DR is short as shown in FIG. 2A, and the peak value Lm of the drain-source voltage Vds of the field-effect transistor 20 shown in FIG. The voltage level does not reach the voltage level Ls higher than Vrc. In this case, since the field effect transistor 42 is not turned on,
The switching loss in the field effect transistor 42 can be prevented. FIG. 2C shows the field effect transistor 2
0 shows the drain current Id.

When the load current is large, as shown in FIG. 3A, the ON period Ton in the drive signal DR becomes long.
At this time, the peak value Lm of the drain-source voltage Vds of the field-effect transistor 20 shown in FIG.
The voltage Vds between the drain and the source becomes the voltage level Ls at the time t1.
, The output signal Sc of the comparator 52 is set to the high level “H”, and the drive signal DT is output as shown in FIG. 3D.
Becomes high level "H", the field effect transistor 42 is turned on, the clamp operation is performed on the drain-source voltage Vds of the field effect transistor 20, and the voltage level is clamped at the level "Ls". afterwards,
When the voltage level of the drain-source voltage Vds becomes lower than the level Ls at the time point t2, the output signal Sc of the comparator 52 is set to the low level "L", and the drive signal DT is set to the low level "L" as shown in FIG. 3D. And the field effect transistor 42 is turned off. 3C shows the drain current Id of the field-effect transistor 20, and FIG. 3E shows the drain-source voltage Vd of the field-effect transistor 42.
dsb and FIG. 3F show the drain current Idb of the field effect transistor 42, respectively.

As described above, the drain-source voltage Vds
When the voltage level reaches the voltage level Ls, the field effect transistor 42 is driven to perform a protection operation so that an overvoltage is not applied to the field effect transistor 20, so that a transistor with a high breakdown voltage is used. A voltage-resonant switching converter can be configured without the need.

In the above-described embodiment, the switching operation of the field effect transistor 42 is performed based on the drain-source voltage Vds of the field effect transistor 20, but the voltage between the terminals of the primary winding 15p of the transformer 15 is used. The switching of the field effect transistor 42 may be performed based on Vp.

Further, as shown in FIG.
In addition, a new winding 15t may be provided, a detection unit may be configured using the winding 15t, and the field effect transistor 42 may be switched using a pulse voltage induced in the winding 15t. In this case, one terminal 15t1 of the winding 15t is connected to the non-inverting input terminal of the comparator 72 via the resistor 71. The other terminal 15t2 is connected to the terminal 15p2 of the primary winding 15p, and the inverting input terminal of the comparator 72 is connected to the suppression start level setting unit 74.
Is connected. The output terminal of the comparator 72 is connected to the sub-drive unit 75.

The suppression start level setting section 74 generates a clamp start voltage Vrd for setting a level at which a clamp operation for the drain-source voltage Vds of the field effect transistor 20 is started.
rd is supplied to the comparator 72. The clamp start voltage Vrd is a voltage based on the terminal 15p2 of the primary winding 15p.

The comparator 72 generates an output signal Sd indicating a comparison result between the voltage supplied to the non-inverting input terminal and the clamp start voltage Vrd, and supplies the output signal Sd to the sub-drive unit 75.
In the sub-drive unit 75, the output signal S from the comparator 72
By generating a drive signal DU based on d and supplying it to the gate of the field effect transistor 42, the field effect transistor 42 is switched.

The output terminal of the comparator 72 is connected to the terminal 15p2 of the primary winding 15p via a resistor 76, and the primary winding 15p is connected via resistors 77 and 78.
Terminal 15p2. Further, one terminal of the capacitor 79 is connected to a connection point between the resistor 77 and the resistor 78, and the other terminal of the capacitor 79 is connected to the terminal 15t1 of the winding 15t via the resistor 80. .

Here, when the load current is small and the on-period Ton in the drive signal DR is short, the current flowing through the field effect transistor 20 is small, and the voltage value of the pulse voltage generated in the primary winding 15p of the transformer 15 is small.
The voltage value of the pulse voltage generated in the winding 15t is also small. Therefore, the voltage of the non-inverting input terminal of the comparator 72 is lower than the clamp start voltage Vrd, the output signal Sd of the comparator 72 becomes low level "L", and the field effect transistor 42 is turned off.

When the load current is large and the on-period Ton in the drive signal DR is long, the field-effect transistor 20
Current flowing through the primary winding 15 of the transformer 15
As the voltage value of the pulse voltage generated at p increases, the voltage value of the pulse voltage generated at the winding 15t also increases.

Here, when the voltage of the non-inverting input terminal of the comparator 72 becomes higher than the clamp start voltage Vrd,
The output signal Sd of the comparator 72 becomes high level "H", and the field effect transistor 42 is turned on. When the voltage at the non-inverting input terminal of the comparator 72 becomes smaller than the clamp start voltage Vrd, the comparator 72
Becomes low level "L", and the field effect transistor 42 is turned off. Therefore, similarly to the case where the overvoltage protection operation is performed based on the drain-source voltage Vds of the field effect transistor 20, the peak value L of the drain-source voltage Vds of the field effect transistor 20 is set.
Since m can be kept low, a voltage resonance type switching converter can be configured without using a transistor having a high withstand voltage.

The resistors 77 and 80 and the capacitor 79
Therefore, when the output signal Sd of the comparator 72 is set to the high level “H”, a feedback operation is performed so as to increase the voltage of the non-inverting input terminal of the comparator 72, and the comparator 72
When the output signal Sd is at a low level “L”,
Since the feedback operation is performed so as to lower the voltage of the non-inverting input terminal of the comparator 72, the switching operation of the field effect transistor 42 can be performed stably.

As described above, when the load current is small and the peak value Lm of the drain-source voltage Vds of the field effect transistor 20 is small, the switching operation of the field effect transistor 42 is stopped, and Is stopped, the occurrence of switching loss in the field effect transistor 42 is prevented as shown in FIG. For this reason, the loss is smaller than in the case where a transistor with a high withstand voltage indicated by a broken line is used, and high power conversion efficiency can be obtained.

When the load current becomes larger than the current value Is, the switching operation of the field effect transistor 42 is started so that an overvoltage is not applied between the drain and the source of the field effect transistor 20. Since the overvoltage protection operation is performed, a voltage resonance type switching converter can be configured without using a transistor having a high withstand voltage.

Further, in the above embodiment, the case of the voltage resonance type switching converter has been described.
In a switching converter, a voltage induced by a transformer by an exciting current is superimposed on an input DC voltage, and if the input DC voltage on which the induced voltage is superimposed is applied to a switch element, a voltage resonance type switching converter is used. It is not limited to converters.

For example, in a flyback converter as shown in FIG. 6, similarly to the voltage resonance type switching converter shown in FIG. It is assumed that the protection transistor 9 includes the effect transistor 42.
By performing the switching operation of the field effect transistor 42 according to 0 according to the drain-source voltage of the field effect transistor 20, it is possible to prevent a high voltage from being applied between the terminals of the switch element. Similarly, a forward converter can prevent a high voltage from being applied between the terminals of the switch element. Further, the present invention can be applied to an inverter that converts an input DC voltage into an AC voltage and outputs the converted AC voltage.

When the power converter configured as described above is used in, for example, a motor device or an image display device using a cathode ray tube, the load current of the device is, for example, as shown in FIG.
7B in the image display device. Here, when the load current increases at the time of starting the motor device, or when the display on the image display device is displayed as a white screen and the load current increases, the voltage between the terminals of the switch element increases to a predetermined voltage. Is exceeded, an overvoltage protection operation is performed, so that a high voltage can be prevented from being applied between the terminals of the switch element. Also, when the motor device is in normal operation or when a program or the like is displayed on the image display device, the overvoltage protection operation is stopped because the load current is small, and unnecessary switching loss occurs. Can be prevented.

[0044]

According to the present invention, during the period in which the voltage between terminals of the switch element is detected as exceeding the predetermined voltage by the detecting means for detecting whether or not the voltage between the terminals exceeds the predetermined voltage. Then, the clamp operation of the voltage between the terminals of the switch element is performed. For this reason, it is possible to prevent an overvoltage from being applied to the inter-terminal voltage of the switch element, and to prevent a loss due to the clamping operation when the inter-terminal voltage is low.

The detecting means detects whether or not the voltage between the terminals of the switch element exceeds a predetermined voltage by using a voltage generated in a winding wound around the transformer. Therefore, even when a high voltage is applied between the terminals of the switch element, the voltage between the terminals of the switch element exceeds the predetermined voltage by adjusting the turns ratio between the winding and the primary winding. Detection can be performed at a low voltage.

Further, the voltage suppressing means has a capacitor and a sub-switch element connected in series to the capacitor,
The clamp operation of the inter-terminal voltage is performed by turning on the sub-switch element. Therefore, the start and stop of the clamp operation can be easily controlled.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a voltage resonance type switching converter according to the present invention.

FIG. 2 is a diagram showing a signal waveform in a field effect transistor 20 when a load current is small.

FIG. 3 is a diagram showing signal waveforms at the field effect transistors 20 and 42 when the load current is large.

FIG. 4 is a diagram showing another configuration of the voltage resonance type switching converter.

FIG. 5 is a diagram showing a relationship between load current and loss.

FIG. 6 is a diagram showing a configuration for a flyback converter.

FIG. 7 is a diagram showing the relationship between the operation of the device and the load current.

FIG. 8 is a diagram showing a configuration of a conventional voltage resonance side switching converter.

FIG. 9 is a diagram showing a signal waveform in the field-effect transistor 20.

FIG. 10 is a diagram showing another configuration of a conventional voltage resonance side switching converter.

FIG. 11 is a diagram showing signal waveforms at the field effect transistors 20 and 42.

FIG. 12 is a diagram illustrating a relationship between load current and loss in a conventional voltage resonance side switching converter.

[Explanation of symbols]

10: commercial AC power supply, 15: transformer, 20,
42 ... field-effect transistor, 25, 25a ...
Main drive unit, 35 ... load, 36 ... error amplifier,
37: Reference voltage generator, 40, 55, 75: Sub-drive unit, 52, 72: Comparator, 54, 74
..Suppression start level setting section, 90... Protection operation control section

Claims (3)

[Claims] A switching output of an exciting current flowing through a primary winding of a transformer is controlled using a switching element, so that a desired output voltage is obtained from a secondary winding side of the transformer. Detecting means for detecting whether a voltage between terminals of the switch element exceeds a predetermined voltage in a power converter in which an exciting current induced voltage generated in the transformer is superimposed on an input DC voltage and applied. And a voltage suppressing means for performing a clamping operation of the inter-terminal voltage during a period in which the detecting means detects that the inter-terminal voltage exceeds a predetermined voltage. 2. The method according to claim 1, wherein the detecting unit detects whether a voltage between terminals of the switch element exceeds a predetermined voltage using a voltage generated in a winding wound around the transformer. The power converter according to claim 1. 3. The voltage suppressing means includes a capacitor and a sub-switch element connected in series to the capacitor.
2. The power converter according to claim 1, wherein a clamp operation of the inter-terminal voltage is performed by making the sub-switch element conductive.