JP2002368566A - Phase shift circuit and phase shifter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase shift circuit and a phase shifter, with which multi- bit operation can be achieved by one circuit, a circuit configuration can be made compact and simple and costs can be reduced. SOLUTION: This device is provided with a capacitor 3a, a first serial circuit composed of an FET 2a and a capacitor 3b connected serially and a second serial circuit composed of an FET 2b and a capacitor 3c connected serially, one terminal of each of capacitor 3a, first serial circuit and second serial circuit is connected to a high frequency signal input/output terminal 1 and the other terminal is connected to the ground.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small-sized phase shift circuit and a phase shifter which realize a multi-bit operation with one circuit.

[0002]

2. Description of the Related Art FIG. 10 shows, for example, IEICE Technical Report, MW94-164,
pp. 67-71, Feb. 1995. This is a configuration diagram showing a conventional phase shift circuit. In FIG.
a is a first field-effect transistor (hereinafter abbreviated as FET), 102b is a second FET, 103a is a first capacitor, and 103b is a second capacitor. 106a
Is the bias terminal of the first FET, and 106b is the second FE
T bias terminal.

One terminal of the capacitor 103a is an FET
The other terminal is grounded to the drain electrode (or source electrode) of 102a. One terminal of the capacitor 103b is connected to the drain electrode (or source electrode) of the FET 102b, and the other terminal is grounded. FET102a
Source electrode (or drain electrode) and FET 10
The source electrode (or drain electrode) 2b is connected to the input / output terminal 101 for a high-frequency signal. FET1
02a and a capacitor 103a in series with a FET
The series circuit including the capacitor 102b and the capacitor 103b is:
They are connected in parallel with each other.

[0004] The FETs 102a and 102b operate as switches for switching between an on state and an off state. The bias terminal 106a is connected to the gate electrode of the FET 102a, and the bias terminal 106b is connected to the gate electrode of the FET 102b. A gate voltage having the same potential as the drain voltage and the source voltage of the FET 102a is supplied to the bias terminal 106a.
, The FET 102a is turned on and exhibits resistance (hereinafter referred to as on-resistance). On the other hand, when a gate voltage equal to or lower than the pinch-off voltage is applied to the bias terminal 106a, the FET 102a is turned off and exhibits a capacitance (hereinafter, referred to as off-capacitance). The FET 102b operates similarly.

Next, the operation will be described. First, FE
This will be described with reference to FIG. 11 which shows an equivalent circuit diagram when T102a is turned on and the FET 102b is turned off.
In the figure, reference numeral 104a denotes the on-resistance of the FET 102a;
5b is the off capacitance of the FET 102b. Off capacity 10
Assuming that the admittance exhibited by the series circuit of the capacitor 5b and the capacitor 103b is sufficiently small, the circuit shown in FIG. 11 can be regarded as a circuit including the on-resistance 104a and the capacitor 103a. Assuming that the ON resistance 104a is sufficiently small, the signal input from the high frequency signal input / output terminal 101 undergoes phase rotation due to the capacitance of the capacitor 103a, and is output from the high frequency signal input / output terminal 101.

Next, the FET 102a is turned off, and the FET 102a is turned off.
FIG. 1 shows an equivalent circuit diagram when the transistor 102b is turned on.
This will be described with reference to FIG. In the figure, 105a is an FET
The off-capacitance 102a and the on-resistance 104b of the FET 102b. Assuming that the admittance exhibited by the series circuit of the off-capacitance 105a and the capacitor 103a is sufficiently small,
The circuit shown in FIG.
3b. ON resistance 10
4b is sufficiently small, the high-frequency signal input / output terminal 10
The signal input from 1 is phase-rotated by the capacitance of the capacitor 103b and output from the high-frequency signal input / output terminal 101.

Here, the reflection phase caused by the capacitance exhibited by the capacitor 103a and the
The difference in the reflection phase caused by the capacitance of b is taken as the required phase shift amount. By doing so, the signal input from the high-frequency signal input / output terminal 1 is reflected by obtaining a required phase shift amount by switching the on / off state of the FET 102a and the FET 102b. Is done.

[0008]

However, the conventional phase shift circuit as described above has a problem that only one bit phase shift circuit can be formed. Further, when a multi-bit phase shifter is configured using a 90 ° hybrid coupler to separate an incident wave and a reflected wave, there is a problem that the circuit becomes large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to realize a multi-bit operation with one circuit and to obtain a compact phase shift circuit and a phase shifter.

[0010]

According to a first aspect of the present invention, there is provided a phase shift circuit comprising: a first capacitor; a first series circuit including a first switch and a second capacitor connected in series; A second series circuit comprising a second switch and a third capacitor connected to each other, and each of the first capacitor, the first series circuit, and one terminal of the second series circuit being connected to a high-frequency signal. It is connected to an input / output terminal and the other terminal is connected to the ground.

According to a second aspect of the present invention, in the phase shift circuit according to the first aspect of the present invention, a third switch is connected in series to the first capacitor to form a third series circuit. One terminal of the series circuit is connected to the high-frequency signal input / output terminal, and the other terminal is connected to the ground.

According to a third aspect of the present invention, in the phase shift circuit of the first aspect, at least one of the first and second series circuits is provided in plural.

A phase shift circuit according to a fourth aspect of the present invention is the phase shift circuit according to the first aspect of the present invention, wherein at least one of the first to third series circuits is provided in plurality.

According to a fifth aspect of the present invention, there is provided a phase shifter according to the first aspect.
5. A phase shift circuit according to any one of (1) to (4), and a 90 ° hybrid coupler combined with the phase shift circuit.

According to a sixth aspect of the present invention, there is provided a phase shifter according to the fifth aspect.
The above-described phase shifters are connected in multiple stages.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described.
Description will be made based on the drawings. Embodiment 1 FIG. FIG. 1 is a configuration diagram showing a phase shift circuit according to Embodiment 1 of the present invention. In the figure, 1 is a high frequency signal input / output terminal, 2a is FE as a first switch.
T, 2b are FETs as second switches, 3a are first FETs
MIM capacitor as a capacitor, 3b as a MIM capacitor as a second capacitor, 3c as a MIM capacitor as a third capacitor, 4a and 4b as bias terminals, 5a to 5c as through holes, 6a and 6b as resistors,
Is a semiconductor substrate. The phase shift circuit shown in FIG. 1 is monolithically formed on a semiconductor substrate 7.

The FET 2a and the MIM capacitor 3b are connected in series to form a first series circuit.
The MIM capacitors 3c are connected in series to form a second series circuit. Then, one terminal of each of the MIM capacitor 3a, the first series circuit, and the second series circuit is connected to the high frequency signal input / output terminal 1, and the other terminals are connected to the ground.

FIG. 2 is an equivalent circuit diagram of FIG. The same or corresponding components as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The FETs 2a and 2b operate as switches for switching between ON and OFF states.
The bias terminal 6a is connected to the gate electrode of the FET 2a, and the bias terminal 6b is connected to the gate electrode of the FET 2b.

When a gate voltage having the same potential as the drain voltage and the source voltage of the FET 2a is applied to the bias terminal 6a, the FET 2a is turned on and exhibits a resistance (hereinafter referred to as on-resistance). On the other hand, when a gate voltage equal to or lower than the pinch-off voltage is applied to the bias terminal 6a, the FET 2a is turned off and exhibits a capacitive property (hereinafter, referred to as off-capacity). F
ET2b performs the same operation.

Next, the operation of FIG. 1 will be described with reference to FIG.
This will be described with reference to FIGS. FIG.
FIG. 6 is an equivalent circuit diagram when both a and FET2b are off. In the figure, 8a is the off-capacity of the FET 2a, 8
b is the off capacitance of the FET 2b. Here, the off-capacity 8
The admittance of the series circuit composed of the capacitor a and the capacitor 3b is sufficiently small, and the off capacitance 8b and the capacitor 3
Assuming that the admittance of the series circuit composed of c is sufficiently small, the circuit shown in FIG. 3 is composed of only the capacitor 3a. Assuming that the capacitance of the capacitor 3a is Ca, the signal input from the input / output terminal 1 of the high-frequency signal is reflected by causing phase rotation by Ca, and is output to the input / output terminal 1 of the high-frequency signal.

FIG. 4 shows that the FET 2a is in the ON state and the FE
FIG. 9 is an equivalent circuit diagram when T2b is off. In the figure, reference numeral 9a denotes the ON resistance of the FET 2a. Here, assuming that the admittance of the series circuit including the off-capacitance 8b and the capacitor 3c is sufficiently small and the on-resistance 9a is sufficiently small, the circuit shown in FIG. 4 includes the capacitor 3a and the off-capacitance 3b. Assuming that the capacitance of the off-capacitance 3b is Cb, the signal input from the input / output terminal 1 for the high-frequency signal is reflected by causing phase rotation by Ca + Cb, and is output to the input / output terminal 1 for the high-frequency signal.

FIG. 5 shows that the FET 2a is off and the FE
It is an equivalent circuit diagram when T2b is in an ON state. In the figure, 9b is the on-resistance of the FET 2b. Here, assuming that the admittance of the series circuit including the off-capacitance 8a and the capacitor 3b is sufficiently small and the on-resistance 9b is sufficiently small, the circuit shown in FIG. 5 includes the capacitor 3a and the off-capacitance 3c. Assuming that the capacitance of the off-capacitance 3c is Cc, the signal input from the input / output terminal 1 of the high-frequency signal is reflected by causing phase rotation by Ca + Cc, and is output to the input / output terminal 1 of the high-frequency signal.

FIG. 6 is an equivalent circuit diagram when both the FETs 2a and 2b are on. Here, assuming that the ON resistance 9a and the ON resistance 9b are sufficiently small, FIG.
Is composed of a capacitor 3a, an off capacitance 3b, and an off capacitance 3c. The signal input from the high frequency signal input / output terminal 1 is reflected by causing phase rotation by Ca + Cb + Cc, and is output to the high frequency signal input / output terminal 1.

As described above, the phase shift circuit according to the first embodiment shown in FIG. 1 switches the on / off state of the FETs 2a and 2b to change the capacitance viewed from the high frequency signal input / output terminal 1, thereby providing high frequency signal input / output. The phase rotation amount generated when the signal input from the terminal 1 is reflected is changed. As an example, when Cb <Cc, the capacitance viewed from the high frequency signal input / output terminal 1 is Ca.
When changing in the order of (state a) → Ca + Cb (state b) → Ca + Cc (state c) → Ca + Cb + Cc (state d), four kinds of phase rotation amounts can be obtained.

As described above, according to the first embodiment, if the capacitance is appropriately set, the required phase shift amount is determined by the difference between the phase rotation amount in each of the states b to d and the phase rotation amount in the state 1. Obtainable. In other words, three phase shift amounts can be obtained by one phase shift circuit, and the effect that two-bit operation can be realized by one circuit can be obtained. Further, there is an effect that the size can be reduced as compared with a case where the 2-bit phase shift circuit is configured separately for each bit.

In this embodiment, the FETs 2a, 2
Although b is used as a switch, any type may be used as long as it has a switching function capable of switching on / off states.

In this embodiment, the passive element is formed on a dielectric substrate, the active element is formed on a semiconductor substrate, and both substrates are electrically connected to each other by metal wires. A phase circuit may be configured.

Embodiment 2 FIG. 7 is a configuration diagram showing a phase shift circuit according to Embodiment 2 of the present invention. In this embodiment, the high-frequency signal input / output terminal 1 and the capacitor 3a in FIG.
Between the gate terminal and the bias terminal 4 via the resistor 6c.
In this example, an FET 2c is connected as a third switch having a switch c.

Here, the capacitor 3a and the FET 2c are connected in series to form a third series circuit, and one terminal of the third series circuit is connected to the high frequency signal input / output terminal 1.
Connect the other terminal to ground. FET2c is FE
Like T2a and FET2b, it operates as a switch to switch on / off state. In FIG. 7,
The same or corresponding components as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

Next, the operation will be described. FET2a, FET2b and FET2 as in the first embodiment.
By switching the on / off operation of c and changing the capacitance viewed from the high frequency signal input / output terminal 1, the amount of phase rotation generated when the signal input from the high frequency signal input / output terminal 1 is reflected is changed. As an example, ON / OFF of the FETs 2a, 2b and 2c
When the off operations are independently switched, there are eight capacitances as viewed from the high-frequency signal input / output terminal 1, and thus eight types of phase rotation amounts can be obtained.

As described above, according to the second embodiment, by setting the capacitance appropriately, seven required phase shift amounts can be obtained with one phase shift circuit, and three-bit operation can be performed with one The effect that it can be realized by a circuit is obtained. Further, there is an effect that the size can be reduced as compared with a case where the 3-bit phase shift circuit is configured separately for each bit.

The FET 2a, FET 2b and FE
The on / off state of T2c may be partially switched and operated. In the present embodiment, the FETs 2a to
Although 2c is used as a switch, any type may be used as long as it has a switching function capable of switching on / off states.

Embodiment 3 FIG. 8 is a configuration diagram showing a phase shift circuit according to Embodiment 3 of the present invention. In the present embodiment, in FIG. 2 showing the configuration of the phase shift circuit according to the first embodiment, the bias terminals 4a to 4c are connected between the high-frequency signal input / output terminal 1 and the ground via the resistors 6a to 6c. FETs 2a to 2c provided with a capacitor 3b
3d are connected in series. The FETs 2a to 2c operate as switches for switching on / off states. In FIG. 8, FIG.
The same or corresponding components are denoted by the same reference numerals, and redundant description will be omitted.

Next, the operation will be described. As in the first embodiment, the signals input from the high-frequency signal input / output terminal 1 are reflected by switching on / off operations of the FETs 2a to 2c to change the capacitance viewed from the high-frequency signal input / output terminal 1. The amount of phase rotation that occurs at the time is changed. FETs 2a to 2c and capacitors 3b to
It is assumed that the number of series circuits composed of 3d connected in series is n. As an example, when the on / off operations of the FETs 2a to 2c are independently switched, there are n ² capacitances as viewed from the high frequency signal input / output terminal 1.
It is possible to obtain n ² kinds of phase rotation amounts.

As described above, according to the third embodiment, (n ² -1) required phase shift amounts can be obtained with one phase shift circuit by appropriately setting the capacitance. The effect is obtained that the n-bit operation can be realized by one circuit. Further, an effect is obtained that the size can be reduced as compared with a case where the n-bit phase shift circuits are individually configured for each bit.

It is to be noted that the on / off states of the FETs 2a to 2c may be partially switched and operated. Further, in the present embodiment, the FETs 2a to 2c are used as switches, but may be of any type as long as they have a switching function capable of switching on / off states.

Embodiment 4 FIG. In the present embodiment, although not shown, in the phase shift circuit of the second embodiment, the FET 2 and the capacitor 3 are provided between the high-frequency signal input / output terminal 1 and the ground, and have a bias terminal via a resistor at the gate terminal. Are connected to form a phase shift circuit. The FET 2 operates as a switch that switches on / off state.

Next, the operation will be described. As in the second embodiment, the on / off operation of the FET 2 is switched to change the capacitance viewed from the high-frequency signal input / output terminal 1 so that the signal input from the high-frequency signal input / output terminal 1 is reflected. Change the amount of phase rotation that occurs. It is assumed that the number of series circuits configured by connecting the FET2 and the capacitor in series is n. As an example, FET
When the on / off operation of the 2 is switched independently,
The capacitance viewed from the high frequency signal input / output terminal 1 is n ²
Therefore, n ² kinds of phase rotation amounts can be obtained.

As described above, according to the fourth embodiment, (n ² -1) required phase shift amounts can be obtained with one phase shift circuit by appropriately setting the capacitance. The effect is obtained that the n-bit operation can be realized by one circuit. Further, an effect is obtained that the size can be reduced as compared with a case where the n-bit phase shift circuits are individually configured for each bit.

Note that the on / off state of the FET 2 may be switched and operated in part. Further, in the present embodiment, the FET 2 is used as a switch, but may be of any type as long as it has a switching function capable of switching on / off states.

Embodiment 5 FIG. FIG. 9 is a configuration diagram showing a phase shifter according to Embodiment 5 of the present invention. In the figure,
10 is a high-frequency signal input terminal, 11 is a high-frequency signal output terminal, 12 is a 90 ° hybrid coupler, 13a, 13b
Is a reflective termination circuit. The phase shifter shown in FIG. 9 is configured monolithically on the semiconductor substrate 7. As the reflective termination circuits 13a and 13b, the phase shift circuits described in any of the first to fourth embodiments are used.

Next, the operation will be described. A high-frequency signal is input from the high-frequency signal input terminal 10 to the 90 ° hybrid coupler 12. A signal having the same phase as the high-frequency signal input to the 90 ° hybrid coupler 12 is applied to the reflective termination circuit 1.
3a, the signal whose phase is delayed by 90 °
b. High-frequency signals having phases different from each other by 90 ° are reflected by the desired phase rotation in the reflective termination circuits 13a and 13b, respectively. The reflected high frequency signal is
It is input to the 90 ° hybrid coupler 12 again. In the high-frequency signal input terminal 10, the reflective termination circuit 13
Since the phases of the signals reflected by a and 13b are different from each other by 180 °, no output appears and an output is obtained only at the high frequency signal output terminal 11.

Here, the phase shift circuit described in any of the first to fourth embodiments is used for the reflective termination circuits 13a and 13b, and the states of the reflective termination circuits 13a and 13b are simultaneously switched. A desired phase shift amount is obtained from the difference between the reflection phases in each state. Thereby, the input signal and the output signal are separated, and the reflective termination circuits 13a, 13a
Only the signal reflected by b can be extracted as an output signal.

As described above, according to the fifth embodiment, it is possible to configure a phase shifter that outputs only the signals reflected by the reflective termination circuits 13a and 13b, and performs multi-bit operation by one phase shift. The effect that it can be realized with a container is obtained. Further, the number of 90 ° hybrid couplers is reduced as compared with the case where a 1-bit phase shifter is connected in multiple stages to form a multi-bit phase shifter, so that the configuration is downsized and the loss of the coupler is reduced. The effect that it can be obtained is obtained.

In the present embodiment, the phase shifter is monolithically configured, but the passive element and the 90 ° hybrid coupler are formed on a dielectric substrate, the active element is formed on a semiconductor substrate, and both are formed by metal wires. The phase shifters may be configured by electrically connecting the substrates.

Embodiment 6.1 In a multi-bit phase shifter configured by connecting multiple stages of 1-bit phase shifters, a multi-bit phase shifter is used for several bits by using the phase shifter of the fifth embodiment. Is configured. Thereby, an effect similar to that of the fifth embodiment can be obtained.

[0047]

As described above, according to the first aspect of the present invention, a first capacitor, a first series circuit including a first switch and a second capacitor connected in series,
A second series circuit comprising a second switch and a third capacitor connected in series, wherein one terminal of each of the first capacitor, the first series circuit, and the second series circuit is connected to a high frequency. Since it is connected to the signal input / output terminal and the other terminal is connected to the ground, two-bit operation can be realized by one phase shift circuit, and the circuit configuration can be reduced in size and simplification, and the cost can be reduced. This has the effect.

According to the second aspect of the present invention, the first
A third switch is connected in series to the capacitor of the third series circuit, one terminal of the third series circuit is connected to the high-frequency signal input / output terminal, and the other terminal is connected to the ground. Therefore, there is an effect that a 3-bit operation can be realized by one phase shift circuit, and the circuit configuration can be reduced in size and simplified, and the cost can be reduced.

According to the third aspect of the present invention, the first
In addition, since at least one of the second series circuits is provided in a plurality, the multi-bit operation can be realized by one phase shift circuit, and the effect that the circuit configuration can be reduced in size and simplified, and the cost can be reduced. is there.

According to the fourth aspect of the present invention, the first
Since at least one of the third to third series circuits is provided, a multi-bit operation can be realized by one phase shift circuit, and the circuit configuration can be reduced in size and simplified, and the cost can be reduced. There is.

According to the invention of claim 5, according to claim 1,
5. Since the phase shift circuit according to any one of (1) to (4) and the 90 ° hybrid coupler combined with the phase shift circuit are provided, multi-bit operation can be realized with one phase shifter, and the circuit configuration is compact. It is possible to reduce the cost and cost of the coupler, and to reduce the loss of the coupler.

Further, according to the invention of claim 6, since the phase shifters of claim 5 are connected in multiple stages, the phase shifters capable of multi-bit operation can be easily connected to several bits by the multi-stage connection. In addition, the circuit configuration can be reduced in size and simplified, the cost can be reduced, and the loss of the coupler can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a phase shift circuit according to Embodiment 1 of the present invention.

FIG. 2 is an equivalent circuit diagram of the phase shift circuit according to the first embodiment of the present invention.

FIG. 3 shows an FET 2a according to the first embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram when is turned off and the FET 2b is turned off.

FIG. 4 is an FET 2a according to the first embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram when is turned on and the FET 2b is turned off.

FIG. 5 is an FET 2a according to the first embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram when is turned off and the FET 2b is turned on.

FIG. 6 shows an FET 2a according to the first embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram when is turned on and the FET 2b is turned on.

FIG. 7 is a configuration diagram showing a phase shift circuit according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram showing a phase shift circuit according to a third embodiment of the present invention.

FIG. 9 is a configuration diagram illustrating a phase shifter according to a fifth embodiment of the present invention.

FIG. 10 is a configuration diagram showing a conventional phase shift circuit.

FIG. 11 is an equivalent circuit diagram when the FET 102a in the conventional phase shift circuit is turned on and the FET 102b is turned off.

FIG. 12 is an equivalent circuit diagram when the FET 102a in the conventional phase shift circuit is turned off and the FET 102b is turned on.

[Explanation of symbols]

1 High frequency signal input / output terminal, 2a to 2c FET, 3a
-3d MIM capacitor or equivalent capacitor, 4a-4c bias terminal, 5a-5c through hole, 6a-6c resistor, 7 semiconductor substrate, 8a, 8b
On-resistance, 9a, 9b Off-capacitance, 10 High-frequency signal input terminal, 11 High-frequency signal output terminal, 12 90 ° hybrid coupler, 13a, 13b Reflective termination circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Michiaki Kasahara 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Nao Takagi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo 3 Rishi Electric Co., Ltd. F-term (reference) 5J012 HA05

Claims (6)

[Claims] 1. A first series circuit comprising a first capacitor, a first switch and a second capacitor connected in series, and a second series circuit comprising a second switch and a third capacitor connected in series. Wherein one terminal of each of the first capacitor, the first series circuit, and the second series circuit is connected to a high-frequency signal input / output terminal, and the other terminal is connected to ground. A phase shift circuit, characterized in that: 2. A third switch is connected in series to the first capacitor to form a third series circuit, and one terminal of the third series circuit is connected to the high frequency signal input / output terminal. 2. The phase shift circuit according to claim 1, wherein the other terminal is connected to a ground. 3. The phase shift circuit according to claim 1, wherein a plurality of at least one of the first and second series circuits are provided. 4. The phase shift circuit according to claim 2, wherein a plurality of at least one of the first to third series circuits are provided. 5. A phase shifter comprising: the phase shift circuit according to claim 1; and a 90 ° hybrid coupler combined with the phase shift circuit. 6. A phase shifter comprising the phase shifter according to claim 5 connected in multiple stages.