JP2002344148A - Printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board which allows a plurality of wirings having various wiring characteristic impedances to be laid, without variously changing the board thickness or lowering the wiring density and enables connection of a system having various interfaces with a simple printed wiring board, without increasing the cost. SOLUTION: A copper foil 1 forming a power source layer or a ground layer on a core board 10 comprises a high impedance area zone 4 having a high proportion of non-copper foil portions 2, resulting in a low copper foil ratio; and a low impedance area zone 5 having a low proportion of non-copper foil portions 3, resulting in a high copper foil ratio. A high impedance wiring layer 6 is formed so as to face the high impedance area zone 4 on a core board facing the core board having the copper foil 1, and a low impedance wiring layer 7 is formed so as to face the low impedance area zone 5 on the core board facing the core board having the copper foil 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board capable of wiring with a plurality of characteristic impedances without adjusting the thickness of the board and without reducing the wiring density. The present invention relates to a printed wiring board which can be connected by one printed wiring board in a system having the same, and can reduce wiring cost by forming one board.

[0002]

2. Description of the Related Art A multilayer printed wiring board is manufactured by sandwiching a pair of core boards having printed wirings provided on both front and back sides with a prepreg for interlayer bonding therebetween and heat-pressing them. The prepreg adheres the core substrates to each other by heating and pressing to make the printed wirings facing each other insulated. As a wiring layer formed by printed wiring,
There are a power layer, a ground layer, and a signal layer. Therefore, the signal layer and the power supply layer often face each other with the insulating layer interposed therebetween, and the signal layer and the ground layer often face each other with the insulating layer interposed therebetween.
Therefore, a capacitive impedance exists between the signal layer and the power supply layer or the ground layer.

Conventionally, the wiring layers incorporated in the printed wiring board have a single characteristic impedance, or even if a plurality of wiring layers have different characteristic impedance, The difference between them was not great. That is, conventionally, when the characteristic impedance is made different among a plurality of wiring layers, the width of the wiring layers is made different. Therefore, the difference between the obtained characteristic impedances was not large.

[0004]

However, recently,
Wiring having various characteristic impedances has been required. In this case, there is a problem that a required characteristic impedance cannot be obtained even if an attempt is made to obtain a difference in characteristic impedance only by adjusting the wiring width as in the related art. Further, reducing the width of the wiring layer has a limit in manufacturing the substrate. Also,
Even if an attempt is made to increase the wiring width, there is a limit in terms of wiring accommodating property and the like, and there is a problem that the wiring density is reduced.

[0005] Further, even if an attempt is made to adjust the characteristic impedance by increasing the thickness of the insulating layer between the wiring layers,
The thickness of the printed wiring board is increased. For this reason, conventionally, there is a disadvantage that the range of the characteristic impedance that can be obtained in one printed wiring board is largely restricted.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is capable of wiring a plurality of wirings having various wiring characteristic impedances without variously changing the substrate thickness and reducing the wiring density. It is an object of the present invention to provide a printed wiring board which enables a system having various interfaces to be connected by one printed wiring board without increasing the cost.

[0007]

According to the present invention, there is provided a printed wiring board in which a pair of wiring layers formed on a pair of core substrates face each other with an insulating layer interposed therebetween. The metal foil constituting the wiring layer is provided with a non-metal foil portion where the metal foil is locally removed, and is divided into a plurality in the width direction of the one wiring layer. In the region, the area ratio of the non-metal foil portion is different from each other. Note that the area ratio of the non-metal foil portion is a ratio of the total area of the non-copper foil portion to the area of the region.

In this printed wiring board, for example,
A plurality of the other wiring layers facing the one wiring layer are provided, and one or a plurality of the other wiring layers are provided so as to face the plurality of regions of the one wiring layer, respectively. Have been.

In this printed wiring board, for example, the one wiring layer is a power supply layer or a ground layer, and the other wiring layer is a signal layer.

Further, the printed wiring board according to the present invention comprises:
A power layer or a ground layer is formed as a wiring layer on one core substrate, a plurality of signal layers are formed as a wiring layer on the other core substrate, and the power layer or the ground layer and the signal layer have an insulating layer interposed therebetween. In the printed wiring board opposed to the first metal foil, the first metal foil constituting the power supply layer or the ground layer is provided with a non-metal foil portion which is locally removed, and the first metal foil is provided with the first metal foil. The foils are different in the area ratio of the non-metallic foil portion from each other in a region divided into a plurality in the wiring width direction, and the signal layer is provided in each of the plurality of regions of the first metal foil. Alternatively, the plurality of core substrates are arranged on the other core substrate so as to be aligned.

In this printed wiring board, for example,
A region where the area ratio of the non-metal foil portion in the metal foil is low and the metal foil ratio is low is a high impedance area region, and a region where the area ratio of the non-metal foil portion is low and the metal foil ratio is high is a low impedance region. Features. The metal foil ratio is a ratio of the total area of the portion occupied by the metal foil in the region, and the total area of the portion where the metal foil excluding the non-metal foil portion is present with respect to the area of the region. It is the ratio of the area.

In this printed wiring board, when the non-metallic foil portions are arranged in a square at a constant pitch, the metal foil ratio is determined by the length of one side and the arrangement pitch. For example, in each of the regions, the arrangement pitch is the same, and one side length is different from each other.

Further, in this printed wiring board, for example, one of the plurality of regions does not have the non-metallic foil portion, and the metal foil ratio is 100%. The non-metallic foil portion does not exist and the metal foil ratio is 10
The signal layer facing the 0% region can be formed to be wider than the signal layer facing the other region.

In the present invention, a non-metal foil portion formed by locally removing a metal foil is formed on one of the wiring layers, such as a power supply layer and a ground layer, facing the other wiring layer such as a signal layer. Since a plurality of regions having different area ratios (metal foil ratios) of the non-metal foil portions are provided in the width direction of the one wiring layer, the metal foil of the power supply layer or the ground layer facing the signal layer is provided. The rate determines the capacitive impedance between the signal layer and the power or ground layer. Thus, a plurality of types of wiring layers having a plurality of capacitance impedances can be provided on one printed wiring board.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a printed wiring board according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a schematic diagram showing a power supply layer or a ground layer of a printed wiring board according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing the structure of the printed wiring board of this embodiment, and FIG. FIG. 4A is a graph showing the relationship between the ratio of copper foil in a layer and impedance, and FIG.
(B) is a plan view showing a pattern of a signal layer. As shown in FIG. 2, the insulating core substrates 10a, 10b, 10c
Is an insulating layer 16 formed by heat-pressing a prepreg,
17 are sandwiched between them. On the surface of the core substrate 10a facing the core substrate 10b,
A power supply layer 11 is formed, and a ground layer 15 is formed on a surface of the core substrate 10c facing the core substrate 10b. The signal layer 12 is formed on the power supply layer 11 side surface of the central core substrate 10b, and the signal layers 13 and 14 are formed on the ground layer 15 side surface of the core substrate 10b.

The power supply layer 11, the signal layers 12, 13 and
The power supply layer 11 and the ground layer 15 are wide as shown in FIG.
5 is formed on almost the entire surface in the width direction. It should be noted that the multilayer printed wiring board is a three-layer core
The present invention is not limited to the case where a, b, and c are stacked, and a core substrate of two layers or four or more layers may be stacked.

As shown in FIGS. 1 and 4 (a), the power supply layer 11 and the ground layer 15 are provided on a core substrate 10 (core substrate 1).
0a, 10c), a copper foil 1 is laminated, and this copper foil 1 has a substantially square region 4 (enclosed by a broken line) in the width direction of the core substrate 10 having a large square shape. Non-copper foil portions 2 formed by removing a large number of portions
The other approximately half region 5 (enclosed by a broken line) is a region having a large number of non-copper foil portions 3 formed by removing a large number of small square portions. ing. The non-copper foil portion 2 in the region 4 has a side length of, for example, 1.2
It forms a 7 mm square, the pitch between the non-copper foil parts 2 is, for example, 1.27 mm, and the entire area of the non-copper foil part 2 is the same as the area of the remaining copper foil part, The ratio of the copper foil (copper foil ratio) in the region 4 is, for example, 50%. The non-copper foil portion 3 in the region 5 is a square having a side length of, for example, 0.84 mm, and the pitch between the non-copper foil portions 3 is, for example, 1.27 mm, and occupies the entire area of the region 5. The total area of the non-copper foil portion 3, that is, the ratio of the copper foil in the region 5 (copper foil ratio) is, for example, 78%. In addition,
The pitch between the non-copper foil portion 2 and the non-copper foil portion 3 may be the same or different.

This copper foil ratio is calculated by the following equation (1).

[0019]

(Equation 1)

Here, Y is the length (mm) of one side of the non-copper foil portion.
(For the case of the non-copper part 3, FIG. 5 shows one side length by Y), X: pitch (mm) of the non-copper part (FIG. 5 shows the pitch by X for the non-copper part 3) ) And Z are copper foil ratios (%).

Thus, as shown in FIG.
%, The signal layer 6 (signal layers 12, 13, 14) facing the region 4 via the insulating layer has a high impedance, and the region 4 is a high impedance wiring area. In the region 5 where the copper foil ratio is 78%, the signal layer 7 (signal layers 12, 13, 14) facing the region 5 via the insulating layer has a lower impedance than the region 4. This area 5 is a low impedance wiring area. In FIG. 1, the signal layers 6, 7
Is superimposed on the copper foil 1 of the power supply layer or the ground layer.

FIG. 3 shows the power supply layer 11 or the ground layer 1 on the horizontal axis.
5 is a graph showing the relationship between the impedance Zo between the power supply layer 11 or the ground layer 15 and the signal layers 6 and 7 opposed thereto via an insulating film on the vertical axis. is there. The measured values shown in FIG. 3 indicate that the power supply layer 11 made of copper foil having various copper foil ratios is obtained when a plurality of signal layers 6 and 7 are arranged at regular intervals as shown in FIG. Alternatively, it is a case in which it is arranged opposite to the ground layer 15 via an insulating layer (so-called strip line structure). The wiring width of the signal layers 6 and 7 is 120 μm, the distance between the signal layers 6 and 7 and the power supply layer 11 or the ground layer 15 opposed to each other with the insulating layer interposed therebetween is 100 μm, and the distance between adjacent signal layers is 100 μm. is there. In FIG.
The relationship between the characteristic impedance and the copper foil ratio is shown by a curve connecting the measured values smoothly. As shown in FIG. 3, the characteristic impedance between the power supply layer or the ground layer and the signal layer (wiring layer) has a correlation with the copper foil ratio, and is obtained when the copper foil ratio is determined. The characteristic impedance between the wiring layers is determined.

Next, the operation of the present embodiment configured as described above will be described. The signal layer 12 shown in FIG.
6 is opposed to the power supply layer 11 with the signal layers 13 and 14 interposed therebetween.
Faces the ground layer 15 with the insulating layer 17 interposed therebetween. As described above, the signal layers 12 to 14 face the wide power supply layer 11 or the ground layer 15 and have a capacitive impedance between these layers. In this case, the signal layer 6
Signal line, signal layer 7 requiring high impedance
Is a signal line that needs to have low impedance, as shown in FIG. 1, the signal layer 6 is a high-impedance wiring area of the copper foil 1 forming the power supply line 11 or the ground line 15 on the core substrate 10. It is arranged in a region facing region 4. On the other hand, the signal layer 7 is
The power supply line 11 or the ground line 15 is arranged in a region facing the low impedance wiring area region 5. Signal layer 6, 7
Has a so-called stripline structure as shown in FIG. 4B, the signal layer 6 is arranged so as to pass right above or immediately below the high-impedance wiring area 4 of the copper foil 1 of the power supply layer or the ground layer. The layer 7 is disposed so as to pass right above or immediately below the low impedance wiring area region 5 of the copper foil 1 of the power supply layer or the ground layer. That is, in plan view, the signal layer 6
Overlaps with the high impedance wiring area 4 and the signal layer 7 overlaps with the low impedance wiring area 5. Thus, signal layers 6 and 7 having different wiring characteristic impedances can be provided on one printed wiring board.

In this case, as shown in FIG. 3, the copper foil ratio of the power supply layer or the ground layer, the power supply layer or the ground layer and the signal If this characteristic curve is obtained by measuring the relationship with the wiring characteristic impedance between the layers, the copper foil ratio for obtaining the desired characteristic impedance can be easily obtained, and the copper foil ratio can be obtained. In addition, a desired characteristic impedance can be easily obtained by adjusting the pattern of the non-copper foil portion of the power supply layer or the ground layer.

That is, in the case of the characteristic curve shown in FIG. 3, if it is desired to obtain a signal layer having a characteristic impedance of 50Ω, it is easily found from FIG. 3 that the copper foil ratio should be 78%. When it is desired to form a signal layer having a characteristic impedance of 75Ω, it is easily found from FIG. 3 that the copper foil ratio should be set to 50%. Therefore, such a copper foil ratio is 78
The power supply layer 11 or the ground layer 15 is formed so as to have the region 5 of% and the region 4 of the copper foil ratio of 50%. For this purpose, as described above, the non-copper foil portion 2 of the region 4 has a side length of 1.2.
7 mm square, pitch between non-copper foil parts 2 is 1.2
By setting it to 7 mm, the copper foil ratio is set to 50%, and the area 5
Of the non-copper foil part 3 is a square having a side length of 0.84 mm,
By setting the pitch between the non-copper foil portions 3 to, for example, 1.27 mm, the copper foil ratio may be set to 78%.

Then, a 75 Ω high impedance signal layer 6 is provided in a region facing the high impedance wiring area region 4, and a 50 Ω low impedance signal layer 7 is provided in a region facing the low impedance wiring area region 5. As a result, the wiring characteristic impedance becomes 75Ω and 50Ω.
The printed wiring board having the two types of characteristic impedances is obtained.

Next, a second embodiment of the present invention will be described. FIG. 6A is a schematic view showing a copper foil 1a of a power supply layer or a ground layer of a printed wiring board according to a second embodiment of the present invention, and FIG. 6B is insulated from the power supply layer or the ground layer. It is a schematic diagram which shows the signal signal layers 6a and 7a which oppose via a layer. FIG. 7 shows the characteristic impedance (Z ₀ ) on the vertical axis.
FIG. 4 is a graph showing the relationship between the copper foil ratio and the characteristic impedance, with the horizontal axis representing the copper foil ratio in the copper foil constituting the power supply layer or the ground layer. In FIG. 6, the low-impedance area region 5 is located at the upper part of the figure, and the high-impedance area area 4 is located at the lower part of the figure.
And it is opposite to the case of the first embodiment shown in FIG.

Also in the present embodiment, the signal lines are 55Ω and 7Ω.
Consider a printed wiring board that requires two types of characteristic impedance of 5Ω. First, the wiring width is set to 120 μm.
m, the relation of the power layer or the ground layer to the signal layer is a strip line structure, the distance between the signal layer and the power layer or the ground layer is 150 μm, and the distance between the signal layers is 150
μm.

Next, a method for designing a wiring of a printed wiring board according to the present embodiment will be described. Also in this embodiment, the first
As in the embodiment, first, the wiring width is 120 μm, the relation of the power layer or the ground layer to the signal layer is a strip line structure, the distance between the signal layer and the power layer or the ground layer is 150 μm, and the distance between the signal layers is 150 μm. The relationship between the copper foil ratio of the copper foil constituting the power supply layer or the ground layer and the characteristic impedance when the distance is 150 μm is actually measured. This allows
A characteristic curve between the copper foil ratio and the characteristic impedance as shown in FIG. 7 can be obtained.

Next, the copper foil ratio is determined using this characteristic curve. First, the characteristic impedance to be obtained is 55
In the case of Ω, the point where the characteristic curve intersects with a straight line extending horizontally from 55Ω on the Y axis in FIG. 7 is extended vertically downward. next,
Read the copper foil ratio where it intersects the X axis. However, in FIG. 7, when the characteristic impedance is 55Ω, there is no intersection in the characteristic curve, and when the copper foil ratio is 100%, the characteristic impedance closest to 55Ω is obtained. However, when the copper foil ratio is 100% and the wiring width is 120 μm, the characteristic impedance exceeds the desired value of 55Ω. Therefore, the desired characteristic impedance is 5
In the case of 5Ω, the wiring width is increased (for example, 130 Ω).
μm). On the other hand, when the desired characteristic impedance is 75Ω, the point where the straight line horizontally extending from 75Ω on the Y axis in FIG. 7 intersects with the characteristic curve is extended vertically downward. When the copper foil ratio at the intersection with the X axis is read, the characteristic impedance is 7
It can be seen that the copper foil ratio in the case of 5Ω is 42%.

Therefore, in the low impedance area region 5 of the copper foil 1a in the power supply layer or the ground layer, since the copper foil ratio is 100%, there is no non-copper foil portion and the copper foil exists in the entire region 5. The low-impedance signal layer 7a disposed opposite to the low-impedance area region 5 has a characteristic width that is not 55Ω when the wiring width is 120 μm.
130 μm.

On the other hand, in the high impedance area 4 where the characteristic impedance is 75 Ω, if the pitch (interval) of the non-copper foil portion 2 a is 1.27 mm, 75 Ω
Is 42%, the one side length of the non-copper foil portion 2a is determined to be 1.37 mm from the mathematical expression 1 showing the relationship between the one side length of the non-copper foil portion and the copper foil ratio.

Therefore, in the high impedance area region 4, the non-copper foil portion 2a may be a square having a side length of 1.37 mm, and the pitch of the non-copper foil portion 2a may be 1.27 mm. The low-impedance area region 5 has a copper foil on the entire surface (copper foil ratio: 100%), the wiring width of the low-impedance signal layer 7a is 130 μm, and the wiring width of the high-impedance signal layer 6a is 120 μm.

As described above, also in this embodiment, it is possible to provide wiring layers having two types of characteristic impedance. In this embodiment, the width of the signal layer 7a is
The width of the signal layer is adjusted by using a copper foil that does not have a non-copper foil part in the power supply layer or the ground layer, as in the past. Unlike the case in which the wiring width is increased, the ratio of increasing the wiring width is extremely small, and does not hinder high-density wiring.

[0035]

As described above in detail, according to the present invention, when wirings having different characteristic impedances are provided on one printed wiring board to form a single board, it is necessary to increase the thickness of the low impedance wiring layer. Therefore, various interfaces having different characteristic impedances can be connected by high-density wiring, and hardware having various interfaces can be provided on one board. Also,
There is no need to change the thickness of the substrate from the current one. Furthermore, by making the wiring width of the wiring layer on the low impedance side larger than the wiring width of the wiring layer on the high impedance side,
Along with the adjustment of the copper foil ratio of the power supply layer or the ground layer, the variation width of the obtained characteristic impedance can be significantly widened.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a relationship between a power layer or a ground layer of a printed wiring board and a signal layer according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a typical structure of a printed wiring board.

FIG. 3 shows the copper foil ratio of the power supply layer or the ground layer on the horizontal axis,
The vertical axis shows the characteristic impedance (Z ₀)
Graph showing the relationship with characteristic impedance (characteristic curve)
FIG.

FIG. 4A shows a copper foil 1 constituting a power supply layer or a ground layer of a printed wiring board according to the first embodiment of the present invention, and FIG. 4B is a schematic view showing a pattern of signal layers 6 and 7; FIG.

FIG. 5 is a schematic view showing a shape of a non-copper foil portion.

FIG. 6A shows a copper foil 1a of a power supply layer or a ground layer of a printed wiring board according to a second embodiment of the present invention,
(B) is a schematic diagram showing a pattern of the signal layers 6a and 7a.

FIG. 7 shows the copper foil ratio of the power supply layer or the ground layer on the horizontal axis,
The vertical axis shows the characteristic impedance (Z ₀)
FIG. 4 is a graph showing a characteristic curve between the characteristic impedance and the characteristic impedance.
is there.

[Explanation of symbols]

 1, 1a; copper foil 2, 2a; non-copper foil 3, 3a; non-copper foil 4, high impedance area 5, low impedance area 6, 6a; high impedance signal wiring layer 7, 7a; low impedance signal Wiring layer 10 (10a, 10b, 10c); core substrate 11; power supply layer 12 to 14; signal layer 15; ground layers 16, 17;

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E338 AA02 AA03 AA11 CC01 CC04 CC06 CD01 CD23 CD24 EE11 EE31 5E346 AA05 AA12 AA15 AA32 AA35 BB02 BB03 BB04 BB06 BB11 CC01 CC31 HH01

Claims (9)

[Claims] In a printed wiring board in which a pair of wiring layers formed on a pair of core substrates face each other with an insulating layer interposed therebetween, a metal foil forming one of the wiring layers includes Non-metal foil portions from which the foil has been locally removed are provided in a dotted manner, and the area ratios of the non-metal foil portions are different from each other in a region divided into a plurality in the width direction of the one wiring layer. A printed wiring board characterized by the following. 2. A plurality of other wiring layers facing the one wiring layer are provided, and one or a plurality of the other wiring layers are provided for each of the plurality of regions of the one wiring layer. The printed wiring board according to claim 1, wherein the printed wiring board is provided so as to face each other. 3. The printed wiring board according to claim 1, wherein the one wiring layer is a power layer or a ground layer, and the other wiring layer is a signal layer. 4. A power supply layer or a ground layer is formed as a wiring layer on one core substrate, and a plurality of signal layers are formed as a wiring layer on the other core substrate. In the printed wiring board opposed to each other with an insulating layer interposed therebetween, the first metal foil constituting the power supply layer or the ground layer is provided with a non-metal foil portion which is locally removed. In the first metal foil, the area ratio of the non-metal foil part is different from each other in a region divided into a plurality in the wiring width direction, and the signal layer includes a plurality of the first metal foils. A printed wiring board, wherein one or a plurality of printed wiring boards are arranged on the other core substrate so as to be aligned with the respective regions. 5. A high-impedance area is a region where the area ratio of the non-metal foil portion is large and the metal foil ratio is low in the metal foil, and a region where the area ratio of the non-metal foil portion is small and the metal foil ratio is high is low impedance. The printed wiring board according to claim 4, wherein the printed wiring board is an area. 6. The print according to claim 4, wherein the non-metallic foil portions are arranged in a square at a constant pitch, and the metal foil ratio is determined by the length of one side and the arrangement pitch. Wiring board. 7. The printed wiring board according to claim 6, wherein the arrangement pitch is the same in each of the regions, and one side length is different from each other. 8. The method according to claim 4, wherein one of the plurality of regions does not include the non-metallic foil portion and has a metal foil ratio of 100%. The printed wiring board as described. 9. The non-metallic foil portion does not exist and the metallic foil ratio is 1
9. The printed wiring board according to claim 8, wherein the signal layer facing the region of 00% is wider than the signal layer facing the other region.