JP2002236611A - Semiconductor device and information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and an information processing system allowing the setting of a flexible device address while improving usability and securing reliability. SOLUTION: This semiconductor device with an internal circuit which performs circuit operation corresponding to a signal inputted and outputted through an input/output interface circuit suited to a serial bus, is provided with a nonvolatile storage circuit for storing identification information. A comparing circuit compares internal identification information stored in the nonvolatile storage circuit, with external identification information included in the input signal supplied through the serial bus. The change of the internal information of the nonvolatile storage circuit is also included by a control circuit which performs circuit operation responding to the input signal supplied in succession through the serial bus by a coincidence detection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and an information processing system, for example, a semiconductor device in which two semiconductor chips are stacked and sealed with one resin sealing body, and identification in an information processing system using the same. The present invention relates to technology effective when applied to information setting technology.

[0002]

2. Description of the Related Art As a semiconductor device, MCP (M ulti C hi
p P ackage) type semiconductor device which is referred is known. Various types of MCP semiconductor devices have been developed and commercialized, but MCP semiconductor devices in which two semiconductor chips are stacked and incorporated into one package are the most widely used. For example, JP-A-2-54
The 55 No. (known document 1), operating the processor units built-in microcomputer chip for programmatically, EEPROM nonvolatile memory unit is built as a memory chip (E lectrically E rasable P
rogrammable the R ead O nly M emory) chip stacking, sealing the two chips in one resin sealing body M
A CP type semiconductor device is disclosed.

[0003] JP-A-5-343609 discloses an MO.
SFET (MetalOxideSemiconductorFieldEffect
Transistor) CMOS with built-in circuits
(ComplementaryMOS) For a chip on a bipolar
Bipolar with a built-in transistor-based circuit
Chips are stacked, and these two chips are sealed with one resin.
An MCP semiconductor device sealed with a body is disclosed.

[0004]

There is an increasing demand for a semiconductor device in which a microcomputer chip and an EEPROM chip are incorporated in one package, and the present inventors have stacked the EEPROM chip on the microcomputer chip, Prior to the development of a semiconductor device in which these two chips are sealed with one resin sealing body, the following problems were found.

In a microcomputer system, device identification information (device address) is individually set in peripheral circuits such as a memory circuit. The setting of the device address is the simplest method, for example, in which an external terminal (address pin) is connected to the power supply voltage VCC or the ground potential VSS of the circuit on the mounting board to set a high-level and low-level binary signal. is there. However, in the above-mentioned MCP type semiconductor device, the identification information is fixed because the address pins are connected to VCC or VSS when they are sealed with one resin sealing body. When the identification information is fixed in this way, a plurality of types of semiconductor devices in which a plurality of types of identification information are set for semiconductor devices having the same function so as to be adaptable to various information processing systems are manufactured. Manufacturing and handling are complicated, for example, inventory management for each device address, mounting of the correct device address at the time of assembly, and the like.

An object of the present invention is to provide a user-friendly semiconductor device and an information processing system. Another object of the present invention is to provide a semiconductor device and an information processing system in which a flexible device address can be set while ensuring reliability. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. A nonvolatile memory circuit for storing identification information is provided in a semiconductor device having an internal circuit that performs a circuit operation corresponding to a signal input / output via an input / output interface circuit adapted to a serial bus, and the nonvolatile memory circuit includes The stored internal identification information is compared with the external identification information included in the input signal supplied through the serial bus by a comparison circuit, and the input signal continuously supplied through the serial bus according to the match detection signal. A change in the internal information of the nonvolatile memory circuit is also included by a control circuit that performs a circuit operation in response to the above.

The following is a brief description of an outline of another representative embodiment of the invention disclosed in the present application. A semiconductor device having an internal circuit that performs a circuit operation corresponding to a signal input / output via an input / output interface circuit adapted to a serial bus is provided with a nonvolatile storage circuit for storing identification information, and an internal state of the internal circuit is determined. When the first state is entered, an operation of changing the identification information by an input signal supplied via the serial bus is included.

The following is a brief description of the outline of still another typical invention among the inventions disclosed in the present application. An information system is provided by a plurality of semiconductor devices each including an internal circuit for performing a circuit operation corresponding to a signal input / output via an input / output interface circuit adapted to a serial bus and a nonvolatile storage circuit for storing identification information. In each semiconductor device, when the internal state of the internal circuit becomes the first state, the individual identification information can be changed by an input signal supplied through the serial bus.

[0010]

FIG. 1 is a schematic block diagram showing one embodiment of a semiconductor device according to the present invention. The semiconductor device (Device) of this embodiment is mounted on a system having a common bus. In other words, an input / output interface circuit adapted to the common bus is provided.
In this embodiment, the device address of the semiconductor device can be set by software by adopting a configuration in which the device address of the semiconductor device is stored in the built-in nonvolatile memory. Although not particularly limited, the common bus is a serial bus such as an IIC bus. Here, IIC (I ² C) is a trademark of Philips.

The device address stored in the nonvolatile memory is transferred to a register. The device address comparison circuit compares the device address held in the register with the device address input through the common bus, and forms a control signal for starting device operation when they match.

The non-volatile memory is not particularly limited, but is an electrically writable and erasable non-volatile memory, which can be rewritten. By this rewriting operation, it is possible to reset the device address in a state where the semiconductor device is mounted on the mounting board constituting the system.

FIG. 2 is a schematic block diagram showing one embodiment of an information processing system using a semiconductor device according to the present invention. In this embodiment, as shown by way of example, an information processing system using at least two substrates C on which two semiconductor devices (Device A, Device B) and (Device M, Device N) are respectively mounted. Is configured. When a plurality of semiconductor devices (Device A to Device N) are mounted on one information processing system as described above, it is necessary to assign different device addresses to each semiconductor device (Device).

In this embodiment, a non-volatile memory is built in as in the embodiment of FIG. This is to make settings in. For this reason, each semiconductor device not only can reduce the number of external terminals for device addresses, but also supports the state in which the semiconductor device is mounted on the system at the time of manufacturing, inventory management, shipping or assembly. It is not necessary to consider the device address at all, and manufacturing and inventory management and system assembly are simplified.

In the configuration in which the device address can be set by software as described above, the board constituting the information processing system can be standardized like the board C. That is, as compared with a case where a device address setting pin is provided on a semiconductor device and the device address setting pin is connected to a power supply voltage VCC line of a mounting substrate or a ground line VSS of a circuit, a plurality of mounting substrates having a wiring pattern corresponding to a device address are used. Since there is no such a wiring pattern on the standardized mounting board C without formation, the board space can be effectively used or the size can be reduced.

FIG. 3 is a block diagram showing one embodiment of an IIC bus interface used in the semiconductor device according to the present invention. In this embodiment, although not particularly limited, an IIC bus interface EEPROM (electrically erasable & programmable read only memory, hereinafter referred to as a serial EEPROM)
Is aimed at.

In the IIC bus interface, 4 bits are assigned as a device code, 3 bits are assigned as a device address, and 1 bit is assigned as R / W for instructing read / write in the first byte of communication following the start condition. The device code is fixed according to the type of each semiconductor device (device).
In the case of a ROM, 4 bits such as 1010 are allocated. Other devices, such as A / D converters, LED drivers, etc., are assigned device codes different from those described above.

Of the input signals supplied through the IIC bus interface, 4 bits corresponding to the device code are input to a device code comparison circuit,
A comparison is made with the assigned fixed device code. This fixed device code is used for the semiconductor device (Devic
e) is fixedly set by wiring etc. at the time of manufacture.
The device code comparison circuit compares the fixedly set device code with the input device code,
If they match, a device code match signal is formed.

Of the input signals supplied through the IIC bus interface, three bits corresponding to the device address are input to a device address comparison circuit and compared with the device address set in the nonvolatile memory. The device address of this nonvolatile memory is set to an arbitrary address by a write operation or a rewrite operation as described later. The device address comparison circuit compares the device address set in the nonvolatile memory with the input device address, and forms a device address match signal if they match.

In the semiconductor device (IIC I / F Device) conforming to the IIC bus interface of this embodiment, when the device code match signal and the device address match signal are formed, the read or write operation is performed in response to the signal R / W. To start. This read or write operation will be described later, but its outline is as follows. An internal address is specified by an address signal included in an input signal that is subsequently input to the input signal including the device code and the device address and the R / W. In a write operation, write data included in the input signal that is subsequently input is captured. A write operation is performed, and in the case of a read operation, read data is output to the IIC bus.

FIG. 4 shows a serial EEP according to the present invention.
A configuration diagram for explaining an example of the operation of the ROM is shown. In the serial EEPROM of this embodiment, the device address is set in a built-in device address memory (non-volatile memory). The power-on reset circuit is
When the power supply voltage VCC reaches a predetermined level, a power-on reset signal is generated. This power-on reset signal is transmitted to the load control logic circuit. When the power-on reset signal is input, the load control logic circuit supplies a device address load signal to the device address memory.

When the device address load signal is supplied, the device address memory reads the stored device address and transfers it to the device address register. As a result, the device address register holds the device address stored in the device address memory.

Therefore, when an input signal as shown in FIG. 3 is supplied to the serial EEPROM via the IIC bus, the device address comparison circuit accesses the device address memory each time and retrieves the device address stored therein. Instead, the device address loaded into the device address register by the power-on reset signal is compared with the input device address. The device address match signal formed by the device address comparison circuit is read / write (repetitive /
Write) is transmitted to the control circuit, and a Read / Write operation start signal is formed.

Although not shown in the figure, the EEPROM includes an address input circuit, an address selection circuit, a memory array, and the like, which are controlled by a control circuit including the above read / write control circuit. It is a thing.

FIG. 5 shows a serial EEP according to the present invention.
A configuration diagram for explaining an example of an address setting operation of the ROM is shown. In the memory map of the serial EEPROM, H'0000 to H'FFFF are allocated, and from H'0000 to H'01FF, the EEPROM memory area is used as a data or program storage area. Remaining address space H'02
From 00 to H'FFFF, a device address memory and an address of a key register are partially allocated, and the rest are reserved.

On the premise of such a memory map address space, a device address rewriting flow (procedure)
Is as follows. In (1), key register access is performed. That is, FIG. 3 through the IIC bus is used.
Is supplied. Device code, device address, and write operation are instructed. As a premise, a temporary device address is written in a device address memory of the serial EEPROM constituted by the nonvolatile memory. This temporary device address is
It is also used for writing and reading memory access in a serial EEPROM probe test or burn-in test after assembly. That is, the serial EE of this embodiment
Since access to the PROM requires input of a device code and a device address, it is necessary to store a temporary device address for the operation test and the like.

An address signal to which the key register is assigned is input using the temporary device address,
In (2), a predetermined key code is input (Writ
e). The internal control circuit compares the key code input to the key register with a preset key code, and if they match, forms a signal permitting access to the device address memory. In (3), an address signal assigned to the device address memory is input,
In (4), a device address different from the temporary device address is input and rewritten.

By adopting such a device address rewriting procedure, an address corresponding to the device address memory is erroneously designated at the time of a normal write operation to the serial EEPROM. It is possible to prevent a part of the device address from being written and the device address to be stored being erroneously rewritten. That is, since the access to the key address register and the key code match, and then the address of the device address memory and the rewritten data are input, the device is not merely erroneously designated in the normal write operation of the serial EEPROM. This is because access to the address memory is not permitted. This allows arbitrary setting or rewriting of the device address while ensuring high reliability.

FIG. 6 is a block diagram showing one embodiment of the information processing system according to the present invention. The information processing system of this embodiment has two ICs on one board having an IIC bus.
One semiconductor device is mounted. Each of the semiconductor devices has a microcomputer (1
Chip microcomputer) and serial EEPROM
OM, and the device address is set to the temporary address n.

When the above two semiconductor devices are mounted on the board, the serial EEPROM has a device address n set in a built-in device address memory, so that address setting on the board becomes unnecessary. Therefore,
The substrate does not require wiring for device address setting corresponding to each semiconductor device mounted thereon, and can be standardized (shared) on condition that the semiconductor device to which the present invention is applied is mounted. Furthermore, the area on the board where the wiring and the like can be reduced can be allocated to mounting of other electronic components, or the board can be made smaller. Microcomputer and serial EEPROM as in this embodiment
If an information processing system consists of only two OMs,
The temporary device address n set in the serial EEPROM can be used as it is.

FIG. 7 is a block diagram showing another embodiment of the information processing system according to the present invention. The information processing system of this embodiment is the same as the II shown in the embodiment of FIG.
One information processing system is configured by combining two boards having the C bus. That is, an information processing system having a multi-CPU configuration is configured by connecting the IIC buses of two boards each having a microcomputer and a serial EEPROM mounted thereon. In such an information processing system,
The device address of the serial EEPROM mounted on one substrate is kept at n, and the device address of the serial EEPROM mounted on the other substrate is
From m to m. Since the change of the device address of the serial EEPROM can be performed on-board, it can be applied even when the system is expanded.

FIG. 8 is a timing chart for explaining a communication protocol in the IIC bus interface. FIG. 1 shows a write operation and a read operation, and these configuration diagrams explain the operation viewed from the master side (for example, the microcomputer side).

In the IIC bus interface, the serial clock (SCL) and the serial input / output (SDA)
It consists of two signal lines. Serial clock (SCL)
Is a clock for setting the timing of serial data input / output, which takes in data at the rise of the clock and outputs data at the fall. FIG. 8 omits the serial clock (SCL).

In the serial input / output terminal of the device, a pull-up resistor is connected to the input / output terminal because the output circuit is constituted by an open drain. Although not particularly limited, the serial EEPROM is provided with a write protect terminal. When the write protect terminal is set to a high level, rewriting of all memory arrays is prohibited. Therefore, when rewriting the memory array, the write protect terminal is set to low level. This write protect terminal is not connected to the serial bus but to a dedicated signal line. A read operation is possible for all memory arrays regardless of the level of the write protect terminal.

The communication protocol (write operation) is as follows. Start condition (start condition) ST
ART is set by changing the serial data (SDA) from high level to low level when the serial clock (SCL) is at high level. START
After that, an 8-bit device address word is transmitted in synchronization with the serial clock (SCL). The device address word has a 4-bit device code,
It is composed of a 3-bit device address and a 1-bit R / W signal. At the time of a write operation, R / W = 0.

In the IIC bus interface, in addition to the device address word, address information and read / write data are transmitted and received in 8-bit units. The acknowledgment signal ACK (Acknowledge) is a signal indicating that the 8-bit data has been normally received, and the receiving side outputs logic 0 (low level) at the ninth clock of the serial clock (SCL). That is, when the master transmits the 8 bits of the device address word, ACK = 0 is transferred at the ninth clock from the serial EEPROM as the slave, and the master receives it.

When the ACK is received, the master transmits the upper 8 bits of the memory address (a15 to a8), and when the ACK corresponding thereto is received, subsequently, the lower 8 bits of the memory address (a7 to a0) are transmitted. Send. ACK corresponding to this memory address lower (a7 to a0)
When the signal is received, the write data (D7 to D0)
Send When an ACK signal corresponding to the write data (D7 to D0) is received, a stop condition (STOP) STOP is transmitted. In the serial EEPROM on the slave side, the write data is written after erasing (erasing) the address. When the serial clock (SCL) is at a high level, the stop condition STOP is set to the serial data (SD).
A) is set by changing A) from a low level to a high level.

In the write operation to the serial EEPROM, the (1) key register access and the (2) key code write of FIG. 5 can be directly performed. That is, the device address specified by the device address word specifies the tentative address (address before rewriting), and the memory address is not the memory area but the key register address (8 × 2). Then, a key code may be input for the write data. Then, input the address (8 × 2) of the device address memory,
For write data, a device address to be rewritten is input. After this, the ACK signal is received from the serial EEPROM and the stop condition (stop condition) STO
Perform P transmission. In the serial EEPROM, the writing operation of the new device address is performed after erasing (erasing) the device address memory.

In this state, a new device address is written in the device address memory, but the previous device address is stored in the device address register.
Power is turned off and then turned on again, or a new device address written in the device address memory is loaded into the device address register by a special signal input as described later.

The communication protocol (read operation) is as follows. A start condition (START) which is the same start condition as described above is input, and an 8-bit device address word is transmitted in synchronization with a serial clock (SCL). The device address word is 4
It comprises a bit device code, a 3-bit device address, and a 1-bit R / W signal. Then R
/ W = 0 (low level). When the ACK corresponding to the device address word is received, the master transmits the upper 8 bits of the memory address (a15 to a8), and when the ACK corresponding thereto is received, subsequently, the lower address of the memory address (a7 to a0) is received. Send 8 bits.
In the operation up to this point, a dummy write operation is performed in spite of the read operation. That is, the dummy write operation is used for inputting an address for a read operation.

The serial EEPROM has an internal address counter, and holds an address (N + 1) obtained by incrementing the last accessed address (N) in the previous read operation or write operation by one address. Therefore, a read operation can be performed using the address (N +). Therefore, it is not necessary to input an address signal each time during a read operation. When setting a new address irrespective of the previous access, the aforementioned dummy write operation is used.

Start condition (STAR)
T) and enter the device address word. That is, when the same device code and device address as described above are input and R / W is set to logic 1, read data D7 to D0 are output from the serial EEPROM after ACK. That is, the read data at the address (N + 1) specified by the dummy write operation is output. When ACK = 1 (the bus may be opened without inputting ACK) after this data output, input in the order of stop condition STOP terminates reading of the serial EEPROM.

If the mode for reading data continuously is set, if ACK is set to logic 0 from the master side, data from the address (N + 2) where the address is incremented by 1 to the above address is transmitted from the serial EEPROM.
When the address of the serial EEPROM becomes the last address, it rolls over to address 0, and continuous data can be read out. To end such a continuous data read operation, as described above, A
When CK = 1 (the bus may be opened without inputting ACK), inputting in the order of stop condition STOP terminates reading of the serial EEPROM.

FIG. 9 shows a serial EEP according to the present invention.
A schematic block diagram of one embodiment of a ROM is shown. Device address memory c. Is composed of a nonvolatile memory as described above, in which 000 is stored as a temporary device address at the time of manufacture. Serial EEPR
When power is supplied to the OM, the power-on reset circuit a.
Monitors the power supply voltage VCC, and when the power supply voltage VCC reaches a certain level, the power-on reset signal k. Occurs.

Control logic circuit b. Is the power-on reset signal k. In response to the load control signal m. Generate. This load control signal m. Is the device address memory c. To input a read operation. Device address memory c. From the device address n. (000) is the device address register d.
Will be forwarded to Thereby, the device address register d. Is the device address n. Is held, and the held device address p. Is a device address comparison circuit e. Tell By such an operation, the device address memory c. Of the device address corresponding to the device address n stored in the. In this state, FIG.
The access to the serial EEPROM as shown in FIG.

The operation of rewriting the temporary device address to an arbitrary address is performed as follows. II
In synchronization with the clock signal SCL of the C bus, the serial data bus SDA serial data x. Corresponding to the start condition and the device address word-memory address upper memory address lower memory write data as shown in FIG. Enter 1. Device address comparison circuit e. Is
A device address (000) included in the device address word and a device address register d. The device address p. (000)
Device address match signal q. To the control logic circuit b. Tell The device codes assigned to the serial EEPROM are also compared, and the condition is that they match.

Control logic circuit b. Is the device address match signal q. (The device code also matches), the key register f.f is assigned from the memory address upper (H'FF) and lower (H'10). Select a write control signal r. And outputs the key code included in the write data to the internal data bus. Thereby, the key register f. Is written with the key code input via the IIC bus.

The key register f. Key code s. Is a key code monitoring circuit g. Conveyed to.
Key code monitoring circuit g. Is a key code set in advance and the key register f. Key code s.
Are compared, and if they match, the device address memory access permission signal t. To generate a control logic circuit b. Tell

From the IIC bus, in synchronization with the clock signal SCL, the serial data bus SDA serial data x corresponding to the start condition and device address word-memory address upper memory address lower memory address-write data as shown in FIG. . Enter 2.

Control logic circuit b. Is the device address match signal q. (The device code also matches), the device address memory c. From the memory address upper (H'FF) and lower (H'09). Is selected and a write control signal u. And the internal data bus has a new device address (1) included in the write data.
01) is output. Thereby, the device address memory c. Is written with the device address input via the IIC bus.

Prior to writing as described above,
The temporary device address 000 is erased. However, if the device address 101 is set by overwriting the temporary address 000 of the nonvolatile memory, the erasing operation can be omitted. That is, if the device address is allowed to be rewritten only once, the erasing operation can be made unnecessary. However, if the device address can be rewritten any number of times, the erasing operation is performed before the writing.

In the above state, the device address memory c. Stores the new device address 101, the device address register d. Holds the loaded device address 000. Therefore, even if the rewritten device address is input as it is, the serial EEPROM cannot be used.
M cannot be accessed. Thus, once the power is turned off and then turned on again, the rewritten device address 101 is stored in the device address register d. To load.

When data is subsequently written to the serial EEPROM, the clock signal S is output from the IIC bus.
As shown in FIG. 8, the start condition and the device address word are synchronized by the serial data bus SDA in synchronization with CL.
Serial data x. Corresponding to memory address upper memory address lower memory address write data Enter 3.

Control logic circuit b. Is the device address match signal q. 5 (H'00) and lower (H'00), select memory cells in the memory area shown in the memory map of FIG. 5 and write control signals (not shown). And outputs write data to the internal data bus. This allows
Data input via the IIC bus is written in the memory area. Prior to the above-described writing, the erasing operation of the memory cell at the address H'0000 is performed.

Although not shown, the serial EEPROM is
A reset signal input terminal may be provided. That is, by setting the reset signal input terminal to a predetermined level, the device address memory c. Is read. In addition, other registers and the like may be initialized by the reset signal input terminal. When such a reset signal input terminal is provided, it is not necessary to turn off and on the power every time the device address is changed. Therefore, when such a reset signal input terminal is provided, the power-on reset circuit can be omitted.

FIG. 10 shows a serial EE according to the present invention.
A schematic block diagram of one embodiment of a PROM is shown.
Device address memory c. Comprises a nonvolatile memory as described above. In this embodiment, the control logic circuit b. Start condition detection circuit a. Is used. This control logic circuit b. Start condition detection circuit a. Is connected to the serial data bus SDA in synchronization with the clock signal SCL as described above.
8 detects the start condition as shown in FIG. 8 and prepares for the input of a device address word to be subsequently input, as well as the load control signal m. To generate a device address memory c. , A read operation is instructed, and the stored device address n. To the device address register d. To transfer. Thereby, the device address comparison circuit e. Performs a comparison operation with a device address input after the start condition.

In this configuration, the device address memory c. Is read out each time according to the start condition, so that when the device address is changed, it is not necessary to turn off and on the power every time. That is, the start condition detection circuit a. Can effectively eliminate the need for the power-on reset circuit. Furthermore, in combination with a power-on reset circuit and a reset input signal terminal, a control register (not shown) initialized by the reset signal is provided, and one of the information in the control register indicates whether or not the device address has been transferred. By updating the information in accordance with the transfer of the device address, the device address can be transferred only once after the reset.

FIG. 11 shows a configuration diagram of an embodiment of the information processing system according to the present invention. In this embodiment, the microcomputer chip and the EEPROM are not particularly limited.
The M chip is configured as one semiconductor device having a laminated structure. The microcomputer chip and the EEPROM chip thus integrally sealed are internally connected by bonding wires corresponding to the IIC bus. A microcomputer on which the above-mentioned EEPROM chips are stacked is connected to an LIC as another peripheral device via an IIC bus formed on a substrate.
LCD with CD (Liquid Crystal Display) driver chip
Connected with driver. Although not particularly limited, the above LC
The D driver is composed of a CMOS device.

When the information processing system has a plurality of peripheral devices such as an EEPROM and an LCD driver, it is necessary to assign a different device address to each device. As in this embodiment, EE
A device address suitable for the system can be assigned to the PROM chip and the LCD driver by storing the device address in the device address memory of the built-in nonvolatile memory as described above. In such a configuration in which the device address is stored in the built-in nonvolatile memory, an address terminal for setting the device address is not required on the semiconductor device side, and the high-level / low-level for the device address is stored in the address terminal on the substrate side. This eliminates the need for wiring for transmission.

FIG. 12 is a block diagram of each semiconductor chip corresponding to a peripheral circuit constituting the information processing system of FIG. EEPROM memory is IIC
Bus interface circuit (IIC Bus I / F)
And a logic control circuit (Control lo) as described above.
gic), device address memory (DA Memo)
ry) and the device address register (DA Res)
istor) and a memory matrix (Memory Matrix) forming a memory area. The device address memory (DA Memory)
Is a Memory Matrix
x) is configured by using the same memory cells as the memory cells configuring (i).

The LCD driver includes an IIC bus interface circuit (IIC Bus I / F), a logic control circuit (Control logic), a device address memory (DA Memory), and a device address register (DA Resistor). , An LCD driver circuit (LCD Driver logic). Since the LCD driver is formed of a CMOS circuit, a nonvolatile memory iFlash memory having a single-layer gate structure that can be manufactured by a CMOS process is used as described later.

FIG. 13 is a schematic sectional view of one embodiment of the nonvolatile memory element used in the present invention.
The MONOS type memory cell and the FLOTOX type memory cell both have a floating gate for storing information charges,
The control gate and the control gate are arranged in a stacked configuration. In the case of an EEPROM in which a memory area is formed using such a memory cell having a two-layer gate structure, a device address memory can be formed using the process of the memory cell as it is. However, in a semiconductor device formed by a CMOS process like the LCD driver, the gate electrode is formed as a single layer, so it is necessary to add a process having a two-layer gate structure only for a device address memory.

On the other hand, in the iFlash type memory cell, the gate formed at the same time as the gate of the N-channel type MOSFET is a floating gate (Floati).
nggate), and a control gate (Control gate) which is capacitively coupled thereto is constituted by an n-type diffusion layer formed in the semiconductor region. This n-type diffusion layer is formed simultaneously with the source and drain diffusion layers of the MOSFET. The floating gate extends as it is and is formed integrally with the floating gate as shown on the right side of the figure, and the floating gate is formed so as to straddle the source and drain diffusion layers. That is, the left sectional view of the iFlash type memory cell is formed in a direction different from the right sectional view by 90 ° in plan view. Because of this single-layer gate structure, it is also called a non-volatile memory having a single-layer gate structure. Regarding the iFlash type memory cell, Japanese Patent Application No. 11-23631, Japanese Patent Application No. 12-38167,
Details are described in Japanese Patent Application No. 12-71079.

The EEPROM is of the MONOS type or FL type.
In addition to the OTOX type, a MOSFET for address selection, that is, a MOSF having a select gate shown in FIG.
The ET may be omitted. Thus, EEP
A nonvolatile memory cell constituting a ROM can employ various embodiments.

FIG. 14 is a schematic plan view of one embodiment of the semiconductor device according to the present invention. In this example, QFP (Q uad F latpack P ackage) type semiconductor device is directed to, it is a state in which the top was removed of the resin sealing body of a semiconductor device that shown schematically. In FIG.
FIG. 15 shows a schematic cross-sectional view substantially along the cutting line aa in FIG. 14. In FIG. 15, each cutting line is partially bent so that a bonding wire and two semiconductor chips appear.

The QFP type semiconductor device 30A of this embodiment
Means two semiconductor chips (microcomputer chip 10, EE
PROM chips 20) are stacked vertically, and the two semiconductor chips are sealed with one resin sealing body 17.

The microcomputer chip 10 and the EEPROM chip 20 are formed in different plane sizes (outer dimensions), and each plane is formed in a square shape. In the present embodiment, the planar shape of the microcomputer chip 10 is, for example, a rectangle of 4.05 [mm] × 4.15 [mm], and the planar shape of the EEPROM chip 20 is, for example, 1.99 [mm] × 1. .23 [mm]. That is, the planar size of the EEPROM chip 20 is smaller than the planar size of the microcomputer chip 10. Here, the plane size means the size of the circuit formation surface, and the area of the circuit formation surface is an EEPROM.
Chip 20 is smaller than microcomputer chip 10.

The microcomputer chip 10 and the EEPROM chip 20 include, for example, a semiconductor substrate made of single-crystal silicon, and a multilayer wiring layer formed by stacking a plurality of insulating layers and wiring layers on the circuit forming surface of the semiconductor substrate. And a surface protective film (final protective film) formed so as to cover the multilayer wiring layer.

A plurality of bonding pads 1 are provided on the circuit forming surface 10A of the opposing circuit forming surface (one main surface) 10A and the back surface (the other main surface) of the microcomputer chip 10.
1 is formed. This plurality of bonding pads 1
1 is formed in the uppermost wiring layer of the multilayer wiring layers of the microcomputer chip 10. The uppermost wiring layer is covered with a surface protection film formed thereon, and a bonding opening for exposing the surface of the bonding pad 11 is formed in the surface protection film.

A plurality of bonding pads 21 are formed on the circuit forming surface 20A of the circuit forming surface (one main surface) 20A and the back surface (the other main surface) of the EEPROM chip 20 which face each other. The plurality of bonding pads 21 are formed on the uppermost wiring layer of the multilayer wiring layers of the EEPROM chip 20. The uppermost wiring layer is covered with a surface protective film formed thereon, and a bonding opening exposing the surface of the bonding pad 21 is formed in the surface protective film.

The plane shapes of the bonding pads 11 of the microcomputer chip 10 and the bonding pads 21 of the EEPROM chip 20 are, for example, 65 [μm] × 65 [μ].
m]. Microcomputer chip 10
Are arranged along four sides of the microcomputer chip 10. EEPROM
The plurality of bonding pads 21 of the chip for
The PROM chips 20 are arranged along four sides.

The EEPROM chip 20 is an EEPROM chip 20.
The M chip 20 is disposed on the circuit forming surface 10A of the microcomputer chip 10 with the back surface, which is the other main surface, facing the circuit forming surface 10A of the microcomputer chip 10. 10 circuit forming surfaces 10
A is adhesively fixed. In the present embodiment, as the adhesive layer 15, for example, a polyimide-based adhesive resin film is used.

The microcomputer chip 10 is bonded and fixed to the die pad 5 with an adhesive layer interposed therebetween, with the back surface facing the die pad 5. Four suspension leads 6 are integrated with the die pad 5, and the die pad 5 and the four suspension leads 6 constitute the support 4.

The planar shape of the resin sealing body 17 is formed in a square shape. In the present embodiment, the planar shape of the resin sealing body 17 is formed, for example, as a square of 10 [mm] × 10 [mm]. The resin sealing body 17 is formed of, for example, an epoxy resin to which a phenol curing agent, silicone rubber, a filler, and the like are added for the purpose of reducing stress. In forming the resin sealing body 17, a transfer molding method suitable for mass production is used.
The transfer molding method is a method of using a molding die having a pot, a runner, an inflow gate, a cavity, and the like, and injecting a resin from the pot into the cavity through the runner and the inflow gate to form a resin sealing body. .

Around the microcomputer chip 10, a plurality of leads 2 arranged along each side of the resin sealing body 17 are arranged. Each of the leads 2 has an internal lead (inner lead) and an external lead (outer lead) formed integrally with the internal lead. The internal lead portion of each lead 2 is a resin sealing body 1
7, and the external lead portion is located outside the resin sealing body 17. That is, the plurality of leads 2 are connected to the resin sealing body 1.
7 extends inside and outside of the base member 7. The external lead portion of each lead 2 is formed by bending into, for example, a gull-wing type lead shape, which is one of the surface mount type lead shapes.

The above-mentioned microcomputer chip 10 and EEPROM
Each bonding pad is commonly connected to a lead 2 connected to the IIC bus of the chip 20 for use. That is, the clock SCL and the serial data SDA
Are connected between the microcomputer chip 10 and the corresponding bonding pads of the EEPROM chip 20 by bonding wires 16 and 16, respectively. . That is, the two bonding wires 16 are connected to the IIC bus structure inside the semiconductor device.

FIG. 16 is a block diagram showing one embodiment of the information processing system according to the present invention. The microcomputer chip 10 includes a processor unit (CPU), an RO
M unit (ROM), RAM unit (RAM), timer unit (TIM), A / D conversion unit (A /
D), a serial communication interface unit (SCI), a data input / output circuit unit (I / O) and the like are mounted on the same semiconductor substrate. These units are interconnected via a data bus 18A and an address bus 18B. The processor unit (CPU) mainly includes a central processing unit, a control circuit unit, an arithmetic circuit unit, and the like. The microcomputer chip 10 configured as described above operates according to a program stored in, for example, a ROM unit (ROM).

The EEPROM chip 20 is a serial chip.
Communication interface unit (S
CI) and a nonvolatile memory unit (EEPROM) are mounted on the same semiconductor substrate. The serial communication interface unit (SCI) includes the control logic circuit, the device address memory register, and the comparison circuit.

The EEPROM chip 20 has, among the plurality of bonding pads 21, a serial data (SDA) bonding pad 21A and a serial clock (SCL) bonding pad 21B which are signal terminals. The microcomputer chip 10 has serial data (SDA) bonding pads 11A and serial clock (SCL) bonding pads 11B, which are signal terminals, among the plurality of bonding pads 11.

The SDA bonding pad 21A of the microcomputer chip 10 is connected to the SDA bonding pad 21A of the EEPROM chip 20 via the signal transmission path 25A.
A of the EEPROM chip 20 electrically connected to
The CL bonding pad 21B is connected to the signal transmission path 25B.
Is electrically connected to the SCL bonding pad 11B of the microcomputer chip 10.

Serial data is written into the nonvolatile memory unit (EEPROM) of the EEPROM chip 20 by the operation of the microcomputer chip 10. That is, E
The nonvolatile storage unit (EE) of the EPROM chip 20
In a PROM, a write operation and a read operation are controlled by a control signal from a processor unit (control circuit) of the microcomputer chip 10. The signal transmission paths 25A and 25B are formed by the internal lead portions and two bonding wires. That is, FIG.
Are electrically connected to the internal lead portions of the leads 2 via the bonding wires 16 as described above.

That is, the microcomputer chip 10 and the EEPROM
The electrical connection with the M chip 20 is made by an inner portion of the lead 2 and two bonding wires 16 inside the resin sealing body 17. With such a configuration, a lead frame developed for the microcomputer chip 10 can be used as it is, so that it is not necessary to newly develop a lead frame for each type of the microcomputer chip 10. Also, EEPROM
It is not necessary to develop a microcomputer chip provided with an EEPROM bonding pad for electrically connecting to the chip 20 for each product type.

The serial data signal is output from the SDA bonding pad 11 A of the microcomputer chip 10, and is transmitted through the bonding wire 16, the lead 2 and the bonding wire 16 to the SDA of the EEPROM chip 20.
Is input to the bonding pad 21A. The serial clock signal is output from the SCL bonding pad 11B of the microcomputer chip 10, and is connected to the EE via the bonding wire 16, the lead 2, and the bonding wire 16.
SCL bonding pad 2 of PROM chip 20
1B.

In this embodiment, two EEPROMs 1 and 2 are provided. One EEPROM 1 is attached to the microcomputer chip 10 in a laminated structure as shown in FIG. 14, and is integrally sealed. In contrast, the hatched EEPROM 2 is an external expansion memory. The EEPROM 1 and the EEPROM 2 are composed of the same semiconductor chip. The EEPROM 1 has a laminated structure with the microcomputer chip 10 as described above.
The ROM 2 is a single semiconductor device. Such an expansion EEPROM 2 is mounted on a mounting board such as the one described above and connected to the IIC bus.

In this embodiment, the EEPROMs 1 and E
Since the EPROM 2 is mounted on one information processing system, it is necessary to set different device addresses for each. By rewriting the device address memory as described above, one may be kept at the temporary device address of 000 as described above and the other may be rewritten to a different device address as 101.

FIG. 17 shows a serial EE according to the present invention.
A timing chart for explaining an example of the operation of the PROM is shown. This embodiment corresponds to the embodiment of FIG. As described above, the control logic circuit b.
Is a power-on reset circuit a. The power-on reset signal k. Receiving the device (EEPRO
M) Device address memory c. Is selected, the device address stored therein is read, and the device address register d. To be stored.

In the figure, a period 1 is a rising period of the power supply voltage Vcc, and a timing A is a load operation start point, that is, a power-on reset release point. At this timing A, the predetermined voltage before the power supply voltage Vcc rises to the steady voltage and the power supply fluctuation allowable value is Vc
If c ± 10%, it is detected that the power supply voltage has reached a predetermined voltage equal to or lower than the minimum voltage, and the reset signal generated in response to the rise of the power supply voltage Vcc is output when the predetermined voltage is reached. To generate a power-on reset signal.

In response to the fall (reset release) of the power-on reset signal, the control logic circuit b. Is
Device address memory c. Corresponding to the internal clock signal as described above. Is selected, the device address stored therein is read, and the device address register d. Is a load operation time. The timing B is a timing at which the loading operation is completed, and the timing from this point is the device usable point.

For example, in period 3, when the external clock signal (SCL) of the IIC bus is at the high level, the external input / output signal (SDA) changes from the high level to the low level, so that the start condition input (Start) is changed. Is set. Thereafter, a device address input period 4 in which a device address word of 8 bits is input is set in accordance with the external clock signal. That is, a 4-bit device code and a 3-bit device address are input, and then, in period 5, the eighth bit write / read mode setting (internally, device address comparison is performed) is set. Then, in period 6 of the ninth bit,
An acknowledge = 0 is sent from the EEPROM, and the device address result is output internally.

The power-on reset circuit a. Is used, in order to generate the power-on reset signal, a voltage set with a certain margin in consideration of the fluctuation of the power supply voltage Vcc is used. Therefore, when the operating voltage of the EEPROM is lowered, the power supply voltage Vcc when the power-on reset signal is generated is generated.
Is even lower. For example, when the power supply voltage Vcc is a relatively high voltage of about 3.3 V, the power-on / reset release voltage can be set to a relatively high voltage such as 2.5 to 2.6 V.

However, when the power supply voltage is 2.0 to 2.5
At a relatively low voltage of about V, the power-on
The reset release voltage is set to a low voltage such as 1.5 to 1.8V. When reset is released at such a low voltage and an attempt is made to access the device address memory as described above, the voltage required for the read operation is insufficient, and the possibility of a malfunction such that a correct device address cannot be read is reduced. Will have. Therefore, the start condition detecting circuit a. To the control logic circuit b. And reading the device address using an external clock signal is advantageous from the viewpoint of preventing malfunction in the case of a device operating at a low voltage (2.0 to 2.5 V).

FIG. 18 shows a serial EE according to the present invention.
A timing chart for explaining another example of the operation of the PROM is shown. This embodiment corresponds to the embodiment of FIG. As described above, the start condition detection circuit a. To the control logic circuit b. The device address is read out using an external clock signal.

In the figure, a period 1 is a rising period of the power supply voltage Vcc as described above, and a timing b is a device usable point at which the power supply voltage Vcc reaches a steady voltage. In this embodiment, without holding a valid device address in the device address register,
The device is brought into a usable state. Therefore, in period 3, when the external clock signal (SCL) of the IIC bus is at the high level, the external input / output signal (SDA) changes from the high level to the low level, so that the start condition input (Start) is set. .

Thereafter, in response to the external clock signal,
A device address input period 4 in which an 8-bit device address word is input is set. That is, 4
The device code of 3 bits and the device address of 3 bits are input, and then, in period 5, the 8th bit write / read mode setting (internally, device address comparison is performed) is set. Then, in a period 6 of the ninth bit, the acknowledge signal = 0 is transmitted from the EEPROM, and the device address result is output internally.

Control logic circuit b. Start condition detection circuit a. When the start condition input input in the period 3 is detected, the clock signal is output in the period 2 in parallel with the device address input included in the period 4 before the device address comparison in the 8th bit is performed. Using a device (EEPROM) internal signal, a device address memory c. Is selected, the device address stored therein is read, and the device address register d. Is to be stored.

In this embodiment, although not particularly limited, in the subsequent 1st address input period 7, the loading operation of the trimming data is performed in the period 2 'newly provided after the acknowledgment = 0 of the period 6 is transmitted. Will be implemented. As this trimmed data, trimming data for compensating for the process variation of the device is stored in a memory device similar to the device address memory, and is read out to be used for compensating the process variation of the circuit.

Although not particularly limited, the EEPROM incorporates a power supply circuit for forming a high voltage for writing or a high voltage for erasing by a charge pump circuit. Since the write voltage or the erase voltage is an important parameter that determines the write amount or the erase amount of the storage element, the voltage needs to be set with high accuracy. However, since it is difficult to set a desired voltage due to manufacturing variations of the MOSFET, trimming data for compensating the voltage is stored in a non-volatile memory, and when the circuit starts operating, it is read out to perform voltage control. By doing so, it is possible to realize a stable writing and erasing operation which is not affected by the process variation of the element.

FIG. 19 shows a serial EE according to the present invention.
A timing chart for explaining another example of the operation of the PROM is shown. This embodiment corresponds to period 2 in FIG.
And the control logic circuit corresponding to the period 2 ′ b. Of the device address loading and the trimming data loading according to FIG.

Clock signal SCL and serial data SD
When the start condition is set by A, the start condition detection circuit a
In the first cycle (device address input period) from the first clock to the ninth clock of the clock signal SCL, the word line selection of the device address is performed at the third clock, and the 8-bit data is changed at the fourth clock. The data is output to the bus D [7: 0], and the device address SLA [2: 0] composed of 3-bit data is stored in the device address register.

Subsequently, in the second cycle (1st memory address input period) from the 1st clock to the 9th clock of the clock signal SCL, the trimming memory word line is selected at the third clock, and the 8-bit data is output at the fourth clock. The data is output to the data bus D [7: 0], and trimming data M composed of 5-bit data is output.
[4: 0] is stored in the trimming register.

As described above, according to the present embodiment, the following effects can be obtained. (1) A nonvolatile memory circuit for storing identification information is provided in a semiconductor device having an internal circuit that performs a circuit operation corresponding to a signal input / output via an input / output interface circuit suitable for a serial bus, The internal identification information stored in the storage circuit is compared with the external identification information included in the input signal supplied via the serial bus by a comparison circuit, and the internal identification information is continuously supplied via the serial bus by the match detection signal. A control circuit that performs a circuit operation in response to an input signal including a change in internal information of the nonvolatile storage circuit also includes a user-friendly operation.
An effect is obtained that a semiconductor device in which flexible device address setting is possible can be obtained.

(2) In addition to the above, the internal identification signal is read out on condition that the identification information stored in the nonvolatile storage circuit is in a predetermined state, and is transferred to the predetermined storage circuit, thereby stably. In addition, an effect is obtained that a high-speed device address can be determined.

(3) In addition to the above, by providing a supply voltage detecting circuit for receiving a power supply voltage, detecting that the power supply voltage has risen to the first level, and creating the predetermined state, it is possible to achieve a stable and stable operation. An effect is obtained that high-speed device address determination can be performed.

(4) In addition to the above, a reset signal input terminal is provided, and the signal level is set to a predetermined level to set the predetermined state, thereby loading the rewritten device address into the device address register. Therefore, it is possible to eliminate the trouble of temporarily turning off and then turning on the power supply voltage, and to eliminate the need for a special supply voltage detection circuit, thereby simplifying the circuit.

(5) In addition to the above, the circuit can be simplified by setting the predetermined state by a predetermined input signal supplied via a serial bus after the power is turned on. Is obtained.

(6) In addition to the above, as a circuit operation by the control circuit, an operation of rewriting identification information in the nonvolatile memory circuit in response to the input signal and an operation of rewriting the internal circuit in response to the input signal By including the directed operation, it is possible to obtain an effect that the device address can be set using the serial bus standard as it is.

(7) In addition to the above, further comprising a second input / output interface circuit adapted to the serial bus, and a signal processing circuit provided via the second input / output interface circuit. The first input / output interface circuit and the signal processing circuit are mounted on a first semiconductor chip, and the first input / output interface circuit, the internal circuit, the nonvolatile memory circuit, the comparison circuit, and the control circuit are provided on the main surface of the first semiconductor chip. By stacking and integrally sealing the second semiconductor chip on which the semiconductor chip is mounted, an effect that a low-cost, small-sized and high-performance semiconductor device can be obtained can be obtained.

(8) In addition to the above, a first bonding wire for connecting a lead and a bonding pad corresponding to a second input / output interface circuit of the first semiconductor chip, and a first bonding wire of the second semiconductor chip. By forming a serial bus connecting between two semiconductor chips by a bonding pad corresponding to the output interface circuit and a second bonding wire connecting the lead, the combination of the two semiconductor chips can be made flexibly and easily. There is an effect that it can be performed.

(9) In addition to the above, the first semiconductor chip includes a processor unit and a ROM in which a procedure of signal processing by the processor unit is written, and the second semiconductor chip stores the identification information. By using a memory circuit to which an address space different from that of the nonvolatile memory circuit to be used is assigned, it is possible to obtain a small and high-performance semiconductor device while flexibly adapting to an information processing system.

(10) In addition to the above, by configuring the memory circuit using memory cells having the same structure as the nonvolatile memory circuit in which the identification information is stored, two circuits formed by different semiconductor processes can be used. Thus, an effect is obtained that one semiconductor device having the above can be rationally manufactured.

(11) In addition to the above, the internal circuit
It can be said that the manufacturing process can be rationalized by using a nonvolatile memory cell having a single-layer gate structure formed by the manufacturing process of the CMOS circuit as the OS circuit and the nonvolatile storage circuit storing the identification information by the manufacturing process of the CMOS circuit. The effect is obtained.

(12) In addition to the above, the internal identification information is referred to as first internal identification information and second internal identification information, and the third external identification information included in the first input signal supplied via the serial bus is: Comparing the first internal identification information stored in the nonvolatile storage circuit with the first internal identification information, and if the first internal identification information matches the third external identification information, the fourth external identification information included in the first input signal The information is compared with the second internal identification information stored in the nonvolatile storage circuit, and provided that the second internal identification information and the fourth external identification information coincide with each other, The control circuit and the comparison circuit perform the operation of changing the first internal identification information in accordance with the second input signal supplied through the device, thereby changing the device address with high reliability. To do The effect that it can be obtained is obtained.

(13) A nonvolatile memory circuit for storing identification information is provided in a semiconductor device having an internal circuit for performing a circuit operation corresponding to a signal input / output via an input / output interface circuit adapted to a serial bus. In addition, when the internal state of the internal circuit becomes the first state, an operation of changing the identification information by an input signal supplied through the serial bus is included, so that an easy-to-use and flexible device address can be provided. The effect is obtained that a semiconductor device in which setting is enabled can be obtained.

(14) In addition to the above, the internal identification information is first internal identification information and second internal identification information, and the third external identification information included in the first input signal supplied via the serial bus is: Comparing the first internal identification information stored in the nonvolatile storage circuit with the first internal identification information, and if the first internal identification information matches the third external identification information, the fourth external identification information included in the first input signal The information is compared with the second internal identification information stored in the nonvolatile storage circuit, and provided that the second internal identification information and the fourth external identification information coincide with each other, The operation of changing the first internal identification information by the second input signal supplied through the internal circuit is performed by the internal circuit, thereby changing the device address with high reliability. It is possible The effect is obtained.

(15) In addition to the above, by using the IIC bus as the serial bus, signals can be transmitted and received through two signal lines, and an effect that the system can be easily constructed can be obtained.

(16) A plurality of circuits each including an internal circuit for performing a circuit operation corresponding to a signal input / output via an input / output interface circuit adapted to a serial bus, and a nonvolatile storage circuit for storing identification information. An information system is constituted by semiconductor devices, and in each semiconductor device, when the internal state of the internal circuit becomes the first state, the individual identification information can be changed by an input signal supplied via the serial bus. By doing so, the device address can be set, and the information processing system can be flexibly adapted to a change or expansion of the system, while effectively utilizing the mounting space of the board constituting the system or reducing the size. The effect that it can be obtained is obtained.

(17) In addition to the above, the identification information of each semiconductor device is defined as first identification information and second identification information, and the third identification information included in the first input signal supplied via the serial bus is used.
The identification information is compared with the first identification information stored in the nonvolatile storage circuit, and when the first identification information and the third identification information match, the fourth identification information included in the first input signal is output.
The identification information is compared with the second identification information stored in the non-volatile storage circuit, and provided that the second identification information and the fourth identification information match via the serial bus following the first input signal, provided that the second identification information matches the fourth identification information. By setting the identification information of each semiconductor device to information different from each other by the second input signal supplied as described above, it is possible to obtain an effect that the device address can be set with high reliability. .

(18) In addition to the above, by using the IIC bus as the serial bus, signals can be transmitted and received by two signal lines, and an effect that the system can be easily constructed can be obtained.

As described above, the invention made by the present inventors is described below.
Although specifically described based on the embodiment, the present invention
The present invention is not limited to the above-described embodiment, and can be variously changed without departing from the gist thereof. For example, as the serial bus, in addition to the above-mentioned IIC bus, a CAN bus standard used mainly for automobiles, a serial ATA for a personal computer, a USB, or a bus such as IEEE 1394 can be similarly used.

The device address memory may use an electrically cut fuse or the like in addition to the above-mentioned nonvolatile memory. However, in this case, 1
Since only one-time writing is possible, a rewritable nonvolatile memory is superior in terms of usability.
INDUSTRIAL APPLICABILITY The present invention can be widely used in various semiconductor devices requiring a device address and an information processing system using a serial bus for accessing a peripheral device using the device address. For example, a system in which a plurality of devices are connected via such a serial bus is a notebook personal computer to which a plurality of battery units can be connected, and each battery unit is connected to the serial bus. And those that allow battery consumption to be monitored. Another example is an audio device or the like mounted on an automobile, in which a device installed later by a driver is mutually distinguished from a device installed earlier.

[0121]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. A nonvolatile memory circuit for storing identification information is provided in a semiconductor device having an internal circuit that performs a circuit operation corresponding to a signal input / output via an input / output interface circuit adapted to a serial bus, and the nonvolatile memory circuit includes The stored internal identification information is compared with the external identification information included in the input signal supplied through the serial bus by a comparison circuit, and the input signal continuously supplied through the serial bus according to the match detection signal. By including the change of the internal information of the nonvolatile memory circuit by the control circuit which performs the circuit operation in response to the above, it is possible to obtain a semiconductor device which is easy to use and in which the device address can be set flexibly.

A nonvolatile memory circuit for storing identification information is provided in a semiconductor device having an internal circuit for performing a circuit operation corresponding to a signal input / output via an input / output interface circuit suitable for a serial bus, When the internal state of the device becomes the first state, an operation of changing the identification information by an input signal supplied through the serial bus is included, so that the device address can be set easily and flexibly. In this manner, a semiconductor device having a reduced size can be obtained.

A plurality of semiconductor devices each having an internal circuit for performing a circuit operation corresponding to a signal input / output via an input / output interface circuit adapted to a serial bus and a nonvolatile storage circuit for storing identification information. By configuring an information system, in each semiconductor device, when the internal state of the internal circuit becomes the first state, the individual identification information can be changed by an input signal supplied through the serial bus. A device address can be set, an effective use of a mounting space of a board constituting the system or a reduction in size can be achieved, and an information processing system which can flexibly adapt to changes or expansion of the system can be obtained. .

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing one embodiment of a semiconductor device according to the present invention.

FIG. 2 is a schematic block diagram showing one embodiment of an information processing system using a semiconductor device according to the present invention.

FIG. 3 is an IIC used in the semiconductor device according to the present invention;
FIG. 2 is a configuration diagram illustrating an embodiment of a bus interface.

FIG. 4 is a configuration diagram for explaining an example of the operation of the serial EEPROM according to the present invention;

FIG. 5 is a configuration diagram for explaining an example of an address setting operation of the serial EEPROM according to the present invention.

FIG. 6 is a configuration diagram showing an embodiment of an information processing system according to the present invention.

FIG. 7 is a configuration diagram showing another embodiment of the information processing system according to the present invention.

FIG. 8 is a timing chart for explaining a communication protocol in the IIC bus interface.

FIG. 9 is a schematic block diagram showing one embodiment of a serial EEPROM according to the present invention.

FIG. 10 is a schematic block diagram showing one embodiment of a serial EEPROM according to the present invention.

FIG. 11 is a configuration diagram showing one embodiment of an information processing system according to the present invention.

FIG. 12 is a block diagram showing one embodiment of each semiconductor chip corresponding to a peripheral circuit constituting the information processing system of FIG. 11;

FIG. 13 is a schematic sectional view showing one embodiment of a nonvolatile memory element used in the present invention.

FIG. 14 is a schematic plan view showing one embodiment of the semiconductor device according to the present invention.

FIG. 15 is a schematic sectional view taken substantially along the line aa of FIG. 14;

FIG. 16 is a block diagram showing an embodiment of an information processing system according to the present invention.

FIG. 17 is a timing chart for explaining an example of the operation of the serial EEPROM according to the present invention.

FIG. 18 is a timing chart for explaining another example of the operation of the serial EEPROM according to the present invention.

FIG. 19 is a timing chart for explaining another example of the operation of the serial EEPROM according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Frame main body, 2 ... Lead, 3 ... Dam bar, 4 ... Support, 5 ... Die pad, 6 ... Hanging lead, 10 ... Microcomputer chip, 11 ... Bonding pad, 15 ... Adhesive layer, 16 ... Bonding wire, 17 ... Resin sealing body, 2
0: EEPROM chip, 21: bonding pad, CPU: processor unit, ROM: ROM unit, RAM: RAM unit, TIM: timer, A /
D: A / D converter, SCI: Serial communication interface.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 (72) Inventor Shinji Kobayashi 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Inside Hitachi North Sea Semiconductor ( 72) Inventor Naoki Fujita 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Within Hitachi Hokkai Semiconductor Co., Ltd. (72) Inventor Masanobu Kawamura 5-2-1 Kamimizu Honcho, Kodaira-shi, Tokyo Within Hitachi Semiconductor Group 72) Inventor Toru Ishida 5-2-1, Josuihoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5B060 MM11 5F038 BG05 DF01 DF04 DF05 DF20 EZ20

Claims (18)

[Claims] A first input / output interface circuit adapted to a serial bus; and an internal circuit for performing a circuit operation corresponding to a signal input / output via the first input / output interface circuit between the first input / output interface circuit and the serial bus. A circuit, a nonvolatile storage circuit storing the identification information, and comparing the internal identification information stored in the nonvolatile storage circuit with the external identification information included in the input signal supplied via the serial bus. A comparison circuit; and a control circuit that responds to an input signal continuously supplied through the serial bus by a match detection signal of the comparison circuit and performs a circuit operation corresponding to the input signal. Semiconductor device. 2. The internal identification information according to claim 1, wherein the internal identification information is read out on condition that the identification information stored in the nonvolatile storage circuit is in a predetermined state and transferred to a predetermined storage circuit. A semiconductor device, comprising: 3. The supply voltage detection circuit according to claim 2, further comprising a supply voltage detection circuit receiving a power supply voltage, wherein the predetermined state is that the supply voltage detection circuit detects that the power supply voltage has risen to a first level. A semiconductor device characterized by being set by: 4. The semiconductor device according to claim 2, wherein the predetermined state is set by a predetermined input signal supplied via a serial bus after power-on. 5. The semiconductor device according to claim 2, further comprising a reset signal input terminal, wherein the predetermined state is set by inputting a predetermined signal to the reset signal input terminal. 6. The circuit operation according to claim 1, wherein the control circuit operates in response to the input signal to rewrite identification information in the nonvolatile memory circuit, and in response to the input signal. A semiconductor device including an operation directed to the internal circuit. 7. The wiring means according to claim 1, wherein one end of the wiring means is adapted to the serial bus and one end of which is connected to the first interface circuit, and the other end of which is connected to the other end of the wiring means. And a signal processing circuit provided via the second input / output interface circuit, wherein the second input / output interface circuit and the signal processing circuit are mounted on a first semiconductor chip, The first input / output interface circuit, the internal circuit and the nonvolatile memory circuit, the comparison circuit and the control circuit are mounted on the second semiconductor chip, and the first semiconductor chip and the second semiconductor chip are integrally sealed. A semiconductor device characterized by the above-mentioned. 8. The semiconductor device according to claim 7, wherein the wiring means comprises: a first bonding wire connecting a bonding pad corresponding to a second input / output interface circuit of the first semiconductor chip to a lead; A semiconductor device comprising: a bonding pad corresponding to a first input / output interface circuit; and a second bonding wire connecting the lead. 9. The signal processing circuit according to claim 7, wherein the signal processing circuit of the first semiconductor chip includes a processor unit and a ROM in which a procedure of signal processing by the processor unit is written. A semiconductor device, wherein the internal circuit includes a memory circuit in which an address space different from that of the nonvolatile storage circuit storing the identification information is allocated. 10. The semiconductor device according to claim 9, wherein the memory circuit is configured using a memory cell having the same structure as a nonvolatile memory circuit in which the identification information is stored. 11. The non-volatile memory circuit according to claim 1, wherein the internal circuit is configured by a CMOS circuit, and the nonvolatile memory circuit storing the identification information is the C circuit.
A semiconductor device comprising a nonvolatile memory cell having a single-layer gate structure formed by a manufacturing process of a MOS circuit. 12. The internal identification information according to claim 1, wherein the internal identification information includes first internal identification information and second internal identification information, and the comparison circuit and the control circuit are connected via a serial bus. Third external identification information included in the supplied first input signal;
The first internal identification information stored in the nonvolatile memory circuit is compared with the first internal identification information. If the first internal identification information matches the third external identification information, the fourth internal identification information is included in the first input signal.
The external identification information is compared with the second internal identification information stored in the nonvolatile storage circuit, and the second internal identification information and the fourth external identification information are followed by the first input signal. A semiconductor device wherein an operation of changing the first internal identification information is enabled by a second input signal supplied via a serial bus. 13. An input / output interface circuit adapted for a serial bus, an internal circuit for performing a circuit operation corresponding to a signal input / output via the input / output interface circuit between the serial bus and the serial bus; A non-volatile storage circuit to be stored, wherein the internal circuit has a configuration in which, when the internal state becomes the first state,
A semiconductor device comprising an operation of changing the identification information by an input signal supplied via the serial bus. 14. The identification information according to claim 13, wherein the identification information has first identification information and second identification information, and the internal circuit is configured to receive the first identification information supplied via a serial bus.
The third identification information included in the input signal is compared with the first identification information stored in the nonvolatile storage circuit. If the first identification information and the third identification information match, the first input signal is Is compared with the second identification information stored in the nonvolatile storage circuit, and the first state is established on condition that the second identification information matches the fourth identification information. A semiconductor device, wherein an operation of changing the first identification information is enabled by a second input signal supplied via a serial bus following one input signal. 15. The semiconductor device according to claim 1, wherein the serial bus is an IIC bus. 16. An input / output interface circuit adapted for a serial bus, an internal circuit for performing a circuit operation corresponding to a signal input / output via the first input / output interface circuit with the serial bus, A plurality of semiconductor devices each including a nonvolatile storage circuit for storing identification information, wherein an internal circuit of each of the semiconductor devices is supplied via the serial bus when the internal state becomes the first state. An information processing system for performing an operation of changing the identification information according to a received input signal. 17. The semiconductor device according to claim 16, wherein the identification information of each of the semiconductor devices comprises first identification information and second identification information, and wherein an internal circuit of each of the semiconductor devices is supplied via a serial bus. The third identification information included in the input signal is compared with the first identification information stored in the nonvolatile storage circuit. If the first identification information and the third identification information match, the first input signal is compared. Is compared with the second identification information stored in the nonvolatile storage circuit,
The first state is set on condition that the second identification information and the fourth identification information match, and the first identification information is changed by a second input signal supplied via a serial bus subsequent to the first input signal. The information processing system according to claim 1, wherein the identification information of each semiconductor device is set to different information. 18. The information processing system according to claim 16, wherein the serial bus is an IIC bus.