JP2002230980A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can control the activating timing of an amplifier circuit. SOLUTION: The semiconductor memory 1000 is provided with a memory cell, a dummy memory cell in which fixed data is written, a timing control circuit 5 detecting read-out of data of the dummy memory cell and outputting a control signal P, and a read-out/write-in circuit 10 having an amplifier circuit provided corresponding to a pair of bit line to be activated in accordance with the control signal P.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a circuit for controlling activation of an amplifier circuit.

[0002]

2. Description of the Related Art A semiconductor memory device includes a memory cell for storing data, a word line for selecting a memory cell, a bit line connected to the memory cell for writing data to the memory cell or reading data from the memory cell, It is composed of a write circuit for outputting write data to a bit line, an amplifier circuit for amplifying data on the bit line, and the like.

[0003]

By the way, the timing of selecting a word line and activating an amplifier circuit greatly affects the characteristics of a semiconductor memory device, and therefore its design is important.

As a method for automatically generating the above timing, there are methods disclosed in Japanese Patent Application Laid-Open Nos. 9-147574 and 11-203877. The point of these techniques is that a certain signal is delayed by a delay circuit to generate a sense amplifier activation signal, and a phase difference between a dummy bit line simulating bit line operation and a sense amplifier activation signal is detected. That is, the delay time of the delay circuit is controlled so that the phase difference becomes a constant value.

[0005] These techniques have the following problems. First, an initial value is required for the delay time. To make the initial value close to the optimum value, an estimation is required at the design stage. Furthermore, an operation of adjusting the delay time to an optimum value at an initial stage of the operation (Japanese Patent Laid-Open No. 11-203877).
Training operation).

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and an object of the present invention is to provide a semiconductor memory device capable of automatically activating an amplifier circuit at an optimum timing. .

[0007]

A semiconductor memory device according to one aspect of the present invention includes a memory cell array including memory cells arranged in a matrix and a plurality of dummy memory cells storing fixed data arranged in a column. A dummy memory cell array, a word line selection circuit for selecting a memory cell and a dummy memory cell, a first amplifier circuit for reading stored data stored in the memory cell array, and data stored in the dummy memory cell array , A memory cell and a dummy memory cell in the same row as the memory cell are selected at the same time, and the plurality of second amplifier circuits are sequentially activated to form a plurality of second amplifier circuits. When at least one of the amplifier circuits reads data from the selected dummy memory cell, the data stored in the selected memory cell is read out. And a control circuit for activating the first amplifier circuit.

Preferably, the control circuit activates the first amplifier circuit when a plurality of the second amplifier circuits read data from the dummy memory cells successively.

In particular, the control circuit activates the plurality of second amplifier circuits sequentially and sequentially. A semiconductor memory device according to a further aspect of the present invention includes a memory cell array including memory cells arranged in a matrix, and a plurality of dummy memory cells storing fixed data arranged so as to surround two adjacent boundary regions of the memory cell array. , A word line selection circuit for selecting a memory cell and a dummy memory cell, a first amplifier circuit for reading data stored in the memory cell array, and a memory cell for storing in the dummy memory cell array A plurality of second amplifier circuits for reading data, a memory cell and a dummy memory cell are selected at the same time, and the plurality of second amplifier circuits are sequentially activated to at least one of the plurality of second amplifier circuits. When one of the memory cells reads data from the selected dummy memory cell, the first data is read from the selected memory cell. An amplifier circuit and a control circuit for activating.

Preferably, the control circuit activates the first amplifier circuit when a plurality of the second amplifier circuits read data from the dummy memory cells successively.

In particular, the control circuit activates the plurality of second amplifier circuits sequentially and periodically.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters or symbols, and description thereof will not be repeated.

[First Embodiment] An example of the configuration of a semiconductor memory device 1000 according to the first embodiment will be described with reference to FIG. As shown in FIG. 1, semiconductor memory device 1000 includes a memory cell array MA including memory cells M1 to M8 arranged in a matrix, and a dummy memory cell column DMC including dummy memory cells DM1 and DM2. The semiconductor memory device 1000 further includes a memory cell M1
To M4 and the word line WL1 for selecting the dummy memory cell DM1, the memory cells M5 to M8 and the word line WL2 for selecting the dummy memory cell DM2, and the memory cell M1,
Bit line pair B1 and / B1 connected to M5, bit line pair B2 and / B2 connected to memory cells M2 and M6, and bit line pair B3 and / B connected to memory cells M3 and M7.
3. Bit line pair B connected to memory cells M4 and M8
4, / B4, and dummy memory cells DM1 and DM
2 includes a pair of dummy bit lines DB and / DB connected to each other.

The semiconductor memory device 1000 further includes a precharge circuit 1 connected to the bit line pair B1, / B1,..., B4, / B4, a precharge circuit 2 connected to the dummy bit line pair DB, / DB, Bit line pairs B1, / B1,
, Transfer gate 3 connected to B4, / B4, transfer gate 4 connected to dummy bit line pair DB, / DB, data line pair DL, / DL connected to transfer gate 3, connected to transfer gate 4 Data line pair DDL and / DDL.

In the precharge circuit 1, PMOS transistors T1 and T2 are arranged for each bit line pair. Transistors T1 and T2 electrically connect a node receiving a power supply voltage and a corresponding bit line pair according to clock signal T.

Precharge circuit 2 includes PMOS transistors T3 and T4. Transistors T3 and T
Reference numeral 4 electrically connects a node receiving a power supply voltage and a corresponding dummy bit line pair according to a clock signal T.

In the transfer gate 3, NMOS transistors T5 and T6 are arranged for each bit line pair. Transistor T corresponding to bit line pair Bi, / Bi
5 and T6 electrically connect the bit line pair and the data line pair DL and / DL according to the column selection signal DYi.

Transfer gate 4 includes NMOS transistors T7 and T8. Transistors T7 and T8 electrically connect dummy bit line pair DB, / DB to data line pair DDL, / DDL according to column select signal DDY.

Semiconductor memory device 1000 further receives a column selection signal DDY, a signal of data line pair DDL and / DDL, and outputs a control signal P, a timing control circuit 5, a clock signal T, a write signal WE, and a control signal. P as an input, a word line control circuit 6 for outputting a word line control signal WT, an X address signal X and a word line control signal W
T is input, a row decode circuit 7 for selectively activating the word line WL1 or WL2, Y address signals Y0 and Y1 and a clock signal T are input, and any one of the column selection signals DY1 to DY4 is selected. A column control circuit 9 which receives a clock signal T and a write signal WE as inputs and outputs a column selection signal DDY, a clock signal T and a write signal WE.
Read / write circuit 10 for writing signal DQ of input / output terminal DQ to a memory cell or outputting read data from the memory cell to input / output terminal DQ according to control signal P.

Next, a specific configuration of the memory cell M1 will be described with reference to FIG. Note that the memory cells M2 to M
8 has the same configuration as the memory cell M1. Memory cell M
1 is a PMOS transistor T10 as shown in FIG.
a and T11a, and NMOS transistor T1
2a to T15a.

The transistors T10a and T12a are
Node receiving power supply voltage and node GN receiving ground voltage
D is connected in series. Transistors T11a and T13a are connected between a node receiving power supply voltage and node GN
D is connected in series. The gates of the transistors T10a and T12a are respectively connected to the transistor T11
a and T13a is connected to a connection node N2a, and the gates of the transistors T11a and T13a are
Connection node N1a between transistors T10a and T12a
Connected to

The transistor T14a is connected between the node N1a and the bit line B1, and has a gate connected to the word line WL.
1 is connected. The transistor T15a is connected to the node N2
a and the bit line / B1, and the gate is connected to the word line WL1.

Next, a specific configuration of the dummy memory cell DM1 will be described with reference to FIG. Note that the dummy memory cell DM2 has the same configuration as the dummy memory cell DM1. The dummy memory cell DM1, as shown in FIG.
It includes PMOS transistors T10b and T11b and NMOS transistors T12b to T15b.

The transistors T10b and T12b are
Node receiving power supply voltage and node GN receiving ground voltage
D is connected in series. Transistors T11b and T13b are connected between a node receiving power supply voltage and node GN
D is connected in series. The gates of the transistors T10b and T12b are respectively connected to the transistors T11 and T12b.
b and T13b are connected to a connection node N2b, and the gates of the transistors T11b and T13b are
Connection node N1b between transistors T10b and T12b
Connected to

The transistor T14b is connected between the node N1b and the dummy bit line DB, and has a gate connected to the word line WL1. Transistor T15b is connected between node N2b and dummy bit line / DB, and has a gate connected to word line WL1.

The sizes of the transistors T10b to T15b are the same as those of the transistors T10a to T15a. In the dummy memory cell, the source and the drain of the transistor T11b are connected, and are in a state equivalent to a memory cell in which fixed data is stored.

Next, an example of a circuit configuration of the timing control circuit 5 according to the first embodiment will be described with reference to FIG. As shown in FIG. 4, the timing control circuit 5 delays the column selection signal DDY and outputs a signal DT1, a delay circuit 11b that delays the signal DT1 and outputs a signal DT2, and delays the signal DT2. Signal D
A delay circuit 11c that outputs T3, amplifies the signal of the data line pair DDL, amplifies the signal SOa, / SOa, and amplifies the signal of the data line pair DDL, / DDL;
An amplifier circuit 12b that outputs the signals SOb and / SOb amplifies the signals of the data line pair DDL and / DDL, and outputs the signals SOc and / SOb.
Circuit 12c that outputs / SOc, a column selection signal D
A precharge circuit 13 for precharging the pair of data lines DDL and / DDL based on DY, an AND circuit 114 receiving signals SOa, SOb and SOc as inputs, and a signal / SO
AND circuit 11 having inputs a, / SOb and / SOc
5, and an RS latch circuit 16 receiving at its inputs the column selection signal DDY and the output of the AND circuit 114.

The precharge circuit 13 includes PMOS transistors T16 to T18. The transistor T18 is
Connected between data lines DDL and / DDL. Transistor T16 is connected between a node receiving power supply voltage and data line DDL, and transistor T17 is connected between a node receiving power supply voltage and data line / DDL. Each gate of transistors T16 to T18 receives column select signal DDY.

The RS latch circuit 16 is a NAND circuit 1
17 and 118. Control signal P is output from NAND circuit 117.

An example of the circuit configuration of the delay circuit 11a is shown in FIG.
This will be described with reference to FIG. The delay circuits 11b and 11c have the same circuit configuration as the delay circuit 11a. Delay circuit 11
a includes inverters I1 to I4 connected in series as shown in FIG.

The configuration of the delay circuit 11a is not limited to that shown in FIG. 5, and the number of stages is not limited as long as it is a series circuit of even-numbered inverters.

Next, an example of the circuit configuration of the amplifier circuit 12a shown in FIG. 4 will be described with reference to FIG. Note that the amplification circuit 1
2b and 12c have the same circuit configuration as the amplifier circuit 12a. As shown in FIG. 6, the amplifier circuit 12a includes transistors T20 to T26. Transistors T20, T2
1, T25 and T26 are PMOS transistors, and transistors T22 to T24 are NMOS transistors.

Transistor T20 is connected between a node receiving the power supply voltage and node N3, and is connected to transistor T20.
22 is connected between the node N3 and the node N5.
Transistor T21 is connected between a node receiving the power supply voltage and node N4, and transistor T23 is connected between nodes N4 and N5. The gates of the transistors T20 and T22 are connected to the node N4
, And respective gates of transistors T21 and T23 are connected to node N3.

The transistor T24 is connected between the node N5 and the node GND, and has a gate connected to the clock signal DT.
Receive 1 Transistor T25 is connected between data line DDL and node N3, and has a gate receiving clock signal D25.
Receive T1. The transistor T26 is connected to the data line / DD
It is connected between L and a node N4, and receives a clock signal DT1 at its gate. Node N3 is connected to signal line SOa transmitting signal SOa, and node N4 is connected to signal / SOa.
Is connected to a signal line / SOa for transmitting

The amplifier circuit 12a operates in synchronization with the clock signal DT1, and is designed to set the signal line SOa to "H" when the potential difference between the data lines DDL and / DDL is small.

Similarly, the amplifier circuit 12b operates in synchronization with the clock signal DT2, and sets the signal line SOb to "H" when the potential difference between the data lines DDL and / DDL is small. The amplifying circuit 12c operates in synchronization with the clock signal DT3, and sets the signal line SOc to "H" when the potential difference between the data lines DDL and / DDL is small. Next, the word line control circuit 6 shown in FIG. An example of the configuration will be described with reference to FIG. Word line control circuit 6, as shown in FIG. 7, includes inverters I5 to I7, AND circuits 119 and 120, and transistors T27 to T30. Transistors T27 and T29 are NMOS transistors, and T28 and T30 are PMOS transistors.

AND circuit 119 receives clock signal T and write signal WE at its inputs. Inverter I5 inverts write signal WE, and inverter I6 inverts control signal P. AND circuit 120 receives as input clock signal T, the output of inverter I5 and the output of inverter I6.

Inverter I7 inverts write signal WE and outputs an inverted write signal / WE. Transistor T2
7 and T28, and transistors T29 and T
Reference numeral 30 turns on / off in response to the write signal WE and the inverted write signal / WE.

When the transistors T27 and T28 are turned on, the output of the AND circuit 119 becomes the word line control signal W
When the transistors T29 and T30 are turned on, the output of the AND circuit 120 is output as the word line control signal WT.

Next, an example of the configuration of the row decode circuit 7 shown in FIG. 1 will be described with reference to FIG. As shown in FIG. 8, row decode circuit 7 includes inverter I8 and AN
D circuits 121 and 122 are included.

Inverter I8 inverts and outputs X address signal X. AND circuit 121 receives as input word line control signal WT and the output of inverter I8, and outputs word line select signal WL1 to word line WL1. AND
The circuit 122 receives the word line control signal WT and the X address signal X as inputs, and outputs a word line selection signal WL2 to the word line WL2.

When word line control signal WT is at "L", word lines WL1 and WL2 are both at "L". On the other hand, when the word line control signal WT is “H”,
According to the X address signal X, the word line WL1 or WL2
Becomes "H".

Next, an example of the circuit configuration of the column decode circuit 8 shown in FIG. 1 will be described with reference to FIG. As shown in FIG. 9, column decode circuit 8 includes inverters I9 and I10, and AND circuits 123 to 126.

Inverter I9 inverts and outputs Y address signal Y1. Inverter I10 inverts and outputs Y address signal Y0. AND circuit 123 receives clock signal T and the outputs of inverters I9 and I10, and outputs column select signal DY1. A
The ND circuit 124 receives the clock signal T and the Y address signal Y
0 and the output of the inverter I9, the column selection signal D
Y2 is output. The AND circuit 125 outputs the clock signal T
And the output of the inverter I10 and the Y address signal Y1, and outputs a column selection signal DY3. AND circuit 12
6 is a clock signal T and Y address signals Y0 and Y1.
And outputs a column selection signal DY4.

When the clock signal T is "L", the column selection signals DY1 to DY4 become "L". When the clock signal T is "H", the Y address signals Y0 and Y1
, One of the column selection signals DY1 to DY4 becomes “H”.

Next, an example of the circuit configuration of the column control circuit 9 shown in FIG. 1 will be described with reference to FIG. As shown in FIG. 10, the column control circuit 9 includes an AND circuit 127 and an inverter I11. Inverter I11 inverts and outputs write signal WE. AND circuit 127 receives clock signal T and the output of inverter I11, and outputs a column selection signal DDY.

Next, an example of the circuit configuration of the read / write circuit 10 shown in FIG. 1 will be described with reference to FIG. The read / write circuit 10, as shown in FIG.
Amplifying circuit S that amplifies the potential of DL and outputs signal DQ
A, a write circuit WD that outputs data to data line pair DL, / DL based on signal DQ, inverter I12, AND
Circuits 128 and 129, and precharge circuit 1
30.

Precharge circuit 130 includes PMOS transistors T31 to T32. Transistor T31
Is connected between the node receiving the power supply voltage and the data line DL, and the transistor T32 is connected between the node receiving the power supply voltage and the data line / DL.
33 is connected between the data lines DL and / DL. The gates of the transistors T31 to T32 are connected to the clock signal T
Receive.

Inverter I12 inverts and outputs write signal WE. The AND circuit 128 includes an inverter I12
, The clock signal T and the control signal P, and outputs a read enable signal SAE. AND circuit 129
Receives write signal WE and clock signal T, and outputs write enable signal WDE.

The amplifier circuit SA has a read enable signal SA
Activated according to E, and write circuit WD is activated based on write enable signal WDE.

When clock signal T is at "L", read enable signal SAE and write enable signal WDE are at "L", and amplifier circuit SA and write circuit WD do not operate.

When the clock signal T is "H", the write signal WE is "L", and the control signal P is "H", the read enable signal SAE becomes "H" and the amplifier circuit SA operates. When the clock signal T is “H” and the write signal WE is “H”, the write enable signal WDE becomes “H”,
The write circuit WD operates.

An example of the circuit configuration of the amplifier SA shown in FIG. 11 will be described with reference to FIG. The amplifier circuit SA is shown in FIG.
2, as shown in FIG.
50 to T53, NAND circuits 131 and 132, and inverters I13 and I14. Transistors T40, T41, T45, T46, T50 and T5
1 is a PMOS transistor, and a transistor T4
2 to T44, T52 and T53 are NMOS transistors.

Transistor T40 is connected between nodes N6 and N8. Transistor T41 is connected between a node receiving power supply voltage and node N7,
Transistor T43 is connected between nodes N7 and N8. Each gate of transistors T40 and T42 is connected to node N7, and each gate of transistors T41 and T43 is connected to node N6.
Connected to

Transistor T44 is connected between nodes N8 and GND, and receives read enable signal SAE at its gate. The transistor T45 is connected to the data line D
Connected between L and node N6, and receives read enable signal SAE at its gate. Transistor T46 is connected between data line / DL and node N7, and receives read enable signal SAE at its gate.

NAND circuit 131 receives the signal at node N 6 and the output of NAND circuit 132, and receives NAND circuit 1.
32 receives the signal of node N7 and the output of NAND circuit 131. The inverter I13 includes a NAND circuit 131
Is inverted to output a signal DQ.

Transistors T50 to T53 are connected in series between a node receiving a power supply voltage and node GND. The gate of transistor T50 receives read enable signal SAE, the gates of transistors T51 and T52 receive signal DQ, and the gate of transistor T53 receives the output of inverter I14 which receives read enable signal SAE at its input. Transistors T51 and T52
Is connected to the output node of NAND circuit 131.

Next, an example of the circuit configuration of the write circuit WD shown in FIG. 11 will be described with reference to FIG. Write circuit WD
Are inverters I15 to I17, as shown in FIG.
And transistors T55 to T62. The transistors T55, T56, T59 and T60 are PMOS transistors, and the transistors T57, T58, T6
1, T62 is an NMOS transistor.

Transistors T55 to T58 are connected in series between a node receiving a power supply voltage and node GND. Transistors T59 to T62 are connected in series between a node receiving power supply voltage and node GND. The connection node between the transistors T56 and T57 is connected to the data line D
L, and a connection node between transistors T60 and T61 is connected to data line / DL.

Inverters I15 and I16 invert write enable signal WDE, and inverter I17 inverts signal DQ.

The gates of transistors T55 and T59 receive the outputs of inverters I15 and I16, and the gates of transistors T56 and T57 receive the output of inverter I17.

The gates of transistors T60 and T61 receive signal DQ, and receive transistors T58 and T58, respectively.
The gate of T62 receives write enable signal WDE.

When the write enable signal WDE is "L", the transistors T55, T58, T59 and T62 are off.

If the write enable signal WDE is "H", the transistors T55, T58, T59 and T62 are turned on, and the potential of the data line pair DL and / DL changes according to the signal DQ.

Next, the operation of the semiconductor memory device 1000 according to the first embodiment will be described with reference to FIG. As an example, a case where data is written to memory cell M1 and data is read from memory cell M1 will be described.

When clock signal T is at "L" (at time t0)
Previously), all word line and column select signals are "L". Therefore, none of the memory cells is selected and is in a data holding state. All bit lines are
The precharge circuit 1 is charged to “H”, and all the dummy bit lines are also charged to “H” by the precharge circuit 2.

X address signal X and Y address signal Y
When 0 and Y1 are set to “L” and the clock signal T and the write signal WE are set to “H”, the writing operation to the memory cell M1 starts (time t0). All the PMOS transistors of the precharge circuits 1 and 2 are turned off, and the precharge state of all bit lines and dummy bit lines is released.

Word line WL1 and column select signal DY
1 becomes "H" level, and the memory cell M1 is selected.

In the case of a write operation, word line control signal W
T has the same waveform as the clock signal T. Since write enable signal WDE attains "H", write circuit WD operates. Thereby, signal DQ applied to data input / output terminal DQ is written to memory cell M1.

When X address signal X, Y address signals Y0 and Y1 and write signal WE are set to "L" and clock signal T is set to "H", the operation of reading data from memory cell M1 starts (time t1). ).

The PMOS transistors of precharge circuits 1 and 2 are all turned off, and the precharge states of all bit lines and dummy bit lines are released.

Word line WL1 and column select signal DY
1 becomes "H" level, and the memory cell M1 is selected. When the word line WL1 becomes "H", the dummy memory cell DM1 is selected at the same time.

The column control signal 9 causes the column selection signal D
DY becomes "H". The data of the dummy memory cell DM1 includes a dummy bit line pair DB, / DB, a data line pair DDL,
It is input to the timing control circuit 5 via / DDL.

The timing control circuit 5 receiving the "H" level column selection signal DDY causes the clock signal DT
1, DT2 and DT3 are generated. Clock signal D
Each of T1, DT2 and DT3 is
a, 12b, and 12c. Amplifying circuit 12a, 1
2b and 12c are activated in order.

If the potential difference between data lines DDL and / DDL is sufficient, an "L" signal is output from each of amplifier circuits 12a, 12b and 12c. Data lines DDL and /
When the potential difference from the DDL is small, the amplification circuit 12a,
"H" is output from each of 12b and 12c.

When any one of the amplifier circuits 12a, 12b, and 12c outputs "L", an "H" level signal is stored in the RS latch circuit 16, and the control signal P becomes "H". ". In FIG. 14, the clock signal DT3
Shows a case where the amplifier circuit 12c outputs “L” in response to the rise of the time (time t2). At this point, the control signal P becomes "H". That is, when the amplitude of the bit line becomes sufficiently large, the control signal P becomes “H”.

When the control signal P becomes "H", the read enable signal SAE becomes "H" and the amplifier circuit SA operates. The signal on data line pair DL, / DL is amplified by amplifier circuit SA, and signal DQ is output to data input / output terminal DQ. Further, the word line WL1 becomes "L", and the current from the bit line to the memory cell stops.

In the above description, the amplifier circuits 12a, 12b and 12c are shown as examples of the amplifier circuits included in the timing control circuit 5, but the number of amplifier circuits is three.
The number is not limited to one, and any number of two or more may be arranged.
Further, the delay circuit 11a may be omitted.

As described above, according to the semiconductor memory device 1000 of the first embodiment, it is automatically detected that the amplitude of the bit line is sufficient, and the data of the memory cell is read according to the detection result. The output amplifying circuit can be activated. This facilitates chip design.

[Second Embodiment] The configuration of a semiconductor memory device 2000 according to a second embodiment will be described with reference to FIG. As shown in FIG. 15, semiconductor memory device 2000 includes a memory cell array MA and a dummy memory cell array DMA in which dummy memory cells DM11 to DM17 are arranged in an L shape.

The dummy memory cells DM11 to DM15 are
The dummy memory cells DM15 to DM15 are arranged in the word line direction.
DM 17 is arranged in the bit line direction. The circuit configuration of each of the dummy memory cells DM11 to DM17 is as follows.
This is the same as the dummy memory cell DM1 described above.

The dummy memory cells DM11 to DM15 are
Connected to a dummy word line DWL and a dummy memory cell D
M16 and DM17 are respectively connected to dummy word lines DWL0 and DWL1 different from the dummy word line DWL.

In the column direction, dummy memory cells DM15 to DM17 include dummy bit line pairs DB, / DB
Connected to Dummy memory cells DM11 to DM14
Are not connected to any bit lines or dummy bit lines.

Semiconductor memory device 2000 further includes a data line pair DL, / DL provided for a bit line pair, and a data line pair DDL, / DL provided for a dummy bit line pair.
DDL, precharge circuits 1 and 2, transfer gates 3 and 4, word line control circuit 6, row decode circuit 7,
Column decode circuit 8, column control circuit 9, and read /
A write circuit 10 is included.

Semiconductor memory device 2000 further receives a column select signal DDY as input, and outputs a signal DWL for driving dummy word line DWL, dummy word line driver circuit RD, clock signal T, data line pair DDL, / DDL.
Of the dummy word line DWL, and a column driver circuit CD that receives the signal of the dummy word line DWL and outputs the control signal DWL2.

The timing control circuit 21 controls the control signal DW
Activated according to L2. A control signal P output from the timing control circuit 21 is supplied to the word line control circuit 6 and the read / write circuit 10.

Next, an example of a circuit configuration of the timing control circuit 21 according to the second embodiment will be described with reference to FIG. As shown in FIG. 16, the timing control circuit 21 generates a pulse signal from the control signal DWL2 and outputs a clock signal DT1, a pulse generation circuit 31, delay circuits 11b and 11c, a data line pair DDL and / DDL.
Circuits 32a, 32b, 32c, N
OR circuits 34 to 38, precharge circuit 13 and R-
An S latch circuit 16 is included.

The delay circuit 11b delays the clock signal DT1 output from the pulse generation circuit 31 and outputs a signal DT2, and the delay circuit 11c delays the signal DT2 and outputs a signal DT3.

Each of the amplifier circuits 32a, 32b and 32c operates according to the clock signals DT1 to DT3.

The amplifier circuits 32a, 32b and 32c are periodically activated in sequence by the clock signals DT1, DT2 and DT3.

The amplifying circuit 32a includes a data line pair DDL, /
Amplifies the signal of DDL, outputs signals SOa and / SOa, amplifies circuit 32b, amplifies the signal of data line pair DDL and / DDL, outputs signals SOb and / SOb, and amplifies circuit 32c. Amplify the signals of DDL and / DDL and output signals SOc and / SOc.

The NOR circuit 34 outputs the signal SOa and the signal SO
b, the NOR circuit 35 outputs the signal SOb and the signal SO
Receive c. NOR circuit 37 receives signal / SOa and signal / SOb, and NOR circuit 38 receives signal / SOb and signal / SOc. NOR circuit 36 receives an output of NOR circuit 34 and an output of NOR circuit 35.

The RS latch circuit 16 controls the control signal DWL
2 and the output of the NOR circuit 36 are received at the input. When either the NOR circuit 34 or 35 outputs “H”,
"H" is stored in the RS latch circuit 16, and the control signal P
Becomes “H”.

An example of the configuration of the pulse generation circuit 31 shown in FIG. 16 will be described with reference to FIG. Pulse generating circuit 31
Are inverters I20 to I21, as shown in FIG.
I30, a delay circuit 41 to which an inverter is connected to an even-numbered stage (six stages in the figure), and an even-numbered stage (two stages to the inverter)
The delay circuit 42 includes NAND circuits 140 and 141 connected thereto.

The delay circuit 41 includes, for example, inverters I22 to I27 connected in series. The delay circuit 42 includes, for example, an inverter I connected in series.
28 and I29.

Inverter I20 inverts the output signal of delay circuit 41. The NAND circuit 140 controls the control signal DW
L2 and the output of inverter I20. Inverter I21 inverts the output of NAND circuit 140. Delay circuit 41 delays the output signal of inverter I21.

The delay circuit 42 delays the output signal of the delay circuit 41. NAND circuit 141 receives at its inputs the output signal of delay circuit 41 and the output of delay circuit 42. The inverter I30 inverts the output of the NAND circuit 141,
The clock signal DT1 is output.

Next, an example of a circuit configuration of the amplifier circuit 32a shown in FIG. 16 will be described with reference to FIG. Note that the amplifier circuits 32b and 32c have the same configuration as the amplifier circuit 32a. As shown in FIG. 18, the amplifier circuit 32a includes transistors T70 to T78 and inverters I31 to I3.
7 and NOR circuits 142 and 143.

Transistors T70, T71, T75, T
76 and T78 are PMOS transistors, and transistors T72 to T74 are NMOS transistors. The output of inverter I36 is applied to signal S1 and inverter I
The output of 37 is denoted as signal S2.

Transistor T70 is connected between the node receiving the power supply voltage and node N10, and transistor T72 is connected between nodes N10 and N12.
Transistor T71 is connected between a node receiving a power supply voltage and node N11, and transistor T73 is connected between nodes N11 and N12.

Each gate of transistors T70 and T72 is connected to node N11, and each gate of transistors T71 and T73 is connected to node N1.
Connected to 0.

The transistor T74 is connected between the node N12 and the node GND, and has a gate connected to the clock signal D.
Receive T1. The transistor T75 is a transistor T75.
The transistor S71 is connected between the gate of the transistor 70 and the gate of the transistor T71, and receives the signal S2 at the gate.

Transistor T76 is connected between data line DDL and node N10, and receives signal S1 at its gate. Transistor T78 is connected between data line / DDL and node N11, and receives signal S1 at its gate.

Inverters I33 to I35 are connected in series, and NOR circuit 142 receives as input clock signal DT1 and the output of inverter I35. Inverter I31
And I32 are connected in series to delay clock signal DT1. NOR circuit 143 receives at its inputs the output of inverter I32 and the output of NOR circuit 142. Inverter I37 inverts the output of NOR circuit 142 and outputs signal S2. The inverter I36 is connected to the NOR circuit 1
The signal S1 is output by inverting the output of 43.

Signal SOa is output from node N10,
Signal / SOa is output from node N11.

Next, the operation of the semiconductor memory device 2000 according to the second embodiment will be described with reference to FIG. In the write operation, data is written to a specific memory cell by the operation described in the first embodiment.

The read operation will be described. When the X address signal X, the Y address signals Y0 and Y1, and the write signal WE are set to "L" and the clock signal T is set to "H", a read operation to the memory cell M1 is started (time t).
1). All the PMOS transistors of the precharge circuits 1 and 2 are turned off, and the precharge state of all bit lines and dummy bit lines is released.

Word line WL1 and column select signal DY
1 becomes "H" level, and the memory cell M1 is selected.

The column control signal 9 causes the column selection signal D
DY becomes "H". Dummy word line driver circuit RD
As a result, the dummy word line DWL becomes "H", and the dummy memory cell DM15 is selected. An “H” level control signal DWL2 is output from the column driver circuit CD.

The data of the dummy memory cell DM15 includes a dummy bit line pair DB, / DB and a data line pair DDL, /
It is input to the timing control circuit 21 via the DDL.

Clock signal DT1 is generated in pulse generation circuit 31 receiving control signal DWL2 at "H" level. The pulse generation circuit 31 periodically generates a pulse during a period when the clock signal T is “H”. The clock signals DT2 and DT are provided by the delay circuits 11b and 11c.
3 is generated.

Each of clock signals DT1, DT2, DT3 is input to amplifier circuits 32a, 32b, 32c. Each of the amplifier circuits 32a, 32b, 32c is repeatedly activated.

When the potential difference between data lines DDL and / DDL is sufficient, "L" is output from each of amplifier circuits 32a, 32b and 32c, and otherwise "H" is output.

Two successive amplifier circuits 32a, 32b,
32c outputs "L", the "H" data is
The control signal P is stored in the S latch circuit 16 and becomes "H".

When control signal P attains "H", read enable signal SAE attains "H", and amplifier SA amplifies the signal on data line pair DL, / DL. As a result, the signal DQ is output to the data input / output terminal DQ. Further, the word line WL1 becomes "L", and the current from the bit line to the memory cell stops.

As described above, according to the semiconductor memory device 2000 of the second embodiment, the amplifier circuit can be automatically operated when the bit line has a sufficient amplitude. This facilitates chip design. Also,
Since the amplifier circuit is used repeatedly, only a small number of amplifier circuits need to be arranged, and the layout area can be reduced.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0118]

As described above, according to the semiconductor memory device of the present invention, the amplifier circuit is automatically operated when the amplitude of the bit line becomes sufficient in accordance with the data reading of the dummy memory cell. be able to. This facilitates chip design.

Further, since a plurality of amplifier circuits used for reading data from the dummy memory cells are used repeatedly, only a small number of amplifier circuits need to be arranged, and the layout area can be reduced.

[Brief description of the drawings]

FIG. 1 is a semiconductor memory device 10 according to a first embodiment;
It is a figure showing an example of composition of 00.

FIG. 2 is a diagram illustrating an example of a circuit configuration of a memory cell according to the first embodiment;

FIG. 3 is a diagram illustrating an example of a circuit configuration of a dummy memory cell according to the first embodiment;

FIG. 4 is a diagram illustrating an example of a circuit configuration of a timing control circuit 5 according to the first embodiment.

FIG. 5 is a diagram illustrating an example of a circuit configuration of the delay circuit illustrated in FIG. 4;

6 is a diagram illustrating an example of a circuit configuration of the amplifier circuit illustrated in FIG.

FIG. 7 is a word line control circuit 6 according to the first embodiment;
FIG. 3 is a diagram showing an example of the circuit configuration of FIG.

FIG. 8 is a row decode circuit 7 according to the first embodiment;
FIG. 3 is a diagram showing an example of the circuit configuration of FIG.

FIG. 9 is a diagram illustrating an example of a circuit configuration of a column decode circuit 8 according to the first embodiment.

FIG. 10 shows a column control circuit 9 according to the first embodiment.
FIG. 3 is a diagram showing an example of the circuit configuration of FIG.

FIG. 11 is a read / write circuit 1 according to the first embodiment;
FIG. 3 is a diagram illustrating an example of a circuit configuration of 0.

12 is a diagram illustrating an example of a circuit configuration of the amplifier circuit SA illustrated in FIG.

FIG. 13 is a diagram illustrating an example of a circuit configuration of a write circuit WD illustrated in FIG. 11;

FIG. 14 is a semiconductor memory device 1 according to a first embodiment.
000 is a timing chart for describing the operation of FIG.

FIG. 15 shows a semiconductor memory device 2 according to a second embodiment.
FIG. 3 is a diagram illustrating an example of a circuit configuration of 000.

FIG. 16 is a diagram illustrating an example of a circuit configuration of a timing control circuit 21 according to the second embodiment.

17 is a diagram illustrating an example of a circuit configuration of the pulse generation circuit 31 illustrated in FIG.

18 is a diagram illustrating an example of a circuit configuration of the amplifier circuit illustrated in FIG.

FIG. 19 shows a semiconductor memory device 2 according to a second embodiment.
000 is a timing chart for explaining the operation of FIG.

[Explanation of symbols]

1,2,13,130 precharge circuit, 3,4 transfer gate, 5,21 timing control circuit,
6 word line control circuit, 7 row decode circuit, 8 column decode circuit, 9 column control circuit, 10 read /
Write circuit, 11a, 11b, 11c Delay circuit, 12a
To 12c, 32a to 32c amplifying circuit, 16 RS latch circuit, 31 pulse generating circuit, SA amplifying circuit, W
D write circuit, DMA dummy memory cell array, RD
Dummy word line driver circuit, CD column driver circuit, 31 pulse generation circuit, B1 to B4, / B1 to /
B4 bit line, DB, / DB dummy bit line, D
L, / DL data line, DDL, / DDL dummy data line, M1 to M8 memory cell, MA memory cell array, DM1 to DM18 dummy memory cell, DMA dummy memory cell array, DMC dummy memory cell column, DWL dummy word line, 1000, 2000 Semiconductor storage device.

Claims (6)

[Claims] 1. A memory cell array including memory cells arranged in a matrix, a dummy memory cell array including a plurality of dummy memory cells storing fixed data arranged in a column, and a memory cell and a dummy memory cell are selected. A word line selection circuit, a first amplifier circuit for reading data stored in the memory cell array, and a plurality of second amplifier circuits for reading data stored in the dummy memory cell array. Simultaneously selecting a memory cell and a dummy memory cell in the same row as the memory cell, sequentially activating the plurality of second amplifier circuits, and selecting at least one of the plurality of second amplifier circuits.
A control circuit for activating the first amplifier circuit so as to read the storage data of the selected memory cell at the time when the data of the selected dummy memory cell is read. 2. The control circuit activates the first amplifier circuit when a plurality of the second amplifier circuits successively read data from the dummy memory cell. 2. The semiconductor memory device according to 1. 3. The semiconductor memory device according to claim 1, wherein the control circuit activates the plurality of second amplifier circuits sequentially and periodically. 4. A dummy memory cell array including a memory cell array including memory cells arranged in a matrix and a plurality of dummy memory cells storing fixed data arranged so as to surround two adjacent boundary regions of the memory cell array. A word line selection circuit for selecting a memory cell and a dummy memory cell; a first amplifier circuit for reading storage data stored in the memory cell array; A plurality of second amplifying circuits for reading data to be read, a memory cell and a dummy memory cell are simultaneously selected, and the plurality of second amplifying circuits are activated in order to form the plurality of second amplifying circuits. When at least one of the circuits reads the data of the selected dummy memory cell, the storage data of the selected memory cell is read. And a control circuit for activating said first amplifier circuit, a semiconductor memory device. 5. The control circuit activates the first amplifier circuit when a plurality of the second amplifier circuits successively read data from the dummy memory cell. 5. The semiconductor memory device according to item 4. 6. The semiconductor memory device according to claim 4, wherein said control circuit activates said plurality of second amplifier circuits sequentially and periodically.