JP2002218278A - Synchronizing separation circuit and method, display device and method and signal processing device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To constitute a synchronizing separation circuit capable of stably outputting vertical synchronizing signals by using a digital circuit. SOLUTION: In an up counter 22, the position of the vertical synchronizing signal is counted from the front edge of a horizontal synchronizing signal H by a clock CLK. Whether the vertical synchronizing signal is an equal phase or a shift phase is discriminated on the basis of a count value in a circuit 24. Stable horizontal data which are the number of the clocks corresponding to one horizontal cycle are multiplied by 1 and 1.5 and the count value of the position of the vertical synchronizing signal is subtracted respectively in subtractors 34 and 35. In a down counter 25, the output of the subtractors 34 and 35 is selected on the basis of an equal/shift discriminated result and down counting is performed by the clock CLK with the selected output as an initial value. The position at which the count value by the down counter 25 is O is defined as the front edge of the vertical synchronizing signal V to be outputted. In a vertical synchronizing signal preparation circuit 27, the signal of a prescribed width is attained and the vertical synchronizing signal V is generated and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization separation circuit and method, a display device and method, and a signal processing device and method capable of stably outputting a vertical synchronization signal using a digital circuit.

[0002]

2. Description of the Related Art When a video signal is subjected to synchronization separation processing in a digital system, a vertical synchronization signal is delayed by a half horizontal period between an odd field and an even field at the timing of a horizontal synchronization signal or from the horizontal synchronization signal. Are output at the respective timings.

[0005] For example, in the case of a video signal corresponding to the NTSC system, the horizontal synchronizing signal can be obtained by slicing a horizontal synchronizing pulse at a predetermined level as shown in an example in FIG.

In recent years, television broadcasting has been
In addition to broadcasting using the TSC system, for example, a high-definition (HDTV) system capable of transmitting images with higher definition than the NTSC system, television broadcasting using a digital system, and the like have been put into practical use. for that reason,
It is required that a television broadcast monitor installed in each home or the like be able to support video signals in each of these systems.

For example, a video signal according to the HDTV system is
As shown in an example in FIG. 16, since the horizontal synchronizing signal has a ternary bipolar waveform, even when sliced at a predetermined level,
Since a horizontal synchronization signal as a pulse for each horizontal period cannot be obtained, it is necessary to use a method different from the NTSC system for detecting the horizontal synchronization signal.

Further, as one of the digital television broadcasting, there is a method called a 720/60 system. This is a non-interlaced video signal with a frame frequency of 60 Hz, and the horizontal synchronization signal has a ternary bipolar waveform. The horizontal cycle of these three systems is, for example, approximately 64 μsec in the NTSC system.
c, approximately 30 μsec for the HDTV system, and approximately 20 μsec for the 720/60 system.

In recent years, video signals output from a personal computer are often input to a television receiver and displayed. The video signal output from the personal computer is of a non-interlaced type, and the vertical and horizontal synchronizing frequencies can be variously selected.

[0008]

By the way, for example, in a home VTR (Video Tape Recorder) device, when a variable speed reproduction for reproducing at a tape speed higher than the tape speed at the time of recording is performed, the output video is output. In some signals, a serration pulse (corresponding to a horizontal synchronization signal) is not included in a vertical synchronization signal in some cases. In this case, there is a problem that the vertical synchronization signal output from the synchronization separation circuit is delayed or jitter occurs. The jitter generated in the vertical synchronization signal appears as a vertical screen shake in a CRT (Cathode Ray Tube) monitor.

As described above, the video signals of a plurality of systems have different horizontal synchronizing signal waveforms and different horizontal periods. Therefore, in the case where video signals are synchronized and separated by an analog method as in the conventional case, in order to support video signals of a plurality of methods as described above, corresponding sync separation circuits are prepared and switched to be used. There was a problem that it was necessary to do.

Therefore, there has been a demand for a sync separation circuit which is constituted by a digital circuit and which does not easily cause vertical jitter. By constructing the sync separation circuit with a digital circuit, for example, only by changing the set data,
It is possible to support a plurality of video signals as described above with one circuit.

A configuration for synchronizing a video signal by a digital system has been proposed, for example, in Japanese Patent Application No. 5-172271 (Japanese Patent Application Laid-Open No. 7-7633). According to this configuration,
The vertical synchronizing signal output is affected by the horizontal synchronizing signal output (next H signal) following detection of the vertical synchronizing signal. The next H signal may be a horizontal synchronizing signal extracted from the input video signal, or may be a horizontal synchronizing signal inserted at a pseudo position. The timings of these two types of horizontal synchronization signals do not exactly match. This is because it is necessary to slightly shift the timing in order to determine the existence of these two types of horizontal synchronization signals and to perform switching and output. Therefore, when a vertical synchronizing signal is generated using the next H signal as in this proposal, the output vertical synchronizing signal is slightly disturbed.
When a CRT is used as a display device, there is a problem that even a slight deviation of the vertical synchronization signal affects the display screen.

Therefore, an object of the present invention is to provide a sync separation circuit and method, a display device and method, and a signal processing device and method which are constituted by using a digital circuit and can stably output a vertical sync signal. To provide.

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a sync separation circuit for outputting a horizontal sync signal and a vertical sync signal corresponding to an input video signal. Horizontal sync signal detecting means for detecting a signal corresponding to the horizontal sync signal, a vertical sync signal detecting means for detecting the presence of a vertical sync signal of the video signal, and a horizontal sync signal detected by the horizontal sync signal detecting means. Position detecting means for detecting the position of the vertical synchronizing signal detected by the vertical synchronizing signal detecting means on the basis of the signal which corresponds to the horizontal synchronizing signal and the position of the vertical synchronizing signal detected by the position detecting means. And a vertical synchronizing signal output means for determining a start position of the vertical synchronizing signal to be output.

According to the present invention, in a sync separation method for outputting a horizontal sync signal and a vertical sync signal corresponding to an input video signal, a horizontal sync signal for detecting a signal corresponding to the horizontal sync signal of the input video signal is provided. A signal detection step, a vertical synchronization signal detection step for detecting the presence of a vertical synchronization signal of the video signal, and a signal corresponding to the horizontal synchronization signal detected in the horizontal synchronization signal detection step. A step of detecting the position of the vertical synchronization signal detected in the step; a signal corresponding to the horizontal synchronization signal and a position of the vertical synchronization signal detected in the position detection step; And a step of outputting a vertical synchronization signal for determining a start position.

According to the present invention, in a display device for displaying an input video signal on a display means, a horizontal synchronization signal detection means for detecting a signal corresponding to a horizontal synchronization signal of the input video signal; A vertical synchronization signal detecting means for detecting the presence of a vertical synchronization signal, and a position of the vertical synchronization signal detected by the vertical synchronization signal detecting means based on a signal corresponding to the horizontal synchronization signal detected by the horizontal synchronization signal detecting means. A vertical synchronizing signal output means for determining a starting position of a vertical synchronizing signal to be output based on a signal corresponding to the horizontal synchronizing signal and a position of the vertical synchronizing signal detected by the position detecting means. A video signal input based on a signal corresponding to the horizontal synchronization signal detected by the signal detection unit and a vertical synchronization signal output from the vertical synchronization signal output unit A display device characterized in that it comprises a signal processing means for performing predetermined signal processing, and display means for displaying the video signal outputted from the signal processing means.

According to the present invention, in a display method for displaying an input video signal on a display means, a step of detecting a horizontal synchronization signal for detecting a signal corresponding to a horizontal synchronization signal of the input video signal, The vertical synchronization signal detected in the vertical synchronization signal detection step based on the signal corresponding to the horizontal synchronization signal detected in the vertical synchronization signal detection step for detecting the presence of the vertical synchronization signal, and the horizontal synchronization signal detected in the horizontal synchronization signal detection step A vertical synchronization signal for determining a start position of a vertical synchronization signal to be output based on a position detection step for detecting the position of the vertical synchronization signal and a position of the vertical synchronization signal detected in the position detection step. The output step, the signal corresponding to the horizontal sync signal detected in the horizontal signal detection step, and the vertical sync signal output step A signal processing step of performing predetermined signal processing on the input video signal based on the output vertical synchronization signal, and a display step of displaying the video signal output from the signal processing step. Display method.

Further, according to the present invention, in a signal processing device for performing predetermined signal processing on an input video signal, a horizontal synchronization signal detecting means for detecting a signal corresponding to a horizontal synchronization signal of the input video signal, A vertical synchronizing signal detecting means for detecting the presence of a vertical synchronizing signal of the signal; and a position of the vertical synchronizing signal detected by the vertical synchronizing signal detecting means based on a signal corresponding to the horizontal synchronizing signal detected by the horizontal synchronizing signal detecting means. A vertical synchronization signal output unit that determines a start position of the output vertical synchronization signal based on a signal corresponding to the horizontal synchronization signal and a position of the vertical synchronization signal detected by the position detection unit, Video input based on a signal corresponding to the horizontal synchronization signal detected by the horizontal time signal detection means and a vertical synchronization signal output from the vertical synchronization signal output means A signal processing apparatus characterized by a signal processing means for performing predetermined signal processing to issue.

Further, according to the present invention, in a signal processing method for performing predetermined signal processing on an input video signal, a horizontal synchronization signal detecting step for detecting a signal corresponding to a horizontal synchronization signal of the input video signal, Based on a vertical synchronization signal detection step for detecting the presence of a vertical synchronization signal in the video signal and a signal corresponding to the horizontal synchronization signal detected in the horizontal synchronization signal detection step, the vertical synchronization signal detected in the vertical synchronization signal detection step is determined. A position detecting step for detecting the position of the synchronizing signal, and a vertical position for determining a starting position of the vertical synchronizing signal to be output based on the signal corresponding to the horizontal synchronizing signal and the position of the vertical synchronizing signal detected in the position detecting step. A step of synchronizing signal output, a signal corresponding to the horizontal synchronizing signal detected in the horizontal signal detection step, and a step of outputting vertical synchronizing signal. A signal processing method characterized by a step of the signal processing for performing predetermined signal processing on the input video signal based on the vertical sync signal outputted from the.

As described above, the present invention detects a signal corresponding to a horizontal synchronization signal of an input video signal, detects the presence of a vertical synchronization signal of the video signal, and converts the signal to a signal corresponding to a horizontal synchronization signal. The position of the vertical synchronization signal is detected based on the vertical synchronization signal, and the start position of the output vertical synchronization signal is determined based on the signal corresponding to the horizontal synchronization signal and the position of the vertical synchronization signal. Even when there is no pulse, a vertical synchronization signal can be output at a necessary timing.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of an example of a video display device 100 to which the present invention can be applied. In this example, the video display device 100 can switch and output a video signal by television broadcast and a video signal (hereinafter, referred to as a PC signal) output from a computer device. Unless otherwise specified, a video signal by television broadcasting is NT
The description will be made assuming that it corresponds to the SC system.

The video signal and the PC signal are input to the switch 10 respectively. The PC signal is, for example, R (Red), G
(Green), RG in which signals of each color B (Blue) are compounded in a predetermined manner
This is the B signal. The output signal from which the input video signal and PC signal are switched as desired by the switch 10 is supplied to the video processing circuit 11 and also to the analog synchronization signal extraction circuit 13.

The synchronizing signal extracting circuit 13 extracts a synchronizing signal from the supplied signal in an analog manner. If the supplied signal is a video signal, as shown in an example in FIG. 2, the video signal is sliced at a predetermined level to remove the video portion and extract the horizontal and vertical synchronization signals. If the supplied signal is an RGB signal, as shown in an example in FIG. 3, a composite synchronizing signal in which the synchronizing signals of the respective RGB components are composited is sliced at a predetermined level, and the synchronizing signal is extracted. In the case of a PC signal, a horizontal / vertical separate synchronization signal can be extracted.

FIG. 4 shows an example of a signal output from the synchronization signal extraction circuit 13. FIGS. 4A and 4B show the video signal and the P signal as shown in FIGS. 2 and 3 described above.
The C signal is a synchronization signal that is sliced and extracted at a predetermined level. FIG. 4C is an example of a signal extracted from the Hi-Vision signal. This corresponds to the signal obtained by slicing the waveform shown in FIG.

The output of the synchronization signal extraction circuit 13 is supplied to a digital synchronization separation circuit 14. In the digital sync separation circuit 14, the video signal processing circuit 1
The components unnecessary for the signal processing in 1 are removed, and the horizontal synchronizing signal H and the vertical synchronizing signal V are separated and generated and output. For example, in the digital sync separation circuit 14,
Equalization pulses are removed from the supplied signal. If a dubbing prevention signal is inserted in the supplied signal, it is removed. The horizontal synchronization signal H and the vertical synchronization signal V output from the digital synchronization separation circuit 14 are
Each is supplied to the video signal processing circuit 11.

The video signal or the PC signal supplied from the switch 10 is converted by the video signal processing circuit 11 into the horizontal synchronization signal H supplied from the digital synchronization separation circuit 14.
The signal is subjected to predetermined signal processing based on the vertical synchronization signal V and is output. The video signal output from the video signal processing circuit 11 is supplied to a video display device 12 using, for example, a CRT (Cathode Ray Tube) as a display device, and a predetermined display is displayed.

FIG. 5 shows an example of the digital sync separation circuit 14 in more detail. In FIG. 5, the signal path with the symbol “/” indicates that the digital data is transmitted. Synchronous signal extraction circuit 13
Are supplied to a horizontal synchronizing signal separating circuit 20 and a vertical synchronizing signal detecting circuit 21 together. The horizontal synchronizing signal separation circuit 20 detects a horizontal synchronizing signal from the supplied signal, converts the supplied signal into a clean horizontal synchronizing signal H required by the video processing circuit 11, and outputs the same.
For example, a clock CLK having a predetermined cycle is supplied to the horizontal synchronizing signal separating circuit 20, and the input signal is converted into a clean horizontal synchronizing signal H by measuring the interval of the horizontal synchronizing signal in clock units.

An example of processing by the horizontal synchronizing signal separating circuit 20 will be described with reference to FIGS. Of these, FIG.
9 show a video signal, a PC signal, and a video signal (high-definition signal) according to the high-definition system, respectively.
Period including vertical synchronization signal (vertical blanking period)
It is shown.

FIG. 6 shows an example of input and output signals when a signal based on a video signal is supplied. As described above, the video signal is sliced at a predetermined level and input to the horizontal synchronizing signal separation circuit 20. In the vertical blanking period, as shown in an example of FIG. 6A, an equalizing pulse is inserted in a half cycle of the horizontal synchronizing signal. Therefore, the equalizing pulse is removed, and as shown in FIG. Pulsed.

FIG. 7 shows an example of input / output signals when a signal based on the PC signal is supplied. In the case of a PC signal, there is no serration during the vertical blanking period, as shown in an example in FIG. 7A. Therefore, a pseudo-horizontal synchronizing signal is input for the vertical blanking period, and output as shown in FIG. 7B.

FIG. 8 shows an example of input / output signals when a signal based on a high definition video signal (high definition signal) is supplied. As shown in FIG. 8A, a signal obtained by slicing a high-definition signal at a predetermined level is input. From this signal, a portion corresponding to the synchronization cycle and the equalization pulse is extracted as shown in FIG. 8B, and further, during the vertical blanking period, the equalization pulse is extracted as shown in FIG. 8C. , And output as a pulse of a horizontal synchronization cycle.

In some cases, for example, a dubbing prevention signal for preventing dubbing from a video tape is inserted into a video signal. FIG. 9A is an example in which a dubbing prevention signal is inserted for each horizontal synchronization cycle. Also in this case, the signal is sliced at a predetermined level to obtain a signal as shown in FIG. 9B. The part of the anti-dubbing signal is removed from this signal,
As shown in FIG. 9C, it is output as a pulse having a horizontal synchronization cycle.

The detection and separation processing of these horizontal synchronization signals in the horizontal synchronization separation circuit 20 can be performed by an analog method using a conventional technique.

The horizontal synchronization signal H separated and output from the horizontal synchronization signal separation circuit 20 as described above is supplied to the video processing circuit 11 and the up counter 22. Further, the horizontal sync separation circuit 20 generates horizontal cycle data corresponding to the detected horizontal sync signal. The horizontal cycle data is a clock C having a predetermined cycle during one horizontal cycle.
LK is the counted data. As an example, NT
In the case of SC video signals, the horizontal cycle is approximately 64 μs
Assuming that the clock frequency is 10 MHz, (64 μsec) × (10 MHz) = 64 in one horizontal period.
This is data counted by 0. That is, the horizontal cycle data is reset by the horizontal synchronization pulse, and 640 counts are performed in one horizontal cycle. This horizontal cycle data is
It is supplied to the stable horizontal data circuit 31 in the down counter initial value generation section 30.

On the other hand, the vertical synchronizing signal detecting circuit 21 detects a vertical synchronizing signal from the input signal. The vertical synchronizing signal is inserted when the signal level is positive for a predetermined period in the case of positive polarity and negative for a predetermined period in the case of negative polarity. For example, if the detection period is a １ ／ horizontal cycle,
If the polarity is positive, a vertical synchronization signal is detected by detecting a positive level in a 水平 horizontal period. Similarly, if the polarity is negative, the vertical synchronization signal is detected by detecting the negative level in the 水平 horizontal period.

FIG. 10 shows how the vertical synchronizing signal is detected by detecting a signal having a width twice the width of the horizontal synchronizing signal.
FIG. 10A is an example of a video signal, and FIG.
It is an example of a signal. The position where the negative level is continuously detected at least twice the width of the horizontal synchronization signal is set as the detection position of the vertical synchronization signal.

FIG. 11 shows an example of the configuration of the vertical synchronization signal detection circuit 21. The vertical synchronizing signal detecting circuit 21 supplies a clock CLK (10M in the above example) having the same frequency and the same phase as the horizontal synchronizing signal separating circuit 20 as an operating clock.
Hz). Although not shown in FIG. 5 described above, the horizontal synchronization signal H separated by the horizontal synchronization signal separation circuit is supplied to the vertical synchronization signal detection circuit 21 and the data of one horizontal cycle based on the clock CLK is supplied. Is set.

The signal supplied to the vertical synchronizing signal detection circuit 21 is supplied to the L section counter 50. The L section counter 50 is a counter that detects the low level period of the supplied signal, is reset by the horizontal synchronization signal H, and counts up with the clock CLK while the signal is at the low level. The count value of the L section counter 50 is
It is supplied to one input terminal of the comparison circuit 53.

On the other hand, the other input terminal of the comparison circuit 53
Detection period data indicating a period for detecting the vertical synchronization signal is supplied. In this example corresponding to an NTSC video signal and having a clock frequency of 10 MHz, the number of clocks in one horizontal cycle is 640 as described above. In this example in which the detection period of the vertical synchronization signal is set to 1/4 horizontal cycle, the set clock number data is reduced to 1/4,
The value is set to "160". This detection period data is supplied to the other input terminal of the comparison circuit 53.

The comparison circuit 53 compares the count value output from the L section counter 50 with the detection period data. If the result of the comparison indicates that the count value is equal to or longer than the detection period data, the input signal is determined to be a vertical synchronization signal, and a vertical synchronization signal detection pulse is output. The vertical synchronization signal detection pulse is, for example, a pulse having a width of one clock.

The vertical synchronizing signal detection pulse output from the vertical synchronizing signal detecting circuit 21 is supplied to an up counter 22. As described above, the horizontal synchronization signal H separated by the horizontal synchronization signal separation circuit 20 is also supplied to the up counter 22. The up counter 22 starts the clock signal CLK from “0” with the leading edge of the horizontal synchronization signal H as a starting point.
Is counted up. The count value at the time when the vertical synchronization signal detection pulse is input is output and stored in the vertical signal detection register 23.

FIG. 12 shows an example of the output of the vertical synchronization signal detection pulse by the vertical synchronization signal detection circuit 21. In this example, as shown in FIG. 12A, the leading edge of the horizontal synchronizing signal H is counted as “0” and counted as “1”, “2”, “3”,. At the time of FIG.
As shown in FIG. 7, a vertical synchronizing signal detection pulse is input. This count value “25” is stored in the up counter 22.
Output from

In the up counter 22, the count value is reset at the leading edge of the next horizontal synchronizing signal H, and the count up is restarted. As shown in an example in FIG. 13A, even if the next horizontal synchronization signal H does not come at the expected timing, the count value becomes a value corresponding to one horizontal cycle (“640” in this example). When it reaches, it is considered that the horizontal synchronization signal H has been detected (see FIG. 13B).
Then, the count value is reset, and the count up is restarted. Therefore, even when the horizontal synchronization signal H is not successfully separated in the horizontal synchronization signal separation circuit 20, the horizontal period is held as the count value of the up counter 22.

The count value stored in the vertical signal detection register 23 is supplied to the subtracters 34 and 35 and also to the equal-shift discriminating circuit 24. In the equal-shift determination circuit 24, based on the supplied count value, whether the horizontal synchronization and the vertical synchronization are in phase (hereinafter, referred to as “equal”), or the horizontal synchronization and the vertical synchronization are shifted by １ ／ horizontal period. (Hereinafter, referred to as “shift”).
The determination result of the equal-shift determination circuit 24 is supplied to a down counter 25.

The threshold for this determination can be appropriately selected. In this example, 1/4
A low level that is equal to or longer than the horizontal cycle is required. In this case, the count value (for example, “3
20 ") can be used as the threshold for discrimination.
That is, when the value stored in the vertical signal detection register 23 is equal to or more than “0” and less than 水平 horizontal cycle, “eq”
uaal ”and“ shift ”when it is equal to or more than １ ／ horizontal cycle and less than 1 horizontal cycle.

For example, as shown in FIG. 12, when the vertical synchronization signal detection pulse is input when the count value is “25”, if the phase is “equal”, the vertical signal detection register 23 stores the value “ 25 ”is stored and“ s
In the case of the “high” phase, the value “345” (= 320 + 25) is stored in the vertical signal detection register 23.

The determination result of the equal-shift determination circuit 24 is supplied to a down counter 25. Further, two outputs of the down counter initial value generation unit 30 are supplied to the down counter 25. The down counter 25 is a counter that counts down using the clock CLK described above. In the down counter 25, equal-sh
Based on the determination result of the if determination circuit 24, one of the outputs of the two systems supplied from the down counter initial value generation unit 30 is set as an initial value of the counter, and the initial value is counted down by the clock CLK.

FIG. 14 schematically shows the processing after the down counter 25. FIG. 14A is an input signal, and FIG.
The detection timing of the vertical synchronization signal is shown. This indicates that the vertical synchronization signal is detected when the horizontal cycle data has the value “25”. In the down counter 25, the set initial value is counted down by the clock CLK from the timing at which the vertical synchronization signal is detected (see FIG. 14C). The counted-down count value is supplied to the zero coincidence detection circuit 26, and the zero coincidence is detected. As a result of the zero coincidence detection, as shown in FIG. 14D, the timing at which the count value “0” is detected is set as the leading edge of the vertical synchronization signal output.

The down counter initial value generator 30 will be described. As described above, in the stable horizontal data circuit 31,
The horizontal cycle data output from the horizontal synchronization signal separation circuit 20 is supplied. The horizontal cycle data is supplied to subtracters 34 and 35 via multipliers 32 and 33 having magnifications of 1 and 1.5, respectively, and the values stored in the vertical signal register 23 (in this example, " 25 ”) is decremented and supplied to the down counter 25.

The data whose value has been multiplied by 1 by the multiplier 32, that is, the data as it is, is set in the down counter 25 as the initial value of the “equal” phase via the subtractor 34. On the other hand, the data whose value has been multiplied by 1.5 by the multiplier 33 is output to the sh
The initial value of the “if” phase is set in the down counter 25.

For example, if the maximum value of the horizontal synchronization data is “64”
If “0”, the output data of the multiplier 32 has the value “64”.
0 ", and the value" 25 "is subtracted by the subtractor 34 to become the value" 615 ". On the other hand, the output data of the multiplier 33 is
The value is “960” (= 640 × 1.5) and the subtractor 35
Subtracts the value “345” (= 320 + 25) to obtain the value “6”.
15 ".

When the leading edge of the vertical synchronizing signal is obtained by the zero coincidence detecting circuit 26, the vertical synchronizing signal generation circuit 27 gives the width of the vertical synchronizing signal based on the timing of the leading edge.
A vertical synchronization signal V is generated (see FIG. 14E). The width of the given vertical synchronizing signal is, for example, the width of one horizontal cycle H. The generated vertical synchronization signal V is supplied to the video processing circuit 11.

As described above, according to the present invention, even if the horizontal synchronization signal cannot be separated in the vertical synchronization signal period regardless of the detection timing of the vertical synchronization signal,
The vertical synchronization signal can be appropriately output using the “equal” and “shift” phases.

Further, according to the present invention, a deviation of the vertical synchronization signal detected by the vertical synchronization signal detection circuit 21 from the horizontal synchronization signal H separated by the horizontal synchronization signal separation circuit 20 is obtained, and this deviation is corrected. The vertical synchronization signal V is generated and output at the same timing. Therefore, when a synchronization signal with a ternary bipolar waveform of a Hi-Vision signal is detected, when a synchronization signal with a binary waveform such as the NTSC system is detected, and when the detection phase of the vertical synchronization signal by the vertical synchronization signal detection circuit 21 is the horizontal cycle , The vertical synchronization signal can be output with the correct phase.

In the above description, the subtracters 34 and 35 are provided, respectively. However, the present invention is not limited to this example. For example, by switching and using a switch circuit,
The subtractors 34 and 35 can be shared.

The up counter 22 can use a down counter by changing the setting of the initial value and the determination of the end of counting. Similarly, the down counter 25
May use an up-counter.

Further, in the above description, the vertical synchronizing signal V is delayed by one horizontal cycle with respect to the vertical synchronizing signal phase of the input signal.
Is assumed, but this is not limited to this example. For example, the vertical synchronization signal V may be output with a delay of two horizontal periods with respect to the vertical synchronization signal phase of the input signal.

Further, the detection of the vertical synchronizing signal performed by the vertical synchronizing signal detecting circuit 21 may be continuous detection for a predetermined period, or may be performed for a low period of one-half horizontal period or more in a half horizontal period. This may be performed by detecting the level.

In the above description, the present invention is applied to a video display device using a CRT as a display device.
This is not limited to this example. That is, as a display device of the image display device, a plasma display, an LC
It can also be used as a sync separation circuit for a video display device having fixed pixels, such as D (Liquid Crystal Display), PALC, FED, and the like.

Further, the present invention provides a video signal processing device and a video signal processing LSI (Large Scale Integrated circuit).
Can be applied to For example, the present invention can be used by being incorporated in an apparatus for performing video processing such as a scan converter, a time base collector, a time shifter, or an LSI. Furthermore, the present invention can be applied to a synchronization signal processing circuit of a video data capture device.

Further, the present invention can be applied to a recording / reproducing apparatus such as a VTR for recording and / or reproducing a video signal. The sync separation circuit according to the present invention can be applied to the sync separation when recording the input video signal.

[0061]

As described above, according to the present invention, a deviation and a phase of the detected vertical synchronization signal with respect to the horizontal synchronization signal H are obtained, and the vertical synchronization signal is corrected at the timing when the deviation and the phase are corrected. V is generated and output. Therefore, when the VTR is variable-speed reproduced, there is no serration pulse in the vertical synchronizing signal, or the horizontal synchronizing signal in the vertical synchronizing signal cannot be correctly separated due to skew caused by switching of a field before the vertical synchronizing signal. Even in such a case, there is an effect that a vertical synchronization signal can be output at a desired timing and phase.

In the embodiment of the present invention, the horizontal synchronizing signal can be output based on the counter operated by the clock CLK.
There is an effect that a horizontal synchronizing signal can be obtained even when there is no serration pulse in the vertical synchronizing signal of the input signal.
Therefore, this embodiment has an effect that it can be applied to driving of a pseudo horizontal synchronization signal and the like.

Further, according to the embodiment of the present invention, the timing for outputting the vertical synchronizing signal is adjusted by the counter. Therefore, even if the vertical synchronizing signal of the input signal contains much noise, it is correct. A vertical synchronization signal can be output at the timing.

Further, in the present invention, a deviation and a phase of the detected vertical synchronization signal with respect to the horizontal synchronization signal H are obtained, and a vertical synchronization signal V is generated and output at a timing at which the deviation and the phase are corrected. Is done.
At the same time, the horizontal synchronizing signal can be output based on a counter operated by the clock CLK. Therefore, there is an effect that a stable signal output having no jitter can be obtained in the non-standard signal of the interlace system.

Therefore, there is an effect that it is suitable for use in a device such as a CRT monitor or a television receiver in which a slight jitter existing in the vertical synchronizing signal affects the display.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an example of a video display device to which the present invention can be applied.

FIG. 2 is a schematic diagram for explaining a method of extracting a synchronization signal from a video signal.

FIG. 3 is a schematic diagram for explaining a method of extracting a synchronization signal from a PC signal.

FIG. 4 is a schematic diagram illustrating an example of a signal output from a synchronization signal extraction circuit.

FIG. 5 is a block diagram showing the configuration of an example of a digital sync separation circuit in more detail;

FIG. 6 is a schematic diagram illustrating an example of input and output signals when a signal based on a video signal is supplied.

FIG. 7 is a schematic diagram illustrating an example of input / output signals when a signal based on a PC signal is supplied.

FIG. 8 is a schematic diagram illustrating an example of input / output signals when a signal based on a Hi-Vision signal is supplied.

FIG. 9 is a schematic diagram illustrating an example of input / output signals when a signal into which a dubbing prevention signal is inserted is supplied.

FIG. 10 is a schematic diagram illustrating a state in which a vertical synchronization signal is detected by detecting a signal having a width twice the width of the horizontal synchronization signal.

FIG. 11 is a block diagram illustrating a configuration example of a vertical synchronization signal detection circuit;

FIG. 12 is a schematic diagram illustrating an example of output of a vertical synchronization signal detection pulse by a vertical synchronization signal detection circuit.

FIG. 13 is a schematic diagram illustrating the operation of an up counter.

FIG. 14 is a schematic diagram for explaining the operation after the down counter.

FIG. 15 is a schematic diagram illustrating an example of a video signal compatible with the NTSC system.

FIG. 16 is a schematic diagram illustrating an example of a video signal compatible with the HDTV system.

[Description of Signs] 11 ... Video processing circuit, 13 ... Synchronization signal extraction circuit, 14 ... Digital synchronization separation circuit, 20 ... Horizontal synchronization signal separation circuit, 21 ... Vertical synchronization signal detection circuit , 22 ... Up counter, 23 ... Vertical signal detection register, 24 ... Equal-shift discrimination circuit, 25 ... Down counter, 26 ... Zero match detection circuit, 27 ... Vertical synchronization signal Creation circuit, 30 ...
Down counter initial value generation unit, 34, 35 ... subtractor, 50 ... L section counter, 53 ... comparison circuit

Claims (18)

[Claims] 1. A synchronizing separation circuit for outputting a horizontal synchronizing signal and a vertical synchronizing signal corresponding to an input video signal, a horizontal synchronizing signal detecting means for detecting a signal corresponding to a horizontal synchronizing signal of the input video signal, A vertical synchronizing signal detecting means for detecting the presence of a vertical synchronizing signal of the video signal; and a signal detected by the vertical synchronizing signal detecting means based on a signal corresponding to the horizontal synchronizing signal detected by the horizontal synchronizing signal detecting means. Position detection means for detecting the position of the vertical synchronization signal, and a start position of a vertical synchronization signal to be output based on a signal corresponding to the horizontal synchronization signal and a position of the vertical synchronization signal detected by the position detection means. And a vertical synchronizing signal output means for determining the synchronization signal. 2. The synchronization separation circuit according to claim 1, wherein the synchronization signal output means corresponds to the next horizontal synchronization signal with respect to the position of the vertical synchronization signal detected by the position detection means. A synchronization separation circuit wherein a leading edge of a signal is the start position of the output vertical synchronization signal. 3. The synchronization separation circuit according to claim 1, wherein the phase of the vertical synchronization signal is started at the same phase as the horizontal synchronization signal based on the position of the vertical synchronization signal detected by the position detection means. And a phase determining unit for determining whether the vertical synchronizing signal is a second phase started in the middle of the horizontal synchronizing signal. 4. The synchronization separating circuit according to claim 3, wherein said vertical synchronization signal output means is configured to determine whether a phase of said vertical synchronization signal is said first phase by said phase determination means. From the position detected by the position detection means, determine the start position of the vertical synchronization signal to be output after a period obtained by subtracting the position detected by the position detection means from the horizontal cycle, and the phase determination means When it is determined that the phase of the vertical synchronization signal is the second phase, the horizontal position of the position detected by the position detecting means is set to 1. A synchronization separation circuit characterized in that a start position of the vertical synchronization signal to be output is determined after a period reduced from a period multiplied by five. 5. The synchronization separation circuit according to claim 1, wherein a clock frequency having a cycle sufficiently shorter than one horizontal cycle from a leading edge of a signal corresponding to the horizontal synchronization signal detected by the horizontal synchronization signal detection means is set to be one. A synchronization separation circuit which counts with a clock having the same and generates a signal corresponding to the next horizontal synchronization signal based on the count value. 6. A sync separation method for outputting a horizontal sync signal and a vertical sync signal corresponding to an input video signal, wherein a step of detecting a horizontal sync signal for detecting a signal corresponding to the horizontal sync signal of the input video signal. A step of detecting a vertical synchronization signal of the video signal; and a step of detecting the vertical synchronization signal based on a signal corresponding to the horizontal synchronization signal detected in the step of detecting the horizontal synchronization signal. Outputting a position based on a position corresponding to the horizontal synchronization signal and a position of the vertical synchronization signal detected by the position detection step, wherein the position is detected by detecting a position of the vertical synchronization signal detected in the step; A step of outputting a vertical synchronization signal for determining a start position of the vertical synchronization signal. 7. A display device for displaying an input video signal on a display means, a horizontal synchronization signal detection means for detecting a signal corresponding to a horizontal synchronization signal of the input video signal, and a vertical synchronization signal of the video signal. Vertical sync signal detecting means for detecting the presence of the signal, and a position of the vertical sync signal detected by the vertical sync signal detecting means based on a signal corresponding to the horizontal sync signal detected by the horizontal sync signal detecting means. Position detecting means for detecting, and a vertical synchronizing signal output means for determining a start position of a vertical synchronizing signal to be output based on a signal corresponding to the horizontal synchronizing signal and a position of the vertical synchronizing signal detected by the position detecting means And a signal corresponding to the horizontal synchronization signal detected by the horizontal signal detection means, and the vertical synchronization signal output from the vertical synchronization signal output means. Display device characterized in that it comprises a signal processing means for performing predetermined signal processing to the input video signal based on the item, and display means for displaying the video signal outputted from said signal processing means. 8. The display device according to claim 7, wherein the synchronization signal output means outputs a signal corresponding to the next horizontal synchronization signal with respect to the position of the vertical synchronization signal detected by the position detection means. A leading edge of the vertical synchronization signal as the start position of the vertical synchronization signal to be output. 9. The display device according to claim 7, wherein the phase of the vertical synchronization signal is started at the same phase as the horizontal synchronization signal based on the position of the vertical synchronization signal detected by the position detection means. A display device, further comprising a phase discriminating means for discriminating a first phase or a second phase in which the vertical synchronizing signal starts in the middle of the horizontal synchronizing signal. 10. The display device according to claim 9, wherein said vertical synchronizing signal output means, when said phase judging means judges that the phase of said vertical synchronizing signal is said first phase, From the position detected by the position detecting means, a period after subtracting the position detected by the position detecting means from the horizontal cycle is determined as a start position of the vertical synchronization signal to be output, and the phase determining means determines When it is determined that the phase of the vertical synchronization signal is the second phase, the horizontal period is set to 1.5 times the position detected by the position detection means from the position detected by the position detection means. A display device, wherein a start position of the output vertical synchronizing signal is determined after a period subtracted from the multiplied period. 11. The display device according to claim 7, wherein a clock frequency of a cycle sufficiently shorter than one horizontal cycle from a leading edge of a signal corresponding to the horizontal synchronization signal detected by the horizontal synchronization signal detection means is provided. A display device which counts with a clock and generates a signal corresponding to the next horizontal synchronization signal based on the count value. 12. A display method for displaying an input video signal on a display means, the method comprising: detecting a signal corresponding to a horizontal synchronization signal of the input video signal; and detecting a vertical synchronization of the video signal. A vertical synchronization signal detection step of detecting the presence of a signal; and the vertical synchronization signal detected in the vertical synchronization signal detection step based on a signal corresponding to the horizontal synchronization signal detected in the horizontal synchronization signal detection step. A position detection step for detecting the position of the signal; and a start position of the output vertical synchronization signal is determined based on the signal corresponding to the horizontal synchronization signal and the position of the vertical synchronization signal detected in the position detection step. A vertical synchronization signal output step, and a signal corresponding to the horizontal synchronization signal detected in the horizontal signal detection step. A signal processing step of performing predetermined signal processing on the input video signal based on the vertical synchronization signal output from the vertical synchronization signal output step; and displaying the video signal output from the signal processing step. And a display step. 13. A signal processing device for performing predetermined signal processing on an input video signal, a horizontal synchronization signal detection means for detecting a signal corresponding to a horizontal synchronization signal of the input video signal, Vertical synchronization signal detection means for detecting the presence of a synchronization signal; and a signal corresponding to the horizontal synchronization signal detected by the horizontal synchronization signal detection means, based on a signal corresponding to the horizontal synchronization signal detected by the vertical synchronization signal detection means. Position detection means for detecting a position; a vertical synchronization signal for determining a start position of a vertical synchronization signal to be output based on a signal corresponding to the horizontal synchronization signal and a position of the vertical synchronization signal detected by the position detection means. Output means; a signal corresponding to the horizontal synchronization signal detected by the horizontal signal detection means; and the vertical signal output from the vertical synchronization signal output means. Signal processing apparatus characterized by a signal processing means for performing predetermined signal processing to the input video signal based on the synchronizing signal. 14. The signal processing device according to claim 13, wherein the synchronization signal output means corresponds to the next horizontal synchronization signal with respect to the position of the vertical synchronization signal detected by the position detection means. A signal processing device wherein a leading edge of a signal is the start position of the output vertical synchronizing signal. 15. The signal processing apparatus according to claim 13, wherein the phase of the vertical synchronization signal is started at the same phase as the horizontal synchronization signal based on the position of the vertical synchronization signal detected by the position detection means. A signal processing apparatus, further comprising: a phase determination unit configured to determine whether the first phase is a second phase or the second phase starts in the middle of the horizontal synchronization signal. 16. The signal processing device according to claim 13, wherein the vertical synchronizing signal output means is configured to determine whether the phase of the vertical synchronizing signal is the first phase by the phase determining means. From the position detected by the position detection means, determine the start position of the vertical synchronization signal to be output after a period obtained by subtracting the position detected by the position detection means from the horizontal cycle, and the phase determination means When it is determined that the phase of the vertical synchronization signal is the second phase, the horizontal position of the position detected by the position detecting means is set to 1. A signal processing device, wherein a start position of the vertical synchronizing signal to be output is determined after a period subtracted from the period multiplied by five. 17. The signal processing device according to claim 13, wherein a clock frequency having a cycle sufficiently shorter than one horizontal cycle from a leading edge of a signal corresponding to the horizontal synchronization signal detected by the horizontal synchronization signal detection means is set. A signal processing device which counts with a clock having the same and generates a signal corresponding to the next horizontal synchronizing signal based on the count value. 18. A signal processing method for performing predetermined signal processing on an input video signal, comprising: a step of detecting a horizontal synchronization signal corresponding to a horizontal synchronization signal of the input video signal; A step of detecting a vertical synchronization signal that detects the presence of a vertical synchronization signal; and a step of detecting the vertical synchronization signal based on a signal corresponding to the horizontal synchronization signal detected in the step of detecting the horizontal synchronization signal. A position detection step for detecting a position of the vertical synchronization signal; and a start position of a vertical synchronization signal to be output based on a signal corresponding to the horizontal synchronization signal and a position of the vertical synchronization signal detected in the position detection step. And a signal corresponding to the horizontal synchronization signal detected in the horizontal signal detection step. , The signal processing method characterized by a step of the signal processing for performing predetermined signal processing to the input video signal based on the above vertical synchronizing signal output from the step of the vertical synchronizing signal output.