JP2002299254A - Manufacturing method for semiconductor wafer and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently produce a high quality semiconductor crystal having little transition and no cracks or polycrystalline lump (high temperature reaction part) by using a comparatively inexpensive silicon as a base wafer. SOLUTION: A reaction-proofing layer (crystalline material B) prevents the reaction of Si with a semiconductor (semiconductor crystal A) of gallium nitride such as GaN. By filming the reaction-proofing layer composed of SiC or AlN, for example, having a fusing point or thermal resistance higher than that of the semiconductor crystal A on the base wafer (Si wafer), even if the crystal A is grown at a high temperature for a long time, the high temperature reaction part is not formed near a silicon interface. Further, stress to be impressed the reaction-proofing layer is relaxed by a void or a membrane part. Therefore, since the reaction-proofing layer through the longitudinal direction can be formed without cracks, and the base wafer and the semiconductor crystal A can be shielded more surely so that the generation of the high temperature reaction part can be prevented more surely. Moreover, the transition density of the semiconductor crystal can be suppressed low by such a stress relaxing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to silicon (Si).
The present invention relates to a method for obtaining a semiconductor substrate by growing a crystal made of a group III nitride compound semiconductor on a base substrate formed by the method. The present invention also relates to a group III nitride compound semiconductor device manufactured using such a semiconductor substrate as a crystal growth substrate.

[0002]

2. Description of the Related Art FIG. 4 is a schematic cross-sectional view of a conventional semiconductor crystal grown on an Si substrate (base substrate). The MOCVD method was employed for this crystal growth step. As illustrated in FIG. 4, a semiconductor crystal (GaN crystal or the like) grown at a high temperature on a Si substrate (base substrate) by a conventional technique has "reaction portions", dislocations, cracks, and the like.

[0003]

Dislocations and cracks are generated as a result of the action of stress generated based on a difference in thermal expansion coefficient and a difference in lattice constant between dissimilar materials. When the semiconductor device is manufactured, the device characteristics are deteriorated. Further, when an independent substrate (crystal) is to be obtained by removing the underlying substrate made of, for example, silicon (Si) and leaving only the growth layer, the large area (1
cm ² ) is almost impossible.

Further, a target semiconductor substrate (semiconductor crystal A)
In the vicinity of the crystal growth temperature of 1000 ° C. to 1150 ° C., silicon (Si) and gallium nitride (GaN) react with each other to form polycrystalline GaN (“reacted portion” in the drawing) in some cases. . Therefore, there is a problem that it is not easy to obtain a single-crystal GaN substrate through a high-temperature crystal growth process.

In order to obtain a single crystal GaN substrate,
Although a method of using a silicon thin film that does not easily generate the above stress as a single crystal growth substrate has been reported, these thin films are easily damaged, and it is not easy to directly handle the thin film before starting the crystal growth. Therefore, it is difficult for these conventional methods to mass-produce a large-area semiconductor substrate with high yield.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to use relatively inexpensive silicon (Si) as a base substrate to form cracks and polycrystalline masses (reaction portions). The objective is to efficiently produce high-quality semiconductor crystals without defects. A further object of the present invention is to manufacture a high-quality semiconductor device by using the above-mentioned semiconductor crystal manufactured with high quality as a crystal growth substrate.

[0007]

Means for Solving the Problems, Functions and Effects of the Invention In order to solve the above-mentioned problems, the following means are effective. That is, the first means of the present invention is the silicon (S
In the process of manufacturing a semiconductor substrate, a semiconductor crystal A made of a group III nitride compound semiconductor is grown on the underlying substrate formed in i), by providing a cavity directly below the crystal growth surface of the underlying substrate. A thin film portion forming step in which the crystal growth surface of the substrate is formed of a thin film portion made of silicon (Si), and a reaction prevention layer made of a crystalline material B having a higher melting point or heat resistance than the semiconductor crystal A is laminated on the thin film portion. This is to provide a reaction preventing layer forming step and a crystal growth step for growing the semiconductor crystal A on the reaction preventing layer.

However, the above-mentioned semiconductor substrate composed of the above-mentioned semiconductor crystal A may have a single-layer structure or a multi-layer structure (multi-layer structure). Also, here, "III
The group nitride compound semiconductor "Generally, binary, ternary, or quaternary" _{Al x Ga y In (1-} xy) N (0 ≦ x ≦ 1,0
≦ y ≦ 1, 0 ≦ x + y ≦ 1) ”, a semiconductor having an arbitrary mixed crystal ratio and a semiconductor further doped with p-type or n-type impurities are also included in the present specification. It falls under the category of “III-nitride compound semiconductors”. Further, a part of the group III elements (Al, Ga, In) is replaced with boron (B) or thallium (Tl), or nitrogen (N) is used.
Part of phosphorus (P), arsenic (As), antimony (S
Semiconductors substituted with b), bismuth (Bi) or the like are also included in the category of “III-nitride compound semiconductors” in the present specification.

The p-type impurities include, for example, magnesium (Mg) or calcium (C
a) and the like can be added. As the n-type impurity, for example, silicon (Si), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), or the like can be added. In addition, two or more of these impurities may be added at the same time, or both types (p-type and n-type) may be added at the same time.

FIG. 1 is a schematic cross-sectional view in a manufacturing process of a semiconductor crystal for exemplifying a basic concept of the present invention. This reaction prevention layer is for preventing the reaction between Si and the gallium nitride-based semiconductor (semiconductor crystal A), and thus has a lower melting point than the gallium nitride-based semiconductor on the underlying substrate (Si substrate). Alternatively, a gallium nitride based semiconductor (semiconductor crystal A) is formed by forming a reaction prevention layer (crystalline material B) made of, for example, SiC or AlN having high heat resistance.
Even when crystal is grown at a high temperature for a long time, the above-mentioned “reaction portion” is not formed near the silicon interface.

Further, since the thin film is formed on the crystal growth surface side of the silicon (Si substrate) by forming the cavity, the stress acting on the reaction preventing layer is alleviated, and these stresses are cracked on the reaction preventing layer. Is formed, so that cracks penetrating in the vertical direction hardly occur in the reaction preventing layer. For this reason, the base substrate (Si substrate) and the gallium nitride-based semiconductor (semiconductor crystal A) can be more reliably blocked by the reaction prevention layer having no crack penetrating in the vertical direction. The generation of the "reaction portion" can be more reliably prevented.

In addition, since the "stress based on the lattice constant difference between the base substrate and the semiconductor substrate" is reduced by the thin film portion or the cavity, the growth of the semiconductor substrate (desired semiconductor crystal A) can be prevented. Unnecessary stress acting on the inside semiconductor substrate is suppressed, and the occurrence density of dislocations and cracks is reduced.
That is, due to the above-described stress relaxing action, dislocations are less likely to be generated in the gallium nitride-based semiconductor (semiconductor crystal A), and the crack generation density can be significantly reduced.

[0013] By the above action and the synergistic effect, it becomes possible or easy to obtain a high-quality semiconductor substrate (semiconductor crystal A) free of the above-mentioned "reaction portion" and cracks and having sufficiently suppressed dislocation density.

The second means is the same as the first means, except that the semiconductor crystal A is replaced by a composition formula of “Al _x Ga
_y In _(1-xy) N (0 ≦ x <1, 0 <y ≦ 1, x + y ≦
1) A group III nitride-based compound semiconductor that satisfies the above condition.

[0015] The third means may be the first or second means.
In the means, the crystalline material B for forming the above-mentioned reaction preventing layer is made of silicon carbide (SiC), aluminum nitride (A
1N) or spinel (MgAl ₂ O ₄ ).

Further, the fourth means is the first or the second means.
In the above method, the crystalline material B for forming the above-mentioned reaction-preventing layer is replaced with an aluminum composition ratio of at least 0.30 or more.
It is composed of 1GaN, AlInN or AlGaInN. Further, as the crystalline material B,
It is desirable to select a stable material having relatively strong bonding strength and high heat resistance (melting point).

Further, the fifth means includes the first to fourth means.
In any one of the means, the thickness of the reaction preventing layer is formed to be 0.1 μm or more and 2 μm or less. If the thickness is too small, the film thickness becomes uneven, or the crystalline material B forming the reaction prevention layer is not a sufficiently stable substance, so that gallium (Ga) or gallium nitride ( GaN) and silicon (Si) cannot be completely cut off. Therefore, the effect of preventing the formation of “reaction portion (polycrystalline GaN)” based on these reactions cannot be sufficiently obtained.

On the other hand, if the thickness of the reaction preventing layer is too large, cracks tend to occur in the reaction preventing layer, and gallium (Ga)
Alternatively, gallium nitride (GaN) and silicon (Si) cannot be completely cut off. Therefore, the effect of preventing the formation of the “reaction portion” based on these reactions cannot be sufficiently obtained. On the other hand, if the thickness of the reaction preventing layer is too large, the lamination time and the laminating material of the reaction preventing layer are additionally required, which is not desirable in terms of production cost and the like.

Further, the sixth means includes the first to fifth means.
After the step of forming a reaction preventing layer by any one of means,
“Al _x Ga ₁ -xN (0 <x ≦
1)) is to provide a step of forming a buffer layer C consisting of:

However, the buffer layer C is approximately 1
A semiconductor layer such as AlN or AlGaN that grows at about 100 ° C. Aside from the buffer layer C, the semiconductor layer further has substantially the same composition as the above-mentioned buffer layer C (eg, AlN or AlGa).
An N) intermediate layer (hereinafter sometimes simply referred to as a “buffer layer”) is provided in a target semiconductor substrate (semiconductor crystal A) periodically, alternately with other layers, or in a multilayer structure. It may be laminated so as to be configured.

By laminating these buffer layers (or intermediate layers), the crystallinity is improved by the same principle of operation as in the prior art such that the stress acting on the semiconductor substrate (growth layer) due to the lattice constant difference can be reduced. It becomes possible. Also,
Such actions and effects are particularly remarkable when the crystalline material B constituting the reaction preventing layer is silicon carbide (SiC) or the like. That is, in this case, it is more desirable to form the buffer layer C on the reaction prevention layer.

A seventh means is that, in the above-mentioned sixth means, the thickness of the buffer layer C is formed to be 0.01 μm or more and 1 μm or less. More preferably, the thickness is 0.02 μm or more and 0.5 μm or less.

If the film thickness is too large, cracks are liable to occur, and the production time, materials, etc. are undesirably increased in cost. If the thickness is too small, it is difficult to form the buffer layer substantially uniformly. For this reason, unevenness in film formation of the buffer layer (a portion where the film is not sufficiently formed) is likely to occur, and unevenness in crystallinity is likely to occur, which is not desirable.

Further, the eighth means includes the first to seventh means.
In any one of the means, the semiconductor crystal A and the underlying substrate are cooled or heated to generate a stress based on a difference in thermal expansion coefficient between the semiconductor crystal A and the underlying substrate, and the stress is used to make use of the side wall of the cavity. To separate the semiconductor crystal A from the underlying substrate by breaking the substrate.

For example, if the semiconductor substrate (semiconductor crystal A) is sufficiently thick, the internal stress or the external stress tends to concentrate on the side wall of the cavity. As a result, these stresses in particular act as shear stress or the like on the side wall of the cavity, and when the stress increases, the thin film portion peels off.
Therefore, if this stress is used, the base substrate and the semiconductor substrate can be easily separated. In addition, as the above-mentioned “cavity” becomes larger, stress (shear stress) tends to concentrate on the side wall of the cavity. That is, according to the ninth means, since the stress can be easily generated, the semiconductor crystal A and the base substrate can be easily separated.

When the base substrate and the semiconductor substrate are separated (separated), a part of the base substrate (such as a thin film portion or broken debris on the side wall of the cavity) may be left on the semiconductor substrate side. That is,
The above-described separation step does not presuppose (requirement) complete separation of each material such that some of these materials are completely eliminated. Such removal of broken debris and the like can be carried out using known means such as lapping and etching as needed.

[0027] The ninth means may be any one of the above-described first to eighth embodiments.
In the crystal growth step of any one of the above means, the semiconductor crystal A is stacked at 50 μm or more. As the thickness increases, the tensile stress on the semiconductor substrate (semiconductor crystal A) is reduced, and the density of dislocations and cracks in the semiconductor substrate can be reduced, and at the same time, the semiconductor substrate can be strengthened.
The above stress is easily concentrated on the side wall.

The thickness of the thin film portion is desirably 20 μm or less. As the thickness is smaller, the tensile stress on the semiconductor substrate (semiconductor crystal A) is reduced, and the density of dislocations and cracks in the semiconductor substrate is reduced. However, when the thickness of the thin film portion is less than 0.02 μm, a problem occurs in the strength of the thin film portion, and it becomes difficult to maintain high productivity. Therefore, in order to ensure the quality and productivity of the crystal growth substrate to be manufactured, the thickness of the thin film portion is desirably 0.02 μm or more and 20 μm or less.

In addition, it is relatively desirable that the thickness of the semiconductor crystal for crystal growth be substantially equal to or greater than the thickness of the thin film portion. With such a setting, the stress on the desired semiconductor crystal is easily alleviated, and the occurrence of dislocations and cracks can be significantly suppressed as compared with the related art. This stress relaxation effect increases as the target semiconductor crystal becomes relatively thick. This stress relaxation effect also depends on the thickness of the thin film portion, but when the thickness of the thin film portion is 20 μm or less, it is substantially saturated at about 50 to 200 μm.

In a tenth aspect, in the thin film portion forming step of any one of the first to ninth aspects, a cavity having an open top is formed physically or chemically in a silicon crystal constituting a base substrate. Forming a cavity and a thin film portion by a migration action near the surface of the base substrate based on a heat treatment at 1000 ° C. to 1350 ° C. provided by a selective etching process.

An eleventh means is characterized in that in the thin film part forming step of any one of the first to ninth means, an ion implantation step of implanting ions into a silicon crystal providing the thin film part, A concave portion forming a cavity having an open top in a silicon crystal constituting a portion other than the thin film portion by physical or chemical etching, a bonding process of bonding the thin film portion to the concave portion by heat treatment, and ion implantation. And a peeling step of peeling off the thin film part with the part as a separation boundary surface.

The "thin film portion forming step" of the present invention can be sufficiently or easily carried out by at least the tenth or eleventh means. However, the “thin film portion forming step” of the present invention is not limited to these means, and may be performed by any other appropriate method. Even in such a case, the operation and effect of the present invention can be obtained to a certain degree or more.

In a twelfth aspect, the height of the cavity formed in the thin film portion forming step of any one of the first to eleventh aspects is set to 0.1 μm or more and 10 μm or less. It is. More preferably, the height of this cavity is
About 0.5 to 5 μm is good. If this value is too large, the formation of the holes, grooves, or columns that support the cavity becomes unstable in terms of strength, or processing becomes gradually difficult or inefficient, which is not desirable. In addition, the processing time is increased, and productivity is not improved. Also, if this value is too small,
This is undesirable because the thin film portion is easily bonded to the bottom surface of the cavity, and the cavity cannot be reliably formed.

According to a thirteenth means, in the group III nitride compound semiconductor device, a semiconductor substrate manufactured by any one of the first to twelfth means is provided as a crystal growth substrate. According to this means, it becomes possible or easy to manufacture a group III nitride compound semiconductor device from a semiconductor having good crystallinity and low internal stress.

A fourteenth means is to manufacture a group III nitride compound semiconductor device by crystal growth using the semiconductor substrate manufactured by any one of the first to twelfth means as a crystal growth substrate. It is to be. According to this means, it becomes possible or easy to manufacture a group III nitride compound semiconductor device from a semiconductor having good crystallinity and low internal stress. By the means of the present invention described above, the above problems can be effectively or rationally solved.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In carrying out the present invention, individual manufacturing conditions may be arbitrarily selected from the following.
These manufacturing conditions may be arbitrarily combined. First, as a method for forming a group III nitride compound semiconductor layer, a metal organic chemical vapor deposition method (MOCVD or MCVD) is used.
OVPE) is preferred. However, molecular beam epitaxy (MBE), halide vapor epitaxy (Halide VPE), liquid phase epitaxy (LPE), etc. may be used, and each layer may be formed by a different growth method. .

The buffer layer has a lattice mismatch.
In the crystal growth substrate or underlayer for reasons such as correcting
It is preferably formed on a substrate or the like. In particular, semiconductor substrates
(Semiconductor crystal A) with buffer layer (intermediate layer)
When forming layers, these buffer layers are formed at low temperature
Group III nitride compound semiconductor Al_xGa_yIn_1-xyN (0 ≦
x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), more preferably Al_xGa _1-x
N (0 ≦ x ≦ 1) can be used. This buffer layer
It may be a single layer or multiple layers having different compositions and the like. Ba
The buffer layer is formed at a low temperature of 380 to 420 ° C.
On the contrary, in the range of 1000 to 1180 ° C, MOCVD method
May be formed. In addition, DC magnetron sputtering equipment
High-purity metallic aluminum and nitrogen gas
Made of AlN by reactive sputtering
A buffer layer can also be formed.

Similarly, the general formula Al _x Ga _y In _1-xy N (0 ≦ x ≦ 1, 0
≦ y ≦ 1, 0 ≦ x + y ≦ 1, the composition ratio is arbitrary). Further, a vapor deposition method, an ion plating method, a laser ablation method, and an ECR method can be used. Buffer layer by physical vapor deposition, 200-600
It is desirable to carry out at ℃. The temperature is more preferably from 300 to 600 ° C, and even more preferably from 350 to 450 ° C. When a physical vapor deposition method such as the sputtering method is used, the thickness of the buffer layer is desirably 100 to 3000 mm. More preferably, 100-400〜, most preferably 100
~ 300Å.

As the multilayer, for example, Al _x Ga ₁ -xN (0 ≦ x
≦ 1) and a GaN layer are alternately formed, and layers having the same composition are alternately formed at a formation temperature of, for example, 600 ° C. or lower and 1000 ° C. or higher. Of course, these may be combined, and the multilayer is composed of three or more group III nitride-based compound semiconductors Al _x Ga _y In _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y
≦ 1) may be laminated. Generally, the buffer layer is amorphous and the intermediate layer is single crystal. A plurality of cycles may be formed with the buffer layer and the intermediate layer as one cycle, and the repetition may be an arbitrary cycle. The more repetitions, the better the crystallinity.

In the buffer layer and the upper group III nitride compound semiconductor, part of the group III element composition can be replaced by boron (B) or thallium (Tl), or the composition of nitrogen (N) can be reduced. Parts are phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi)
The present invention can be substantially applied even if it is replaced by. Further, these elements may be doped to such an extent that they cannot be displayed in composition. For example, a group III nitride-based compound semiconductor having no indium (In) or arsenic (As) in the composition of Al _x Ga _1-x N (0
≦ x ≦ 1), by doping aluminum (Al), indium (In) having a larger atomic radius than gallium (Ga), or arsenic (As) having a larger atomic radius than nitrogen (N), a nitrogen atom The crystal distortion may be improved by compensating for the expansion strain of the crystal due to the loss of the crystal with the compression strain.

In this case, since the acceptor impurity easily enters the position of the group III atom, a p-type crystal can also be obtained by as-grown. By improving the crystallinity in this way, threading dislocations can be further increased by 100 to 100 in accordance with the present invention.
It can be reduced to about 1/0. Buffer layer and
In the case of a base layer in which the group III nitride compound semiconductor layer is formed in two or more periods, it is more preferable to dope an element having a larger atomic radius than the main constituent element in each group III nitride compound semiconductor layer. When a light-emitting element is used, it is preferable to use a binary or ternary group III nitride-based compound semiconductor.

When an n-type group III nitride compound semiconductor layer is formed, Si, Ge, Se, Te,
A group IV element or a group VI element such as C can be added. Examples of p-type impurities include Zn, Mg, Be, Ca, Sr, and Ba.
A Group IV element or a Group IV element can be added. These may be doped with plural or n-type impurities and p-type impurities in the same layer.

It is also optional to reduce dislocations in the group III nitride compound semiconductor layer by using lateral epitaxial growth. At this time, any method using a mask or filling the step by etching can be used.

As an etching mask, polycrystalline silicon, polycrystalline silicon,
Polycrystalline semiconductors such as crystalline nitride semiconductors, silicon oxide (SiO_x),
Silicon nitride (SiN_x), Titanium oxide (TiO_X), Zirconium oxide
(ZrO _X), Oxides, nitrides, titanium (Ti), tungsten
High melting point metal such as (W)
Can be. These film forming methods include vapor deposition, sputtering, CV
Any method other than the vapor phase growth method such as D can be used.

When etching, reactive ion beam etching (RIBE) is desirable, but any etching method can be used. Instead of forming a step having a side surface perpendicular to the substrate surface, an anisotropic etching may be used to form, for example, a V-shaped section having no bottom surface at the bottom of the step.

Semiconductor devices such as FETs and light emitting devices can be formed on group III nitride compound semiconductors. In the case of a light-emitting element, the light-emitting layer may have a homo-structure, a hetero-structure, or a double-hetero structure in addition to a multiple quantum well structure (MQW) and a single quantum well structure (SQW). May be formed.

Hereinafter, the present invention will be described with reference to specific examples. However, the present invention is not limited to the embodiments described below. (First Embodiment) An outline of a procedure for manufacturing a semiconductor crystal (crystal growth substrate) in an embodiment of the present invention will be described below.

[1] Thin Film Part Forming Step This manufacturing step is provided with a concave part forming step in which a cavity with an open top is formed by physical or chemical etching in a silicon crystal constituting a base substrate.
The cavity and the thin film portion are formed by the migration action near the surface of the base substrate based on the heat treatment at ~ 1200 ° C.

(A) Formation of a recess on a silicon substrate A silicon (111) substrate was subjected to plasma etching using a plasma CVD apparatus.
iO ₂ film approximately 1μm deposited and patterned and etched by photolithography and RIE the part and the Si substrate of SiO ₂ film, Si (111) having a diameter of about 0.8μm on the surface of the substrate, a depth of about 3μm Many holes are made at a period (interval) of 1.2 μm. After that, the above SiO ₂ film was
Remove with HF.

(B) Migration Next, the Si substrate on which the concave portions are formed is heat-treated at 1100 ° C. in an H ₂ atmosphere to migrate Si atoms on the surface of the substrate, thereby forming a thin film portion having a thickness of about 1 μm. (Membrane) is formed above the concave portion. That is, by closing the upper part of the concave portion with the thin film portion D1, a number of cavities as illustrated in FIG. 1 are formed. Thereafter, the surface of the obtained substrate is changed to SiO ₂ by wet oxidation at 1150 ° C., and the thickness of the remaining Si thin film portion is reduced to about 0.1 μm.

(C) Washing Thereafter, the SiO ₂ film is removed with buffered hydrofluoric acid. Through the above steps (a) to (c), a Si substrate D having a cavity and a thin film portion D1 as illustrated in FIG. 1 was manufactured.

[2] Step of Forming Reaction Prevention Layer This step of forming a reaction prevention layer is a manufacturing step of laminating a reaction prevention layer on an undersubstrate (Si substrate D) having the thin film portion D1. In the present reaction preventing layer forming step, first, S
On the crystal growth surface (thin film portion D1) of the i (111) substrate, a reaction prevention layer B made of aluminum nitride (AlN) is formed to a thickness of about 1 μm at about 1100 ° C. by vapor phase epitaxy (MOVPE).

[3] Crystal Growth Step Thereafter, in the present crystal growth step, the growth step until the semiconductor crystal A (GaN) grows on the reaction preventing layer B into a thick film having a thickness of about 200 μm is performed using an organic metal compound. This is performed according to a vapor phase growth method (MOVPE method). In this crystal growth step, ammonia (NH ₃ ) gas, carrier gas (H ₂ , N ₂ )
, Trimethylgallium (Ga (CH ₃ ) ₃ ) gas (hereinafter “TMG”)
And trimethylaluminum (Al (CH ₃ ) ₃ ) gas (hereinafter referred to as “TMA”).

On the reaction preventing layer B, a GaN layer (semiconductor crystal A) was grown by about 200 μm by MOVPE. The crystal growth rate of the GaN layer in this MOVPE method is about 30 μm / Hr.

[4] Separation Step (a) After the above-mentioned crystal growth step, while the ammonia (NH ₃ ) gas is flowing into the reaction chamber of the crystal growth apparatus, the base substrate (Si
The wafer having the substrate is cooled to approximately room temperature. The cooling rate at this time is generally “-50 ° C./min to −5 ° C./mi
n ”.

(B) Thereafter, when these were taken out of the reaction chamber of the crystal growing apparatus, a GaN crystal (semiconductor crystal A) separated from the underlying substrate (Si substrate) was obtained. However, this crystal is formed on the back surface of the GaN layer (semiconductor substrate) by the thin film portion D.
No. 1 and broken debris on the side wall of the cavity remain.

[5] Debris Removal Step After the above separation step, lapping treatment is performed to remove the thin film portion D1 made of Si remaining on the back surface of the GaN crystal and broken debris on the side wall of the cavity. However, this debris removal step may be performed by etching using a mixed solution of nitric acid and hydrofluoric acid. Further, the reaction prevention layer B may be removed.

By the above manufacturing method, the film thickness is about 200 μm
Quality GaN crystal (GaN
Layer), that is, a desired semiconductor substrate (semiconductor crystal A) independent of the underlying substrate can be obtained. That is, by the above-described method for manufacturing a semiconductor crystal, a single crystal of gallium nitride (GaN) having excellent crystallinity and a crack-free gallium nitride (GaN) can be obtained.

Therefore, when such a high-quality single crystal is used as a part of a semiconductor light emitting device such as a crystal growth substrate, a high-quality single crystal having a high luminous efficiency or a suppressed driving voltage as compared with the conventional one is obtained. It becomes possible or easy to manufacture semiconductor products such as semiconductor light emitting elements and semiconductor light receiving elements. The use of such a high-quality single crystal makes it possible or easy to manufacture not only an optical element but also a so-called semiconductor electronic element such as a semiconductor power element having a high withstand voltage or a semiconductor high-frequency element operating up to a high frequency. be able to.

In order to correct the lattice constant mismatch between the reaction preventing layer forming step and the crystal growing step, 1000 ° C.
A buffer layer forming step of performing crystal growth at a high temperature of about 1180 ° C. may be provided.

In the above embodiment, as illustrated in FIG. 1, a large number of cavities are provided near the crystal growth surface of the underlying substrate to form the thin film portion of the underlying substrate. It may be formed from a series of cavities. Thus, for example, 1
The hollow of the present invention may be formed by forming the tubular tunnel-type hollow into a long and narrow spiral.
FIG. 1 described above can also be interpreted as a cross-sectional view of a base substrate having a cavity configured as described above. That is, the shape, size, spacing, arrangement, orientation, and the like of the cavity for forming the thin film portion of the base substrate are generally arbitrary.

(Second Embodiment) In the second embodiment, the thin film portion forming process of the first embodiment is replaced by the following "thin film portion forming process".
The other steps need not be changed. Hereinafter, in the present embodiment,
Only the “thin film portion forming step”, which is different from the first embodiment, will be described.

[1] Thin Film Part Forming Step This manufacturing step includes an ion implantation step of implanting ions into a silicon crystal that provides a thin film part, and a silicon crystal constituting a part other than the thin film part of the base substrate. Forming a cavity by a physical or chemical etching process, a bonding step of bonding the thin film portion to the recess by heat treatment, and a peeling step of peeling the thin film portion with the ion-implanted portion as a separation boundary surface. This is for forming a thin film portion.

(A) Ion Implantation Step Hydrogen ions are injected into a silicon crystal (Si (111) substrate) providing the thin film portion D1 at an incident energy of 4 keV and a dose of 2 × 10 ¹⁶ to 1 × 10 ¹⁷ [cm ⁻² ]. inject. FIG.
Is a graph illustrating the number of implanted ions (density) versus the depth at which ions are implanted in the second embodiment.
As can be seen from this figure, an ion implantation layer having a locally high ion density is formed near the ion implantation surface of the silicon crystal.

(B) Concavity forming step On the other hand, another Si (111) substrate (corresponding to symbol D in FIG. 1)
Using a plasma CVD device, the SiO ₂ film is
After forming a film, a part of the SiO ₂ film and the Si substrate are patterned and etched by photolithography and RIE to form a large number of columns having a diameter of about 0.6 μm and a height of about 3 μm on the surface of the Si substrate at intervals of about 2 μm (interval). ).

(C) Joining Step Next, the ion-implanted surface of the silicon crystal for providing the thin film portion D1 is vertically joined to a large number of columns on the surface of the Si substrate.

(D) Separation Step By performing heat treatment at 500 ° C., the silicon crystal providing the thin film portion D1 is separated at the ion implantation portion, and a cavity closed by the thin film portion D1 is formed above.

Through the above steps (a) to (d), a Si substrate D having a cavity and a thin film portion D1 as illustrated in FIG. 1 was manufactured.

The following is an example of a range in which the above-described second embodiment can be modified. For example, hydrogen ions (H
^{Even if} (He ⁺ ) is used instead of ( ⁺ ), substantially the same operation and effect as in the second embodiment can be obtained.

Although the dose of hydrogen ions depends on the material of the underlying substrate and the like, it is approximately 1 × 10 ¹⁵ [/ cm ² ].
It is effective in the range of 1 × 10 ²⁰ [/ cm ² ], and under these conditions, substantially the same operation and effect as described above can be obtained. More preferably, the dose of hydrogen ions is 3 × 1
It is preferably about 0 ¹⁵ to 1 × 10 ¹⁷ [/ cm ² ], and more preferably about 8 × 10 ¹⁵ to 2 × 10 ¹⁶ [/ cm ² ].

If this value is too small, the thin film portion D1
It is difficult to reliably separate the thin film portion D1 from the silicon crystal that provides the above. Also, if this value is too large,
Damage to the thin film portion D1 is increased, and it becomes difficult to separate the thin film portion D1 from the underlying substrate into a shape that is connected to the thin film portion D1 with a substantially uniform thickness.

It is also possible to control the thickness of the thin film portion separated from the underlying substrate by changing the incident energy. FIG. 3 illustrates a measurement result of the depth at which ions are implanted (the maximum density depth h) with respect to the ion implantation energy. For example, as described above, the depth at which ions are implanted (the maximum density depth h) is substantially proportional to the ion implantation energy. Therefore, by adjusting the incident energy (acceleration voltage), the thickness of the thin film portion can be reduced. Can be appropriately controlled.

Further, by performing heat treatment after the ion implantation, a partially broken portion (void) is formed in the ion implantation layer in advance, and at the same time, the crystallinity of the ion implantation portion of the underlying substrate damaged by the ion irradiation is recovered. Can be done. Further, the heat treatment of the thin film portion D1 at the time of forming the cavity can improve the crystallinity of the semiconductor grown thereon.

The thickness of the thin film portion D1 is desirably 20 μm or less. As the thickness is smaller, the tensile stress on the target semiconductor crystal is reduced, and the density of dislocations and cracks is reduced. Therefore, more preferably, the thickness of the thin film portion is preferably 2 μm or less, and more preferably 200 nm or less. In order to realize these values, the ion implantation energy (acceleration voltage) may be adjusted so that the peak of the number of implanted ions has such a depth according to FIG. However, when the thickness of the ion-implanted layer becomes large, it is difficult to control the thickness of the thin film portion.

Although the thickness of the ion-implanted layer cannot be strictly defined, for example, the half-width with respect to the peak value of the number of implanted ions in FIG. The thickness of the thin film portion is more easily controlled as the thickness of the ion implantation layer is reduced. Therefore, means for maintaining the ion implantation energy (acceleration voltage) at a constant value as much as possible is effective in accurately controlling the thickness of the thin film portion.

In each of the embodiments after the first embodiment, the crystalline material B for forming the reaction preventing layer is Al
_x Ga _1-x N (0 <x <1) or the like may be used. With these crystalline materials B, substantially the same functions and effects as those of the above embodiment can be obtained. More generally, as the crystalline material B for forming the reaction prevention layer, silicon carbide (SiC), aluminum nitride (AlN), spinel (MgAl ₂ O ₄ ), or Al having an aluminum composition ratio of at least 0.30 or more is used.
GaN, AlInN or AlGaInN can be used.

Further, the semiconductor crystal A forming the target semiconductor substrate is not limited to gallium nitride (GaN), and is not limited to the above-mentioned general “III-nitride compound semiconductor”.
Can be arbitrarily selected. The target semiconductor substrate (semiconductor crystal A) may have a multilayer structure.

That is, the present invention has no particular limitation on the type (material) of the underlying substrate and the target semiconductor crystal, and includes any known or arbitrary combination of the above-described materials of the underlying substrate and the semiconductor crystal. It can be applied to any kind of heteroepitaxial growth.

In the above embodiment, the metal organic compound vapor phase epitaxy (MOVPE) was used. However, the crystal growth of the present invention can also be performed by the halide vapor phase epitaxy (HVPE). is there.

Further, in the above embodiment, the method of using the semiconductor crystal A as a crystal growth substrate of a semiconductor device after separating the undersubstrate and removing debris has been described, but these separation and debris removal are performed. The process may be performed after laminating the semiconductor layers of the semiconductor element itself, or may be used as a semiconductor element without performing a separation step or the like.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view in a manufacturing step of a semiconductor crystal for exemplifying a basic concept of the present invention.

FIG. 2 is a graph illustrating the number of implanted ions (density) with respect to the depth at which ions are implanted.

FIG. 3 is a graph illustrating the depth at which ions are implanted (the maximum density depth h) with respect to the ion implantation energy.

FIG. 4 is a schematic cross-sectional view illustrating a conventional semiconductor crystal grown on an Si substrate (base substrate).

[Explanation of symbols]

 A: Semiconductor crystal (target semiconductor substrate) B: Reaction prevention layer (crystalline material) D: Silicon substrate (base substrate) D1: Thin film portion of silicon substrate D

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Seiji Nagai 1 Ochiai Nagahata, Kasuga-cho, Nishi-Kasugai-gun, Aichi Prefecture Inside Toyoda Gosei Co., Ltd. (1) Inside the Toyota Central Research Institute Co., Ltd. 1 at 41, Yokomichi, Yokomichi, Toyoda Central Research Laboratory, F-term (reference) 4G077 AA03 BE11 BE15 DB08 ED06 EE01 EE06 EF03 FJ03 TK04 TK08 TK10 TK11 5F045 AA04 AA05 AA10 AA18 AA19 AB06 AB09 AB14 AB17 AB18 AB38 AD14 CA09 DA53 DA67 HA01 HA03 HA04 HA05 HA06

Claims (14)

[Claims] 1. A method for obtaining a semiconductor substrate by growing a semiconductor crystal A made of a group III nitride compound semiconductor on an undersubstrate formed of silicon (Si), comprising: By providing a cavity directly below the surface, the crystal growth surface of the underlying substrate is made of silicon (S
i) forming a thin-film portion comprising a thin-film portion; and a reaction-preventing layer forming step of laminating a reaction-preventing layer made of a crystalline material B having a higher melting point or heat resistance than the semiconductor crystal A on the thin-film portion. And a crystal growth step of growing the semiconductor crystal A on the reaction preventing layer. Wherein said semiconductor crystal A has a composition formula _{"Al x Ga y In (1-} xy) N (0 ≦ x <1,
2. The method according to claim 1, wherein the semiconductor substrate is made of a group III nitride-based compound semiconductor satisfying 0 <y ≦ 1, x + y ≦ 1). 3. The crystalline material B for forming the reaction preventing layer includes silicon carbide (SiC), aluminum nitride (Al
3. The method according to claim 1, wherein the substrate is made of N) or spinel (MgAl ₂ O ₄ ). 4. The crystalline material B for forming the reaction preventing layer, wherein the AlGa having an aluminum composition ratio of at least 0.30 or more.
3. The method according to claim 1, wherein the semiconductor substrate is made of N, AlInN, or AlGaInN. 5. The method according to claim 1, wherein the thickness of the reaction preventing layer is 0.1 μm or more.
The method according to claim 1, wherein the semiconductor substrate is formed to have a thickness of 2 μm or less. 6. After the step of forming a reaction preventing layer, “Al _x Ga ₁ -xN (0 <x ≦
6. The method of manufacturing a semiconductor substrate according to claim 1, further comprising: forming a buffer layer C comprising: 7. The method according to claim 6, wherein the thickness of the buffer layer C is not less than 0.01 μm and not more than 1 μm. 8. The semiconductor crystal A and the underlying substrate are cooled or heated to generate a stress based on a difference in thermal expansion coefficient between the semiconductor crystal A and the underlying substrate. 8. The method according to claim 1, further comprising a separation step of separating the semiconductor crystal A from the base substrate by breaking a sidewall of the cavity. 9. . 9. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the crystal growth step, the semiconductor crystal A is stacked at a thickness of 50 μm or more. 10. The thin film portion forming step includes a concave portion forming step of providing the cavity having an open upper side by physical or chemical etching in a silicon crystal constituting the base substrate, and comprising: 1000 ° C. to 1350 ° C. The method of manufacturing a semiconductor substrate according to claim 1, wherein the cavity and the thin film portion are formed by a migration action near the surface of the base substrate based on the heat treatment. 11. The thin film portion forming step includes: an ion implantation step of implanting ions into a silicon crystal providing the thin film portion; and an upper portion opened to a silicon crystal constituting a portion of the base substrate other than the thin film portion. Forming a concave portion by physically or chemically etching the cavity, bonding a thin film portion to the concave portion by heat treatment, and peeling the thin film portion using the ion-implanted portion as a separation boundary surface. The method for manufacturing a semiconductor substrate according to claim 1, further comprising a peeling step. 12. The semiconductor according to claim 1, wherein the height of the cavity formed in the step of forming the thin film portion is 0.1 μm or more and 10 μm or less. Substrate manufacturing method. 13. A group III nitride manufactured using the method for manufacturing a semiconductor substrate according to any one of claims 1 to 12, comprising the semiconductor substrate as a crystal growth substrate. -Based compound semiconductor devices. 14. A semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor substrate is manufactured by crystal growth using the semiconductor substrate as a crystal growth substrate. Group III nitride compound semiconductor device.