JP2002287706A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to reduce the power consumption further, and to realize miniaturization of a liquid crystal display by reducing circuit parts because the power supply efficiency has been improved to an extreme and resistance elements and differential amplifiers are not required. SOLUTION: The power supply circuit for feeding electricity to a VM voltage terminal of a scanning line driving circuit is constructed only by connecting a stabilizing capacitor across the VM power supply terminal and the ground.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a plurality of scanning lines and a plurality of signal lines arranged in a matrix, a modulation signal applied to the signal lines, and a writing applied line-sequentially to the scanning lines. The present invention relates to a liquid crystal display device that turns on and off a liquid crystal element by a voltage difference from a voltage, and a voltage generation circuit therefor.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been used in most electronic devices because of their features such as light weight, thinness, small size, and low power consumption.

[0003] In particular, there is a strong demand for further lowering power consumption for driving a battery of a portable device or the like, and the development of a reflective liquid crystal display device that does not require a backlight is also progressing. Also, miniaturization is an important issue in portable devices and the like, and there is a strong demand for parts reduction and miniaturization in peripheral circuits of liquid crystal display devices.

A conventional liquid crystal display device will be described with reference to FIG. In FIG. 7, a conventional liquid crystal display device has an L
A scanning line driving circuit 805 for alternately arranging the scanning lines 809 of 1 to L4 and the signal lines 811 of S1 to S4 and applying a predetermined voltage to the scanning lines 809 line by line;
A signal line driving circuit 807 for applying a predetermined modulation voltage according to display data, a selection voltage generating circuit 801 for generating a positive side selection voltage VA and a negative side selection voltage VB to be input to the scanning line driving circuit 805, The reference voltage V which is 1/2 of the value VDD
It comprises a reference voltage generation circuit 803 for generating M.

A signal line driving circuit 807 shown in FIG. 7 captures display data (D0 to D3) by an input display data latch clock (CP), and outputs from each signal line S1 by an output timing control clock (LP). When the display data for one horizontal line in S4 is “1”, the power supply VDD is set when the AC signal DF is “1”, the driving voltage of VSS is set when the AC conversion signal DF is “0”, and the display data is set to “0”. In this case, when the AC signal DF is “1”, the power supply VSS is set.
D from the signal line drive circuit 807 to each signal line S1
To S4.

[0007] Control signals other than those described above are also input as signals to be input to the signal line driving circuit 807, but they are omitted in FIG.

The scanning line driving circuit 805 selects a scanning electrode driven every one horizontal scanning time by an internal logic circuit in accordance with an input frame signal (FRM) and an output timing control clock (LP), and selects the selected scanning electrode. The scanning electrode is supplied to a selection voltage generation circuit 8 based on an alternating signal (DF).
01, and scan voltages (non-selected scan lines) other than the selected scan lines are scanned with the reference voltage VM supplied from the reference voltage generation circuit 803. Apply to lines L1 to L4.

Next, a method of generating each power supply will be described. The selection voltage generation circuit 801 that generates VA and VB
Power supply V composed of switching regulator and supplied
VA is generated from DD by coil boosting. Since the configuration of the switching regulator may be a general one, detailed description is omitted. On the other hand, the negative-side selection voltage VB is equal to the reference voltage V
Since the potential difference between M and the positive side selection voltage VA is equal and a voltage inverted to the negative side is required, the power supply VB is generated by inverting the positive side selection voltage VA with respect to the reference voltage VM. There are a number of ways to generate the inversion. For example, there is a charge pump type inversion circuit. VA and VD
A rectangular wave composed of two voltages of D and having an amplitude of (VA-VDD) is generated, a DC component is cut through a capacitive element, the + side of the rectangular wave is clamped to VSS, and then rectified, then inverted with respect to VM VB is obtained. In the method using the coil output of the switching regulator, when the output of the coil is clamped to VSS by a diode via a capacitor and rectified, VB inverted with respect to the reference voltage VM is obtained. There are various circuit configurations other than the above.

Next, a reference voltage generating circuit 8 for generating a VM
03 will be described. A configuration example of the reference voltage generation circuit 803 will be described with reference to FIG. FIG. 8 shows a circuit for generating the reference voltage VM. The output of the differential amplifier 901 forms a voltage follower that feeds back to the negative input, and the positive input has a potential of 1/2 (VDD) which is an intermediate potential between VDD and VSS.
−VSS) + VSS voltage is input. Since the input voltage of the voltage follower is output as it is to the output voltage, a voltage of VM = Ｖ (VDD−VSS) + VSS is obtained as a VM output.

[0010] In the circuit configuration of FIG.
The reference voltage VM is generated by generating an intermediate voltage from VDD and VSS supplied to the scan line 7, and VA and VB supplied to the scanning line driving circuit 805 are generated symmetrically with respect to the reference voltage VM. On the other hand, the liquid crystal display device disclosed in JP-A-9-50007 has a circuit configuration different from that of FIG. FIG. 7 shows the minimum voltage VLC4 and the maximum voltage VLC0.
VA and VB at the same time, and the voltage between them, VLC
1 (corresponding to VDD in FIG. 7), VLC3 (corresponding to VSS)
Is generated by resistance division, and the reference voltage VLC2 (V
M) are generated by resistance division, impedance-converted by voltage followers, and output. In addition, JP-A-2
000-75260, VH
(VA) and VL (VB)) to the reference voltage VM (VM)
Is set by the resistance partial voltage, and V1 (VSS) generated separately is set to V
V0 (VDD) is generated by inverting an M reference with an inverting amplifier, impedance-converted by a voltage follower, and output.

As described above, as a method of generating the reference voltage VM, the reference voltages are different from each other. In each case, a desired reference voltage is set by resistance division, and the impedance is set by a voltage follower using a differential amplifier. The data is converted and supplied to the VM voltage power supply terminal of the scanning line driving circuit.

[0012]

Since the above-mentioned liquid crystal display device is used as a display device of a mobile device such as a notebook computer, a mobile phone, a PDA, etc., it is strongly desired to reduce the power consumption thereof. In common between the two disclosed liquid crystal display devices, all voltages are generated by resistance division and output by a voltage follower. Therefore, when focusing on power consumption, the power consumed by the resistance division and the voltage follower are expressed as follows. The power consumed by the constituent differential amplifier is always consumed as useless power. On the other hand, in the prior art shown in FIG. 7, only the reference voltage VM is generated by the resistance division and the voltage follower, and the other voltages are constituted by the switching regulator and the inverting circuit of the charge pump. Since the power consumption can be reduced, the power consumption is lower than that of the above two disclosed liquid crystal display devices.

However, in FIG. 7 as well, in the circuit for generating the VM, the power consumed by the resistor is wasted. Also, the power consumed by the differential amplifier is wasted. Furthermore, since the charge / discharge power of the liquid crystal flowing through the differential amplifier is also consumed as wasted power, there is still much wasted power. This will be described in detail with reference to FIG.

FIG. 9 is a circuit diagram for explaining power consumed by charging and discharging of liquid crystal in one pixel formed by the scanning line L1 and the signal line S1. Referring to FIG.
The circuit composed of 1 and the resistor 903 is the VM generation circuit shown in FIG. 8, and the VM output is connected to the scanning line L1 via the scanning line driving circuit 805. The signal line driving circuit 807 selects the input power supplies VDD and VSS according to the display data and applies the selected power supplies to the signal line S1. One pixel including the scanning line L1 and the signal line S1 can be represented by an equivalent circuit of a parallel circuit of the liquid crystal capacitor 302 and the liquid crystal resistor 301.

Now, the signal line driving circuit 807 is connected to the signal line S1.
, A charging current 1003 flows from the signal line S1 to the liquid crystal capacitor 302. At this time, assuming that the capacitance of the liquid crystal capacitor 302 is C,
2 is charged with a charge of C (VDD-VM). Next, when the signal line S1 is applied to VSS by the signal line drive circuit 807, a charging current 1002 flows from the scanning line L1 to the liquid crystal capacitor 302. At this time, the charge C (VDD-VM) held in the liquid crystal capacitor 302 is discharged to the signal line S1. Further, the liquid crystal capacity is changed to C (VM
−VSS). Next, when the signal line driving circuit 807 is switched to VDD again, C (VM-VSS)
Is discharged and charged again by the charging current 1003.

The power consumed here will be described.
The charge charged in the liquid crystal capacitor 302 is C (VM-VSS)
But the power supply VDD of the differential amplifier 901 that generates VM
Charge / discharge current 1002 flows from. Signal line drive circuit 80
Assuming that f is the frequency at which 7 switches between VDD and VSS, f
The power consumed as a whole is W = f × C × (VM−VSS) × (VDD−VSS) (Equation 1). On the other hand, the power charged and discharged by the liquid crystal capacitor 302 is:
Each time the charge is switched, the electric charge C (VDD−VM) = C (VM−
VSS) is charged and discharged, so _WLC = f × C × (VM−VSS) ² (Equation 2). Considering VM = (VDD-VSS) / 2 + VSS (Equation 3), Wp represented by the following equation is a useless power consumed except for charging and discharging the liquid crystal. Wp = W−W _LC = f × C × (VM−VSS) ² (Equation 4) In other words, it can be seen that power equivalent to the power consumed in charging and discharging becomes useless power and the efficiency is 50%.

Further, in addition to the above Wp, the power consumed by the resistance of the resistance dividing circuit for generating the VM and the power consumed by the differential amplifier are consumed as wasted power, and the efficiency of the VM generating circuit is about 20%. It has become. As described above, in the related art, the power generation circuit consumes more wasteful power than the charge / discharge power to the liquid crystal element, and the low power consumption characteristic of the liquid crystal display device cannot be sufficiently obtained.

(Object of the Invention) An object of the present invention is to solve the above-mentioned problems, and by improving the efficiency of a power supply generation circuit of a liquid crystal display device and realizing low power consumption. is there. Another object of the present invention is to reduce the number of circuit components to achieve a reduction in size and cost.

[0019]

In order to solve these problems, a liquid crystal display device according to the present invention employs the following means.

In the liquid crystal display device of the present invention, a liquid crystal is sandwiched between a first electrode substrate having a plurality of signal lines and a second electrode substrate having a plurality of scanning lines intersecting the plurality of signal lines. A liquid crystal panel, a signal line drive circuit that drives the plurality of signal lines, a scan line drive circuit that drives the plurality of scan lines, and a power supply circuit that supplies a plurality of drive voltages to the scan line drive circuit. A power supply terminal for receiving a supply of a positive / negative selection voltage; a reference voltage power supply terminal for receiving a supply of a reference voltage which is an intermediate voltage between the selection voltages; A liquid crystal display device having an output circuit for selecting one from the above and connecting to the scanning line, providing a capacitor, connecting one terminal of the capacitor to one of the power supply lines, and connecting the other terminal to the reference. Connected to the piezoelectric source terminal, without supplying a voltage from the outside, and is configured to generate the reference voltage by a voltage generated in the condenser.

Further, the liquid crystal display device of the present invention is configured such that the capacitance of the capacitor is 100 times or more the capacitance of the liquid crystal panel.

Further, in the liquid crystal display device of the present invention, a liquid crystal is sandwiched between a first electrode substrate having a plurality of signal lines and a second electrode substrate having a plurality of scanning lines intersecting the plurality of signal lines. A liquid crystal panel, a signal line drive circuit for driving the plurality of signal lines, a scan line drive circuit for driving the plurality of scan lines, and a power supply circuit for supplying a plurality of drive voltages to the scan line drive circuit Wherein the scanning line driving circuit includes a selection voltage power supply terminal for receiving supply of positive and negative selection voltages, a reference voltage power supply terminal for receiving supply of a reference voltage that is an intermediate voltage of the selection voltage, In a liquid crystal display device having an output circuit for selecting one from power supply terminals and connecting to the scanning line, a first capacitor and a second capacitor are provided, and one terminal of the first capacitor is connected to one of the power supply terminals. Connect to wire Said Rutotomoni other terminal second
Connected to one terminal of the capacitor, and the other terminal of the second capacitor is connected to any other power line,
The reference voltage is generated by a voltage generated in the first capacitor without supplying a voltage from outside.

Further, in the liquid crystal display device of the present invention, the sum of the capacitance of the first capacitor and the capacitance of the second capacitor is at least 100 times the capacitance of the liquid crystal panel. It is configured.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a preferred embodiment of a liquid crystal display according to the present invention. Note that the same reference numerals are added to the same components as those in the related art. In all the drawings in the present embodiment, the same components are denoted by the same reference numerals, and description thereof is omitted.

[Embodiment 1: FIGS. 1 to 4] FIG. 1 is a configuration diagram of a liquid crystal display device according to the first embodiment. In FIG. 1, each scanning line 809 from L1 to L4 and S1 to S4
The signal lines 811 are alternately arranged, and a scanning line driving circuit 805 for applying a predetermined voltage line-sequentially to the scanning lines 809 and a signal line driving circuit for applying a predetermined modulation voltage to the signal lines 811 in accordance with display data. A circuit 807, a selection voltage generation circuit 801 for generating a positive selection voltage VA and a negative selection voltage VB input to the scanning line driving circuit 805, a power supply of a voltage VDD input to the signal line driving circuit 807, and a voltage VSS. Power supply. Up to this point, the configuration is the same as that of the conventional technique, but in this embodiment, one terminal of the stabilizing capacitor 101 is connected to the VM voltage power supply terminal of the scanning line driving circuit 805 in order to stabilize the voltage. And the other terminal to V
Connect to SS.

The signal line drive circuit 807 receives a display data latch clock CP, data signals D0 to D3, an output timing control clock LP, and an AC signal DF. The scanning line driving circuit 805 has an output timing control clock L
P, a frame signal FRM, and an alternating signal DF are input.

Next, the operation of each component will be described. The signal line driving circuit 807 captures display data (D0 to D3) for one line by the input display data latch clock (CP). Next, the output timing control clock (L
According to P), when the display data of each of the signal electrodes S1 to S4 is "1", the power supply V when the AC signal DF is "1".
DD is a drive voltage of the power supply VSS when “0”, and
When the display data is "0", the AC signal DF is "1".
And the power supply VDD is output from the signal line drive circuit 807 to each of the signal lines S1 to S4 when the power supply voltage is "0".

It should be noted that although control signals other than those described above may also be input as signals to be input to each signal line drive circuit, they are omitted in FIG.

The scanning line driving circuit 805 selects a scanning electrode driven every one line scanning time by an internal logic circuit according to an input frame signal (FRM) and an output timing control clock (LP), and selects the selected scanning electrode. The scanning electrodes (selected scanning lines) are supplied with VA or VB supplied from the selection voltage generation circuit 801 based on the AC signal (DF).
Is applied to the selected scanning electrodes of the scanning lines L1 to L4. Further, scanning lines other than the selected scanning line (non-selected scanning lines) are connected to the V line of the scanning line driving circuit 805.
Connected to M power terminal.

FIG. 2 shows waveforms applied to the electrodes by the signal line driving circuit 807 and the scanning line driving circuit 805.
In FIG. 2, the alternating signal DF is a frame inversion drive for inverting every frame of a first frame (F1) and a second frame (F2). T (L1) to T (L4) indicate periods during which each scanning line is selected, and are synchronized with the output timing control clock (LP). A waveform 201 is an application waveform of the L1 scanning line. In the period T (L1), the selection voltage VA is applied in the first frame and the selection voltage VB is applied in the second frame. A waveform 201 is an application waveform of the L2 scanning line, and the selection voltage is applied in a period of T (L2). In the waveform 203, the display data is “1” for each scanning line,
It is a waveform applied to the signal line S1 when it is switched to “0”. In the period of T (L1) in which L1 is selected, VSS is applied in the first frame because DF is “0”, and VDD is applied in the second frame because DF is “1”. In T (L2), which is the selection period of L2, VD in the first frame in response to the switching of the display data.
D is applied with VSS in the second frame. Waveform 20
Reference numeral 4 denotes a waveform applied to the signal line S2 when the display data is switched between “0” and “1” for each scanning line.
Is “0”, VDD is applied. In the second frame, DF is “1”, so VSS is applied.

As shown in FIG. 2, the polarity of the waveform applied to the scanning line and the polarity of the waveform applied to the signal line are switched by the AC signal DF. Since each applies a target voltage with respect to the reference voltage VM, the effective value applied to the liquid crystal pixel located at the intersection of the scanning line and the signal line is constant, and AC driving in which the direction of current flowing alternately can be realized. ing. The important point here is that since the alternating signal DF is inverted every frame, the application period of the drive voltage VDD and VSS applied to the signal line is always the same regardless of the display data. If this is not the case, a DC voltage is applied to the liquid crystal element, which causes deterioration of the liquid crystal and significantly impairs the quality such as image sticking and reliability deterioration. Therefore, all the liquid crystal display devices are driven so that the application periods of VDD and VSS are always equal within a period of several frames.

Next, a method of generating each power supply will be described. The selection voltage generation circuit 801 that generates VA and VB
Power supply V composed of switching regulator and supplied
VA is generated from D by boosting the coil. Since the configuration of the switching regulator may be a general one, detailed description is omitted. On the other hand, the negative side selection voltage VB is equal to the reference voltage VM.
Since the potential difference is equal to the positive side selection voltage VA and a voltage inverted to the negative side is required, the power supply VB is generated by inverting the positive side selection voltage VA with respect to the reference voltage VM. There are a number of ways to generate the inversion. For example, there is a charge pump type inversion circuit. VA and VD
A rectangular wave having an amplitude of (VA-VDD) consisting of two voltages of D is generated, a DC component is cut through a capacitive element, the + side of the rectangular wave is clamped to VSS, and then rectified, then inverted with respect to VM. VB is obtained. In the method using the coil output of the switching regulator, the output of the coil is clamped to VSS by a diode via a capacitor and rectified to obtain an inverted VB.

Next, a method of generating the reference voltage VM will be described. In FIG. 1, one electrode of the stabilizing capacitor 101 is connected to the VM power supply terminal of the scanning line driving circuit 805,
The other electrode is connected to VSS. In FIG. 1, the other electrode is connected to VSS, but may be connected to VDD or another stable potential. The reference voltage VM is generated only by the stabilizing capacitor 101 connected as described above. This embodiment differs greatly from the prior art in that a reference voltage VM is not generated by using an active element to generate a new external power supply, but a waveform induced from a scanning line is stored in a stabilizing capacitor 101. The point is to generate.

FIG. 3 is a circuit diagram of one pixel constituted by the scanning line L1 and the signal line S1, and is a circuit diagram in a non-selection period (T (L2) to T (L4)) in FIG.
In FIG. 3, there are a liquid crystal resistor 301 and a liquid crystal capacitor 302 at the intersection of the scanning line L1 and the signal line S1. Since the scanning line L1 is in the non-selection period, the scanning line driving circuit 805 connects the VM voltage power supply terminal to the scanning line L1, so that the scanning line L1 is connected to the stabilizing capacitor 101 connected to the VM voltage power supply terminal. Become. The signal line driving circuit 807 alternately selects the input power supplies VDD and VSS and applies the waveform 203 of FIG. 2 to the signal line S1.

How the voltage at the terminal A of the stabilizing capacitor 101 changes will be described with reference to FIG. FIG. 4 is a graph showing a voltage change at the terminal A of the stabilizing capacitor 101, in which the vertical axis represents the voltage V and the horizontal axis represents the time T. A waveform 401 is a voltage waveform at the terminal A of the stabilizing capacitor 101. At T = 0, which is equivalent to turning on the power to the liquid crystal display device, the voltage is 0 V because the stabilizing capacitor 101 is not charged.

Thereafter, when the power is turned on, the waveform 2 in FIG.
As shown in FIG. 03, VDD and VSS are alternately applied to the signal line S1. At this time, charging is started by an integrating circuit formed by the liquid crystal resistor 301 and the stabilizing capacitor 101. The time constant τ at this time is represented by τ = R · Cs (Equation 5), where R is the resistance value of the liquid crystal resistor 301 and Cs is the capacitance of the stabilizing capacitor 101. In a normal liquid crystal, the resistance value R is several 100 kΩ to several MΩ depending on the screen size, so that if 1 μF is used for the stabilizing capacitor 101, the charging time constant is about 1 second. As shown in the waveform 203 of FIG.
Since D and VSS are switched for each frame by the AC conversion signal DF, as described above, during driving of the liquid crystal display device, the sum of the period during which VDD is applied to the signal line S1 and VSS during a few frames are reduced. The sum of the applied periods is always equal. The frame period in FIG.
Since the period is 4 msec or less and the period is much shorter than the time constant τ, the voltage VM at the terminal A of the stabilizing capacitor 101 is an intermediate voltage between VDD and VSS. VM = (VDD−VSS) / 2 + VSS 6) is charged as the final voltage. A waveform 403 in FIG. 4 shows a state of charging.

Further, since the liquid crystal capacitance 301 and the stabilizing capacitor 101 are connected in series, the fluctuation of ΔV obtained by dividing the fluctuation of the potential of the signal line S1 by the two capacitance elements is superimposed. ΔV at this time is as follows: ΔV = Cs / (C + Cs) × (VDD−VSS) (Equation 7). A waveform 401 obtained by superposing this voltage variation on the waveform 403 in FIG. 4 is the actual charging waveform of the voltage VM at the terminal A of the stabilizing capacitor 101.

Referring to the waveform 401 of FIG. 4, if the voltage VM at the terminal A of the stabilizing capacitor 101 has a sufficient time constant τ, a voltage waveform is obtained by superimposing Equations 6 and 7. Here, if the capacitance Cs of the stabilizing capacitor 101 is set to be 100 times or more as large as the capacitance C of the liquid crystal capacitance 301, ΔV in Expression 7 becomes 1/100 or less, and is expressed by Expression 6. The variation is very small compared to the voltage VM. That is, the amount of change in Expression 7 can be ignored, and the voltage VM at the terminal A of the stabilizing capacitor 101 can be regarded as always being charged with the voltage represented by Expression 6.

The voltage of the equation (6) is an intermediate potential between VDD and VSS, and is a desired reference voltage. That is,
The reference voltage VM can always be obtained from the stabilizing capacitor 101.

Next, a sufficient time elapses after the power is turned on,
The charge / discharge power when the scanning line L1 is driven when the reference voltage VM shown in Expression 6 is charged in the stabilizing capacitor 101 is calculated. In FIG. 3, the charging current 310
Is the charging current when the signal line driving circuit 807 selects VDD, and the charging current 311 is
This is the charging current when S is selected. Here, considering that the capacitance ratio between the liquid crystal capacitance C and the stabilizing capacitor Cs is sufficiently large and that the stabilizing capacitor 101 is already charged to the voltage VM, the signal line driving circuit 807 selects VDD. In this case, the liquid crystal capacitor 302 is charged with a charge of C (VDD−VM) by the charging current 310. Subsequently, when VSS is selected, the charge charged via the charging current 311 is discharged, and C (VM-VS
The charge of S) is charged. Therefore, assuming that the frequency at which the signal line driver circuit 807 switches between VDD and VSS is f, W = f / 2 × C ((VDD−VM) ² + (VM−VSS) ² ) (Equation 8) ). This is equivalent to the power that is charged and discharged by the liquid crystal capacitance (Equation 2). That is, useless power Wp is not generated unlike the related art, which means that the power supply efficiency is almost 100%. Further, since no resistance element, no differential amplifier, etc. are used unlike the prior art, it is clear that there is no loss.

In the first embodiment, the capacitance of the stabilizing capacitor 101 is set to 100 times the liquid crystal capacitance.
According to Equation 7, the higher the magnification is, the more the variation Δ of the VM power supply is.
V can be reduced. Since the fluctuation ΔV of the VM power supply adversely affects the display as image noise called crosstalk, it is important to keep the fluctuation ΔV of the VM power as small as possible. Generally, it is considered that there is no problem if it is within ± 1% which is equivalent to the class of the high performance power supply circuit. Therefore, in the present embodiment, it is necessary to suppress the variation within 1%. However, in order to make ΔV a variation of 1%, the capacitance of the stabilizing capacitor 101 is set to 10% of the liquid crystal capacitance.
It can be seen that it is sufficient to set it to 0 times. In general, the liquid crystal capacity of the entire liquid crystal panel is about 0.01 u to 0.1 u (F), so that even if it is set to 100 times, the capacitance of several to 10 μ (F) is enough, so it is set to 100 times or more. It is relatively easy to do.

In the above description, the signal line S1 and the scanning line L1 are cut out.
2 to L4 are also connected to the VM power supply terminal of the scanning line driving circuit 804 during the non-selection period.
, An application waveform of S4 is induced. In this case as well, from the viewpoint of the principle of liquid crystal AC drive, VDD and V
The selection period of SS always becomes equal, and the stabilizing capacitor 1
In 01, the voltage VM of Expression 6 can be obtained.

[Second Embodiment: FIG. 5] Next, a second embodiment will be described. FIG. 5 shows a configuration diagram in the second embodiment. In FIG. 5, a configuration different from that of the first embodiment is the first stabilizing capacitor 101 and the power supply voltage VD.
The point is that the second stabilizing capacitor 501 is added between D. Referring again to FIG. 4 showing the state of the charging waveform in the first embodiment, the time constant τ is about 1 second. Depending on the device using the present liquid crystal display device, it may be necessary to rapidly display after turning on the power. The second embodiment aims to improve the rise after the power is turned on.

In FIG. 5, immediately after the power is turned on, the second stabilizing capacitor 501 and the first stabilizing capacitor 101 are not charged. After this, the power is turned on,
When a voltage of VDD is applied to the second stabilizing capacitor 501, the capacitance of the second stabilizing capacitor 501 becomes C
Assuming that c, the voltage VM at the terminal A is as follows: VM = (VDD−VSS) × Cs / (Cc + Cs) + VSS (Equation 9) Now, the capacitance Cc of the second stabilizing capacitor 501 is changed to the capacitance Cs of the first stabilizing capacitor 101.
If it is equal to, VM = (VDD−VSS) / 2 + VSS (Equation 10), which is equal to the voltage of Equation 6. The time constant τ until this voltage becomes about several seconds because the internal resistance of the power supply VDD is very low. FIG. 6 shows the charging current waveform at this time. 6, a waveform 601 is a power supply waveform of the voltage VM at the terminal A in FIG. As shown in FIG. 6, the voltage rapidly rises to the voltage of Expression 10 with the time constant τ, and thereafter, the voltage change of the signal line is induced as in the first embodiment, and the first stable voltage around the voltage of Expression 10 is obtained. A voltage fluctuation of ΔV is superimposed on the multiplexing capacitor 101.

In the second embodiment, the terminal A is rapidly charged to the voltage of Expression 10 immediately after the power is turned on by adding the second stabilizing capacitor 501. Since the operation is completely the same, the power supply efficiency is also almost 100%. Since no resistance element, no differential amplifier and the like are used as in the prior art, there is no loss.

In the second embodiment, the terminal of the second stabilizing capacitor 501 is connected to VDD. However, according to Equation 9, even if the terminal of the second stabilizing capacitor 501 is connected to a power source other than VDD, the second stabilizing capacitor 501 is connected. By adjusting the capacitance Cc of
Obviously, it can be equal to the desired reference voltage VM indicated by. Further, it is not necessary to make the voltage equal to the voltage of Expression 6, and the rise at the time of turning on the power can be considerably improved only by setting the voltage roughly. In this case, the capacitance Cc of the second stabilizing capacitor 501 can be reduced, which is advantageous for downsizing the circuit.

[0047]

As described above, according to the present embodiment,
The stabilizing capacitor connected to the VM voltage power supply terminal can obtain a DC voltage of an intermediate potential between VDD and VSS applied to the signal line, and it is not necessary to newly generate a VM power unlike the conventional technology, so that the size is small. Is possible. Furthermore, in the present embodiment, the power supply efficiency is almost 100%, and the power consumption can be reduced by a factor of two or more as compared with the conventional technology. Since there is no wasted power, it is possible to further reduce power consumption.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing applied waveforms according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram according to the first embodiment of the present invention.

FIG. 4 is a voltage-time characteristic of a voltage VM at a terminal A according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram illustrating a configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a voltage-time characteristic of a voltage VM at a terminal A according to the second embodiment of the present invention.

FIG. 7 is a configuration diagram illustrating a configuration of a liquid crystal display device according to a conventional technique.

FIG. 8 is a circuit diagram of a VM generation circuit according to a conventional technique.

FIG. 9 is a circuit diagram for explaining an operation in a conventional technique.

[Explanation of symbols]

101 Stabilizing capacitor 201 Applied waveform of scanning line L1 203 Applied waveform of signal line S1 301 Liquid crystal resistor 302 Liquid crystal capacitance 310 Charging current when VDD is applied to signal line S1 in FIG. 1 311 Apply VSS to new word line S1 in FIG. Charge current when applied 401 Voltage waveform of voltage VM at terminal A in FIG. 1 501 Second stabilizing capacitor 601 Voltage waveform of voltage VM at terminal A in FIG. 5 803 Generating circuit of voltage VM in prior art 901 Differential Amplifier 903 Resistance element 1002 Conventional charging current 1003 Conventional charging current

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2H093 NA31 NC01 ND39 ND42 ND54 5C006 AC02 AC27 AF69 BB11 BC16 BF37 BF42 FA41 FA47 FA51 5C080 AA10 BB05 DD22 DD26 DD27 FF03 FF09 JJ02 JJ03 JJ04 JJ05

Claims (4)

[Claims] A first electrode substrate having a plurality of signal lines; and a second electrode having a plurality of scanning lines intersecting the plurality of signal lines.
A liquid crystal panel having liquid crystal sandwiched between the electrode substrates, a signal line driving circuit for driving the plurality of signal lines, a scanning line driving circuit for driving the plurality of scanning lines, and the scanning line driving circuit. A power supply circuit for supplying a plurality of drive voltages, wherein the scanning line drive circuit receives a selection voltage power supply terminal for receiving supply of positive and negative selection voltages, and a supply of a reference voltage which is an intermediate voltage of the selection voltages. In a liquid crystal display device having a reference voltage power supply terminal and an output circuit for selecting one of the respective power supply terminals and connecting to the scanning line, a capacitor is provided, and one terminal of the capacitor is connected to one of the power supply lines. Connecting the other terminal to the reference voltage power supply terminal, and generating the reference voltage by a voltage generated in the capacitor without supplying a voltage from outside. A liquid crystal display device. 2. The liquid crystal display device according to claim 1, wherein the capacitance of the capacitor is at least 100 times the capacitance of the liquid crystal panel. 3. A first electrode substrate having a plurality of signal lines and a second electrode having a plurality of scanning lines intersecting the plurality of signal lines.
A liquid crystal panel having liquid crystal sandwiched between the electrode substrates, a signal line driving circuit for driving the plurality of signal lines, a scanning line driving circuit for driving the plurality of scanning lines, and the scanning line driving circuit. A power supply circuit for supplying a plurality of drive voltages, wherein the scanning line drive circuit receives a selection voltage power supply terminal for receiving supply of positive and negative selection voltages, and a supply of a reference voltage which is an intermediate voltage of the selection voltages. A first capacitor and a second capacitor, wherein the first capacitor and the second capacitor are provided, wherein the first capacitor and the second capacitor are provided. Is connected to one of the power supply lines, the other terminal is connected to one terminal of the second capacitor, and the other terminal of the second capacitor is connected to any other power supply line. , Without supplying an external voltage, the liquid crystal display device and generates the reference voltage by a voltage generated in the first capacitor. 4. The capacitance of the first capacitor and the capacitance of the second capacitor are 100 times or more the capacitance of the liquid crystal panel. 4. The liquid crystal display device according to 3.