JP2002125145A - Image pickup device and drive method for solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To propose an image pickup device with a simple configuration that picks up an image of an object at a high-speed. SOLUTION: After thinning out reading where only charges thinned out from the parts of pixels in the vertical direction among all pixels formed to an image pickup face of a solid-state image pickup element 3 are read, only charges by number of lines corresponding to the thinned out number of the pixels are vertically transferred, and by alternately executing the thinning out reading and the vertical transfer of the charges the image pickup interval can be reduced even more than that of the conventional technology without the need for a design change of the solid-state image pickup element 3 thereby enabling high-speed image pickup with a simple configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus and a method for driving a solid-state image pickup device, and is suitable for application to, for example, a digital still camera.

[0002]

2. Description of the Related Art Conventionally, there is a digital still camera that converts a captured image of a subject into digital data, and stores and stores the converted digital data in a memory. This digital still camera has a solid-state image sensor (CCD: Charge Coupled Device) as an image sensor.
Is adopted.

[0003]

In this digital still camera, when performing continuous imaging, it is necessary to read out all pixels constituting one screen each time imaging is performed. Imaging was the limit.
For example, when the horizontal drive frequency is 14.3 [MHz] and the number of pixels is 330,000, imaging can be performed only at intervals of 23 [ms], and high-speed continuous imaging cannot be realized.

Therefore, as a method of realizing high-speed continuous imaging, a method of reducing the number of pixels from which signals are read out of the pixels constituting the CCD to increase the frame rate (ie, the number of images that can be acquired per second), or , Reading frequency of horizontal transfer register (ie, reading speed)
To raise the frame rate.

However, in the method of increasing the frame rate by reducing the number of pixels for reading, the number of pixels itself is reduced, so that it is inevitable that the image quality deteriorates, and the reading frequency of the horizontal transfer register is increased. In the method of increasing the frame rate, the transfer efficiency in the horizontal transfer register deteriorates, and the margin of the clock used in the signal processing circuit provided at the subsequent stage of the CCD is insufficient.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is an object of the present invention to propose an imaging apparatus and a driving method of a solid-state imaging device capable of performing high-speed continuous imaging with a simple configuration.

[0007]

According to the present invention, in order to solve the above-mentioned problems, a thinning-out operation for reading out electric charges by thinning out only a part of pixels in a vertical direction among all pixels formed on an imaging surface of a solid-state imaging device. After performing the readout, vertical transfer is performed only for the number of lines corresponding to the number of thinned pixels of the pixel, and the thinned readout and the vertical transfer are alternately performed. The imaging interval can be further reduced.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a digital still camera as a whole, and an incident light L1 incident from the subject side passes through an optical lens 2 to a solid-state imaging device (CC).
D: Charge Coupled Device) 3. CCD
3 generates an image signal S1 by photoelectrically converting the received incident light L1 based on a signal supplied from the timing generation circuit 4, and samples and holds the image signal S1.
H) Send to circuit 5.

That is, as shown in FIG.
3 receives the incident light L1 by the photo sensor unit 10. The photosensor unit 10 receives the incident light L
An electric charge is obtained by photoelectrically converting 1 and the electric charge is accumulated. Then, the electric charge accumulated in the photo sensor unit 10 is transferred from the photo sensor unit 10 to the vertical transfer register 11 at a timing based on the read pulse signal S2 supplied from the timing generation circuit 4.

Subsequently, the electric charge transferred to the vertical transfer register 11 is transferred from the vertical transfer register 11 to the horizontal transfer register 12 line by line at a timing based on the vertical transfer clock signal S3 supplied from the timing generation circuit 4. Will be transferred.

The electric charge transferred to the horizontal transfer register 12 is transferred from the horizontal transfer register 12 to the output unit 13 at a timing based on the horizontal transfer clock signal S4 supplied from the timing generation circuit 4, and is output from the output unit 13. It is output for each line as the image signal S1.

The S / H circuit 5 generates an analog image signal S10 based on the image signal S1 supplied from the CCD 3, and sends it to an analog / digital (A / D) conversion circuit 20. The A / D conversion circuit 20 converts the image signal S10 from analog to digital, and sends the resulting image data S11 to the camera signal processing circuit 21.

The camera signal processing circuit 21 outputs the image data S
For example, image data S12 is obtained by performing data processing such as gamma correction and gain control on the liquid crystal display 11 via a switching circuit 22.
CD: Liquid Crystal Display (LC) 23
D23 is displayed.

In this state, when the user performs an operation for recording the image data S12 on the operation unit 30, the operation unit 30 issues an instruction signal S14 for performing the recording operation.
To the controller 31. The controller 31
Based on the supplied command signal S14, a recording control signal S15 for controlling the recording of the image data S12 is generated, and the recording control signal S15 is sent to the memory control 32 and the switching circuit 22.

The switching circuit 22 controls the recording control signal S15
Image data S12 supplied from the camera signal processing circuit 21 via the data bus BUS to the DRAM
(Dynamic Random Access memory) 33.

The memory control 32 is supplied with a horizontal synchronizing signal H and a vertical synchronizing signal V from the timing generation circuit 4 via the camera signal processing circuit 21.
The image data S12 is once written in the DRAM 33 while the horizontal synchronization signal H and the vertical synchronization signal V are added to the image data S12 based on the recording control signal S15 supplied from.

Thereafter, the memory control 32
The image data S12 is read from the RAM 33, and the read image data S12 is sent to the compression / decompression circuit 34 via the data bus BUS. The compression / decompression circuit 34
JPEG (Joint Photographic Coding Experts Group
) Image data S12 by a coding method based on the standard
Is compressed and encoded to generate compressed image data S17, which is written and stored in the flash memory 35.

In this state, when the user performs an operation for reproducing the compressed image data S17 on the operation unit 30, the operation unit 30 issues a command signal S1 for performing the reproduction operation.
4 to the controller 31. Controller 31
Generates a playback control signal S20 for playing back the compressed image data S17 based on the supplied command signal S14, and sends out the playback control signal S20 to the flash memory 35, thereby reading out the compressed image data S17 from the flash memory 35 and compressing it. / Expansion circuit 34.

The compression / decompression circuit 34 decompresses and decodes the compressed image data S17 supplied from the flash memory 35, and transfers the resulting image data S21 to the data bus BUS.
To the switching circuit 22 via In the switching circuit 22,
The reproduction control signal S20 generated based on the command signal S15 by the controller 31 is supplied to the switching circuit 2
2 displays the image data S21 supplied from the compression / decompression circuit 34 on the LCD 23 based on the reproduction control signal S20.
And displays it on the LCD 23.

By the way, this digital still camera 1
Has been made to be able to perform high-speed imaging,
When the user performs an operation for performing high-speed imaging on the operation unit 30, the operation unit 30 sends a command signal S <b> 14 for performing high-speed imaging to the controller 31. The controller 31 generates a high-speed imaging control signal S25 based on the supplied command signal S14, and sends it to the timing generation circuit 4, the camera signal processing circuit 21, the switching circuit 22, and the memory control 32.

The timing generation circuit 4 includes a controller 3
1 together with the solid-state imaging device driving means, and based on the supplied high-speed imaging control signal S25, the readout pulse signal S
2. Generate a vertical transfer clock signal S3 and a horizontal transfer clock signal S4 and send them to the CCD 3. CCD
3 performs a so-called thinning-out readout in which electric charges are read out from only some of the vertical pixel rows among all the pixels based on the readout pulse signal S2 supplied from the timing generation circuit 4.

The CCD 3 executes the thinning-out reading and transfers the electric charges to the vertical transfer register 11, and then transfers the electric charges to the vertical transfer register 11 at a timing based on the vertical transfer clock signal S 3 supplied from the timing generation circuit 4. To the horizontal transfer register 12 for vertical transfer. As described above, the CCD 3 enables high-speed imaging by alternately performing thinning-out reading and vertical transfer.

Specifically, as shown in FIG.
D <b> 3 reads out charges from only one-eighth of the photosensor units 10 provided for each pixel and transfers them to the vertical transfer register 11. That is, only the electric charges accumulated in the photosensor unit 10 of one of the eight lines (for example, the first line, the ninth line,...) Are read.

The electric charge transferred to the vertical transfer register 11 is transferred from the vertical transfer register 11 to the horizontal transfer register 12 at a timing based on the vertical transfer clock signal S 3 supplied from the timing generation circuit 4.
Stage (ie, one line) transfer.

Then, after a predetermined exposure time has elapsed, the CCD 3 performs thinning-out reading of charges again and executes vertical transfer. In this manner, the CCD 3 alternately repeats the thinning-out reading and the vertical transfer eight times, thereby obtaining
Eight images (A to H) with different exposure timings are obtained.

In this case, the electric charge transferred to the horizontal transfer register 12 is transferred from the horizontal transfer register 12 to the output unit 13 at a timing based on the horizontal transfer clock signal S4 supplied from the timing generation circuit 4, and the output unit 13 1
3 is output for each line as an image signal S30.

FIG. 3 shows a timing chart for executing high-speed imaging. FIG. 3A shows the read pulse signal S2, and FIG. 3B shows the vertical transfer clock signal S3. FIG. 3C shows the exposure time, which is determined by the read pulse signal S2. FIG. 3 (D)
Indicates the output timing of each line of the image signal S30 output from the output unit 13, that is, the CCD 3, and the image signal S30 is generated by the vertical transfer clock signal S3 for each line.
Is output in synchronization with.

In this case, since the CCD 3 cannot output the image signals S30 of all the picked-up lines during the imaging period, the CCD 3 cannot output the image signals of the remaining lines during the reading period even after the end of the imaging period. Signal S
30 is output (FIG. 3D).

The image signal S30 output from the CCD 3 is converted into image data S31 through the S / H circuit 5, the A / D conversion circuit 20 and the camera signal processing circuit 21 in this order, and then the switching circuit 22 The data is sequentially written to the DRAM 33 via the data bus BUS.

Since the image signal S30 is generated by alternately executing the thinning-out reading and the vertical transfer in the CCD 3, the image signal S30 is transferred from the vertical transfer register 11 to the horizontal transfer register 12 irrespective of the order of the exposure timing.
Are output line by line in the order of transfer.

Therefore, the memory controller 32 rearranges the image data S31 on the DRAM 33 based on the high-speed imaging control signal S25 supplied from the controller 31, thereby generating eight correct images for each exposure timing. Are transmitted to the camera signal processing circuit 21 via the data bus BUS as image data S32.

Since the image data S32 has a data amount reduced to 1/8 in the vertical direction, the camera signal processing circuit 21 performs a vertical interpolation process on the image data S32 and obtains the result. The interpolated image data S33 is sent to the compression / decompression circuit 34 via the data bus BUS. The compression / expansion circuit 34 calculates the interpolation image data S33
Is compressed and encoded to generate compressed image data S34, which is written and stored in the flash memory 35.

In this state, when the user performs an operation for reproducing the compressed image data S34 on the operation unit 30, the controller 31 reads the compressed image data S34 from the flash memory 35 and compresses / compresses the compressed image data S34. The data is transmitted to the LCD 23 via the decompression circuit 34, the data bus BUS, and the switching circuit 22 for display.

In the above-described configuration, the CCD 3 has one-eighth of all pixels formed by the photo sensor unit 10 at the time of high-speed imaging.
Charges are read out from only the pixels of the number. And CCD3
Performs the thinning-out read and transfers the electric charges to the vertical transfer register 11, and then performs one-stage vertical transfer. In this way, the CCD 3 enables high-speed imaging by alternately performing thinning-out reading and vertical transfer.

That is, the minimum interval between image pickups is the sum of the time required to transfer charges to the vertical transfer register 11 and the time required for one-stage vertical transfer, and is several tens of μs.
Can be taken at intervals of. This makes it possible to further reduce the imaging interval as compared with the related art. For example, the transfer time to the vertical transfer register 11 is 3.5 [μ].
s] The time required for one-stage vertical transfer is 15 [μs]
Then, continuous imaging at intervals of about 19 [μs] becomes possible.

Further, since the CCD 3 does not require a special structure and a general-purpose CCD can be used, high-speed imaging can be performed with a simple configuration without changing the design of the CCD 3. Further, in this digital still camera 1,
At the time of high-speed imaging, 1/8 of all pixels are read out. On the other hand, by reading out all pixels at normal times, high-speed imaging can be performed while suppressing deterioration of image quality.

According to the above-described configuration, after performing the thinning-out reading for reading out the charges from only some of the vertical pixel rows among all the pixels of the photo sensor unit 10 formed on the imaging surface of the CCD 3, the charge To the vertical transfer register 11
To perform one-stage vertical transfer, and alternately perform the thinning-out reading and the one-stage vertical transfer, thereby obtaining the CC.
The imaging interval can be further shortened as compared with the related art without changing the design of D3, and thus high-speed imaging can be performed with a simple configuration.

In the above-described embodiment, a case has been described in which electric charges are read out from only 1/8 of all the pixels. However, the present invention is not limited to this. For example, 1/10 of all the pixels may be read out. The charge may be read out from only the number of pixels, that is, the charge may be read out from only some of the vertical pixel rows among all the pixels.

In the above-described embodiment, a case has been described in which one-stage vertical transfer is performed after charges are transferred to the vertical transfer register 11, but the present invention is not limited to this. For example, two-stage vertical transfer is performed. In other words, the vertical transfer may be performed by the number of stages (that is, by the number of lines) corresponding to the number of thinned pixels to be read.

In the above-described embodiment, a case has been described in which the charge is read from the photosensor unit 10 at the timing based on the read pulse signal S2 supplied from the timing generation circuit 4 to adjust the exposure time.
The present invention is not limited to this, and sweeps out the charge accumulated in the photo sensor unit 10 of the CCD 3 at a timing based on the sub-pulse signal as shown in FIG.
(F)), the exposure time can be further finely adjusted by controlling the generation timing of the sub-pulse signal.

In the above-described embodiment, the case where charges are read from the photosensor section 10 at the timing based on the read pulse signal S2 supplied from the timing generation circuit 4 has been described, but the present invention is not limited to this. Alternatively, the image capturing may be performed by setting the exposure time and the image capturing interval for each exposure, or may be performed at a preset exposure time and image capturing interval for one trigger.

In the above-described embodiment, the case where the present invention is applied to the CCD 3 has been described. However, the present invention is not limited to this, and may be, for example, a CMOS (Complementory Metal).
Various other solid-state imaging devices such as Oxide Semiconductor may be applied to the present invention.

Further, in the above-described embodiment, the case where the present invention is applied to the digital still camera 1 has been described. However, the present invention is not limited to this. The present invention can be widely applied.

[0045]

As described above, according to the present invention, after performing the thinning-out reading for reading out the electric charges by thinning out only some of the pixels in the vertical direction among all the pixels formed on the imaging surface of the solid-state imaging device. By performing vertical transfer only for the number of lines corresponding to the number of thinned pixels of the pixel, and alternately performing the thinned readout and vertical transfer, the imaging interval can be further reduced compared to the conventional one without changing the solid-state image sensor design Thus, high-speed imaging can be performed with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an imaging device according to the present invention.

FIG. 2 is a schematic diagram illustrating a configuration of a CCD.

FIG. 3 is a schematic diagram illustrating a timing chart at the time of high-speed imaging.

[Explanation of symbols]

1 ... digital still camera, 2 ... optical lens, 3
…… CCD, 4 …… Timing generation circuit, 5… S / H
Circuit, 10 photosensor section, 11 vertical transfer register, 12 horizontal transfer register, 13 output section,
20 A / D conversion circuit, 21 Camera signal processing circuit, 22 Switching circuit, 23 LCD, 30 Operation unit, 31 Controller, 32 Memory control, 33 DRAM, 34 compression / decompression circuit, 35
...... Flash memory.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) // H04N 101: 00 H01L 27/14 B

Claims (4)

[Claims] 1. A thinning-out readout operation for reading out charges by thinning out only some of pixels in a vertical direction among all pixels formed on an imaging surface of a solid-state imaging device, and then performing a thinning-out reading in accordance with the thinning-out number of the pixel An imaging apparatus comprising: a solid-state imaging device driving unit that performs vertical transfer only for the number of lines and alternately performs the thinning-out reading and the vertical transfer. 2. The solid-state image pickup device driving means includes: an all-pixel reading mode for reading out electric charges from all of the pixels in response to a user's input operation; The imaging apparatus according to claim 1, wherein the imaging apparatus is adaptively switched to a thinning-out reading mode for reading out. 3. A thinning-out readout for reading out charges by thinning out only some of the pixels in the vertical direction among all the pixels formed on the imaging surface of the solid-state imaging device, and then executing a line corresponding to the thinning-out number of the pixel A method for driving a solid-state imaging device, wherein vertical transfer is performed for only a number of pixels, and the thinning-out reading and the vertical transfer are performed alternately. 4. An all-pixel reading mode for reading out electric charges from all the pixels in response to a user input operation, and a thinning-out reading mode for reading out electric charges by thinning out only some of the pixels in the vertical direction among all the pixels. 4. The method for driving a solid-state imaging device according to claim 3, wherein the switching is performed in a selective manner.