JP2002108707A - Cache memory control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache memory control system which improves use efficiency and stabilizes performance without forming free-area fragments in a mounted cache memory such as a disk cache. SOLUTION: The cache memory 1 is divided into segments 3, each of which stores a different cache page 2 and cache data of the same property. If a specific segment 3 becomes full, a determined segment is used as a free segment according to priority.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control method, and more particularly to a control method of a cache memory mounted on a disk cache (disk array device).

[0002]

2. Description of the Related Art A disk cache or a RAM disk (RAM-disk) uses a part of a main storage area of a computer or an external RAM in place of a (magnetic) disk to reduce access time. Software and hardware. This can be broadly classified into two types: software that can handle a part of the main storage area as a disk device and an external semiconductor memory device that can handle the same as a disk device.

[0003] As a method of controlling a cache memory mounted on such a disk cache, two methods have been proposed: a method of managing a cache page as a storage unit of cache data with a fixed length and a method of managing a cache page with a variable length. ing. In the former, because the processing unit is fixed,
It is characterized by a relatively simple control method with little overhead. However, for an access that is sufficiently larger than the page size, overhead for the number of page divisions tends to always occur. On the other hand, the latter has a feature that a certain overhead can be maintained irrespective of the cache page size, and particularly in the case of write processing, a hit can be made in accordance with the requested access size. However, due to the variable length, management of cache pages tends to be complicated.

A conventional example of such a cache memory control method is disclosed, for example, in Japanese Patent Application Laid-Open No. 2-98755, entitled "Cache Invalidation Processing Method". This patent publication discloses that the n kinds of block data having different meanings or different sizes registered in the cache memory of the buffer storage device are individually invalidated to wastefully erase the registered block data. There is disclosed a block data invalidation processing method that eliminates the problem and enables high-speed processing.

[0005]

In the cache control method using a variable-length cache page size as described above, the cache data replacement algorithm is performed by the LRU algorithm. Therefore, when the cache data is discarded (see FIG. 3A), sporadic areas are often discarded (see FIG. 3B). For this reason, if the size of the cache page to be discarded is small or if the cache page at a distant place on the cache memory is often discarded, the empty area becomes sporadic and fragmentation occurs. In this state, it is necessary to always manage the free area by performing garbage collection and the like. Therefore, the performance of the disk array device is reduced by complicated cache control.

[0006]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a control method of a cache memory mounted on a disk cache or the like which solves or reduces the above-mentioned problems of the prior art and prevents a decrease in performance due to the occurrence of an empty area. It is.

[0007]

A cache memory control system according to the present invention controls a cache memory so as to store cache data of a variable-length cache page. And cache data having the same attribute is stored in one of the segments.

According to a preferred embodiment of the cache memory control system of the present invention, the attribute of the cache data is:
The determination is made based on read / write or sequential access / random access of a host command. Segments are provided with priorities, and when a segment storing cache data of a specific attribute becomes full, cache data of a segment having a lower priority is discarded to create an empty segment. In addition, segments having the same attribute are managed by the LRU algorithm, and a segment to be discarded is selected with the least access frequency.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a cache memory control system according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing the internal configuration of a preferred embodiment of a cache memory control system according to the present invention. In FIG. 1, a cache memory 1 indicates the entire cache memory. The cache page 2 is variable-length cache data, and is a unit of continuous data when data is stored in the cache memory 1. The segment 3 is an area obtained by dividing the cache memory 1 into a certain size, and is an aggregate of cache pages 2.

Next, an example of the operation when data is written in the cache memory 1 of the present invention shown in FIG. 1 will be described. First, cache pages 2 arranged in a plurality of segments 3 are all of the same type (attribute) in the same segment 3. For example, the type of this attribute is divided according to the pattern of a command (host command) issued from the host.

FIG. 3 is a flowchart showing the attribute discriminating process. First, a host command is received (step S1). Next, read / write (read / write) is determined (step S2). Next, it is determined whether the access is sequential access or random access (step S3). Further, a segment attribute is determined (step S4). Then, the sequential write segment (step S5), the random write segment (step S5)
6), sequential read segment (step S
7) and random read segment (step S8)
I do.

As described above, by dividing the data into read and write commands, the data can be clearly divided into clean data and dirty data. Therefore, it is possible to easily distinguish a segment requiring write-back from another segment. Also,
By separating the cache data obtained by the sequential access from the cache data obtained by the random access, there is an advantage that the cache data can be linked with the prefetching process of the cache data.

Next, a case where a new cache page 2 is created in the cache memory 1 will be described. What is important in this case is in which segment 3 the cache page 2 is created. Since the segment attribute is uniquely determined, the cache page 2 may be created in the segment indicating the attribute.

However, if the target segment 3 is already full and there is no other segment 3 having the same attribute, a new segment 3 having that attribute must be created. For that purpose, it is necessary to discard one segment 3 and secure it as an empty segment 3. The method of selecting the segment 3 to be discarded is as follows.

First, a priority is set for each attribute in the case of being discarded. And segment 3 with lower priority,
Increase the probability of being discarded. Conversely, the segment 3 having a higher priority can be made resident in the cache memory 1. In addition, since there may be many segments having the same priority, the segment 3 to be discarded can be selected as the segment 3 to be discarded by managing the segment 3 having the same attribute by the LRU algorithm. It is.

As described above, when newly creating an empty area,
By discarding the cache data for each segment, a continuous memory area can be secured at a time. As a result, the cache memory 1 can be used efficiently even for a variable-length cache page.

The configuration and operation of the preferred embodiment of the cache memory control system according to the present invention have been described above in detail. However, such embodiments are merely exemplary of the present invention,
It should be noted that the present invention is not limited in any way. It will be readily apparent to those skilled in the art that various modifications can be made in accordance with the particular application without departing from the spirit of the invention.

[0019]

As will be understood from the above description, the cache memory control system according to the present invention has the following remarkable practical effects. That is, when the cache data in the cache memory is discarded, a continuous area (segment) can always be used as a free area, so that a separated free area does not occur as in the related art. Usage efficiency is improved. Also,
According to the present invention, it is possible to always provide stable performance.

[Brief description of the drawings]

FIG. 1 is a diagram showing an internal configuration of a cache memory for explaining a cache memory control method according to the present invention.

FIG. 2 is a flowchart illustrating a cache page attribute determination process according to the present invention.

3A and 3B show a conventional technique, in which FIG. 3A shows the destruction of cache data in a cache memory, and FIG. 3B shows an empty area divided after the destruction.

[Explanation of symbols]

 1 Cache memory 2 Cache page 3 Segment

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 12/08 557 G06F 12/08 557

Claims (5)

[Claims] In a cache memory control method for controlling a cache memory so as to store cache data of a cache page of a variable length, the cache memory is divided into a plurality of segments of a predetermined fixed size. A cache memory control method wherein cache data having the same attribute is stored in one segment. 2. The cache memory control method according to claim 1, wherein the attribute of the cache data is determined by reading or writing a host command. 3. The cache memory control method according to claim 1, wherein the attribute of the cache data is determined by sequential access or random access of a host command. 4. A segment is provided with a priority, and when a segment storing cache data of a specific attribute becomes full, the cache data of the segment with a lower priority is discarded to create an empty segment. The cache memory control method according to claim 1, 2 or 3, wherein 5. The segment according to claim 1, wherein the segments having the same attribute are managed by an LRU algorithm, and the segment to be discarded is selected with the least access frequency. Cache memory control method.