JP2002100978A - Bipolar level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem where there is no circuit for simultaneously level-converting signals in both directions of a positive pole side and a negative pole side, even though there is a potential conversion circuit to one side for a conventional level shift circuit, in a semiconductor integrated circuit using a MOSFET. SOLUTION: This circuit is composed of a high potential system latching circuit connected to the power source of a high potential system, for which an inverter circuit is tucked up and a low potential system signal drive circuit connected to the power source of a low potential system, for which output is controlled by the signals of a high potential system latch on an output terminal side. The output signals of the low potential system signal circuit are added directly to the high potential system latching circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device using an insulated gate field effect transistor (hereinafter abbreviated as a MOSFET) or a device using such parts, which has a negative polarity and a positive polarity of a total of four or more potentials. Using a power supply,
The present invention relates to a configuration of a level shift circuit that converts a low-voltage (small amplitude) signal of a different potential into a high-potential (large amplitude) signal in each circuit.

[0002]

2. Description of the Related Art A conventional typical level shift circuit is a ninth type.
As shown in Japanese Patent Publication No. 57-59690, the conversion circuit only used one signal level. Alternatively, in the sense of converting a small amplitude into a large amplitude, a small amplitude is converted to a power supply potential by a comparator circuit or an operational amplifier circuit as shown in FIG.

[0003]

There is a problem in that the above-described conventional conversion circuit using only one-sided level signal cannot be applied to a multi-power supply circuit having four or more potentials. Further, the method using the comparator circuit or the operational amplifier circuit has a problem that a large amount of current always flows.

Accordingly, the present invention solves such a problem, and an object of the present invention is to convert a low potential (small amplitude) signal of a high potential system (large amplitude) into a multi-power supply circuit of 4 potentials or more. An object of the present invention is to provide a circuit configuration in which a signal, that is, both a positive polarity side and a negative polarity side are converted at the same time, and after conversion once, there is no leakage current, that is, a low power consumption level shift circuit.

[0005]

A bipolar level shift circuit according to the present invention comprises a low potential signal driving circuit connected to a low potential power supply, and two inverter circuits connected to a high potential power supply. , And a signal of the low-potential-system signal drive circuit is connected to an inverting output terminal of the high-potential-system latch circuit, and an output terminal of the high-potential-system latch circuit is connected. A signal is connected via a signal inverting circuit to control the output of the low-potential-system signal driving circuit.

According to the above configuration of the present invention, since the high-potential-system latch circuit is formed by crossing the inverter circuit,
The inverting output terminal of the high-potential-system latch circuit is easily changed by the output signal of the low-potential-system signal drive circuit, so that the high-potential-system latch circuit can be easily inverted. Also,
The output signal of the high-potential latch circuit controls the output of the low-potential signal drive circuit via the signal inverting circuit. The output signal of the potential does not collide with the output signal of the high potential at the inverted output terminal of the high-potential latch circuit. As described above, low power consumption bipolar level conversion without leakage current can be performed.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to examples. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, a circuit surrounded by a broken line 10 is a low-potential-system signal driving circuit. The low-potential signal drive circuit is -VSS1,
+ VDD1 power supply is used. The circuit surrounded by the broken line 20 is a high-potential-system latch circuit. The high potential system latch circuit 20 uses a power source of -VSS2 and + VDD2. Where-
FIG. 2 shows the relationship between the power supply potentials VSS2, -VSS1, + VDD1, and + VDD2. In FIG. 2, -VSS2 is a negative first power supply potential, -VSS1 is a negative second power supply potential,
+ VSS1 is a positive third power supply potential, and + VSS2 is a positive fourth power supply potential. In the dashed line 10 in FIG. 1, 11 and 12 are P-type MOSFETs, and 13 and 14 are N-type MOSFETs.
Type MOSFET. The source electrode of the P-type MOSFET 11 is connected to + VDD1, and the drain electrode is a P-type MOSFET.
It is connected to the source electrode of FET12. N-type MOS
The source electrode of the FET 13 is connected to -VSS1, and the drain electrode is connected to the source electrode of the N-type MOSFET 14. P-type MOSFET 12 and N-type MOSFET 14
Are connected to each other. P-type MOS
The drain electrodes of the FET 12 and the N-type MOSFET 14 are connected to each other, and serve as an output terminal 24 as the low-potential-system signal drive circuit 10. The P-type MOSFET 11 and N
The gate electrodes of the MOSFET 13 are connected to each other and serve as an input terminal 23 as the low-potential signal drive circuit 10. Next, in the dashed line 20, 15, 16, and 21 are P-type MOSFETs, and 17, 18, and 22 are N-type MOSFETs.
SFET. The source electrode of the P-type MOSFET 21 is connected to + VDD2 and the drain electrode is a P-type MOSFET.
15 source electrodes. N-type MOSFET
The source electrode 22 is connected to -VSS2, and the drain electrode is connected to the source electrode of the N-type MOSFET 17. Drain electrode of N-type MOSFET 17 and P-type MOS
The drain electrodes of the FETs 15 are connected to each other to form an inverted output terminal 25 as the high-potential latch circuit 20. The gate electrode of the P-type MOSFET 15 is an N-type MOSFET.
It is connected to the gate electrode of ET17. P-type MOSF
The source electrode of ET16 is connected to + VDD2. N
The source electrode of the MOSFET 18 is connected to -VSS2. Drain electrode of P-type MOSFET 16 and N-type M
The drain electrodes of the OSFET 18 are connected to each other and serve as an output terminal 26 as the high-potential-system latch circuit 20. Gate electrode of P-type MOSFET 16 and N-type MOSF
The gate electrodes of the ET 18 are connected to each other and to the inverted output terminal 25. The output terminal 26 as the high-potential-system latch circuit 20 is connected to the gate electrode of the P-type MOSFET 15 and the gate electrode of the N-type MOSFET 17 and to the input terminal of the signal inversion circuit 19 having the function of an inverter circuit. I have. Signal inversion circuit 1
9 is a P-type M in the low potential system signal drive circuit 10.
It is connected to the gate electrode of the OSFET 12 and the gate electrode of the N-type MOSFET 14. The output terminal 24 as the low-potential-system signal drive circuit 10 is connected to the high-potential-system latch circuit 20.
As the inverted output terminal 25. The input terminal 23 as the low potential system signal drive circuit 10 is a P-type MOSF
It is connected to the gate electrode of the ET 21 and the gate electrode of the N-type MOSFET 22. The power supply of the signal inversion circuit 19 is derived from -VSS1 and + VDD1 which are low-potential power supplies.

First, as an initial state, the input terminal 23 as the low-potential-system signal drive circuit 10 is -VSS1, which is a low-potential-system low signal, and the inverted output terminal as the high-potential-system latch circuit 20. 25 is + VDD2 which is a high-potential high signal, and the output terminal 26 as the high-potential latch circuit 20 is a high-potential low signal.
It is assumed that the signal is a -VSS2 signal. At this time, the input signal of the signal inversion circuit 19 is a low signal -V.
Since the signal is the SS2 signal, the output signal of the signal inverting circuit 19 is + VDD1, which is a low-potential high signal, and the P-type MOSFET 12 of the low-potential signal driving circuit 10
Is off (OFF). Further, the N-type MOSFET 14 of the low-potential-system signal drive circuit 10 is on (ON), but the input terminal 23 of the N-type MOSFET 13 is low (Lo).
w) Since the signal is the -VSS1 signal, the output terminal 24 of the low-potential-system signal drive circuit 10 is not output as an output signal because it is turned off (OFF), so the inverted output terminal as the high-potential-system latch circuit 20 No electrical collision with 25. Further, the input terminal 23 of the low potential system signal drive circuit 10
Is a low (−VSS1) signal, the P-type MOSFET 21 of the high-potential system latch circuit 20 is turned on (O
N), and also serves to supply a power supply potential of + VDD2 for generating a high-potential high signal to the inverted output terminal 25. At this time, an inverter circuit composed of the P-type MOSFET 15 and the N-type
The SFET 16 and the inverter circuit formed by the N-type MOSFET 18 are in a relationship in which the input terminal and the output terminal are so-called cross-connected to each other, and latch signals.

Next, the input terminal 23 of the low-potential-system signal drive circuit 10 is connected to a low-potential low signal of -V.
From SS1, + VD which is a high signal of a low potential system
If it is changed to D1, the N-type MOSFETs 13 and 22 are turned on (ON), and the P-type MOSFET 11 is turned off (OF).
F). The source electrode of the P-type MOSFET 21 is +
Since the gate electrode becomes + VDD1 with respect to VDD2, if the voltage difference is larger than the threshold voltage of the P-type MOSFET 21, the gate electrode is not completely turned off, but the driving force is reduced almost like off. . Therefore, first, the N-type MOSFET 13 is originally turned on (O
N) to the output terminal 24 of the low-potential-system signal driving circuit 10 through the N-type MOSFET 14 which has been operated (Low).
w) The signal -VSS1 flows. At this time, the inversion output terminal 25 serving as the high-potential-system latch circuit 20 originally has a potential of + VDD2 which is a high-potential-system high signal, and competes. However, the driving capability of the P-type MOSFET 15 is set relatively small. And a P-type MO
Since the potential of + VDD1 is applied to the gate electrode of the SFET 21 and the driving force is reduced so as to be close to OFF (OFF), the gate electrodes of the P-type MOSFET 16 and the N-type MOSFET 18 have a low (-Low) signal of -VSS1. A near potential is applied, and the output terminal 26 of the high-potential-system latch circuit 20 is at + V, which is a high-potential high signal.
DD2. Therefore, the P-type MOSFET 15 and the N-type M
The gate electrode of the OSFET 17 has a high potential Hi (Hi)
gh) The signal + VDD2 is applied, and the N-type MOSFET is connected to the inverted output terminal 25 as the high-potential latch circuit 20.
17 and the N-type MOSFET 22, a high-potential low signal -VSS2 enters. on the other hand,
The output signal of the signal inverting circuit 19 is a low-potential row (Lo).
w) Since the signal becomes -VSS1, the N-type MOSFET
14 is turned off (OFF), no electrical competition occurs between the output terminal 24 of the low-potential-system signal drive circuit 10 and the inverted output terminal 25 as the high-potential-system latch circuit 20, and the inverted output terminal 25 is pure. To the potential of -VSS2 which is a high-potential low signal. Therefore, the output terminal 26 and the inverted output terminal 25 of the high potential system latch circuit 20 are stabilized at + VDD2 and -VSS2, respectively. Further, as described above, since there is no electrical competition between the output terminal 24 of the low-potential-system signal drive circuit 10 and the inverted output terminal 25 as the high-potential-system latch circuit 20, there is no leakage current in a stable state. . From the above, it can be understood that a low-potential signal can be converted to a high-potential signal.

Next, the input terminal 23 of the low-potential-system signal driving circuit 10, which is the case where the input signal changes reversely, changes from + VDD1 which is a low-potential-system high signal to a low-potential-system low signal. It is assumed that the signal again changes to -VSS1. At this time, the P-type MOSFETs 11 and 21 are turned on (O
N), and the N-type MOSFET 13 is turned off (OFF).
The N-type MOSFET 22 does not completely turn off when the voltage difference is larger than the threshold voltage of the N-type MOSFET 22 because the source electrode is −VSS2 and the gate electrode is −VSS1.
Of the driving force close to the above. Therefore, first, + VDD1 which is a low-potential high signal flows into the output terminal 24 of the low-potential signal drive circuit 10 through the P-type MOSFET 11 and the P-type MOSFET 12 which was originally turned on. At this time, the inversion output terminal 25 serving as the high-potential-system latch circuit 20 originally has a potential of -VSS2 which is a high-potential-system Low signal, and competes. However, the driving capability of the N-type MOSFET 17 is relatively small. N-type MOSFET 2
2 is applied with a potential of -VSS1 to the gate electrode and turned off (OF
Since the driving force is reduced as close to F), a potential close to + VDD1 which is a high signal is applied to the gate electrodes of the P-type MOSFET 16 and the N-type MOSFET 18, so that the output of the high-potential latch circuit 20 is output. The terminal 26 becomes -VSS2 which is a high-potential low signal. Therefore, the P-type MOSFET 15 and the N-type MOSFET 17
-VSS2, which is a high-potential low signal, is applied to the gate electrode of P-type MOSFET 15 and P-type MOS to inverting output terminal 25 as high-potential latch circuit 20.
+ VDD2 which is a high signal of a high potential system enters through the FET 21. On the other hand, the signal inversion circuit 19
Is a high-potential high signal.
VDD1, the P-type MOSFET 12 is turned off (OF
F) Then, electrical competition between the output terminal 24 of the low-potential-system signal drive circuit 10 and the inverted output terminal 25 as the high-potential-system latch circuit 20 does not occur, and the inverted output terminal 25 becomes a pure high-potential system. + VDD2 which is a high signal of
Potential. Therefore, the output terminal 26 and the inverted output terminal 25 of the high potential system latch circuit 20 are stabilized at -VSS2 and + VDD2, respectively. As described above, the low-potential row (Lo) input to the input terminal 23 of the low-potential signal drive circuit 10 is obtained.
w) Both the −VSS1 signal and the + VDD1 signal are output terminals 26 of the high-potential latch circuit 20.
It can be seen that the signal can be converted into -VSS2 which is a high-potential low signal or + VDD2 which is a high signal.

In FIG. 1, each MOSFET is formed on a silicon-on-insulator (SOI) substrate having a buried oxide film layer. Accordingly, even if the potential of -VSS2 or + VDD2 of the high potential system enters the output terminal 24 of the low potential system signal driving circuit 10 from the inverted output terminal 25 of the high potential system latch circuit 20, P
There is no backflow from the drain of the MOSFET 12 or N-type MOSFET 14 to the substrate.

Although FIG. 1 shows an example in which an SOI substrate is used, the SOI substrate is not necessarily used, and the P-type MOSFET 12 or the N-type M
Instead of setting the substrate potential of the OSFET 14 to the potential of + VDD1 or -VSS1, the substrate may be configured independently and set to + VDD2 or -VSS2, respectively. Alternatively, it may be connected to the drain side of each MOSFET. With this configuration, the potential of -VSS2 or + VDD2 of the high-potential system enters the output terminal 24 of the low-potential-system signal drive circuit 10, and flows from the drain of the P-type MOSFET 12 or the N-type MOSFET 14 via the substrate to the + VDD1 of the low-potential system.
Alternatively, the current does not flow into the power supply of -VSS1.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. In FIG. 3, a circuit surrounded by a broken line 10 is a low-potential-system signal driving circuit. The low-potential-system signal drive circuit 10 has a −VSS
1, + VDD1 power supply is used. The circuit surrounded by the broken line 30 is a high-potential-system latch circuit. The high potential system latch circuit 30 uses a power supply of -VSS2 and + VDD2. Reference numeral 19 denotes a signal inversion circuit, which uses a power source of -VSS1, + VDD1. The circuit diagram of FIG. 3 is different from the circuit of FIG. In the high potential system latch circuit 30, 15 is a P-type MOSFET,
Reference numeral 17 denotes an N-type MOSFET. P-type MOSFET15
Source electrode is connected to + VDD2, N-type MOSFET
The source electrode 17 is connected to -VSS2. P type M
The gate electrodes of the OSFET 15 and the N-type MOSFET 17 are connected to each other, and the drain electrodes thereof are also connected to each other to form an inverter circuit. 16 is a P-type MOSFET, 18 is an N-type MOSFET
FET. The source electrode of the P-type MOSFET 16 is +
VDD2, and the source electrode of the N-type MOSFET 18 is connected to -VSS2. The respective gate electrodes of the P-type MOSFET 16 and the N-type MOSFET 18 are connected to each other, and the respective drain electrodes are also connected to each other to form an inverter circuit. These two inverter circuits connect the input terminal and the output terminal to each other so as to form a latch circuit. When comparing the high-potential-system latch circuit 20 of FIG. 1 with the high-potential-system latch circuit 30 of FIG.
The high potential latch circuit 30 shown in FIG. 3 is obtained by removing the OSFET 21 and the N-type MOSFET 22. Despite the differences described above, the high-potential latch circuit 20 of FIG. 1 and the high-potential latch circuit 30 of FIG. 3 basically operate in substantially the same manner. However, in the high-potential-system latch circuit 30 of FIG. 3, when the signal potential of the output terminal 24 of the low-potential-system signal drive circuit 10 and the signal potential of the inverted output terminal 25 of the high-potential-system latch circuit 30 collide, Output terminal 2 of drive circuit 10
4 so that the P-type MOSFET 2 of FIG.
The drive capability of the P-type MOSFET 15 and the N-type MOSFET 17 in the high-potential latch circuit 30 in FIG. As long as this condition is satisfied, the circuit of FIG. 3 has the advantage that the layout area can be reduced with a simple circuit having a smaller number of transistors than the circuit of FIG.

FIG. 4 is a circuit diagram of a third embodiment of the present invention. In FIG. 4, a circuit surrounded by a broken line 40 is a low-potential-system signal driving circuit. The low-potential-system signal drive circuit 40 has a voltage of -VSS.
1, + VDD1 power supply is used. The circuit surrounded by the broken line 30 is a high-potential-system latch circuit. The high potential system latch circuit 30 uses a power supply of -VSS2 and + VDD2. Reference numeral 19 denotes a signal inversion circuit, which uses a power source of -VSS1, + VDD1. The circuit diagram of FIG. 4 differs from the circuit of FIG. 3 in the configuration of the low-potential-system signal drive circuit 40. In the low-potential-system signal driving circuit 40 shown in FIG.
ET, and 13 and 14 are N-type MOSFETs. P
The source electrode of the MOSFET 12 is connected to + VDD1, and the drain electrode is connected to the source electrode of the PMOSFET 11. The source electrode of the N-type MOSFET 14 is connected to -VSS1, and the drain electrode is an N-type MOSFET.
It is connected to the source electrode of SFET13. Comparing the low-potential-system signal drive circuit 40 of FIG. 4 with the low-potential-system signal drive circuit 10 of FIG.
Positional relation to VDD1, and N-type MOSFET 13
The basic operations and functions are the same except that the positional relationship between the power supply 14 and the power supply VSS1 is switched. FIG. 4 is a circuit example showing that the configuration of the low-potential-system signal drive circuit is not one type.

FIG. 5 is a circuit diagram of a fourth embodiment of the present invention. In FIG. 5, a circuit surrounded by a broken line 10 is a low-potential-system signal driving circuit. The low-potential-system signal drive circuit 10 has a −VSS
1, + VDD1 power supply is used. The circuit surrounded by the broken line 20 is a high-potential-system latch circuit. The high potential system latch circuit 20 uses a power source of -VSS2 and + VDD2. Reference numeral 59 denotes a signal inversion circuit, which uses a power supply of -VSS2 and + VDD2. The circuit diagram of FIG. 5 differs from the circuit of FIG. 1 in how the power supply of the signal inversion circuit 59 is taken. The signal inversion circuit 19 of FIG. 1 receives power from the low potential system -VSS1, + VDD1. On the other hand, the signal inversion circuit 59 in FIG. 5 receives power from the high potential system -VSS2 and + VDD2. The other circuit configuration is the same as the circuit of FIG. The circuit in FIG. 5 shows that the power supply of the signal inverting circuit can be taken from either the low potential system or the high potential system depending on the layout pattern.

FIG. 6 is a circuit diagram of a fifth embodiment of the present invention. In FIG. 6, a circuit surrounded by a broken line 10 is a low-potential-system signal driving circuit. The low-potential-system signal drive circuit 10 has a −VSS
1, + VDD1 power supply is used. The circuit surrounded by the broken line 30 is a high-potential-system latch circuit. The high potential system latch circuit 30 uses a power supply of -VSS2 and + VDD2. Reference numeral 59 denotes a signal inversion circuit, which uses a power supply of -VSS2 and + VDD2. The circuit diagram of FIG. 6 differs from the circuit of FIG. 3 in how the power supply of the signal inversion circuit 59 is taken. The signal inversion circuit 19 of FIG. 3 takes power from the low potential system -VSS1, + VDD1. On the other hand, the signal inversion circuit 59 in FIG. 5 receives power from the high potential system -VSS2 and + VDD2. The other circuit configuration is the same as the circuit in FIG. The circuit of FIG.
Also in this circuit, the power of the signal inverting circuit can be obtained from either the low potential system or the high potential system due to the layout pattern.

FIG. 7 is a circuit diagram of a sixth embodiment of the present invention. In FIG. 7, a circuit surrounded by a broken line 10 is a low-potential-system signal driving circuit. The low-potential-system signal drive circuit 10 has a −VSS
1, + VDD1 power supply is used. The circuit surrounded by the broken line 20 is a high-potential-system latch circuit. The high potential system latch circuit 20 uses a power source of -VSS2 and + VDD2. Reference numeral 59 denotes a signal inversion circuit, which uses a power supply of -VSS2 and + VDD2. Further, 79 is an inverter circuit, which is -VSS2,
+ VDD2 power supply is used. In the circuit diagram of FIG. 7, the inverter circuit 79 receives the output signal of the signal inverting circuit 59, and the output is the output terminal 76 of the high-potential latch circuit 20. Although the circuit of FIG. 7 has basically the same operation and function as the circuit of FIG. 5, the output terminal 76 of the high-potential latch circuit 20 has two stages of inverter circuits so that the driving capability can be increased. I understand.

FIG. 8 is a circuit diagram of a seventh embodiment of the present invention. In FIG. 8, a circuit surrounded by a broken line 10 is a low-potential-system signal driving circuit. The low-potential-system signal drive circuit 10 has a −VSS
1, + VDD1 power supply is used. The circuit surrounded by the broken line 30 is a high-potential-system latch circuit. The high potential system latch circuit 30 uses a power supply of -VSS2 and + VDD2. Reference numeral 59 denotes a signal inversion circuit, which uses a power supply of -VSS2 and + VDD2. Further, 79 is an inverter circuit, which is -VSS2,
+ VDD2 power supply is used. In the circuit diagram of FIG. 8, the inverter circuit 79 receives the output signal of the signal inversion circuit 59, and the output is the output terminal 86 of the high-potential latch circuit 30. The circuit of FIG. 8 has basically the same operation and function as the circuit of FIG. 6, but has a circuit configuration that can increase the driving capability because the output terminal 76 of the high-potential-system latch circuit 30 has two stages of inverter circuits. I understand.

In the above, the case where the power supply has a total of four potentials has been described. However, the power supply may have five potentials or more, and the level may be converted between them.

In the above, the signal inverting circuit and the inverter circuit are usually a P-type MOSFET and an N-type MOSFET.
Although each of the gate electrodes and each of the drains described above have been described as being connected to each other, other configurations may be used as long as they have an inversion function. For example, the input terminals of a NAND circuit (non-OR circuit) may be connected to each other, or the input input terminals of a NOR circuit (non-OR circuit) may be connected to each other.

As described above, according to the present invention, there is an effect that a signal of a low potential system (small amplitude) can be simultaneously converted into a signal of a high potential system (large amplitude) on the positive electrode side and the negative electrode side.

Further, in the stationary state where the operation is completed, no leakage current flows and the power consumption is low.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a potential relationship diagram showing a relationship between respective potentials of a multiple power supply system in which the present invention is used.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 9 is a circuit diagram showing a conventional level shift circuit.

FIG. 10 is a circuit diagram showing a conventional example of a circuit for converting a small amplitude into a large amplitude.

[Explanation of symbols]

10, 40 ... low-potential-system signal drive circuit 20, 30 ... high-potential-system latch circuit 11, 12, 15, 16, 21 ... P-type MOSF
ET 13, 14, 17, 18, 22 ... N-type MOSF
ET 19, 59, 79 ... signal inverting circuit, inverter circuit 23 ... input terminal of low-potential signal drive circuit 24 ... output terminal of low-potential signal drive circuit 25 ... high-potential latch circuit Inverted output terminals 26, 36, 76, 86 ... output terminals of the high-potential latch circuit

Claims (8)

[Claims] 1. A semiconductor integrated circuit device using MOSFETs having first, second, third, and fourth power supply potentials, wherein a first P-type MOS having a source potential connected to a fourth potential power supply.
FET, second P-type MOSFET and fifth P-type MOSFET
T, a series circuit of a first N-type MOSFET in which a source potential is connected to a power source of a first potential, a series circuit of a second N-type MOSFET and a fifth N-type MOSFET.
The gate electrode and the drain electrode of the first N-type MOSFET and the gate electrode of the first N-type MOSFET are connected to each other to form a first inverter circuit.
The drain electrodes of the series circuit of the P-type MOSFET and the series circuit of the second N-type MOSFET and the fifth N-type MOSFET are connected to each other, and the second P-type MOSFET and the second
A second inverter circuit is formed by connecting gate electrodes of the N-type MOSFET to each other, and a gate electrode serving as an input terminal of the first inverter circuit is connected to a drain electrode serving as an output terminal of the second inverter circuit, Second
The gate electrode serving as an input terminal of the inverter circuit is the first electrode.
A high-potential-system latch circuit connected to a drain electrode serving as an output terminal of the inverter circuit; a series circuit of third and fourth P-type MOSFETs;
The third and fourth P-type MOSFETs.
One end of the series circuit of the MOSFETs is connected to a third potential power supply, and one end of the series circuit of the third and fourth N-type MOSFETs is connected to the power supply of the second potential.
The other end of the series circuit of SFETs and the third and fourth N-type MOSs
The other ends of the series circuit of FETs are connected to each other to become output terminals, and the third P-type MOSFET and the third N-type MOSFET are connected to each other.
The gate electrodes of the low potential signal driving circuit are connected to each other, and are composed of a low potential signal driving circuit composed of a low potential signal input terminal and a signal inverting circuit composed of a P-type MOSFET and an N-type MOSFET inverter circuit. An output terminal is an output terminal of a second inverter circuit forming the high-potential-system latch circuit, and is connected to an inverting output terminal as the high-potential-system latch circuit. And an output terminal as a high-potential latch circuit is connected to an input terminal of the signal inverting circuit, and the output terminal of the signal inverting circuit is connected to a fourth P-type MOSFET and a fourth N-type of the low-potential signal driving circuit. Gates of a fifth P-type MOSFET and a fifth N-type MOSFET connected to the gate electrode of the MOSFET and constituting the high-potential latch circuit. Bipolar level shift circuit, wherein the input terminal of the low-potential system signal driving circuit is connected to the pole. 2. A semiconductor integrated circuit device using MOSFETs having first, second, third, and fourth power supply potentials, wherein a first potential and a second potential having a source potential connected to a fourth potential power source are provided. And a first and second N-type MOSFETs having a source potential connected to a power source of a first potential and a gate electrode and a drain electrode of the first P-type MOSFET and the first N-type MOSFET connected to each other and a first inverter. Forming a circuit, the second P-type MOSFET and a second
A gate electrode and a drain electrode of the N-type MOSFET are connected to each other to form a second inverter circuit;
A gate electrode serving as an input terminal of the first inverter circuit is connected to a drain electrode serving as an output terminal of the second inverter circuit, and a gate electrode serving as an input terminal of the second inverter circuit is connected to an output terminal of the first inverter circuit. High-potential latch circuit connected to the drain electrode, and a series circuit of third and fourth P-type MOSFETs and third and fourth N-type MOSFETs.
The third and fourth P-type MOSFETs.
One end of the series circuit of the MOSFETs is connected to a third potential power supply, and one end of the series circuit of the third and fourth N-type MOSFETs is connected to the power supply of the second potential.
The other end of the series circuit of SFETs and the third and fourth N-type MOSs
The other ends of the series circuit of FETs are connected to each other to become output terminals, and the third P-type MOSFET and the third N-type MOSFET are connected to each other.
And a signal inverting circuit formed by a P-type MOSFET and an N-type MOSFET inverter circuit. The low potential signal driving circuit comprises a low potential signal input terminal and a low potential signal input terminal connected to each other. An output terminal of the drive circuit is an output terminal of a second inverter circuit constituting the high-potential-system latch circuit, and is connected to an inverting output terminal as the high-potential-system latch circuit. An output terminal of the circuit, and an output terminal serving as a high-potential latch circuit is connected to an input terminal of the signal inverting circuit;
An output terminal of the signal inverting circuit is connected to gate electrodes of a fourth P-type MOSFET and a fourth N-type MOSFET of the low-potential-system signal drive circuit. 3. The bipolar level shift circuit according to claim 1, wherein said signal inverting circuit is connected to a low-potential power supply of second and third potentials. Level shift circuit. 4. The bipolar level shift circuit according to claim 1, wherein said signal inverting circuit is connected to a high-potential power supply of first and fourth potentials. Shift circuit. 5. The bipolar level shift circuit according to claim 1, wherein the shape of the MOSFET is set such that the driving capability of the first inverter circuit of the high-potential latch circuit is higher than the driving capability of the second inverter circuit. And a bipolar level shift circuit. 6. The bipolar level shift circuit according to claim 1, wherein the driving capability of the second inverter circuit of the high-potential-system latch circuit is lower than the driving capability of the low-potential-system signal driving circuit. A bipolar level shift circuit characterized in that: 7. The bipolar level shift circuit according to claim 1, wherein the MOSFET semiconductor integrated circuit device is formed on a silicon-on-insulator substrate. 8. The bipolar level shift circuit according to claim 1, wherein the substrate potentials of the P-type and N-type MOSFETs connected to the output terminal of the low-potential-system signal drive circuit are set to the third and fourth levels, respectively. A bipolar level shift circuit, which is independent of a power supply potential.