JP2002198462A - Wiring board for mounting semiconductor device and its manufacturing method, and semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board for mounting semiconductor devices, which can achieve high density mounting and fine wiring, corresponding to the increase in the number of terminals and the narrowing of a pitch of a semiconductor device, achieve the narrow pitch of an external electrode corresponding to the miniaturization and increased density of a system, and has improved packaging reliability. SOLUTION: The wiring board for mounting semiconductor devices comprises an insulating layer, wiring provided on the upper surface of the insulating layer, an electrode that is provided at the lower surface side of the insulating layer while at least the periphery of the side surface of the upper end of the electrode comes into contact with the insulating layer, and at least the lower surface of the electrode does not come into contact with the insulating layer, a via that is positioned on the upper surface of the electrode and provided in the insulating layer for connecting the electrode to the wiring, and a support that is provided on the surface of the insulating layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board, a method of manufacturing the same, and a method of manufacturing the same, which are suitable for realizing high-speed and high-density modules and systems on which various semiconductor devices can be mounted at a high density. The present invention relates to a semiconductor package having a semiconductor device mounted on a substrate.

[0002]

2. Description of the Related Art In recent years, as the number of terminals has been increased and the pitch has been narrowed due to the increase in speed, multifunction, and integration of semiconductor devices, the density of mounting wiring boards on which semiconductor devices are mounted has been increased more than ever. Therefore, fine wiring is required.

[0003] A build-up multilayer board, which is a kind of multilayer wiring board, is widely used as a mounting wiring board at present.

[0004] This build-up multilayer board is manufactured as follows using a glass epoxy printed board as a base core board. First, an epoxy resin layer is formed on both sides of the glass epoxy printed circuit board. Next, via holes are formed in these epoxy resin layers by a photolithography method or a laser method. Thereafter, a wiring layer and a via conductor are formed on the epoxy resin layer by a combination of electroless or electrolytic Cu plating and photolithography. By repeating the above steps sequentially, a build-up laminated structure is formed.

However, in this build-up multilayer board, since a glass epoxy printed board having low heat resistance is used for the base core board, the glass epoxy printed board is shrunk by heat treatment at the time of manufacturing the build-up multilayer board. There is a problem that problems such as warpage, undulation and the like occur. These problems significantly reduce the accuracy in the exposure step, and it is difficult to form a high-density and fine wiring pattern on a glass epoxy printed circuit board.

Further, when a semiconductor device is mounted on such a build-up multilayer substrate by a flip-chip method, a connection failure between the semiconductor device and the build-up multilayer substrate is caused by heat treatment at the time of chip mounting or solder reflow. And distortion may occur, and thus long-term connection reliability may be reduced.

In order to solve the above problem, there has been proposed a mounting wiring board in which a build-up laminated structure is formed on a base substrate made of a metal plate (Japanese Patent Laid-Open No. 2000-2000).
No. -3980).

FIG. 18 shows a manufacturing process diagram of the mounting wiring board. First, as shown in FIG.
An insulating layer 102 is formed on the insulating layer 01, and a via hole 103 is formed in the insulating layer 102. Next, as shown in FIG. 18B, a wiring pattern 104 is formed on the insulating layer 102 including the via hole 103. Then, FIG.
As shown in (c), the insulating layer 1 is formed on the wiring pattern 104.
06 is formed, and the wiring pattern 104 is formed on the insulating layer 106.
Is formed. Finally, as shown in FIG. 18D, the metal plate 101 is etched from below, and the substrate reinforcing member 107 and the external electrode terminals 1 are etched.
08 is formed.

[0009]

In recent years, in addition to the above-described high density and fine wiring, an external board has been required for the mounting wiring board in order to realize the miniaturization and high density of the system. It is strongly demanded that external electrodes for electrical connection with devices and devices be made narrower in pitch.

However, in the conventional mounting wiring board shown in FIG.
Since 1 is formed by etching, it is very difficult to form the external electrode terminals 108 having a narrow pitch due to the limit of the side etching amount control at the time of etching.

When the mounting wiring board is mounted on an external board or device, the external electrode terminals 108
Stress concentrates on the interface between the substrate and the insulating layer 102, and an open failure is likely to occur, and sufficient mounting reliability cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and can realize a high density and fine wiring corresponding to an increase in the number of terminals and a narrow pitch of a semiconductor device, and a miniaturization of a system. It is another object of the present invention to provide a wiring board for mounting a semiconductor device, a method of manufacturing the same, and a semiconductor package which can realize a narrower pitch of external electrodes corresponding to a higher density and are excellent in mounting reliability.

[0013]

According to the present invention, there is provided an insulating layer, a wiring provided on an upper surface of the insulating layer, and an electrode provided on a lower surface side of the insulating layer, wherein at least a periphery of a side surface of an upper end of the electrode is provided. An electrode provided in contact with the insulating layer and at least the lower surface of the electrode not in contact with the insulating layer; and an electrode located on the upper surface of the electrode and provided in the insulating layer so as to conduct the electrode and the wiring. And a support provided on the surface of the insulating layer.

The present invention also relates to the above-mentioned wiring board for mounting a semiconductor device, wherein the electrode has a side surface in contact with the insulating layer, and a lower surface of the electrode is flush with a lower surface of the insulating layer.

Further, the present invention relates to the above-mentioned wiring board for mounting a semiconductor device, wherein the insulating layer has a concave portion on the lower surface, and the lower surface of the electrode forms the bottom surface of the concave portion.

The present invention also relates to the wiring board for mounting a semiconductor device, wherein the lower end of the electrode protrudes from a lower surface of the insulating layer.

Further, according to the present invention, Cu
The present invention relates to the above-described wiring board for mounting a semiconductor device, which has a laminated structure in which at least one different conductive layer is arranged at a lower end side of the layer.

Further, the present invention has a multilayer wiring structure in which an insulating layer and one or more sets of wirings formed on the upper surface of the insulating layer are sequentially and alternately provided on the upper surface of the insulating layer on which the wiring is formed. The present invention relates to the above-described wiring board for mounting a semiconductor device.

Further, according to the present invention, there is provided an electrode provided on the lower surface side of the insulating layer, wherein at least the periphery of the upper end of the electrode is in contact with the insulating layer and at least the lower surface of the electrode is not in contact with the insulating layer. An electrode, a dielectric layer provided on the upper surface of the electrode, and a conductive layer provided on the upper surface of the dielectric layer and being conductive to a wiring provided on the upper surface of the insulating layer. The present invention relates to the above-described wiring board for mounting a semiconductor device having a capacitor.

The present invention also relates to the wiring board for mounting a semiconductor device, wherein the support is provided on a lower surface of the insulating layer so that a lower surface of the electrode is exposed.

The present invention also relates to the above-mentioned wiring board for mounting a semiconductor device, wherein the support is provided on the entire lower surface of the insulating layer.

The present invention also relates to a wiring board for mounting a semiconductor device, wherein the above-mentioned wiring board is provided on the upper surface and the lower surface side of a laminated board on which two substrates are bonded, respectively, using the substrate as the support.

The present invention also relates to a semiconductor package in which a semiconductor device is mounted on the above-mentioned wiring board.

Further, according to the present invention, there is provided an insulating layer, a wiring provided on an upper surface of the insulating layer, and an electrode provided on a lower surface side of the insulating layer, at least a periphery of an upper end of the electrode being in contact with the insulating layer. And an electrode provided so that at least the lower surface of the electrode is not in contact with the insulating layer, and a via located in the upper surface of the electrode and provided in the insulating layer so as to conduct the electrode and the wiring. The present invention relates to a wiring board and a semiconductor package having a semiconductor device mounted on the wiring board.

The present invention also relates to the above semiconductor package, wherein a periphery of a side surface of the electrode is in contact with the insulating layer, and a lower surface of the electrode is flush with a lower surface of the insulating layer.

Further, the present invention relates to the above semiconductor package, wherein the lower surface of the insulating layer has a concave portion, and the lower surface of the electrode forms the bottom surface of the concave portion.

The present invention also relates to the above semiconductor package, wherein a lower end of the electrode protrudes from a lower surface of the insulating layer.

The present invention also relates to the above semiconductor package having a laminated structure in which the electrode has a Cu layer at an upper end thereof and at least one different conductive layer at a lower end thereof.

Further, the present invention has a multilayer wiring structure in which an insulating layer and one or more sets of wirings formed on the upper surface of the insulating layer are sequentially and alternately provided on the upper surface of the insulating layer on which the wiring is formed. The present invention relates to the above semiconductor package.

Further, according to the present invention, there is provided an electrode provided on a lower surface side of the insulating layer, wherein at least a periphery of an upper end of the electrode is in contact with the insulating layer and at least a lower surface of the electrode is not in contact with the insulating layer. An electrode, a dielectric layer provided on the upper surface of the electrode, and a conductive layer provided on the upper surface of the dielectric layer and being conductive to a wiring provided on the upper surface of the insulating layer. The present invention relates to the above semiconductor package having a capacitor.

The present invention also provides a step of forming an electrode pattern on a substrate, a step of forming an insulating layer on the substrate so as to cover the electrode pattern, and forming a via hole reaching the electrode pattern in the insulating layer. Forming a conductive layer on the insulating layer so as to fill the via hole, and patterning the conductive layer to form a wiring pattern. .

Further, the present invention further comprises a step of forming a dielectric layer on a predetermined electrode pattern after forming the electrode pattern, wherein the dielectric layer, the electrode pattern below the dielectric layer and the dielectric layer are formed. The present invention relates to the above-mentioned manufacturing method, wherein a capacitor is formed with a conductor layer embedded in a via hole reaching a body layer.

The present invention also relates to the above-mentioned manufacturing method, comprising a step of selectively removing the substrate to expose the electrode pattern and using a remaining portion of the substrate as a support.

Further, the present invention relates to the above-mentioned manufacturing method, further comprising the step of removing the substrate and exposing the electrode pattern after mounting the semiconductor device.

The present invention also relates to the above-mentioned manufacturing method, wherein the exposed electrode pattern is selectively etched and removed by a predetermined thickness to form a concave portion on the lower surface of the insulating layer.

In the present invention, in the step of forming an electrode pattern on the substrate, a resist layer having an opening pattern corresponding to the electrode pattern is formed on the substrate by using a conductive substrate as the substrate. The present invention relates to the above-described manufacturing method in which a metal is deposited in a pattern by a plating method to form the electrode pattern.

Further, according to the present invention, the substrate is etched using the resist layer as a mask to form a concave portion corresponding to an opening pattern of the resist layer on the upper surface of the substrate, and then a metal is deposited on the concave portion to form the electrode. The present invention relates to the above manufacturing method for forming a pattern.

Further, according to the present invention, there is provided a step of preparing a laminate obtained by bonding a first substrate and a second substrate, forming a first electrode pattern on the first substrate, Forming a second electrode pattern on the substrate, forming first and second insulating layers on the laminate so as to cover the first and second electrode patterns, respectively,
Forming a via hole reaching the first electrode pattern in the insulating layer; forming a via hole reaching the second electrode pattern in the second insulating layer; and forming the via hole so as to fill the via hole. Forming a conductive layer on each of the first and second insulating layers, and patterning the conductive layer to form first and second wiring patterns. About.

Further, according to the present invention, the first substrate and the second substrate
And a step of separating the substrate from the substrate.

Further, according to the present invention, the first substrate and the second substrate
And a method of selectively removing the first and second substrates after the substrate is separated from the substrate, exposing the electrode pattern, and using a remaining portion of the substrate as a support.

The present invention also relates to the above-described manufacturing method, further comprising a step of removing the first and second substrates after mounting the semiconductor device to expose the electrode pattern.

The present invention also relates to the above-mentioned method for manufacturing a wiring board, wherein the exposed electrode pattern is selectively etched and removed by a predetermined thickness to form a recess on the lower surface of the insulating layer.

Further, in the present invention, in the step of forming the first and second electrode patterns, a conductive substrate is used as the first and second substrates, and the first and second substrates are formed on the first and second substrates, respectively. Forming a resist layer having an opening pattern corresponding to the first and second electrode patterns, and depositing a metal in the opening pattern by plating to form the first and second electrode patterns; It relates to a manufacturing method.

Further, according to the present invention, the first and second support substrates are respectively etched by using the resist layer as a mask to form a concave portion corresponding to the opening pattern of the resist layer on the upper surface of the substrate, and then the concave portion is formed on the concave portion. The present invention relates to the above-described method for manufacturing a wiring board, wherein a metal is deposited on the substrate to form the first and second electrode patterns.

Further, according to the present invention, there is provided the above-mentioned method for manufacturing a wiring board, wherein the electrode pattern is formed in a laminated structure in which a Cu layer is disposed at an upper end of the electrode pattern and at least one different conductive layer is disposed at a lower end. About.

According to the present invention, in the formation of the electrode pattern, a Cu layer is disposed on an upper end thereof, a barrier conductive layer for diffusion of solder is disposed on a lower end side, and a barrier conductive layer for etching removal of the substrate is disposed on a lower end side. The present invention relates to a method for manufacturing the above-mentioned wiring board for forming a laminated structure.

[0047]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a wiring board for mounting a semiconductor device (hereinafter, appropriately referred to as a "wiring board"), a semiconductor package, and a method of manufacturing the same according to the present invention will be described.

[Wiring Board] FIG. 1 is a schematic sectional view of an embodiment of the wiring board of the present invention.

The wiring board according to this embodiment includes an insulating layer 6, a wiring 8 provided on the upper surface of the insulating layer 6,
An electrode 5 provided on the lower surface side of the substrate, a via 7 provided on the upper surface of the electrode 5 and provided in the insulating layer 6 so as to conduct the electrode 5 and the wiring 8, and a lower surface of the insulating layer 6. Support 16
Having.

The entire periphery of the side surface of the electrode 5 in this embodiment is in contact with the insulating layer 6, and the lower surface of the electrode 5 is in the same plane as the lower surface of the insulating layer 6. That is, the electrode 5 is embedded in the insulating layer 6 such that the lower surface is exposed from the insulating layer 6. According to the present invention, since the electrodes 5 are buried in the insulating layer 6 as described above, stress and strain on the electrodes 5 are alleviated, concentration of stress can be reduced, and mounting on an external board or device can be achieved. A highly reliable wiring board can be obtained.

The electrode on the lower surface of the insulating layer in the wiring board of the present invention may be provided so that at least the periphery of the upper end of the electrode is in contact with the insulating layer and at least the lower surface of the electrode is not in contact with the insulating layer. In addition to the structure shown in FIG. 1, the structure shown in FIGS.

In the structure shown in FIG. 2A, the insulating layer 6 has a concave portion 41 on the lower surface side, and the electrode 5 is provided in the insulating layer 6 such that the lower surface forms the bottom surface of the concave portion. I have. According to this structure, stress and strain on the electrode 5 are alleviated, stress concentration is reduced, and a wiring board with excellent mounting reliability on an external board or device can be obtained.
Can be easily provided on each electrode 5 even if they are arranged at a narrow pitch.

In the structure shown in FIG. 2B, the lower end of the electrode 5 projects from the lower surface of the insulating layer 6. According to this structure, stress and strain on the electrode 5 are alleviated, stress concentration is reduced, and a wiring board having excellent reliability in mounting on an external board or device can be obtained. Connection reliability can be improved.

FIG. 3 is a schematic sectional view showing a structure in which solder balls 31 are provided on electrodes 5 in the configuration shown in FIG. If necessary, solder resist 1 around electrode 5
7 may be provided. This solder resist 17 is shown in FIG.
The same structure can be provided in the structures shown in (a) and (b). The solder resist can be formed from a usual resist material. By providing such a solder resist, rolling can be prevented at the time of solder ball installation and workability can be improved, and after installation, stress concentration at the joint between the solder ball and the electrode can be reduced, Installation stability can be improved.

The electrode on the lower surface side of the insulating layer in the wiring board of the present invention can be formed of various conductive materials such as metals and alloys such as Cu, Ag, Au and Ni.
A laminated structure including a solder diffusion preventing layer and an electrode strength reinforcing layer may be employed. As an electrode having a laminated structure, an electrode (Au / Ni) in which Au, Ni, and Cu are laminated in this order from the lower end side.
Ni / Cu electrode), Ni, Au, Ni, Cu from the lower end side
Is an electrode (Ni / Au / Ni / Cu electrode) laminated in this order, an Au / Ni / Cu electrode from which the lowermost Ni layer is removed from the Ni / Au / Ni / Cu electrode, and Cu from the lower end side. , Ag, and Cu are laminated in this order (Cu / A
g / Cu electrode). In the above electrode, the intermediate Ni layer functions as a solder diffusion preventing layer.
In the Cu / Ag / Cu electrode, the Ag layer functions as a reinforcing layer for improving the strength of the electrode.

The support provided on the surface of the insulating layer in the wiring board of the present invention is provided to reinforce the wiring board. By providing the support on the wiring board, deformation such as warpage of the wiring board is suppressed, and the reliability of mounting the semiconductor chip (device) on the wiring board, and the mounting reliability of the wiring board or the semiconductor package on an external board or the like. Can be secured.

In the embodiment shown in FIG.
Is provided on the lower surface of the insulating layer 6 and is provided in a frame shape around the insulating layer 6. FIG. 4 shows a schematic bottom view (bottom view) of the wiring board of the present embodiment. The shape of the support in the wiring board of the present invention may be a frame shape as shown in FIG. 4 or a lattice shape or a mesh shape in a region other than the electrode 5 (so that the electrode 5 is exposed). Further, the support in the wiring board of the present invention may be provided on the upper surface of the wiring board within a range where the semiconductor device can be mounted. Further, in this case, when sufficient strength can be secured by the support provided on the upper surface, a wiring substrate having no support on the lower surface can be provided.

In order to mount a wiring board or a semiconductor package having a semiconductor chip mounted on the wiring board, the electrodes 5 need to be exposed. If it is possible to perform a process for exposing the electrodes 5 later, For example, a form in which a support (support plate) is provided on the entire lower surface of the wiring board may be adopted. In this case, after forming the semiconductor package by mounting the semiconductor chip on the wiring board, the support 5 can be selectively removed in a frame shape or the like to expose the electrode 5. Since the support is formed on the entire lower surface, the flatness of the wiring board can be more sufficiently secured when the semiconductor chip is mounted, and the mounting reliability of the semiconductor chip can be improved. When removing the support for exposing the electrode 5, if the manufactured semiconductor package has sufficient strength to ensure sufficient mounting reliability on an external board even without the support, wiring The entire support on the lower surface of the substrate may be removed.

The material of the support can impart sufficient strength to the wiring board as described above, and can be used for mounting the semiconductor chip on the wiring board,
The material is not particularly limited as long as it has heat resistance enough to withstand heat treatment at the time of mounting a wiring board or a semiconductor package, but a conductive material is preferable from the viewpoint of manufacturing electrodes, vias, and wiring. As such a conductive material, while having sufficient strength, it is inexpensive and easy to process.
Metals composed of stainless steel, copper, copper alloys, aluminum, nickel and the like are preferred.

The insulating layer in the wiring board of the present invention can be formed as a single layer made of a single material, but has a laminated structure in which two or more different materials are laminated as shown in FIG. May be.

The thickness of the insulating layer is preferably 10 μm or more in view of the reliability of mounting the semiconductor chip on the wiring board and the reliability of mounting the wiring board or the semiconductor package on an external board or the like.

The insulating layer may be made of an epoxy resin, a resin obtained from an acrylate compound having both ends having a fluorene skeleton, a polyimide resin, polybenzoxazole, polybenzocyclobutene, or two or more of these. Various insulating resins, such as a mixture of the above, can be applied. In particular, the film strength is 70 MPa or more, the elongation at break is 5% or more, the glass transition temperature is 150 ° C. or more,
A single-layer film made of an insulating material having a coefficient of thermal expansion of 60 ppm or less (hereinafter, abbreviated as “insulating material A” as appropriate), or an elastic modulus of 10 GPa or more, a thermal expansion coefficient of 30 ppm or less, and a glass transition temperature of 150 ° C. or more It is preferable to have at least a single-layer film made of the insulating material (hereinafter, abbreviated as “insulating material B” as appropriate). The thickness of these single-layer films is preferably 10 μm or more. Here, the film strength and the elongation at break are values measured by a tensile test of an insulating material in accordance with JIS K 7161 (tensile property test), and the elastic modulus is 0.1% of strain based on the result of the tensile test. Is a value calculated from the intensity at. Thermal expansion coefficient is JIS C
The glass transition temperature is a value measured by a TAM method according to JIS C 6481, and the glass transition temperature is a DMA value according to JIS C 6481.
It is a measured value by the method.

As the insulating material A, for example, epoxy resin (manufactured by Hitachi Chemical; MCF-7000LX), polyimide resin (manufactured by Nitto Denko; AP-6832C), benzocyclobutene resin (manufactured by Dow Chemical; Cycloten)
e4000 series), polyphenylene ether resin (manufactured by Asahi Kasei; Zylon), liquid crystal polymer film (manufactured by Kuraray; LCP-A), expanded porous fluororesin-impregnated thermosetting resin (manufactured by Japan Gore-Tex; MICOLAM6)
00) and the like are preferable.

As the insulating material B, for example, an epoxy resin impregnated with glass cloth (manufactured by Hitachi Chemical; MCL-E-67)
9), aramid nonwoven fabric impregnated epoxy resin (manufactured by Shin-Kobe Denki; EA-541), stretched porous fluororesin impregnated thermosetting resin (manufactured by Japan Gore-Tex; MICROLAM4)
00) and the like are preferable.

When the insulating layer of the wiring board of the present invention has a laminated structure, it is preferable to have a layer made of an insulating material A or B, but the other layer is made of a double-ended acrylate having a fluorene skeleton. It is preferable to use a resin obtained from a compound (hereinafter, appropriately referred to as “fluorene-based resin”). Further, in order to further add or improve desired characteristics, a resin mixture containing a fluorene-based resin mixed with another resin as a main component may be used. Such a resin mixture preferably contains at least 80% by mass of a fluorene-based resin, for example, 5 to 20% by mass, preferably 5 to 10% by mass of an epoxy resin.
Resin mixtures containing a certain amount can be suitably used.
Fluorene resin has heat resistance, low dielectric constant, low thermal expansion coefficient,
It has excellent properties such as low water absorption and is suitable as an insulating material used for high-density and fine wiring boards, and is disclosed in, for example, JP-A-9-214141.

As such a resin, a resin obtained from an acrylate compound at both ends having a 9,9-diphenylfluorene skeleton represented by the following general formula (I) can be mentioned.

[0067]

Embedded image

In the formula, R is independently a hydrogen atom or a lower alkyl group such as methyl, ethyl, n-propyl or isopropyl, and n is an integer of 0-20.

By using the resin material as described above for the insulating layer, it is possible to obtain a wiring board having excellent film strength and elongation at break, and particularly excellent crack resistance.
A semiconductor chip having a narrow pitch of less than μm pitch and a large number of pins can be mounted.

The present inventors conducted a pressure cooker test (temperature: 121 ° C., humidity: 100%) on a wiring board having an insulating layer made of these resins.
No resin delamination was observed after 92 hours.

The semiconductor package shown in FIG. 9C, in which each of the following four types of resins is used as the insulating layer 6, is subjected to a temperature cycle test (-65 ° C. for 30 minutes, 150 ° C. for 30 minutes to make one cycle). ), No disconnection or crack occurred even after 1000 cycles.

Resin a: film strength: 78 MPa, elongation at break: 8.5%, glass transition temperature: 175 ° C., coefficient of thermal expansion: 55 pp
m, elasticity 2.5 GPa, resin b; film strength 180 MPa, elongation at break 30%, glass transition temperature 385 ° C., coefficient of thermal expansion 28 ppm, elasticity 6.
0 GPa, resin c; glass transition temperature 180 ° C., coefficient of thermal expansion 11 pp
m, modulus of elasticity 11 GPa, resin d; glass transition temperature 200 ° C, coefficient of thermal expansion 18 pp
m, modulus of elasticity 12 GPa.

The wiring board of the present invention has a multilayer wiring structure in which an insulating layer and one or more pairs of wirings formed on the upper surface of the insulating layer are alternately formed on the upper surface of the insulating layer provided with the wirings. be able to. FIG. 6 shows an embodiment having a multilayer wiring structure in which a set of an insulating layer and a wiring is further laminated on the structure shown in FIG. An insulating layer 12 is provided on the insulating layer 6 so as to cover the wiring 8.
A wiring 13 is provided on 2, and a via is provided in the insulating layer 12 so as to conduct the wiring 13 and the wiring 8. In such a multilayer wiring structure, at least one of the insulating layers is preferably made of an insulating material A or B,
It is preferable that another insulating layer is made of the above-mentioned fluorene-based resin.

In the wiring board of the present invention, as in the embodiment shown in FIG. 7, a dielectric layer 93 is provided on the upper surface of a part of the plurality of electrodes 5 provided on the lower surface side. A via conductor 7 may be provided thereon, and a capacitor including the electrode 5, the dielectric layer 93 and the via conductor 7 may be provided.
By forming such a capacitor, transmission noise can be reduced, and a wiring board optimal for high-speed operation can be obtained. Materials for the dielectric layer include titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), silicon oxide (SiO ₂ ), niobium oxide (Nb ₂ O ₅ ), and BST. (Ba _x Sr _1-x TiO ₃ ),
PZT (PbZr _x Ti _1-x O ₃ ), PLZT (Pb _1-y L
_{a y Zr x Ti 1-x} O 3), it may be mentioned perovskite material such as SrBi ₂ Ta ₂ O _9.

FIGS. 8A and 8B show a wiring board according to the present invention.
As shown in (2), a configuration in which the above-described wiring board structure is formed on both surfaces of a laminated plate on which two support substrates 1 are bonded, respectively, may be adopted. In this embodiment, two support substrates are separated into two wiring substrates or a semiconductor package before or after the mounting of the semiconductor chip, and the support substrate 1 is removed so that the electrodes 5 are exposed as described above, respectively. It can be in a form that can be mounted on another board or the like.

[Semiconductor Package] The semiconductor package of the present invention can be formed by mounting a semiconductor chip on the upper surface of the wiring board of the present invention. The electrical connection portion such as a pad of a semiconductor chip and the wiring of the wiring board can be electrically connected by various methods, for example, a flip chip method, a wire bonding method, and a tape bonding method.

FIG. 9 shows an embodiment using the flip chip method. FIG. 9A shows a semiconductor package according to the present invention.
As shown in (1), a configuration in which the substrate 1 is provided on the entire lower surface of the wiring substrate can be adopted. In this case, when mounting on another board or the like, the substrate 1 is removed so that the electrodes 5 are exposed. As a form in which the electrodes 5 are exposed, as shown in FIG. 9B, the substrate 1 is processed and left on the lower surface of the insulating layer 6 in a frame shape, a lattice shape, or a mesh shape, and a support for reinforcing a semiconductor package is formed. 16 can be used. If sufficient strength can be ensured without forming such a support, the entire substrate 1 may be removed to obtain a form as shown in FIG. 9C. As shown in FIGS. 9A to 9C, when a semiconductor chip is sealed with a mold resin, the mold resin also functions as a support, so that sufficient strength is secured without providing the support 16. It is possible.

FIG. 9 shows a semiconductor package according to the present invention.
As in the embodiment shown in FIG. 1, the pads 19 provided on the semiconductor chip 18 and the wirings 8 of the wiring structure 9 corresponding to the wiring board of the present invention are electrically connected via, for example, metal bumps 20. Can be. At this time, the semiconductor chip 18
The space between the wiring structure 8 and the wiring structure 8 can be filled with an underfill resin 21 if necessary. Further, the semiconductor chip on the wiring structure 9 can be encapsulated by a transfer molding method using the molding resin 22. Alternatively, as shown in FIG. 9D, a heat sink 33 may be provided on the semiconductor chip 18 and then sealed by another sealing method, as shown in FIG. 9D.

Further, the semiconductor package of the present invention has the structure shown in FIG.
As shown in FIG. 0, the semiconductor chip may be mounted on both sides. Such an embodiment can be formed by mounting semiconductor chips on both surfaces of the wiring board of the embodiment described with reference to FIG. When this semiconductor package is mounted on another board or the like, the laminated substrate on which the two substrates are bonded is separated into two semiconductor packages, and the electrodes 5 of the wiring structure 9 are respectively formed as described above. The substrate 1 can be removed so that the substrate is exposed, and can be mounted on another board or the like.

[Method of Manufacturing Wiring Substrate and Semiconductor Package] FIG. 11 is a sectional process view of an embodiment of the manufacturing method of the present invention.

First, as shown in FIG. 11A, a resist layer for forming an electrode pattern is formed on a substrate 1 made of a metal plate of stainless steel, Cu, Cu alloy, Al, Ni, etc. The layer is patterned to form a resist mask 2 having an opening 3 corresponding to a predetermined electrode pattern.

Next, as shown in FIG.
Then, a plating layer 4 is formed on the substrate 1 in the opening 3 by electrolytic plating. Next, as shown in FIG. 11C, the resist mask 2 is removed, and a plating layer 4 having a predetermined electrode pattern corresponding to the opening pattern of the resist mask 2 is left on the substrate 1, and this is replaced with an electrode 5 And As described above, the formation of the electrode 5 is based on reliability.
Although it is desirable to use an electrolytic plating method capable of depositing a dense metal, the opening 3 is formed by an electroless plating method.
The electrode 5 can also be formed by depositing the plating layer 4 on the substrate.

Next, as shown in FIG.
An insulating layer 6 is formed on the substrate 1 on which is formed, and a via hole 7a reaching the electrode 5 is formed in the insulating film 6 by photolithography or laser processing.

As the material of the insulating layer 6, various insulating resins such as epoxy resin, fluorene resin, polyimide resin, polybenzoxazole, and polybenzocyclobutene can be used. This insulating layer 6
May be composed of a plurality of resin layers as shown in FIG. 5, for example, in order to improve the mounting reliability.

Next, as shown in FIG. 11E, a conductor layer is formed on the insulating layer 6 so as to fill the via holes 7a by sputtering, electroless plating, electrolytic plating, or the like. The wiring layer 8 is formed by patterning the body layer by photolithography. Alternatively, after forming a conductor layer so as to fill the via hole 7a, an unnecessary conductor layer on the upper surface of the insulating layer 6 is removed to form the via hole 7a.
A via 7 may be formed while leaving a conductor only in a, followed by forming a conductor layer of the same or different kind connected to the via, and patterning the same to form a wiring layer 8.

As described above, the wiring board of this embodiment can be formed. To make the wiring board mountable on another board or the like, for example, as shown in FIGS. The substrate 1 in a predetermined area is selectively etched to expose the electrode 5 for electrical connection to the outside, and the substrate left in a frame shape on the outer periphery of the insulating layer 6 is used as a support 16. As described above, the support 16 may be formed in a lattice shape or a mesh shape in addition to the frame shape.

Thereafter, if necessary, as shown in FIG. 3, a solder resist 17 may be formed around the electrode 5 in order to mount a solder ball on the electrode 5, and further, the solder ball 31 is mounted thereon. Is also good.

After forming the wiring layer 8, as shown in FIG. 12, a cover coat 10 is formed on the insulating layer 6 so as to cover the wiring layer 8, and a semiconductor chip is provided at a predetermined position of the cover coat 10. An opening can also be provided as a pad portion 11 for conducting with the device. The pad portion 11 can be used as an electrode pad by embedding a conductor in the opening.

After forming the wiring layer 8, as shown in FIG. 6, the insulating layer 12 is formed on the insulating layer 6 so as to cover the wiring layer 8.
Is formed, and a via is formed in the insulating layer 12 and the wiring layer 13 is formed on the insulating layer 12 in the same manner as described above to provide a multilayer wiring structure. By repeating this process, the number of layers can be increased to an arbitrary number.

According to the manufacturing method of this embodiment, it is extremely easy to narrow the pitch of the electrodes 5 and to increase the precision. Further, since the electrode 5 has a structure embedded in the insulating film 6, the stress and strain on the electrode 5 can be reduced, and the stress concentration is reduced, so that the mounting reliability with an external board or device is excellent. A wiring board can be manufactured. If a semiconductor chip is mounted on the wiring board of the present embodiment to form a semiconductor package, the reliability of mounting the semiconductor package on an external board or device can be improved.

Further, the substrate 1 used for forming the electrode 5 was
Since it can be left as the support 16 of the wiring board during the removal step for exposing the electrode 5, there is no need to provide a separate support, and it is easy to handle, has excellent handleability, and has high chip mounting reliability. In addition, it is possible to manufacture a wiring board having excellent mounting reliability on another board or the like.

A wiring board having a wiring structure formed on both sides of a laminate as shown in FIG. 8 can be manufactured, for example, as follows.

First, as shown in FIG. 13A, a laminated board 25 in which a first substrate and a second substrate are bonded is prepared. For example, an epoxy-based or polyimide-based heat-resistant adhesive resin is arranged around one substrate 1 (adhesion region 24), and the other substrate is bonded and fixed to the surface.

Next, a resist layer is formed on each side of the laminate in the same manner as described above, and these are patterned to form an opening pattern corresponding to the predetermined first and second electrode patterns. Next, energization is performed from the substrate 1,
A plating layer is formed in the opening of the resist layer by an electrolytic plating method, and subsequently, the resist layer is removed to form first and second electrodes 5 on both surfaces of the laminate 25, respectively. Next, in the same manner as described above, the insulating layers 6 are formed on both sides of the laminate 25, and via holes are formed in these insulating layers, respectively. Then, a conductive film is formed so as to fill these via holes. Then, these are patterned to form the wiring 8 (FIG. 13B). Thereafter, FIG.
At the position indicated by the dotted line (inside the bonding area 24) shown in FIG.
By cutting 6, as shown in FIG.
By separating the bonded first and second substrates 1, two wiring substrates can be obtained. Alternatively, a semiconductor chip is mounted on at least one surface of a wiring board, and a semiconductor package is formed by mounting a semiconductor chip on both surfaces, for example, as shown in FIG. To obtain two semiconductor packages.

According to such a manufacturing method, since the steps can be simplified, the productivity can be improved and the cost can be reduced.

[Method of Manufacturing Wiring Substrate Having Stacked Electrodes] FIG. 14 shows an embodiment of a method of manufacturing a wiring board having stacked electrodes.

In the manufacturing method of this embodiment, a stainless steel plate is used as the substrate 1, and an electrode having a three-layer structure in which an Au plating layer, a Ni plating layer, and a Cu plating layer are laminated in this order from the lower surface side of the wiring substrate is formed. .

First, as shown in FIG. 14A, a resist layer for forming a plating film is formed on a substrate 1 made of stainless steel (for example, Nisshin Steel; SUS304), and this resist layer is patterned. Thus, a resist mask 2 having an opening 3 corresponding to a predetermined electrode pattern is formed.

Here, the preferable thickness of the substrate 1 is 0.1 m
m to 1.0 mm, more preferably 0.2 mm to
0.8 mm. The reason is that if the plate thickness is too thin, warpage is likely to occur in the manufacturing process of the wiring board, and it becomes difficult to form fine wiring with reduced accuracy, and if the plate thickness is too thick, This is because the handleability is reduced due to the increased weight.

Next, as shown in FIG. 14 (b), the Au plating layer 4a, the Ni plating layer 4b, and the C plating are formed on the substrate 1 in the opening 33 by electrolytic plating or electroless plating.
The u plating layer 4c is formed in this order. The thickness of each plating layer is as follows.
It is preferable that the thickness of the plating layer is 1 μm to 7 μm and the thickness of the Cu plating layer is 5 μm or more.

Next, as shown in FIG.
The resist mask 2 is removed from above, leaving a plating layer having a predetermined electrode pattern corresponding to the opening pattern of the resist mask 2 on the substrate 1 to form an electrode 5 having a three-layer structure of Au / Ni / Cu.

Next, as shown in FIG.
An insulating layer 6 is formed on the substrate 1 on which is formed, and a via hole 7 a reaching the electrode 5 is formed in the insulating layer 6.

Next, as shown in FIG. 14E, a conductor layer is formed on the insulating layer 6 so as to fill the via hole 7a, and the conductor layer is patterned to form a wiring layer 8.

Finally, as shown in FIG. 14F, a predetermined region of the substrate 1 is removed from the lower surface by etching to expose the electrode 5, and at the same time, a support 16 is formed.

In the present embodiment having the electrode 5 having a three-layer structure of Au / Ni / Cu, there is sufficient adhesion at the interface between the substrate 1 made of stainless steel and the Au plating layer, so that peeling does not easily occur. Further, the Au plating layer is formed of the insulating layer 6.
Depending on the heat history at the time of manufacturing such as formation of
Difficult to diffuse to plating layer. For this reason, the Au plating layer can fulfill a sufficient function as a barrier metal at the time of etching the substrate 1, and the etching conditions can be selected widely. Therefore, the production yield, productivity, and handleability can be improved. Further, when a solder ball is mounted on the electrode 5 and is electrically connected to an external board or device, the Ni plating layer functions as a solder diffusion preventing layer, so that mounting reliability can be improved.

As another method of manufacturing a wiring board having laminated electrodes, a Cu plate or a Cu alloy plate (for example, KFC; KFC) is used as the substrate 1, and a Ni plating layer, Au Plating layer, Ni plating layer,
An electrode having a four-layer structure in which Cu plating layers are stacked in this order can be formed. This structure can be formed in the same manner as the above method except that the electrode structure is different from that of the substrate 1.

The thickness of the substrate 1 is set to 0.1 as in the above method.
mm to 1.0 mm, the thickness of the Ni plating layer is 1 μm or more from the substrate 1 side, and the thickness of the Au plating layer is 0.3 μm.
m to 3 μm, the thickness of the Ni plating layer is preferably 1 to 7 μm, and the thickness of the Cu plating layer is preferably 5 μm or more.

The substrate 1 made of Cu or a Cu alloy (hereinafter appropriately referred to as “Cu substrate”) can be easily etched with a copper chloride or iron chloride etching solution, and thus has the advantage of further improving the productivity.

According to the inventor's intensive studies, the Cu substrate has different characteristics from the substrate made of stainless steel. Therefore, if an Au plating layer is formed directly on the Cu substrate, It has been found that, due to the thermal history in the manufacturing process, metal diffusion occurs between the Cu substrate and the Au plating layer and does not function as a barrier metal at the time of etching. Therefore, as a result of intensive studies, it has been found that this problem of metal diffusion can be solved by forming another plating layer on a Cu substrate via a Ni plating layer 52. Further, since the intermediate Ni layer also functions as a diffusion preventing layer for solder, it was found that the electrode 5 having a multilayer structure of Ni / Au / Ni / Cu plating was most suitable as an electrode for a wiring board.

In another embodiment, Cu / Ag / C
The u-electrode can be formed in the same manner as the above method. In this case, the substrate is not particularly limited, but for example, a Cu substrate or a stainless steel plate can be used.

[Method of Manufacturing Wiring Board Having Recessed Electrode Structure] The electrodes in the wiring board of the present invention are exposed from the bottom surface of the recess 41 provided on the lower surface of the insulating layer 6 as shown in FIG. It can also be structured. This structure can be obtained by, for example, removing the electrode 5 from the lower surface side of the wiring board (insulating layer 6) by a predetermined thickness to form the concave portion 41 as shown in FIG. FIG.
As shown in FIG. 5, in the case of an electrode having a multilayer structure composed of a plurality of different material layers, the electrode can be easily removed by a predetermined thickness in layer units due to the difference in etching rate depending on the material. For example, the aforementioned Ni / Au / Ni / Cu
In the electrode 5 having a plated multilayer structure, only the Ni plating layer is removed by etching, so that a structure depressed with respect to the lower surface of the insulating layer (lower surface of the wiring board) can be formed. With such a structure, the solder balls can be easily mounted even when the electrodes 5 have a narrow pitch.

[Method of Manufacturing Wiring Board Having Protruding Electrode Structure] The electrodes of the wiring board of the present invention may have a structure projecting from the lower surface of the insulating layer 6 as shown in FIG. This structure can be formed, for example, as follows.

First, as shown in FIG. 16A, a resist layer for forming an electrode pattern is formed on a substrate 1 made of a metal plate, and the resist layer is patterned to form an opening corresponding to a predetermined electrode pattern. A resist mask 2 having a portion 3 is formed.

Next, as shown in FIG. 16B, the upper surface of the substrate 1 is etched using the resist mask 2 as an etching mask to form a concave portion 51 corresponding to the opening 3 of the resist mask 2 on the upper surface of the substrate 1. I do.

Next, as shown in FIG. 16C, a metal is deposited on the exposed substrate 1 by plating to form
Then, a plating layer 4 is formed in the opening 3. Then, FIG.
As shown in FIG. 6D, the resist mask 2 is removed, and the plating layer 4 having a predetermined electrode pattern corresponding to the opening pattern of the resist mask 2 is left on the substrate 1 to form an electrode 5.

Next, as shown in FIG.
An insulating layer 6 is formed on the substrate 1 on which is formed, and a via hole 7a reaching the electrode 5 is formed in the insulating layer 6 by photolithography or laser processing.

Next, as shown in FIG. 16F, a conductor layer is formed on the insulating layer 6 so as to fill the via holes 7a by sputtering, electroless plating, electrolytic plating, or the like. The wiring layer 8 is formed by patterning the body layer by photolithography.

Thereafter, as shown in FIG. 2B, the substrate 1 in a predetermined region is selectively etched from the lower surface side to expose the electrode 5 for electrically connecting to the outside.
For example, the substrate is left as a support 16 in a frame shape on the outer periphery of the insulating layer 6.

As described above, a convex electrode can be easily formed. Note that by adjusting the etching amount in the step shown in FIG. 16B, the size of the electrode projecting from the lower surface of the insulating layer can be adjusted.

[Manufacturing Method of Wiring Board Having Capacitor] As described above, the wiring board of the present invention may be configured to have a capacitor as shown in FIG. 7, for example. The configuration having a capacitor can be formed, for example, as follows.

First, as shown in FIG. 17A, the electrodes 92 are formed on the substrate 1 in accordance with the above-described plating method.
To form

Next, as shown in FIG. 17B, a dielectric layer 93 is formed on some of the plurality of electrodes by, for example, a sputtering method using a metal mask.

Next, as shown in FIG.
2 and an insulating layer 94 on the substrate 1 on which the dielectric layer 93 is formed.
Is formed, and via holes 95a are formed in the insulating layer 94 by photolithography or laser processing.

Next, as shown in FIG. 17D, a conductor layer is formed on the insulating film 94 so as to fill the via hole 95a, and the conductor layer is patterned to form a wiring layer 96.
To form

Thereafter, as shown in FIG. 17 (e), the substrate 1 in a predetermined region is selectively etched from the lower surface side to expose the electrode 92 for electrically connecting to the outside and to attach the support 97 to the substrate 97. Form.

The dielectric layer 93 and the electrode 9 below the dielectric layer 93
2 and the via conductor layer 95 on the dielectric layer 93 have a function as a capacitor, so that transmission noise can be reduced. This makes it possible to obtain a wiring board that is optimal for high-speed operation.

[0127]

As described above, according to the present invention, it is possible to realize a high-density and fine wiring of a wiring board corresponding to an increase in the number of terminals and a narrow pitch of a semiconductor device, and to reduce the size of a system. It is possible to realize a narrow pitch of the external electrodes of the wiring board corresponding to the high density. Furthermore, a wiring board having excellent mounting reliability can be provided, and a semiconductor package having high performance and excellent reliability can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of one embodiment of a wiring board for mounting a semiconductor device of the present invention.

FIG. 2 is a schematic sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.

FIG. 3 is a schematic sectional view of another embodiment of a wiring board for mounting a semiconductor device according to the present invention.

FIG. 4 is a schematic bottom (bottom) view of one embodiment of a wiring board for mounting a semiconductor device of the present invention.

FIG. 5 is a schematic sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.

FIG. 6 is a schematic sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.

FIG. 7 is a schematic sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.

FIG. 8 is a schematic sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.

FIG. 9 is a schematic sectional view of an embodiment of a semiconductor package of the present invention.

FIG. 10 is a schematic sectional view of another embodiment of the semiconductor package of the present invention.

FIG. 11 is a sectional process view showing one embodiment of a method for manufacturing a wiring board for mounting a semiconductor device of the present invention.

FIG. 12 is a schematic sectional view of another embodiment of the wiring board for mounting a semiconductor device of the present invention.

FIG. 13 is a sectional process view showing another embodiment of the method for manufacturing a wiring board for mounting a semiconductor device of the present invention.

FIG. 14 is a sectional process view showing another embodiment of the method of manufacturing a wiring board for mounting a semiconductor device according to the present invention.

FIG. 15 is a sectional process view showing another embodiment of the method for manufacturing a wiring board for mounting a semiconductor device of the present invention.

FIG. 16 is a sectional process view showing another embodiment of the method of manufacturing a wiring board for mounting a semiconductor device according to the present invention.

FIG. 17 is a sectional process view showing another embodiment of the method for manufacturing a wiring board for mounting a semiconductor device of the present invention.

FIG. 18 is a sectional process view showing a conventional method of manufacturing a wiring board for mounting a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Resist mask 3 Opening 4 Plating layer 5 Electrode 6 Insulating layer 7 Via 7a Via hole 8 Wiring layer 9 Wiring structure 10 Cover coat 11 Pad part 12 Insulating layer 13 Wiring layer 16 Support 17 Solder resist 18 Semiconductor chip 19 Pad 20 Metal bump 21 Underfill resin 22 Mold resin 24 Adhesion area 25 Laminated board 26 Wiring board 31 Solder ball 32 Dielectric layer 33 Heat sink 41 Depression 51 Depression 91 Substrate 92 Electrode 93 Dielectric layer 94 Insulation layer 95 Via conductor 96 Wiring 97 Support 101 Metal Plate 102 Insulating Layer 103 Via Hole 104 Wiring Pattern 105 Flip Chip Pad 106 Insulating Layer 107 Substrate Reinforcement 108 External Electrode Terminal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Koji Matsui, Inventor 5-7-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Inventor Kazuhiro Baba 5-7-1 Shiba, Minato-ku, Tokyo Japan Inside Electric Co., Ltd.

Claims (51)

[Claims] 1. An insulating layer, a wiring provided on an upper surface of the insulating layer, and an electrode provided on a lower surface side of the insulating layer, at least a periphery of an upper end of the electrode being in contact with the insulating layer and at least an electrode An electrode provided with a lower surface not in contact with the insulating layer, a via located in the insulating layer positioned on the upper surface of the electrode and conducting the electrode and the wiring, A wiring board for mounting a semiconductor device, comprising: a support provided on a surface. 2. The wiring board for mounting a semiconductor device according to claim 1, wherein a periphery of a side surface of the electrode is in contact with the insulating layer, and a lower surface of the electrode is in the same plane as a lower surface of the insulating layer. 3. The wiring board for mounting a semiconductor device according to claim 1, wherein said insulating layer has a concave portion on a lower surface thereof, and said electrode has a lower surface forming a bottom surface of said concave portion. 4. The wiring board for mounting a semiconductor device according to claim 1, wherein a lower end of the electrode protrudes from a lower surface of the insulating layer. 5. The semiconductor device according to claim 1, wherein the electrode has a stacked structure in which a Cu layer is disposed at an upper end thereof and at least one different conductive layer is disposed at a lower end thereof. Wiring board for mounting. 6. A multilayer wiring structure in which an insulating layer and one or more pairs of wirings formed on an upper surface of the insulating layer are sequentially and alternately provided on the upper surface of the insulating layer on which the wiring is formed. 6. The wiring board for mounting a semiconductor device according to any one of items 5 to 5. 7. An insulating layer comprising an insulating material having a film strength of 70 MPa or more, a breaking elongation of 5% or more, a glass transition temperature of 150 ° C. or more, and a thermal expansion coefficient of 60 ppm or less. The wiring board for mounting a semiconductor device according to claim 1. 8. An elastic modulus of not less than 10 GPa and a coefficient of thermal expansion of 3
The wiring board for mounting a semiconductor device according to claim 1, further comprising an insulating layer made of an insulating material having a glass transition temperature of 0 ° C. or less and a glass transition temperature of 150 ° C. or more. 9. The wiring board for mounting a semiconductor device according to claim 7, further comprising an insulating layer formed of a resin formed from an acrylate compound having both ends having a fluorene skeleton. 10. An electrode provided on the lower surface side of the insulating layer, wherein at least the periphery of the upper end of the electrode is in contact with the insulating layer and at least the electrode lower surface is provided so as not to be in contact with the insulating layer; A capacitor comprising a dielectric layer provided on the upper surface of the electrode and a conductive layer provided on the upper surface of the dielectric layer and being conductive to a wiring provided on the upper surface of the insulating layer. Claims 1 to 9 having
The wiring board for mounting a semiconductor device according to any one of the above. 11. The support member is provided on a lower surface of the insulating layer so that a lower surface of the electrode is exposed.
11. The wiring board for mounting a semiconductor device according to any one of claims 10 to 10. 12. The wiring board for mounting a semiconductor device according to claim 11, wherein a solder ball is provided on a lower surface of the electrode. 13. The wiring board for mounting a semiconductor device according to claim 1, wherein the support is provided on the entire lower surface of the insulating layer. 14. The support according to claim 1, wherein said support is made of metal.
14. The wiring board for mounting a semiconductor device according to 1, 12, or 13. 15. A semiconductor device comprising: a wiring board according to claim 1 provided on an upper surface and a lower surface of a laminated plate on which two substrates are bonded, each of which uses the substrate as the support. Wiring board for mounting. 16. A semiconductor package in which a semiconductor device is mounted on the wiring board according to claim 1. Description: 17. The semiconductor package according to claim 15, wherein a semiconductor device is mounted on at least one surface. 18. The semiconductor package according to claim 16, wherein the semiconductor device is sealed with a transfer mold resin. 19. The semiconductor package according to claim 16, wherein a heat sink is provided on the semiconductor device. 20. An insulating layer, a wiring provided on an upper surface of the insulating layer, and an electrode provided on a lower surface side of the insulating layer, wherein at least a periphery of an upper end of the electrode is in contact with the insulating layer and at least the electrode A wiring substrate having an electrode provided such that the lower surface does not contact the insulating layer, and a via provided in the insulating layer and located on the upper surface of the electrode and conducting the electrode and the wiring; And a semiconductor package having a semiconductor device mounted on the wiring board. 21. The semiconductor package according to claim 20, wherein the side surface of the electrode is in contact with the insulating layer, and the lower surface of the electrode is flush with the lower surface of the insulating layer. 22. The insulating layer has a concave portion on a lower surface thereof,
21. The semiconductor package according to claim 20, wherein the lower surface of the electrode forms a bottom surface of the concave portion. 23. The semiconductor package according to claim 20, wherein the lower end of the electrode protrudes from a lower surface of the insulating layer. 24. The semiconductor package according to claim 20, wherein the electrode has a laminated structure in which a Cu layer is disposed at an upper end and at least one different conductive layer is disposed at a lower end. 25. A multilayer wiring structure in which an insulating layer and one or more sets of wirings formed on the upper surface of the insulating layer are sequentially and alternately provided on the upper surface of the insulating layer on which the wiring is formed. 25. The semiconductor package according to any one of claims 24 to 24. 26. An insulating layer comprising an insulating material having a film strength of 70 MPa or more, a breaking elongation of 5% or more, a glass transition temperature of 150 ° C. or more, and a thermal expansion coefficient of 60 ppm or less. A semiconductor package according to claim 1. 27. The semiconductor package according to claim 20, further comprising an insulating layer made of an insulating material having an elastic modulus of 10 GPa or more, a thermal expansion coefficient of 30 ppm or less, and a glass transition temperature of 150 ° C. or more. 28. The semiconductor package according to claim 26, further comprising an insulating layer made of a resin formed from an acrylate-based compound having a fluorene skeleton at both ends. 29. An electrode provided on a lower surface side of the insulating layer, wherein at least a side surface of an upper end of the electrode is in contact with the insulating layer and at least a lower surface of the electrode is not in contact with the insulating layer; A capacitor comprising a dielectric layer provided on the upper surface of the electrode and a conductive layer provided on the upper surface of the dielectric layer and being conductive to a wiring provided on the upper surface of the insulating layer. The semiconductor package according to any one of claims 20 to 28, comprising: 30. The semiconductor package according to claim 20, further comprising a solder ball on a lower surface of said electrode. 31. The semiconductor package according to claim 20, wherein the semiconductor device is sealed with a transfer mold resin. 32. The semiconductor package according to claim 20, further comprising a heat sink on the semiconductor device. 33. A step of forming an electrode pattern on a substrate, a step of forming an insulating layer on the substrate so as to cover the electrode pattern, and a step of forming a via hole reaching the electrode pattern in the insulating layer. Forming a conductive layer on the insulating layer so as to fill the via hole, and patterning the conductive layer to form a wiring pattern. 34. After forming the electrode pattern, the method further comprises forming a dielectric layer on a predetermined electrode pattern, wherein the dielectric layer, the electrode pattern below the dielectric layer, and the dielectric layer 4. A capacitor is formed by the conductive layer embedded in the via hole.
3. The production method according to 3. 35. The method according to claim 33, further comprising the step of selectively removing the substrate to expose the electrode pattern and using the remaining portion of the substrate as a support. 36. The manufacturing method according to claim 33, further comprising a step of removing the substrate and exposing the electrode pattern after mounting the semiconductor device. 37. The manufacturing method according to claim 35, wherein the exposed electrode pattern is selectively etched and removed by a predetermined thickness to form a recess on the lower surface of the insulating layer. 38. A step of forming an electrode pattern on the substrate, using a conductive substrate as the substrate, forming a resist layer having an opening pattern corresponding to the electrode pattern on the substrate, and forming a resist layer in the opening pattern. 38. The manufacturing method according to claim 33, wherein the electrode pattern is formed by depositing a metal by a plating method. 39. The substrate is etched using the resist layer as a mask to form a concave portion corresponding to the opening pattern of the resist layer on the upper surface of the substrate, and then a metal is deposited on the concave portion to form the electrode pattern. Claim 3
9. The production method according to 8. 40. A step of preparing a laminate obtained by bonding a first substrate and a second substrate, forming a first electrode pattern on the first substrate, and forming a first electrode pattern on the second substrate. Forming a second electrode pattern, forming first and second insulating layers on the laminated plate to cover the first and second electrode patterns, respectively, and forming the first insulating layer Forming a via hole reaching the first electrode pattern, forming a via hole reaching the second electrode pattern in the second insulating layer, and forming the first and second via holes so as to fill the via hole. Forming a conductive layer on each of the second insulating layers, and patterning the conductive layers to form first and second wiring patterns. 41. The manufacturing method according to claim 40, further comprising a step of separating the first substrate and the second substrate. 42. After separating the first substrate and the second substrate, the first and second substrates are selectively removed to expose the electrode patterns and remove the remaining portion of the substrate. 42. The production method according to claim 41, comprising a step of forming a support. 43. After mounting the semiconductor device, the first
42. The manufacturing method according to claim 41, further comprising removing the second substrate and the second substrate to expose the electrode pattern. 44. The method according to claim 42, wherein the exposed electrode pattern is selectively etched and removed by a predetermined thickness to form a recess on the lower surface of the insulating layer. 45. In the step of forming the first and second electrode patterns, a conductive substrate is used as the first and second substrates, and the first and second substrates are respectively formed on the first and second substrates. A resist layer having an opening pattern corresponding to the second electrode pattern is formed, and a metal is deposited in the opening pattern by a plating method to form the first and second electrode patterns. 2. The method for manufacturing a wiring board according to claim 1. 46. The first and second substrates are respectively etched by using the resist layer as a mask to form a concave portion corresponding to the opening pattern of the resist layer on the upper surface of the substrate, and then a metal is deposited on the concave portion. 47. The method according to claim 45, wherein the first and second electrode patterns are formed. 47. The wiring substrate according to claim 38, wherein in forming the electrode pattern, a laminated structure is formed in which a Cu layer is disposed at an upper end of the electrode pattern and at least one different conductive layer is disposed at a lower end. Manufacturing method. 48. In the formation of the electrode pattern, a laminated structure in which a Cu layer is disposed at the upper end, a barrier conductive layer for diffusion of solder at the lower end, and a barrier conductive layer for etching removal of the substrate at the lower end is provided. The method for manufacturing a wiring board according to claim 38, wherein the wiring board is formed. 49. The substrate according to claim 38, wherein the substrate is a stainless steel plate, and the electrode pattern is formed by laminating an Au plating layer, a Ni plating layer, and a Cu plating layer on the substrate in this order. Manufacturing method of wiring board. 50. The substrate is a Cu plate or a Cu alloy plate, and the electrode pattern is formed by laminating a Ni plating layer, an Au plating layer, a Ni plating layer, and a Cu plating layer on the substrate in this order. A method for manufacturing a wiring board according to claim 38 or 45. 51. The electrode pattern is provided on the substrate,
The method for manufacturing a wiring board according to claim 38 or 45, wherein a Cu plating layer, an Ag plating layer, and a Cu plating layer are formed by laminating in this order.