JP2002196035A - Manufacturing method and carrier for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device capable of realizing the cost reduction of an electrical characteristic test and that of a product by using existing test jigs and testing devices, and provide a carrier used for it. SOLUTION: During a burn-in test in manufacturing a memory product or a microcomputer/logic product, a chip 1 is so inserted into a through hole 6 of a base 4 as to direct its electrodes downward, a lid 5 is closed, and thereafter, the carrier 2 with the chip 1 mounted is inserted into a socket 3 on a burn-in board, and the burn-in test of the chip 1 mounted in the carrier 2 is executed in this condition. A tape circuit board 8 having interchangeability with a package in the arrangement and signal assignment of terminals 11 connected to contact parts 10 is used for the carrier 2, so that an existing burn-in board and the like can be used as they are. The carrier 2 used in the burn-in test is used in a selection test as well.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, for example, a chip product, a package product,
In a semiconductor device such as a module product, the present invention particularly relates to a method of manufacturing a semiconductor device capable of reducing cost by using an existing jig or device for an electrical characteristic test, and a technique effective when applied to a carrier used for the method.

[0002]

2. Description of the Related Art As a technique studied by the present inventor, the following technique can be considered for an electrical characteristic test of a semiconductor device.

[0003] For example, a burn-in test and a screening test of chips cut from a wafer and individually separated include a chip-level method in which chips are individually separated and a wafer before separation. There is a wafer-level method performed in the state described above. The chip-level methods include a mechanical connection method and a temporary attachment method. In the former mechanical connection method, a dedicated sheet with bumps corresponding to the chip electrodes is placed in a carrier, placed in a socket, and pressure is applied from the back of the chip to apply the chip electrodes and the dedicated sheet. This is to connect with the bump. In the latter method, a wire is temporarily attached to the electrode of the chip,
This is a method in which a test is carried out by placing this in a socket, and the wire is removed from the chip after this test.

[0004] Incidentally, as a technique relating to such an electrical characteristic test of a semiconductor device, for example, “Roadmap on MCM / KGD Technology” published by the Japan Electronics Machinery Association.
Techniques described in P23 to P32 are exemplified.

[0005]

The inventors of the present invention have studied the techniques of the mechanical connection system and the tacking system as described above, and as a result, the following has become clear.

For example, the former mechanical connection method requires a dedicated socket corresponding to each chip having different dimensions and the like, and the unit price of the socket becomes expensive.
The latter tacking method requires a tacking wire as an auxiliary material, and the cost of this wire poses a problem. further,
The tacking method requires a process of removing the wire after the test, and also requires a technique of performing wire bonding so that the wire can be easily removed.

Therefore, the present inventor has adopted an existing test jig or test apparatus for testing a package, for example, in order to minimize the cost of the socket while adopting the former mechanical connection method. It was diverted to chip testing as it was, and it was noted that this would make it possible to reduce the cost of testing. That is, conventionally, a process of sealing the chips separated from the wafer and individually separated and assembling them into a package structure, and then performing an electrical characteristic test of a burn-in test and a screening test, has been performed. I thought that it was possible to use jigs and test equipment as they were.

Accordingly, an object of the present invention is to provide a chip product,
In semiconductor devices such as package products and module products, it is possible to reduce the cost of electrical characteristic tests and further reduce the cost of products, especially by diverting existing test jigs and test equipment of the mechanical connection method. An object of the present invention is to provide a method for manufacturing a semiconductor device and a carrier used for the method.

In the above-mentioned mechanical connection system,
There are many points of contact such as carriers and sockets, and the signal path is long, resulting in high impedance. Therefore, there is a limit to application to high-speed products planned in the future. Therefore, it is necessary to develop a carrier capable of high-speed operation.

Therefore, another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing characteristic impedance due to a contact resistance, a signal path length, and the like in a mechanical connection system and realizing a high speed product. This is to provide a carrier used for this.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the first method for manufacturing a semiconductor device of the present invention, a chip cut from a wafer and individually separated is compatible with a package and terminal arrangement and signal assignment when the chip is sealed. The carrier on which this chip is mounted is mounted on a socket for testing the electrical characteristics of the package, and the electrical characteristics of the chip are tested. As a result of the electrical characteristics test,
It has various steps for shipping a good chip as a chip product.

Further, according to the second method of manufacturing a semiconductor device of the present invention, a chip cut from a wafer and individually separated is compatible with a package and terminal arrangement and signal assignment when the chip is sealed. The carrier on which this chip is mounted is mounted on a socket for testing the electrical characteristics of the package, and the electrical characteristics of the chip are tested.As a result of the electrical characteristics test, a good chip is obtained. It has various steps of assembling into a package structure or a module structure and shipping it as a package product or a module product.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the first or second method for manufacturing a semiconductor device, the electrical characteristic test is applied to a burn-in test and / or a screening test. It is.

Further, the carrier according to the present invention mounts a chip cut from a wafer and individually separated, and is mounted on a socket for performing an electrical characteristic test of a package when the chip is sealed. It has each contact portion that contacts the electrode, and each terminal that is electrically connected to each contact portion and that is compatible with the package in arrangement and signal assignment.

Further, in the carrier according to the present invention, in the carrier, each contact portion and each terminal are formed on a tape-shaped circuit board, and each contact portion and each terminal are connected by each wiring on the circuit board. Then, each electrode of the chip is directly connected to each terminal through each contact portion and each wiring.

Therefore, according to the method of manufacturing a semiconductor device and the carrier, in a burn-in test and a screening test of a chip, a carrier having compatibility in arrangement of packages and terminals and signal allocation is used, and thus an existing burn-in board or the like can be used. Since the test jig and the test apparatus can be used as they are, the cost of the electrical characteristic test can be reduced. Furthermore, the cost of testing can be reduced, so that chip products, package products,
It is possible to reduce the cost of a semiconductor device such as a module product.

Further, in the chip selection test, by using a carrier that is directly connected from each electrode of the chip to each terminal through each contact portion, contact resistance is reduced and signal path length is minimized. Since the characteristic impedance can be reduced, it is possible to realize high-speed products.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a configuration diagram showing a test jig for performing an electrical characteristic test in the embodiment, and FIGS. 4 is a plan view and a side view showing an outer shape comparison between the carrier and the package, and FIGS. 5 and 6 are a plan view showing a terminal arrangement and a signal allocation comparison between the carrier and the package.

First, a manufacturing flow of an example of a method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIG. The method for manufacturing a semiconductor device according to the present embodiment is applied to, for example, shipping as a chip product or a package / module product in the manufacture of a memory product or a microcomputer / logic product, and is performed by the following steps.

(1) Chip preparation process (step S1,
In S2), a wafer on which a desired integrated circuit is formed is cut into chips to prepare individually separated chips. Here, a memory chip and a microcomputer / logic chip are prepared as chips separated from the wafer and individually separated. The wafer is cut into chips after a desired integrated circuit is formed by repeating wafer processing steps such as oxidation / diffusion / impurity introduction, wiring pattern formation, insulating layer formation, and wiring layer formation in the previous process. And separated separately.

(2) In the chip carrier packing step (step S3), the chips cut from the wafer and individually separated are made compatible with each other in the arrangement of the package and terminals and the signal assignment when the chips are sealed. Mount on a carrier that has

(3) In the step of packing the carrier into the burn-in board (step S4), the carrier on which the chip is mounted is mounted on a socket on the burn-in board for performing an electrical characteristic test of the package.

(4) Burn-in test step (step S
In 5), with the carrier mounted on the socket on the burn-in board, a burn-in test is performed on the chip mounted on the carrier. In the burn-in test, for example, a temperature and a voltage stress exceeding the rating are applied to screen a chip that may be defective in the future.

(5) In the carrier burn-in board removing step (step S6), the carrier on which the chip is mounted is removed from the socket on the burn-in board.

(6) In the screening test step (step S7), while the chips are mounted on the carrier, a screening test of the chips mounted on the carrier is performed by a test apparatus.
In the selection test, for example, for a memory, a memory test is performed by using a predetermined test pattern by a write and read operation, and a function test for confirming whether the memory operates as a predetermined function or an input / output pad is performed. DC tests such as an open / short test, a leak current test, and a power supply current measurement, and an AC test for testing an AC timing of memory control are performed. For microcomputer logic, a logic test is performed using a predetermined test pattern to check whether or not the circuit operates as specified, an open / short test between input / output pads, A DC test such as a leak current inspection and a measurement of a power supply current, an AC test for testing an AC timing of logic control, and the like are performed.

(7) In the chip carrier removing step (step S8), the chip is removed from the carrier.

(8) Chip Shipment Step (Step S9)
As a result of the electrical characteristic test by the burn-in test and the screening test, non-defective chips are shipped as chip products. Here, memory chip products and microcomputer logic chip products are shipped.

(9) In a package and module assembling step (step S10), non-defective chips are assembled into a package structure or a module structure. In assembling these packages and modules, for example, a memory chip and a microcomputer / logic chip can be assembled by incorporating only one chip, or two or more such chips can be assembled and assembled, or a memory chip and a microcomputer chip can be assembled. Logic chips can be mixed and assembled. For example, there are MCP and MCM.

In the assembling process, for example,
Die bonding for mounting memory chips and microcomputer / logic chips on a substrate, wire bonding for connecting the electrodes of this chip to pads on the substrate with wires, and molding with resin to protect the chips and wire parts By performing resin molding and lead molding for molding and surface treatment of external leads, the assembly process of the package structure and the module structure is completed.
In the assembling process, it is also possible to use flip-chip bonding for connecting the ball-shaped electrodes of the chip to the pads on the substrate.

(10) In a package / module shipping step (step S11), a package product or a module product assembled in a package structure or a module structure is shipped. As described above, in addition to shipping as a chip product, it is also possible to ship as a package product or a module product.

Next, with reference to FIG. 2, a description will be given of an example of the configuration of a test jig for performing an electrical characteristic test in the method of manufacturing a semiconductor device according to the present embodiment. (A) shows the state when the lid of the carrier is opened, (b) shows the state when the lid of the carrier is closed, and (c) shows the socket. Here, a case where an existing test jig of the TSOP package is used is shown as an example, but it goes without saying that a test jig of another package can be used according to the type and structure of the chip. .

At the time of the burn-in test, the carrier 2 on which the chip 1 is mounted and the carrier 2 on which the chip 1 is mounted
A test jig such as a socket 3 on a burn-in board (not shown) on which is mounted is used. Here, as the chip 1, a so-called center pad structure in which electrodes are arranged in a line at a substantially central portion along the long side direction will be described as an example. However, the present invention is not limited to this. Is also applicable.

The carrier 2 includes a base 4 into which the chip 1 is inserted, a lid 5 that can be opened and closed on the base 4, and the like. A through hole 6 for accommodating the chip 1 is formed in the base 4, and a chip positioning guide 7 is provided at a lower portion of the inner peripheral side surface of the through hole 6. A tape circuit board 8 having a multilayer wiring structure and a reinforcing plate 9 for reinforcing the tape circuit board 8 are provided on the back surface of the base 4. The tape circuit board 8 has contact portions 10 that contact the respective electrodes of the chip 1, and is electrically connected to the contact portions 10.
Each terminal 11 has compatibility with the package of P and the layout and signal assignment. Each terminal 11 of the tape circuit board 8 protrudes from the side surface of the base 4 and is exposed and arranged on the front and back surfaces of the tape circuit board 8. The lid 5 is provided with a pusher 12 inside,
In the closed state, the chip 1 can be pressed against the tape circuit board 8. When the lid 5 is closed, the latch 13 provided on the lid 5 is fitted to the fitting portion 14 of the base 4.

The socket 3 has a T when the chip 1 is sealed.
It has the same structure as the socket on the burn-in board that performs the burn-in test of the SOP package, and it is possible to use the existing burn-in test test jigs and test equipment that were performed after assembling the chip 1 into the package structure. ing. A recess 15 is formed in the socket 3 into which the carrier 2 on which the chip 1 is mounted is inserted, and each pin 16 that contacts each terminal 11 of the tape circuit board 8 of the carrier 2 is formed around the inner bottom surface of the recess 15. The pins 16 are connected to respective wires on a burn-in board (not shown).

At the time of the burn-in test, the chip 1 is inserted along the chip positioning guide 7 in the through hole 6 of the base 4 so that the electrode of the chip 1 faces down. 13 is fitted into the fitting portion 14 of the base 4, the carrier 2 on which the chip 1 is mounted is inserted into the recess 15 of the socket 3 on the burn-in board,
In this state, a burn-in test of the chip 1 mounted on the carrier 2 is performed.

Also, at the time of the screening test, the carrier 2 used in the burn-in test is used, and while the chip 1 is mounted on the carrier 2, the screening test of the chip 1 mounted on the carrier 2 is performed by a test apparatus. . As a result, the electrodes of the chip 1 are directly connected to the terminals 11 through the contact portions 10 of the tape circuit board 8 of the carrier 2, the contact resistance from the chip 1 to the test device is reduced, and the signal path length is minimized. be able to.

Next, an example of an outer shape comparison between a carrier and a package will be described with reference to FIGS. FIG. 3 shows a carrier, and FIG. 4 shows a package.
Shows a plan view, and (b) shows a side view.

The package 21 of the TSOP when the carrier 2 and the chip 1 are assembled into a package structure.
Means that the planar outer shape has almost the same dimensions,
That is, the dimensions A1 and B1 in the long side direction and the dimension A in the short side direction
2 and B2, dimensions A3 and B3 of the terminal 11 of the carrier 2 and the lead (outer lead) 22 of the package 21;
Dimensions A4 and B4 are formed to be substantially the same. In particular, the terminals 11 of the carrier 2 and the leads 22 of the package 21 are arranged at the same interval (dimensions A5 and B5) and at the same position (dimensions A6 and B6).
And the lead 22 of the package 21 have a compatible positional relationship. Also, in the side shape,
The thickness of the terminal 11 of the carrier 2 and the thickness of the lead 22 of the package 21 are the same (A7 and B7).

Next, with reference to FIGS. 5 and 6, an example of the arrangement of terminals of a carrier and a package and a comparison of signal allocation will be described. 5 shows a tape circuit board of a carrier, and FIG. 6 shows a lead frame of a package. FIG. 5 (a) shows a plan view seen from the front, and FIG. 5 (b) shows a plan view seen from the back. Represents.

The aforementioned tape circuit board 8 of the carrier 2
Has a two-layer wiring layer structure, and has a first-layer wiring layer (FIG. 5).
(A)) 31 and a second wiring layer (FIG. 5B) 32 are laminated with an insulating layer (not shown) interposed therebetween, and the surface of the first wiring layer 31 and the back surface of the second wiring layer 32 Is the contact portion 10 and the terminal 11
Except for the connection portion such as, the semiconductor device is covered with a protective film (not shown). In the first wiring layer 31, each contact portion 10 that contacts each electrode of the chip 1 and each terminal 11a that is electrically connected to each contact portion 10 via each wiring 33 are formed. . Each terminal 11b provided at the same position as each terminal 11a of the first wiring layer 31 is electrically connected to the second wiring layer 32 via a through hole 34 with the first wiring layer 31. A power supply, a ground potential wiring 35 and the like are formed. The terminals 11a of the first wiring layer 31 come into contact with the pins 16 of the socket 3 during the burn-in test, and the terminals 11b of the second wiring layer 32 come into contact with the probe of the test device from the back of the carrier 2 during the screening test. It is provided in.

The tape circuit board 8 includes the carrier 2
Two types of through holes 36 and 37 for positioning with the base 4 and the reinforcing plate 9 are formed. One of the four through holes 36 is used for positioning with the base 4, and the other two through holes 36 are used. The holes 37 are used for positioning between the base 4 and the reinforcing plate 9, and a screw member for fixing the reinforcing plate 9 is passed through two through holes 37, and the tape circuit board 8 and the reinforcing member are reinforced by the screw members. The plate 9 is positioned and fixed to the base 4.

The lead frame 41 of the package 21
Each inner lead 44 connected to each electrode 42 of the chip 1 via each wire 43, and each inner lead 44
The outer leads 45 electrically connected to the outer leads 45 are formed. In this example, the chip 1 is arranged on the back surface side of the lead frame 41, and the electrodes 42 of the chip 1 and the inner leads 44 of the lead frame 41 are electrically connected via wires 43. After this wire bonding, resin molding, lead molding, and the like are performed to form a package structure.

When the terminal arrangement and signal assignment of the carrier 2 and the package 21 configured as described above are compared, the terminals 11a and the second terminals of the first wiring layer 31 provided on the tape circuit board 8 of the carrier 2 are compared. Terminal 11 of layer wiring layer 32
“b” has the same arrangement and signal assignment as the outer leads 45 of the lead frame 41 of the package 21. That is, the terminals 10 (11a, 11a,
The number assigned to 11b) and the number assigned to the outer lead 45 of the lead frame 41 correspond to the same signal. For example, in the case of memory, signals such as address, data, and control signals are assigned to terminals at the same position. For microcomputer logic, signals such as input / output signals are assigned to terminals at the same position. Have been.

Therefore, according to the present embodiment, the chip 1
Package 21 in burn-in test and screening test
By using the carrier 2 having compatibility in the arrangement of the outer leads 45 and the terminals 11 and signal assignment, existing test jigs and test equipment such as burn-in boards can be used as they are. Therefore, the cost of the electrical characteristic test can be reduced, and the cost of a chip product, a package product, and a module product can be reduced.

Further, in the selection test of the chip 1, the contact resistance is reduced and the signal path length is minimized by using the carrier 2 which is directly connected from each electrode of the chip 1 to each terminal 11 through each contact portion 10. Since the characteristic impedance can be reduced by minimizing the characteristic impedance, it is possible to realize high-speed products.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, T
Although the case where the existing test jig of the SOP package is used has been described as an example, the case where the test jig of another package such as TQFP when the chip is sealed is used depending on the type and structure of the chip is also described. Applicable.

Further, the package and module are effective not only for MCP and MCM but also for KGD applied products, and can be widely applied to all semiconductor products requiring a burn-in test of a chip.

[0051]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) In the electrical characteristic test of the chip,
By using carriers that are compatible in package and terminal arrangement and signal assignment during burn-in tests and screening tests, existing burn-in boards and other test jigs and test equipment can be reused as they are. It is possible to reduce the cost of the characteristic test.

(2) According to the above (1), the cost of the electrical characteristic test can be reduced.
It is possible to reduce the cost of semiconductor devices such as package products and module products.

(3) In the electrical characteristic test of the chip,
During the screening test, using a carrier that connects directly from each electrode of the chip to each terminal through each contact, it is possible to reduce the contact resistance and minimize the characteristic path length by minimizing the signal path length. Therefore, it is possible to realize high-speed products for semiconductor devices.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 2A, 2B, and 2C are configuration diagrams showing a test jig for performing an electrical characteristic test in one embodiment of the present invention.

FIGS. 3A and 3B are a plan view and a side view showing a carrier in a comparison between the outer shape of the carrier and the package according to the embodiment of the present invention.

FIGS. 4A and 4B are a plan view and a side view showing a package in an outer shape comparison between a carrier and a package according to an embodiment of the present invention.

FIGS. 5A and 5B are plan views showing a tape circuit board of a carrier in a comparison of terminal arrangement and signal assignment between a carrier and a package according to an embodiment of the present invention.

FIG. 6 is a plan view showing a lead frame of the package in a terminal arrangement of the carrier and the package and a comparison of signal allocation in the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Chip 2 Carrier 3 Socket 4 Base 5 Lid 6 Through hole 7 Chip positioning guide 8 Tape circuit board 9 Reinforcement plate 10 Contact part 11, 11a, 11b Terminal 12 Pusher 13 Latch 14 Fitting part 15 Depression 16 Pin 21 Package 22 Lead 31 First wiring layer 32 Second wiring layer 33 Wiring 34 Through hole 35 Wiring 36, 37 Through hole 41 Lead frame 42 Electrode 43 Wire 44 Inner lead 45 Outer lead

Continuing on the front page (72) Inventor Akio Hasebe 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. No. 1 F-term in Hitachi Semiconductor Co., Ltd. F-term (reference) 2G003 AA07 AG01 AG12 2G011 AA14 AA15 AA16 AC14 AE22 AF02 AF04 2G032 AA00 AB02 AF01 AJ05 AJ07 AL00

Claims (5)

[Claims] 1. A step of mounting a chip cut from a wafer and individually separated on a carrier having compatibility in arrangement of a package and terminals and signal allocation when the chip is sealed, and mounting the chip Mounting the carrier on a socket for performing an electrical property test of the package, and performing an electrical property test of the chip; and, as a result of the electrical property test, a step of shipping a good chip as a chip product. And a method of manufacturing a semiconductor device. 2. A step of mounting chips individually cut and separated from a wafer on a carrier having compatibility in arrangement of a package and terminals and signal assignment when the chips are sealed, and mounting the chips. Mounting the carrier thus obtained in a socket for performing an electrical property test on the package, and performing an electrical property test on the chip; and, as a result of the electrical property test, converting a good chip into a package structure or a module structure. Assembling and shipping as a package product or a module product. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the electrical characteristic test is a burn-in test and / or a screening test. 4. A chip, which is cut from a wafer and individually separated, is mounted on a socket for performing an electrical characteristic test of a package when the chip is sealed, and each of the chips is in contact with each electrode of the chip. A carrier comprising: a contact portion; and terminals electrically connected to the respective contact portions and having compatibility with the package in arrangement and signal assignment. 5. The carrier according to claim 4, wherein each of the contact portions and each of the terminals are formed on a tape-shaped circuit board, and a gap between each of the contact portions and each of the terminals is formed on the circuit board. A carrier which is connected by wiring, and is directly connected from each electrode of the chip to each terminal through each contact portion and each wiring.