JP2002176232A - Alignment mark - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an alignment mark having a high recognizability in the production of a multilayer wiring board for mounting a semiconductor chip. SOLUTION: In a metal layer having a wiring pattern and an alignment mark 120 formed by electrolytic plating as a lead for electrolytic plating, a protective mask 150 is formed over the alignment mark and the periphery thereof, the metal layer and the wiring pattern are roughened and then the protective mask is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to alignment. More specifically, the present invention relates to highly recognizable alignment (alignment) marks in the manufacture of a multilayer wiring board on which semiconductor chips are mounted.

[0002]

2. Description of the Related Art In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have been progressing. Semiconductor packages are becoming smaller and more multi-pin than ever before.

[0003] A conventional circuit board is called a printed wiring board. A copper foil, which is made by impregnating a glass fiber woven fabric with an epoxy resin, is attached to a glass epoxy laminate, and then a plurality of the circuit boards are stacked and bonded. Then, a through-hole was formed by drilling, a via was formed by performing copper plating on the wall surface of the hole, and a wiring board in which electrical connection between layers was performed was mainly used. However, the mounting components have been reduced in size and density, and the wiring density of the above-mentioned wiring boards has become insufficient, and problems have arisen in mounting components.

[0004] Against this background, build-up multilayer wiring boards have recently been adopted. The build-up multilayer wiring board is formed while stacking an insulating layer made of only a resin and a conductor. As the via forming method, a variety of methods such as a laser method, a plasma method, and a photo method are used instead of the conventional drilling, and a high-density is achieved by freely arranging small-diameter via holes. Blind vias (Blind Vi) are used as interlayer connection parts.
a) and a buried via (Buried Via: a structure in which a via is filled with a conductor), and the like, and a buried via hole capable of forming a stacked via on the via is particularly attracting attention. The buried via hole is classified into a method of filling the via hole with plating and a method of filling the via hole with a conductive paste or the like. On the other hand, as a method of forming a wiring pattern, there are a method of etching a copper foil (subtractive method), a method of electrolytic copper plating (additive method), and the like. Is starting to be.

The method of manufacturing a build-up multilayer wiring board is roughly divided into the following two methods. (1) A method of sequentially stacking build-up layers by repeating formation of an insulating layer, formation of vias, and formation of a wiring pattern based on a core substrate (hereinafter, referred to as a sequential method). (2) Build-up A method of stacking build-up layers by forming layers independently in advance and aligning and stacking build-up layers on a core substrate (hereinafter, referred to as a parallel method)

In the sequential method, since a build-up layer is sequentially formed on a core substrate as a base, if a defect occurs in an intermediate step, there is a problem that all of the defects become defective at that time. . There is also a problem that it takes a long time from the start of production until a product is obtained. All the steps need to be performed sequentially (sequentially), and as the number of build-up layers increases, this problem becomes more remarkable and is difficult to solve.

On the other hand, in the parallel method, since the build-up layer can be formed independently in advance, even if there is a defect in the formed build-up layer, inspection and sorting can be performed at that time. Therefore, only good products in the build-up layer are selected,
There is an advantage that stacking (alignment stacking on the core substrate) is possible. However, when a failure occurs in the stacking of the build-up layers, it is inevitable that all the products become defective. Further, since the formation of the build-up layer and the lamination of the build-up layer can be performed in parallel, the time from the start of production to the time when a product is obtained is not as long as that of the sequential method.

It can be said from the above description that the additive method is advantageous for forming the wiring pattern, and the parallel method is advantageous for laminating the build-up layers. 1 to 3 are cross-sectional views showing an example of a method for manufacturing a multilayer wiring board using an additive method and a parallel method. Hereinafter, the manufacturing method will be briefly described with reference to the drawings.

The build-up layer 110 shown in FIG.
Can be obtained by the steps shown in FIGS. 1 (a) to 2 (i). The structure will be described briefly with reference to FIG. The build-up layer 110 includes a wiring pattern 104 and an alignment mark 120 formed on the surface of the metal layer 101, an insulating layer 105 formed so as to cover them, and a conductor post 107 penetrating the insulating layer 105.
And a bonding metal material 108 formed on the surface of the conductor post 107, and an insulating layer 105 and a bonding metal material 108.
Is formed so as to cover the adhesive 109.

Using this build-up layer 110, FIG.
By the steps shown in (j) to (k) of FIG.
After the alignment of the build-up layer 110 is performed, the metal layer 101 is formed by the process shown in FIG.
Is removed by etching. In addition, build-up layer 1
In FIG. 10, since the resist metal 103 is formed to protect the wiring pattern 104 and the alignment mark 120 from an etchant, even if the metal layer 101 is etched, the wiring pattern 104 and the alignment mark 120 are not etched. Subsequently, FIG.
By repeating the steps shown in (j) to (l) of FIG.
A multilayer wiring board 140 as shown in FIG. 3 (m) can be obtained.

Here, among the steps shown in FIGS. 1A to 2I, that is, the steps related to the alignment mark among the steps for obtaining the build-up layer 110 will be described. FIG. 1D shows a structure in which a wiring pattern 104 and an alignment mark 120 are formed on the metal layer 101 using the metal layer 101 as a lead (electrode for power supply) for electrolytic plating. On the wiring pattern 104 and the alignment mark 120, an insulating layer 105 is formed.
(E)), a via 106 penetrating the insulating layer 105 is formed (FIG. 1 (f)). As a method for forming the via 106, there is a laser or the like. The most important point here is that the via 106 is accurately formed at a predetermined position. Since the formation position of the via 106 with respect to the alignment mark 120 is determined by design, if the position of the alignment mark 120 can be accurately obtained (recognized), the via 106 is formed.
Can be accurately determined. In order to recognize the alignment mark 120, an image processing device using a CCD is generally used, and it is important to accurately recognize the alignment mark 120 by the image processing device.

On the other hand, when forming the insulating layer 105 on the wiring pattern 104 and the alignment mark 120, the wiring pattern 104 and the alignment mark 12
0 is preliminarily subjected to a roughening process. This is because the wiring pattern 104 and the alignment mark 120 and the insulating layer 1
The purpose is to ensure adhesion to the H.05. However, the wiring pattern 104 and the alignment mark 1
When the roughening process is performed on the surface 20, the roughened shapes of the alignment mark 120 and the metal layer 101 around the alignment mark 120 become substantially the same. Therefore, the recognizability of the alignment mark 120 by the image processing apparatus is significantly reduced,
As a result, it is difficult to form the via 106 at an accurate position.

[0013]

SUMMARY OF THE INVENTION The present invention provides an alignment mark with high recognizability in view of such a current problem of an alignment mark of a build-up layer in manufacturing a multilayer wiring board on which a semiconductor chip is mounted. The purpose is to do.

[0014]

That is, the present invention relates to an alignment mark formed with one surface in contact with a metal layer, wherein the roughened shape of the metal layer surface around the alignment mark and the alignment mark surface An alignment mark characterized by having a different shape from a roughened shape.

Further, the present invention is an alignment mark characterized in that after the metal layer is roughened, the metal layer is formed by electrolytic plating using the metal layer as a lead for electrolytic plating.

Further, according to the present invention, in a metal layer having a wiring pattern and an alignment mark formed by electrolytic plating using a metal layer as a lead for electrolytic plating, a protective mask is formed at least on the alignment mark and a peripheral portion thereof. And an alignment mark obtained by subjecting the metal layer and the wiring pattern to a roughening treatment and then removing the protective mask.
The metal layer may be roughened before performing electrolytic plating.

According to the present invention, there is provided an alignment mark formed with one surface in contact with a metal layer, wherein the alignment mark surface is covered with a barrier metal layer.

The present invention also provides an alignment mark formed by electrolytic plating using a metal layer as a lead for electrolytic plating, wherein a barrier metal layer is formed on the surface of the alignment mark, and the metal layer is subjected to a roughening treatment. Is an alignment mark obtained by:

According to the present invention, there is provided an alignment mark which is obtained by etching an alignment mark embedded in an insulating layer so that one surface thereof is in contact with a metal layer and a metal layer located at a peripheral portion thereof. It is.

Further, according to the present invention, in a metal layer having a wiring pattern and an alignment mark formed by electrolytic plating using the metal layer as a lead for electrolytic plating, at least a portion where the alignment mark is formed and a peripheral portion thereof are provided. And an alignment mark obtained by etching a metal layer to form an opening.

Preferably, the metal layer is made of copper or a copper alloy, and the alignment mark is
It preferably comprises copper.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto. FIG. 4 is a cross-sectional view for explaining the first alignment mark of the present invention.
This is an improvement on the method for manufacturing the multilayer wiring board shown in FIG. Therefore, while describing the steps of FIGS. 1A to 2I, a description of the improved point (first alignment mark) will be added. 2 (j) to FIG. 3 (m) are as described above, and thus description thereof will be omitted.

As a method of manufacturing a multilayer wiring board, first, a plating resist 10 patterned on a metal layer 101 is formed.
2 is formed (FIG. 1A). This plating resist 10
2 can be formed, for example, by laminating an ultraviolet-sensitive dry film resist on the metal layer 101, selectively exposing it using a negative film or the like, and then developing it. The material of the metal layer 101 may be any material as long as it is suitable for this manufacturing method. In particular, the material has resistance to the used chemical solution and can be finally removed by etching. It is necessary. Examples of the material of such a metal layer 101 include copper, a copper alloy, a 42 alloy, and nickel. In addition, the metal layer 101 includes a metal plate and a metal foil, and in particular, a copper foil, a copper plate, and a copper alloy plate can be selected not only from electrolytic plated products and rolled products, but also from various thicknesses. Therefore, it is preferable to use it as the metal layer 101. The metal layer 101 is generally subjected to a roughening treatment in order to improve the adhesion with the plating resist 102.

Next, a resist metal 103 is formed by electrolytic plating using the metal layer 101 as a lead (electrode for power supply) for electrolytic plating (FIG. 1B). By this electrolytic plating, a resist metal 103 is formed on a portion of the metal layer 101 where the plating resist 102 is not formed. The material of the resist metal 103 may be any material as long as it is suitable for this manufacturing method. In particular, the resist metal 103 has a resistance to a chemical used when the metal layer 101 is finally removed by etching. is necessary. As a material of the resist metal 103, for example, nickel, gold, tin,
Silver, solder, palladium and the like can be mentioned. The purpose of forming the resist metal 103 is to change the wiring pattern 104 and the alignment mark 120 shown in FIG.
Is to be prevented from being etched. Therefore, the chemical used for etching the metal layer 101 is
When the wiring pattern 104 and the alignment mark 120 shown in FIG. 1C have resistance, the resist metal 103 is not necessary.

Next, a wiring pattern 104 and an alignment mark 120 are formed by electrolytic plating using the metal layer 101 as a lead (electrode for power supply) for electrolytic plating (FIG. 1C), and the plating resist 102 is removed (FIG. 1C). Figure 1
(D)). By this electrolytic plating, a wiring pattern 104 and an alignment mark 120 are formed on a portion of the metal layer 101 where the plating resist 102 is not formed. Wiring pattern 104 and alignment mark 1
The material of the material 20 may be any material as long as it is suitable for this manufacturing method. In particular, the material of the material 20 has resistance to a chemical used when the resist metal 103 is finally removed by etching. is necessary. Actually, the wiring pattern 104 and the alignment mark 12
It is advisable to select a resist metal 103 that can be etched with a chemical solution that does not etch 0. As a material of the wiring pattern 104 and the alignment mark 120, for example, copper, nickel, gold, tin, silver, palladium, or the like can be used. Particularly, when copper is used, a low-resistance and stable wiring pattern 104 is obtained, which is preferable. .

At this time, the surface of the alignment mark 120 has a gloss after electrolytic plating, and the metal layer 101 around the alignment mark 120 has a roughened shape before the plating resist 102 is formed. The contrast between the alignment mark 120 and the metal layer 101 around the alignment mark 120 is obtained by the processing apparatus, and the recognizability of the alignment mark 120 is very high.

Next, a protective mask 150 is formed on the alignment mark 120 and its peripheral portion.
(D ')). Further, after performing a roughening process on the metal layer 101 and the wiring pattern 104, the protection mask 150 is removed. Through these steps, the surfaces of the metal layer 101 and the wiring pattern 104 have a finely roughened shape. On the other hand, since the alignment mark 120 and the metal layer 101 around the alignment mark are not subjected to the roughening treatment, the contrast between the alignment mark 120 and the metal layer 101 around the alignment mark 120 is obtained by the image processing apparatus as described above, and the alignment mark 120 The recognizability of the is not reduced. The protective mask 150 can be formed, for example, by laminating an ultraviolet-sensitive dry film resist, selectively exposing it to light using a negative film or the like, and then developing it.

Next, an insulating layer 105 is formed on the formed wiring pattern 104 and the alignment mark 120 (FIG. 1E). As the resin forming the insulating layer 105, any resin suitable for this manufacturing method can be used. The insulating layer 105 may be formed by a method suitable for the resin to be used. For example, a resin varnish may be directly applied by printing, curtain coating, bar coating, or the like, or a dry film type resin may be vacuum-laminated, vacuum-coated. A method of laminating by a method such as pressing may be used. In particular, commercially available copper foil with resin is easily available, and the wiring pattern 104 and the alignment mark 1 are formed by vacuum lamination.
If the copper foil is etched while embedding and embedding the irregularities of the wiring pattern 20, the surface of the insulating layer 105 becomes the wiring pattern 10.
4 and very flat without being affected by the unevenness of the alignment mark 120. In addition, since the fine roughened shape of the copper foil surface is transferred to the surface of the insulating layer 105,
Adhesion with the adhesive 109 shown in FIG. 2 (i) can be ensured.

Next, a via 10 is formed in the formed insulating layer 105.
6 is formed (FIG. 2F). The method for forming the via 106 may be any method as long as it is a method suitable for this manufacturing method, and examples thereof include dry etching by laser and plasma, and chemical etching. When the insulating layer 105 is made of a photosensitive resin, the via 106 can be formed by selectively exposing and developing the insulating layer 105. Here, as described above, it is important to accurately form the via 106 at a predetermined position. The alignment mark 120 obtained through the process of FIG. 4D has high recognizability by the image processing apparatus.
The position of the alignment mark 120 can be determined accurately, and as a result, the via 106 can be accurately formed at a predetermined position.

Next, the conductor post 107 is formed by electrolytic plating using the metal layer 101 as a lead (electrode for power supply) for electrolytic plating (FIG. 2 (g)). By this electrolytic plating, a conductor post 107 is formed in a portion of the insulating layer 105 where the via 106 is formed. If the conductor post 107 is formed by electrolytic plating, the shape of the tip of the conductor post 107 can be freely controlled. Conductor post 1
07 may be any material as long as it is suitable for this manufacturing method. For example, copper, nickel,
Gold, tin, silver, palladium, or the like can be used. Particularly, when copper is used, a low-resistance and stable conductor post 107 can be obtained, which is preferable.

Next, the surface (tip) of the conductor post 107
Next, a bonding metal material 108 is formed (FIG. 2H).
As a method for forming the bonding metal material 108, a method for forming by electroless plating, a method for forming the metal layer 101 as an electrolytic plating lead (electrode for power supply) by electrolytic plating, and a paste containing the bonding metal material 108. Is printed. In the printing method, the printing mask needs to be accurately positioned with respect to the conductor post 107. In the method of electroless plating or electrolytic plating, the bonding metal material 108 is used in addition to the surface of the conductor post 107. Since the conductor post 107 is not formed,
It is easy to cope with miniaturization and high density. In particular, the method using electroplating is very suitable because the metal that can be plated is more diverse and the management of the chemical solution is easier than the method using electroless plating. Metallic material for joining 10
8 may be any metal as long as it can be metal-bonded to the core substrate 130 shown in FIG.
An example is solder. Among solders, Sn and I
n or Sn, Ag, Cu, Zn, Bi, Pd, S
It is preferable to use at least two kinds of solders of b, Pb, In, and Au. More preferably, it is an environment-friendly Pb-free solder.

Next, the adhesive 10 is applied to the surface of the insulating layer 105.
9 (FIG. 2 (i)). The formation of the adhesive 109
A method suitable for the resin to be used may be used, such as a method in which a resin varnish is directly applied by printing, curtain coating, bar coating, or the like, or a method in which a dry film type resin is laminated by a method such as vacuum lamination or vacuum pressing. No.
In FIG. 2I, the adhesive 1 is applied to the surface of the insulating layer 105.
Although the example in which the substrate 109 is formed has been described, the adhesive 109 may be formed on the surface of the core substrate 130. Of course, it may be formed on both surfaces of the insulating layer 105 and the core substrate 130.

The steps of FIG. 2 (j) to FIG. 3 (m) are as described above, and the description is omitted.

Next, the second alignment mark according to the present invention will be described in detail with reference to FIG. FIGS. 5C to 5D are cross-sectional views for explaining the second alignment mark of the present invention, and show steps performed instead of FIGS. 1C to 1D. It is for explanation. Therefore, here, portions different from the first alignment mark will be described in detail, and description of the same portion will be basically omitted.

In the step shown in FIG. 5C, the metal layer 10
After forming the wiring pattern 104 and the alignment mark 120 by electrolytic plating using 1 as a lead for electrolytic plating (power supply electrode), the barrier metal layer 160 is formed only on the surface of the alignment mark 120. Subsequently, the plating resist 102 is removed in the step of FIG. Next, a roughening process is performed on the entire metal layer 101, and a barrier metal layer 160 is formed on the surface of the alignment mark 120.
No roughening treatment is performed because of the formation of. The barrier metal layer 160 is formed on the surface of the alignment mark 120, and the metal layer 10 around the alignment mark 120 is formed.
1 has a roughened shape before the formation of the plating resist 102, and therefore, the alignment mark 120 is formed by the image processing apparatus.
And the contrast with the surrounding metal layer 101 are obtained,
The recognizability of the alignment mark 120 is very high.

In order to form the barrier metal layer 160 only on the surface of the alignment mark 120, the plating resist 1 other than the portion where the alignment mark 120 is formed is formed.
02, a resist is further formed on the surface, electrolytic plating,
A method such as electroless plating or a method such as printing may be used. The material of the barrier metal layer 160 may be any material as long as it is suitable for this manufacturing method. In particular, it is necessary that the material has resistance to a roughening treatment. As a material of the barrier metal layer 160, for example,
Nickel, gold, tin, silver, solder, palladium and the like can be mentioned, but it is preferable to select gold having resistance to most roughening treatments.

Next, the third alignment mark according to the present invention will be described in detail with reference to FIG. FIG. 6 is a cross-sectional view for explaining a third alignment mark of the present invention, and is for explaining a step added between FIGS. 1 (e) to 1 (f). So here,
Parts different from the first alignment mark will be particularly described in detail, and description of the same parts will be basically omitted.

After the plating resist 102 is removed in the step shown in FIG. 1D, the entire metal layer 101 is subjected to a roughening treatment without taking any measures for the alignment mark 120. Therefore, at this point, the recognizability of the alignment mark 120 is extremely low. Next, an insulating layer 105 is formed on the wiring pattern 104 and the alignment mark 120 (FIG. 1E). The part 170 is formed (FIG. 6E '). By forming the opening 170, the periphery of the alignment mark 120 becomes only the insulating layer 105, so that the recognizability of the alignment mark 120 is greatly improved.

The first, second and third alignment marks according to the present invention have the following two features. (1) In order to improve the recognizability of the alignment mark 120, a difference (roughened shape, material) is provided between the alignment mark 120 and its peripheral portion. (2) The recognizability of the alignment mark 120 can be remarkably improved only by adding a technically easy process.

[0040]

As is clear from the above description, the present invention can significantly improve the recognizability of the alignment mark. Therefore, by using the alignment mark of the present invention, it is possible to improve the positional accuracy of via formation. Can be
As a result, a multilayer wiring board having a finer wiring pattern can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a method for manufacturing a multilayer wiring board used in the present invention.

FIG. 2 is a sectional view showing an example of a method for manufacturing a multilayer wiring board used in the present invention (continuation of FIG. 1).

FIG. 3 is a cross-sectional view illustrating an example of a method for manufacturing a multilayer wiring board used in the present invention (continuation of FIG. 2).

FIG. 4 is a cross-sectional view showing an example of an additional step for forming a first alignment mark of the present invention.

FIG. 5 is a cross-sectional view showing an example of a changing step for forming a second alignment mark of the present invention.

FIG. 6 is a cross-sectional view showing an example of an additional step for forming a third alignment mark of the present invention.

[Explanation of symbols]

 Reference Signs List 101 metal layer 102 plating resist 103 resist metal 104 wiring pattern 105 insulating layer 106 via 107 conductor post 108 bonding metal material 109 adhesive 110 build-up layer 120 alignment mark 130 core substrate 140 multilayer wiring board 150 protective mask 160 barrier metal layer 170 Aperture

Continuing from the front page (72) Inventor Masaaki Kato 2-5-8 Higashishinagawa, Shinagawa-ku, Tokyo Sumitomo Bakelite Co., Ltd. (72) Inventor Hideki Hara 2-5-2-8 Higashishinagawa, Shinagawa-ku, Tokyo Sumitomo Bakelite shares Company F-term (reference)

Claims (10)

[Claims] An alignment mark formed with one surface in contact with a metal layer, wherein the roughened shape of the metal layer surface around the alignment mark is different from the roughened shape of the alignment mark surface. Characteristic alignment mark. 2. An alignment mark formed by electrolytic plating using a metal layer as a lead for electrolytic plating after roughening the metal layer. 3. A metal layer having a wiring pattern and an alignment mark formed by electrolytic plating using the metal layer as a lead for electrolytic plating, wherein a protective mask is formed at least on the alignment mark and a peripheral portion thereof. And an alignment mark obtained by subjecting the wiring pattern to a roughening treatment and then removing the protective mask. 4. The alignment mark according to claim 3, wherein the metal layer is subjected to a roughening treatment before performing the electrolytic plating. 5. An alignment mark formed with one surface in contact with a metal layer, wherein the alignment mark surface is covered with a barrier metal layer. 6. An alignment mark formed by electrolytic plating using the metal layer as a lead for electrolytic plating, wherein a barrier metal layer is formed on the surface of the alignment mark.
An alignment mark obtained by subjecting a metal layer to a roughening treatment. 7. An alignment mark obtained by etching an alignment mark embedded in an insulating layer such that one surface thereof is in contact with a metal layer and a metal layer located at a peripheral portion thereof. 8. In a metal layer having a wiring pattern and an alignment mark formed by electrolytic plating using the metal layer as a lead for electrolytic plating, at least the metal layer at a portion where the alignment mark is formed and a peripheral portion thereof is formed. An alignment mark obtained by forming an opening by etching. 9. The alignment mark according to claim 1, wherein the metal layer is copper or a copper alloy. 10. The alignment mark according to claim 1, wherein the alignment mark includes copper.