JP2002171766A - Resonant inverter - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce switching loss of a resonant inverter. An inverter output current I _L detects a zero-cross timing when moving from a positive value to a negative value, the frequency command value as the zero-cross timing and the turn-on timing of the switching element SW2 is coincident f ^*
To update. By the load voltage V ₂ and the predetermined value v _S controls the pulse width of the output voltage pulse V ₁ of the inverter 10 to match the deviation to zero cross timing of the inverter output current I _L and the turn-off timing of the switching element SW2 even if, because the frequency of the output voltage pulse V ₁ in response to the displacement is controlled, the phase of the inverter output current I _L, shifted in the direction in which the zero-cross timing and the turn-on timing of the switching element SW2 is matched, The switching element SW2 performs a zero current switching operation, so that its turn-on loss is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resonance type inverter in which a reactor and a capacitor connected in series are connected to an output side of an inverter circuit to perform a resonance operation, and more particularly, to a turn-on loss and a turn-off thereof. The present invention relates to a resonance-type inverter configured to reduce a loss.

[0002]

2. Description of the Related Art Conventionally, in a so-called resonant inverter having an inverter for alternately outputting positive and negative voltage pulses and a reactor and a capacitor connected in series to its output terminal, the output voltage pulse of the inverter is known. The voltage supplied to the load is adjusted by performing PWM control that changes the ratio of the period during which the voltage becomes a positive or negative voltage to the period during which the voltage becomes zero. Then, in order to keep the load voltage at a desired value irrespective of the fluctuation of the power supply voltage or the load, the load voltage is monitored, and the PWM control is performed so that the load voltage becomes a desired voltage value. To adjust.

That is, as shown in FIG. 4, for example, a reactor L and a capacitor C are connected to the output terminal of a full-bridge inverter 10 composed of four switching elements SW1 to SW4 in which diodes D1 to D4 are connected in anti-parallel. Are connected in series, the voltage detector 12 detects the voltage across the load connected in parallel with the capacitor C.

Then, in the pulse width control circuit 22,
The pulse width command value is set so that the load voltage detected by the voltage detector 12 becomes a predetermined voltage, and an instruction is given to the switch control circuit 24. The switch control circuit 24 So that the output voltage pulse V ₁ has a predetermined frequency set in advance, and has a pulse width designated by the pulse width control circuit 22.
Each of the switching elements SW1 to SW4 is alternately switched with a dead time therebetween as shown in FIG. As a result, an output voltage pulse V ₁ having a specified voltage value of a specified frequency is output, and a desired load voltage V ₂ is obtained.

[0005]

In the inverter 10, the switching elements SW1 to SW
It is known that a turn-on loss and a turn-off loss occur when switching 4. The turn-on loss and the turn-off loss can be reduced by performing a zero-current switching operation of switching the switching element SW1~SW4 when the inverter output current I _L does not flow.

However, as described above, when the pulse width of the output voltage pulse is adjusted by PWM control in order to maintain the load voltage at a predetermined value, by adjusting this pulse width, as shown in FIG. Switching element S
Shift amount varies between switching timing and the zero-cross timing of the inverter output current I _L of W1～SW4, there is a problem that the turn-on loss and the turn-off loss in some cases increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional unsolved problem, and it is possible to reduce an increase in turn-off loss and turn-on loss caused by controlling a pulse width. It is intended to provide a simple resonance type inverter.

[0008]

In order to achieve the above object, a resonant inverter according to a first aspect of the present invention has a plurality of semiconductor switching elements, and controls the semiconductor switching elements to be positive and negative. Zero-cross timing for detecting the zero-cross timing of the output current of the inverter circuit in a resonance-type inverter including an inverter circuit that alternately outputs the voltage pulses of the above, and a reactor and a capacitor connected in series to the output terminal of the inverter circuit. Detecting means; edge detecting means for detecting a rising edge or a falling edge of an output voltage pulse of the inverter circuit; zero cross timing detected by the zero cross timing detecting means; and edge detecting timing detected by the edge detecting means. To detect deviation from Imming shift detecting means, frequency control means for controlling the frequency of the output voltage pulse of the inverter circuit so that the timing shift detected by the timing shift detecting means is eliminated, and the frequency of the output voltage pulse set by the frequency control means And a switch control means for controlling the semiconductor switching element so that the frequency becomes the specified frequency.

According to a second aspect of the present invention, in the resonance type inverter according to the first aspect, the supply voltage to the load is controlled by changing a pulse width of an output voltage pulse of the inverter circuit. It is characterized by becoming. This claim 1 and claim 2
In the resonance type inverter, the rising edge or the falling edge of the output voltage pulse of the inverter circuit is detected, the zero-cross timing of the output current of the inverter circuit is detected, and the difference between the edge detection timing and the zero-cross timing is detected. Is detected. Then, the frequency of the output voltage pulse output from the inverter circuit is controlled so as to eliminate the timing shift.

That is, when the frequency of the output voltage pulse changes, the phase of the output current of the inverter circuit advances or delays accordingly, so that the falling edge or the rising edge coincides with the zero-cross timing of the output current. If the frequency is adjusted as described above, the switching elements constituting the resonance type inverter will perform the zero current switching operation, and the switching loss of each switching element can be reduced.

In particular, in a resonance type inverter in which the supply voltage to the load is controlled by changing the pulse width of the output voltage pulse of the inverter circuit, when the pulse width is updated, the falling or rising edge and the zero-cross timing are changed. In some cases, the turn-on or turn-off loss may increase accordingly.
However, since the frequency control is performed so that the falling or rising edge of the output voltage pulse whose pulse width has been changed matches the zero-cross timing, the falling or rising edge and the zero-cross timing do not depend on the change in the pulse width. Will match
Turn-on or turn-off loss can be reduced.

[0012]

Embodiments of the present invention will be described below. FIG. 1 is a schematic configuration diagram of a resonant inverter to which the present invention is applied. That is, as shown in FIG. 1, the inverter 10 is connected to both ends of the DC power supply 1, and the reactor L and the capacitor C connected in series are connected to the output terminal. The load 50 is connected to both ends of the capacitor C.

The inverter 10 is a so-called full-bridge type inverter and is composed of self-extinguishing type switching elements SW1 to SW4 such as transistors, for example, and the switching elements SW1 and SW2, and SW3 and SW4.
Are connected in series, respectively, and the switching elements SW1 and SW2, SW3 and SW4 connected in series
Are connected in parallel to the DC power supply 1. Diodes D1 to D4 are connected in anti-parallel to the switching elements SW1 to SW4, respectively.

One end of a reactor L is connected to a connection point of the switching elements SW1 and SW2 connected in series with the inverter 10, and a connection point between the other end of the reactor L and a connection point of the switching elements SW3 and SW4. Is connected to a capacitor C. The connection point between the switching elements SW1 and SW2 and the connection point between the switching elements SW3 and SW4 are connected to the inverter 10.
Of is an output terminal, the voltage between these are supplied to the load 50 as an output voltage pulse V ₁ of the inverter 10.

Further, the voltage detector 12 is provided for the both ends of the capacitor C that measures the load voltage, further, the output current I _L of the resonant inverter between the output terminal and the capacitor C of the inverter 10 Current detector 14 to detect
Is provided. The detection voltage of the voltage detector 12 is:
The pulse width control circuit 22 outputs the detected voltage to the pulse width control circuit 22.
As a pre-specified load voltage set according to the load 50, to set the pulse width of the output voltage pulse V ₁ of the said inverter 10, and outputs to the switch control circuit 24 so as pulse width command value.

The current detected by the current detector 14 is as follows:
Is output to the phase difference detector 26, phase difference detector 26, based on the detection signal of the current detector 14 detects a zero-cross timing of the inverter output current I _L. And
A zero-cross timing of the inverter output current I _L, is input from the switch control circuit 24, on the basis of the switching timing information of the switching elements SW1 to SW4, the turn-on timing of the switching element SW1 or SW2, or the switching element SW3 or SW
The shift between the turn-off timing of No. 4 and the zero-cross timing is detected, and it is determined whether or not the zero-cross timing is ahead of the switching timing of each of the switching elements SW1 to SW4. The result of the determination is output to the frequency control circuit 28 as timing deviation information.

Here, the switching of the switching element is performed.
Timing and inverter output current I _LZero cross tie
The detection of the deviation from the output voltage pulse V₁Standing
Switch that defines rising and falling edges
Switching timing of the switching element,
Switching element switching tie causing switching loss
And the output voltage pulse V₁Falling edge of
And inverter output current corresponding to rising edge
I_LDetects deviation from zero cross timing
You.

That is, as shown in FIG.₁₁At
Output voltage pulse V₁Switch rise timing.
Is determined by the turn-on timing of the switching element SW1.
Therefore, the turn-on timing of the switching element SW1
And the inverter output current I _LChanges from negative to positive
Between the zero-cross timing
You. Also, at time t₁₄Output voltage pulse V at₁Fall of
The switching timing is when the switching element SW2 is turned on.
Because it is determined by the timing, the switching element SW
2 and the inverter output current I_L
The zero-cross timing when
To detect the deviation.

Further, the fall timing of the output voltage pulse V ₁ of the at t ₁₂ is determined by the turn-off timing of the switching element SW4, the rise timing of the output voltage pulse V ₁ of the at t _15, the turn-off of the switching element SW3 determined by their timing, it detects the turn-off timing of the switching element SW4, the deviation between the zero-cross timing of the inverter output current I _L is changed to a negative value from the positive value, similarly, the turn-off timing of the switching element SW3, the inverter output current I _L detects the deviation between the zero-cross timing that changes to a positive value from a negative value.

The frequency control circuit 28 sets the frequency of the output voltage pulse V ₁ based on the timing deviation information from the phase difference detector 26. That is, the phase difference detector 26, when the direction of the zero cross timing of the inverter output current I _L is determined to leads the switching timing of the switching element, the predetermined frequency Δf set the frequency command value f ^* in advance Only decrease. Conversely, when the direction of the zero cross timing of the inverter output current I _L is determined to slower than the switching timing of the switching element increases the frequency command value f ^* by the predetermined frequency Delta] f.

The switch control circuit 24 has a designated frequency based on a pulse width command value from the pulse width control circuit 22 and a frequency command value f ^* from the frequency control circuit 28. In order to output an output voltage pulse V ₁ having a pulse width, the switching elements SW1~
Controls the switching timing of SW4, as a positive voltage and negative voltage are alternately output as the output voltage pulse V _1, both off together off or switching elements SW3 and SW4, the switching elements SW1 and SW2 Each switching element SW1
SW4 is turned on / off. That is, as shown in FIG. 2, by turning on both the switching elements SW1 and SW4, an output voltage pulse V1 which becomes the power supply voltage + E of the DC power supply ₁ is output, and conversely, the switching elements SW2 and SW3 are turned on. As a result, −E is output. Then, in the time other than this, the output voltage pulse V ₁ was a zero voltage.

If the polarity of the voltage and current between the output terminals of the inverter 10 is different, the diodes D1 and D1
4, or the diodes D2 and D3 conduct, but the diode connected in anti-parallel to the switching element to which the drive signal is given from the switch control circuit 24 is turned on, so that the drive signal is given as on. This is equivalent to a state where the switching element is conducting.

[0023] Here, inverter 10 corresponds to the inverter circuit, the process of detecting the zero-cross timing of the inverter output current I _L corresponds to the zero-cross timing detecting means in the current detector 14 and the phase difference detector 26,
The process of outputting the switching timing information of each switching element from the switch control circuit 24 to the phase difference detector 26 corresponds to the edge detecting means, and the phase difference detector 26 detects a shift between the zero cross timing and the switching timing of the switching element. The processing corresponds to the timing deviation detecting means, the frequency control circuit 28 corresponds to the frequency control means, and the switch control circuit 24 corresponds to the switch control means.

Next, the operation of the above embodiment will be described.
Now, the operation frequency of the inverter 10 is changed to the frequency initial value f _0.
In driving, also the load when the voltage V ₂ is assumed to be driven to a predetermined value v _S, the frequency control circuit 28, the switch controlled by setting the frequency initial value f ₀ as the frequency command value f ^* circuit 24 output (FIG. 3 step S1), the addition, in the pulse width control circuit 22 sets the pulse width command value load voltage V ₂ can become the predetermined value v _S, and outputs it to the switch control circuit 24.

The switch control circuit 24 switches each of the switching elements SW1 to SW4 at a predetermined timing so that the specified frequency command value f ^* and the specified pulse width command value are obtained. As a result, an output pulse voltage V ₁ having a specified frequency f ^* and a specified pulse width is output from inverter 10, and reactor L
Due to the resonance operation by the capacitor C and the load voltage V ₂ larger than the output voltage pulse V ₁ , the load voltage V ₂ is applied to the load 50.

The load voltage V ₂ is detected by the voltage detector 12 and output to the pulse width control circuit 22. The pulse width control circuit 22 compares the detection voltage detected by the voltage detector 12 with a predetermined value v _S , and when the detection voltage is larger than the predetermined value v _S , the interval in which the output voltage pulse V ₁ becomes zero becomes longer. The pulse width command value is set so as to increase, and conversely, when the detected voltage is smaller than the predetermined value v _S , the pulse width command value is set so that the section in which the output voltage pulse V ₁ becomes + E or −E is increased. Set the value.

[0027] In the switching control circuit 24, to match the pulse width command value whose pulse width is specified in the output voltage pulse V _1, because switching the respective switching elements SW1 to SW4, the pulse width output voltage pulse V ₁ are controlled, the load voltage V ₂ is controlled to coincide with a predetermined value v _S. At this time, the current detector 14, which detects the inverter output current I _L, and outputs the detection result to the phase difference detector 26, the phase difference detector 26, a zero-cross timing of the inverter output current I _L Detected.
For example, among the switching information of a switching element SW1~SW4 from the switch control circuit 24, detects whether the turn-on timing of the switching element SW2, and a zero-cross timing of the inverter output current I _L is a negative value from a positive value to match If they do not match, it detects which timing is advanced.

[0028] In this case, for example, and on-off states of the switching elements SW1~SW4 when the frequency f _V of the output voltage pulse V ₁ is a f _V = f _0, the relationship shown in the inverter output current I _L Togazu 5 in some cases, detected zero-cross timing of the inverter output current I _L at time t _13, the turn-on timing of the inverter output current I _L of the switching element SW2 is to be detected at t _14. Therefore, since progressed towards zero-cross timing of the inverter output current I _L, and notifies the frequency control circuit 28.

In the frequency control circuit 28, the phase difference detector 2
Based on the timing deviation information from 6, to determine whether there is a deviation in the zero-cross timing and the switching timing (step S2), the on when there is no displacement between them, subsequently frequency initial value as the frequency command value f ^* f
Set _0, the frequency of the output voltage pulse V ₁ is but an instruction to the frequency initial value f _0, it is notified from the phase difference detector 26 is displaced to the zero-cross timing and the switching timing, step Step S2 from S2
Move to 3. In this case, since the direction of the zero cross timing of the inverter output current I _L is advanced, and proceeds from step S3 to step S4, the frequency command value f
^* Is increased by Δf, and this is instructed to the switch control circuit 24.

Thus, the switch control circuit 24 changes the switching timing of each of the switching elements SW1 to SW4 and controls the switching of the switching elements SW1 to SW4 so that the frequency becomes larger by Δf than before. with the changes in frequency of the output voltage pulse V _1. Thus the frequency of the output voltage pulse V ₁ changes, since a change in the impedance of the resonant circuit composed by the reactor L and the capacitor C, the phase of the inverter output current I _L is delayed, 5, time t displacement of the turn-on timing of the switching element SW2 of the zero-cross timing and the time point t ₁₄ of the ₁₃ shifts in the direction to become smaller.

If the zero-cross timing and the turn-on timing do not match, step S4
Then, the process returns to step S2, further proceeds to step S4 via step S3, and adds Δf to the frequency command value f ^* to further increase the frequency. Thus, the phase of the inverter output current I _L is delayed slightly, eventually when the frequency f _V of the output voltage pulse V ₁ is controlled to f _V = fs, as shown in FIG. 2, the inverter output current at the time point t ₃ zero-cross timing of I _L and the switching element SW2
Turn-on timing.

[0032] In the frequency control circuit 28, because these zero cross timing and the turn-on timing match, stops updating the frequency command value f ^*, the frequency instruction value f ^* at this time, the switch control circuit 24 Continue to instruct. Conversely, when the zero-cross timing of the inverter output current I _L is delayed from the turn-on timing of the switching element SW2, the process proceeds from step S3 to step S5, the frequency command value f ^* delta
Decrease by f. Therefore, since the frequency f _V decreases the output voltage pulse V _1, the phase of the inverter output current I _L advances, the zero cross timing of the inverter output current I _L is varied in the direction approaching the turn-on timing of the switching elements SW2, eventually These match.

Therefore, when the load voltage V ₂ changes due to a change in the power supply voltage of the DC power supply 1 or a change in the load 50, the pulse of the output voltage pulse V ₁ is controlled so as to suppress the change in the load voltage V _2. The width has changed, and accordingly,
And switching timing of the switching elements SW1 to SW4, the relationship between the zero-cross timing of the inverter output current I _L is changed. At this time, if the zero-cross timing of the turn-on timing and the inverter output current I _L of the switching element SW2 is shifted, so that the inverter output current I _L flows in the turn-on timing of the switching element SW2, the turn-on loss Will occur.

[0034] However, as is the turn-on timing of the zero-cross timing and the switching element SW2 match, because adjusting the phase of the inverter output current I _L by controlling the frequency of the output voltage pulse V _1, the switching element SW2 is zero current In the switching state,
The turn-on loss of the switching element SW2 can be reduced.

Since the turn-on timing of the switching element SW1 and the turn-on timing of the switching element SW2 are shifted by a half cycle, the turn-on timing of the switching element SW2 and the zero-cross timing are made to coincide with each other, whereby the switching element SW1 is turned on.
Of the switching element SW1 and the zero-cross timing coincide, and the turn-on loss of the switching element SW1 is also reduced.

In the above embodiment, since the inverter output current _IL is directly detected and the zero-cross timing is detected based on this, the zero-cross timing can be detected with high accuracy. By performing the frequency adjustment based on the zero-cross timing, the switching loss can be more accurately reduced.

Further, since the switching loss can be reduced as described above, the power efficiency of the entire device can be improved. In addition, when a switching loss occurs, it is necessary to dissipate the heat due to the switching loss, so that the device is increased in size. In the above embodiment, however, the switching loss can be reduced, thereby suppressing the increase in the size of the device. be able to.

In the above embodiment, the turn-on loss of the switching element SW2 is reduced by changing the operation frequency of the inverter 10. Therefore, the current value may increase by changing the operation frequency, and the turn-off loss may increase with the increase in the current value at the time of turn-off. However, there is no problem because the increase in the turn-off loss is small compared to the reduction in the turn-on loss.

Further, by controlling the operating frequency of the inverter 10, the switching loss can be reduced, so that the present invention can be realized without largely changing the existing configuration. Further, even when it is difficult to reduce the loss by another method such as soft switching, the loss can be reduced by controlling the operating frequency of the inverter 10, and further, the loss can be reduced by combining these. , The loss can be further reduced.

In particular, when the pulse width is controlled by the PWM control, the shift amount between the switching timing of the switching element and the zero-cross timing changes according to the change in the pulse width, and the switching loss may increase. but an increase in the switching loss due to the change in pulse width, by changing the frequency of the output voltage pulse V _1, it is preferable because it is possible to suppress.

[0041] In the above embodiment, by matching the zero-cross timing of the turn-on timing and the inverter output current I _L of the switching elements SW2, with the case of reducing the turn-on loss of the switching elements SW1 and SW2 has been described, the present invention is not limited thereto, may be caused to coincide with the zero-cross timing of turn-on timing and the inverter output current I _L of the switching element SW1 is a positive value from a negative value, in this case, the switching elements SW1 and S
The turn-on loss of W2 can be reduced.

In the above embodiment, the case where the turn-on loss of the zero-cross switching elements SW1 and SW2 is reduced is described. However, the present invention is not limited to this, and the turn-off loss of the switching elements SW3 and SW4 is reduced. It is also possible to make it. In this case, the zero cross timing turn-off timing and the inverter output current I _L of the switching element SW3 is a positive value from a negative value, or turn-off timing and the inverter output current I of the switching device SW4
_What is necessary is to make the zero-cross timing from the positive value of _L to the negative value coincide.

Further, as described above, the switching element SW1
ON loss of switching element SW2 and switching element SW
Both the turn-off loss of SW3 and SW4 can be reduced, but not both.
Therefore, which loss should be reduced may be selected from the one with the larger loss or the one that is difficult to reduce the loss by another method such as soft switching.

In the above embodiment, the load 5
Although the case where 0 is connected in parallel with the capacitor C has been described, the present invention can be applied even when the load 50 is connected between the reactor L and the capacitor C. Also, the case where the present invention is applied to a full-bridge type inverter has been described. However, the present invention is not limited to this. For example, the present invention can be applied to a half-bridge type inverter. The present invention can be applied to any resonance type inverter.

In the above embodiment, the case where the frequency command value f ^* is updated by Δf has been described, but the present invention is not limited to this. For example, the amount of deviation between the switching timing of the switching element and the zero-cross timing is detected, and PI (proportional / integral)
Using a controller or the like, if the deviation amount is relatively large, update the frequency command value f ^* relatively large,
The frequency may be updated little by little.

[0046]

As described above, according to the first aspect of the present invention,
According to the resonant inverter according to claim 2, the frequency is controlled such that the timing of the rising or falling edge of the output voltage pulse of the inverter circuit matches the zero-cross timing of the output current of the inverter circuit. Therefore, the switching loss of the switching elements forming the inverter circuit can be easily reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an example of a resonance type inverter to which the present invention is applied.

FIG. 2 is a timing chart for explaining the operation of the resonant inverter of the present invention.

FIG. 3 is a flowchart illustrating an example of a processing procedure of the frequency control circuit of FIG. 1;

FIG. 4 is a schematic configuration diagram showing an example of a conventional resonance type inverter.

FIG. 5 is a timing chart for explaining the operation of a conventional resonant inverter.

[Description of Signs] 1 DC power supply 10 inverter 12 voltage detector 14 current detector 22 pulse width control circuit 24 switch control circuit 26 phase difference detector 28 frequency control circuit 50 load

Claims (2)

[Claims] An inverter circuit having a plurality of semiconductor switching elements and alternately outputting positive and negative voltage pulses by controlling the semiconductor switching elements, and a reactor connected in series to an output terminal of the inverter circuit And a capacitor, comprising: a zero-cross timing detecting means for detecting a zero-cross timing of an output current of the inverter circuit; and an edge detecting means for detecting a rising edge or a falling edge of an output voltage pulse of the inverter circuit. A timing shift detecting means for detecting a shift between the zero cross timing detected by the zero cross timing detecting means and an edge detection timing detected by the edge detecting means; and a timing shift detected by the timing shift detecting means. Frequency control means for controlling the frequency of the output voltage pulse of the inverter circuit, and switch control means for controlling the semiconductor switching element so that the frequency of the output voltage pulse becomes the frequency set by the frequency control means. And a resonance type inverter. 2. The resonant inverter according to claim 1, wherein a supply voltage to a load is controlled by changing a pulse width of an output voltage pulse of said inverter circuit.