JP2002027665A - Intelligent power module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure compatibility for an existing system which can output only a kind of alarm signal and to provide adequate measure for generation of a fault by enabling transmission of a factor for fault to an external side. SOLUTION: There are provided semiconductor switching elements 11 to 14, drive circuit 31 to 34, various detection circuit and warning circuits for detecting serious fault or predictive faults of the switching element or drive circuit or the like, fault detection logics 51 to 54, drive circuits 31 to 34 or the like for protection the operations of these switching elements 11 to 14 when a fault is detected by these circuits, control circuits 91, 92 for outputting a signal, based on a fault detection signal to external circuit and a transmission circuit 110. The transmission circuit 110 is provided with an output terminal for outputting an alarm signal, when the serious fault is detected and an output terminal for outputting a fault factor identification signal, which indicating a factor of fault including serious fault and predictive fault. It is preferable that these output terminals are used in common as a single output terminal 130.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power module used for a power converter such as a PWM inverter and an uninterruptible power supply, and an intelligent power module including a power semiconductor switching element, a drive circuit therefor, and a protection circuit. (Intelligent Power Module: hereinafter referred to as IPM as necessary).

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional IPM. It should be noted that the IPM usually has three phases, but for convenience of explanation, a single phase is shown. In FIG. 6, 11-1
Reference numeral 4 denotes IGBTs 21 to 21 as bridge-connected semiconductor switching elements constituting a PWM inverter, for example.
24 is a freewheeling diode (FWD) connected in anti-parallel to these IGBTs 11 to 14, 31 to 34
Is a drive circuit of the IGBTs 11 to 14, and 61 to 64 are an IGB
Control circuits for controlling the T drive circuits 31 to 34;
21, 431, 441 are IG when upper and lower arm short circuit or ground fault
Overcurrent detection circuits for detecting overcurrent flowing through the BTs 11 to 14, 412, 422, 432 and 442 are IGBTs
11-14 overheat detection circuits, 413, 423, 433,
A drive voltage drop detection circuit 443 detects a drop in the control power supply voltage required to drive the IGBTs 11 to 14;
1 to 54 are input with an abnormality detection signal from each detection circuit,
This is an abnormality detection logic for sending a cutoff signal to the drive circuits 31 to 34 via the control circuits 61 to 64 and outputting an alarm signal to the outside. In the inverter main circuit, P and N indicate DC input terminals, and U and V indicate AC output terminals.

In FIG. 6, control circuits 61 to 64 are IGBTs based on a signal (control input) from an insulated signal transmission element such as a photocoupler for performing optical insulation (not shown).
On / off of the IGBTs 11 to 14 is controlled via the drive circuits 31 to 34. When the abnormality detection logics 51 to 54 detect at least one of the various abnormality detection signals from the respective detection circuits, as described above, they determine that the abnormality is fatal (major failure), and respectively determine the IGBT drive circuits 31 to 34. The IGBTs 11 to 14 are shut off via the. Here, all IGBTs 1 are output by the output signal of one abnormality detection logic.
1 to 14 can also be blocked. Then, the abnormality detection logics 51 to 54 output an alarm signal from the alarm signal output terminal 130 via the control circuits 61 to 64 in order to notify the occurrence of the abnormality to the outside. Here, for safety, the alarm signal is insulated by a photocoupler or the like and output to the outside.

In the example of FIG. 6, an alarm signal is output by wired OR only from the abnormality detection logics 51 and 53 of the lower arm, but the abnormality detection signals from the abnormality detection logics 52 and 54 of the upper arm are also insulated, respectively. Then, it can be output as an alarm signal.

[0005] Another prior art is disclosed in Japanese Patent No. 288.
A MOS gate driver circuit described in Japanese Patent No. 6495 is known. This prior art relates to a MOS gate driver circuit for a high-voltage side switching circuit having overcurrent detection, cutoff, and notification output.

[0006]

In the prior art shown in FIG. 6, there is only one type of alarm signal. Therefore, in the case of three-phase, what kind of element is in which phase out of six IGBTs or freewheeling diodes. It cannot be determined from the outside whether any abnormalities have occurred. If the location of the abnormality (phase, element, etc.) and the cause of the abnormality can be identified, the cause can be easily removed. In recent years, it is required to output the location of the abnormality and the cause of the abnormality to the outside of the IPM as a signal. Is coming.

Further, if a precursory abnormal phenomenon before a catastrophic abnormality can be detected, it is possible to perform a tripless operation (operation without element shut-off). For this reason, it is required that the cause of the abnormality can be identified. Have been. In the tripless operation, for example, in the case of overheating of the IGBT, a warning (warning) signal is output when the temperature of the IGBT exceeds a slightly lower threshold temperature as a precursory abnormality at a stage before the IGBT becomes fatal. When this warning signal is output, it is realized by controlling the maximum value of the current flowing through the element to a low value or reducing the carrier frequency. Thereby, a temperature rise that would cause a fatal abnormality if left as it is can be suppressed, and the IGBT can be protected from overheating.

However, if the cause of the abnormality is identified by causing each of the various abnormality detection signals of each phase to be output as an alarm in order to know the cause of the abnormality in detail, the number of output terminals of the alarm signal increases, and from the viewpoint of safety, A large number of insulating photocouplers are required, which increases the cost. Further, in order to make the IPM capable of outputting various types of alarm signals according to the cause of the abnormality compatible with the conventional IPM having one type of alarm signal, the system configuration must be changed. There is a problem.

Furthermore, the MOS gate driver circuit described in Japanese Patent No. 2888695 is intended only for detecting an overcurrent flowing through the element and outputting an alarm therefor, and other factors such as abnormalities and precursory abnormalities are taken into consideration. Not.

Therefore, the present invention provides compatibility with a conventional system that does not need to identify the cause of an abnormality, and if there is an external request to identify various abnormal causes such as fatal abnormalities and precursory abnormalities. An object of the present invention is to provide an IPM capable of outputting various causes of abnormalities in response to this. In addition, the present invention outputs an alarm signal when a fatal abnormality occurs and a warning signal when a precursor abnormality occurs from separate output terminals or the same output terminal, respectively, and outputs the logic of these output signals. It is an object of the present invention to provide an IPM in which an abnormal factor can be identified by a combination.

[0011]

SUMMARY OF THE INVENTION In order to solve the above problems, an invention according to claim 1 includes a power semiconductor switching element, driving means for the switching element, a fatal abnormality of the switching element or the driving means, and Abnormality detection means (a drive voltage drop detection circuit, a drive voltage drop warning circuit, an overheat detection circuit, an overheat warning circuit, an overcurrent detection circuit, and the like in each embodiment described later) for detecting a precursory abnormality at the preceding stage; Protection means for performing a protection operation of the switching element when the abnormality is detected by the abnormality detection means (an abnormality detection logic for shutting off the element, an element driving circuit, etc.), and a signal based on the abnormality detection signal from the abnormality detection means to the outside Related to intelligent power modules with abnormal output means (such as transmission circuits) for outputting A. In the invention according to claim 1, the abnormality output means includes an output terminal for outputting an alarm signal when a fatal abnormality is detected by the abnormality detection means, and an abnormality factor including a fatal abnormality and a precursory abnormality. And an output terminal for outputting an abnormal cause identification signal indicating the above.

According to a second aspect of the present invention, in the intelligent power module according to the first aspect, the abnormality factor identification signal is output as a serial signal.

According to a third aspect of the present invention, in the intelligent power module according to the first or second aspect, the output terminal for outputting the alarm signal and the output terminal for outputting the abnormality cause identification signal are the same terminal. There is a feature. As a result, it is possible to output an abnormal cause identification signal as a serial signal following the alarm signal.

The invention described in claim 4 is the first and second inventions.
Alternatively, in the intelligent power module described in 3, the abnormal factor identification signal is output in synchronization with an abnormal factor output request signal input from outside. That is, an abnormality factor identification signal relating to a fatal abnormality and a precursor abnormality is output to the outside using the abnormality factor output request signal as a read clock.

According to a fifth aspect of the present invention, in the intelligent power module according to the fourth aspect, the abnormality factor output request signal has a transmission preparation signal for a predetermined time, and the transmission preparation signal causes the abnormality output means to receive the signal. And updates the abnormal cause identification signal stored in the parallel-in / serial out shift register, and causes the shift register to output the abnormal cause identification signal in response to a read clock following the transmission preparation signal. The data (error cause identification signal) in the internal parallel-in / serial out shift register of the transmission circuit or the like is updated by the transmission preparation signal, and the error cause identification signal is sequentially output as a serial signal by the subsequent read clock.

According to a sixth aspect of the present invention, in the intelligent power module according to the fourth or fifth aspect, when the fatal abnormality occurs, the abnormality output means is provided regardless of the presence or absence of the abnormality factor output request signal. And outputs an alarm signal from the abnormality output means in time synchronism with the abnormality factor output request signal when the precursory abnormality occurs. That is, the alarm signal due to the fatal abnormality is output even when the abnormal factor output request signal is not input, and when the precursor error occurs, the abnormal factor identification signal is output only after the abnormal factor output request signal is input. .

The invention described in claim 7 is based on claim 1,
In the intelligent power module described in 2, 3, 4, 5 or 6, when the catastrophic abnormality occurs, the element is self-cut off via a drive circuit of the semiconductor switching element.

The invention described in claim 8 is the first invention.
In the intelligent power module described in 2, 3, 4, 5, 6, or 7, the semiconductor switching element is configured as a single-phase bridge.

The ninth aspect of the present invention is the first aspect of the present invention.
2. The intelligent power module according to 2, 3, 4, 5, 6, or 7, wherein the semiconductor switching element has a three-phase bridge configuration.

According to a tenth aspect of the present invention, in the intelligent power module according to the eighth or ninth aspect, an abnormality detection signal from the abnormality detection means corresponding to the bridge-configured upper-arm semiconductor switching element is set to a high level. The signal is transmitted to the lower arm via the pressure-resistant level shifter. The abnormality detection signal transmitted to the lower arm side is sent to abnormality output means together with the abnormality detection signal of the lower arm side, and is also used to simultaneously shut off the semiconductor switching element of the lower arm side.

The invention described in claim 11 is the same as the claim 10.
In the intelligent power module described in (1), the high withstand voltage level shifter transmits a plurality of abnormality detection signals in parallel.

The invention described in claim 12 is the same as the claim 10.
In the intelligent power module described in (1), the plurality of abnormality detection signals are encoded by an encoder and transmitted in parallel by the high withstand voltage level shifter.

The invention described in claim 13 is the invention in claim 10
Wherein the plurality of abnormality detection signals are converted into serial signals by a parallel-in / serial-out shift register or the like and serially transmitted to a high voltage level shifter.

According to a fourteenth aspect of the present invention, as in the first aspect, a power semiconductor switching element, a driving means for the switching element, a fatal abnormality of the switching element or the driving means, and a precursor to the preceding stage. Abnormality detection means (a drive voltage drop detection circuit, a drive voltage drop warning circuit, an element overcurrent detection circuit, an overheat detection circuit, an overheat warning circuit, etc. in each embodiment described later), and the abnormality detection means Protection means for performing the protection operation of the switching element when an abnormality is detected (an abnormality detection logic for shutting off the element, an element driving circuit, and the like).
The present invention relates to an intelligent power module including: an abnormality output unit (such as a transmission circuit) for outputting a signal based on an abnormality detection signal from the abnormality detection unit to the outside. In the invention according to claim 14, the abnormality output means outputs an alarm signal when a fatal abnormality is detected by the abnormality detection means, and a precursory abnormality is detected by the abnormality detection means. And a separate output terminal for outputting a warning signal in some cases. With such a configuration, the cause of the abnormality is identified by a combination of the logic of the output signal of each output terminal.

The invention described in claim 15 is the invention according to claim 14
In the intelligent power module described in the above description, the semiconductor switching element is configured as a bridge, and an OR of an abnormality detection signal indicating a fatal abnormality on the upper arm side and an abnormality detection signal indicating a fatal abnormality on the lower arm side is performed. The alarm signal is generated, and the warning signal is generated by ORing the abnormality detection signal indicating the precursory abnormality on the upper arm side and the abnormality detection signal indicating the precursory abnormality on the lower arm side. . An abnormal factor such as a drop in the drive power supply voltage or overheating of the element is identified by a combination of the logics of the alarm signal and the warning signal.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, FIG. 1 is a circuit block diagram showing a first embodiment of the present invention, and the same components as those in FIG. 6 are denoted by the same reference numerals. In addition, in the embodiment shown in FIG. 1 and the subsequent drawings, a portion where a signal transmission path between each block is indicated by a thick arrow indicates that a signal is transmitted in parallel.

In this embodiment, a single control circuit (lower arm control circuit) 91, 92 is provided for each phase. These control circuits 91 and 92 are connected to IGB via high withstand voltage level shifters 71 and 72 composed of high withstand voltage ICs and the like.
A control signal is input to the T drive circuits 32 and 34, and the IGBTs 12 and 14 of the upper arm are turned on and off. The IGBTs 11 and 13 of the lower arm are ON / OFF controlled by inputting a control signal directly from the control circuits 91 and 92 to the IGBT drive circuits 31 and 33.

With the above configuration, the upper arm IGBT 1
A control signal (level shift signal) based on the IGBTs 11 and 13 of the lower arm is transmitted to the IGBTs 2 and 14.
On and off of the switches 12 and 14 are controlled. Normally, this control signal is transmitted as short on-pulses and off-pulses to reduce losses in the level shifters 71 and 72,
SR (set / reset) in level shifters 71 and 72
IGB is re-converted to a state signal by a flip-flop.
The signals are sent to the T drive circuits 32 and 34.

In this embodiment, each of the IGBTs 11 to
As a detection circuit corresponding to 14, in addition to the various detection circuits shown in FIG. 6, a freewheeling diode (FWD)
Overheat detection circuits 414, 424, 434, 444 and drive voltage drop warning circuits 415, 425, 435, 4
45 and IGBT overheat warning circuits 416 and 42
6,436,446. Here, the drive voltage drop warning circuits 415, 425, 435, 445
And IGBT overheating warning circuits 416, 426, 4
36 and 446, when the drive voltage drop or the IGBT temperature reaches a lower threshold value (higher threshold value for drive voltage drop) than when it is determined to be a fatal abnormality, the warning signal is determined as a precursory abnormality. Output.

In this embodiment, the overcurrent detection circuits 411, 421, 431, 441 and the overheat detection circuit 41
2, 422, 432, 442, drive voltage drop detection circuit 4
13, 423, 433, 443, FWD overheat detection circuit 4
The output signals of 14, 424, 434, 444 are called alarm signals, and drive voltage drop warning circuits 415, 42
The output signals of the 5,435,445 and the IGBT overheating warning circuits 416, 426, 436, 446 are called warning signals. Further, both the alarm signal and the warning signal are collectively referred to as an abnormality detection signal.

On the output side of the abnormality detection logics 52 and 54 of the upper arm, high voltage level shifters 81 and 82 composed of high voltage ICs and the like are provided.
1,92. These level shifters 8
Numerals 1 and 82 are for converting the level of the abnormality detection signal on the upper arm side (DC high potential side) into the level on the lower arm side (DC low potential side).

In any of the upper arm and the lower arm, the abnormality detection logics 51 to 54 are connected to the IGBTs 11 to 34 via the drive circuits 31 to 34 only when a fatal abnormality occurs and at least one alarm signal is input. 14 is interrupted for a certain period, and when a warning signal is input, IGB
Do not block T11-14. That is, when an alarm signal is input to the abnormality detection logics 52 and 54 of the upper arm, the IGBT driving circuits 32 and 34 cause the IGBT 1
2, 14 are shut off for a certain period. When an abnormality detection signal (alarm signal or warning signal) is input to the abnormality detection logics 52 and 54, these abnormality detection signals are transmitted to the control circuit 9 via the level shifters 81 and 82.
1, 92 and latched. Control circuits 91, 9
2, when the alarm signal is latched, the level shifter 7
An off signal to the IGBTs 12 and 14 of the upper arm is output to the IGBTs 1 and 72, and thereafter, the upper arm is prohibited from turning on again.

When an alarm signal is input to the abnormality detection logics 51 and 53 due to a fatal abnormality in the lower arm, the IGBT driving circuits 31 and 33 also use the IGBTs.
11 and 13 are cut off for a certain period. When an abnormality detection signal (alarm signal or warning signal) is input to the abnormality detection logics 51 and 53, these abnormality detection signals are transmitted to the control circuits 91 and 92 and latched. Then, when the alarm signal is latched, an off signal of the IGBTs 11 and 13 is output to the IGBT drive circuits 31 and 33, and thereafter, the IGBTs 11 and 13 are prohibited from being turned on again.

The abnormality detection signals latched by the control circuits 91 and 92 are held until reset by a power-on reset signal (not shown) or an external reset signal. Further, when an abnormality factor output request signal from the system side is input from the input terminal 120, the transmission circuit 110 reads an abnormality factor identification signal described later among the abnormality detection signals latched by the control circuits 91 and 92, and
The signal is output from the alarm signal output terminal 130 in synchronization with the abnormal factor output request signal.

Next, FIG. 2 is a timing chart showing the timing of the abnormal factor output request signal and the abnormal factor identification / alarm signal in this embodiment. FIG. 2 (a)
2 is a timing chart of an abnormal factor output request signal input from the input terminal 120 of FIG. 1, and FIG. 2B is an abnormal factor identification / alarm signal output from the output terminal 130 of FIG. 1 and has no alarm signal. FIG. 2C shows a timing chart in the case where there is an alarm signal.

In FIG. 2, the abnormality detection signal to be transmitted to the serial output parallel-in / serial out shift register in the transmission circuit 110 is shifted at the falling edge of the abnormality factor output request signal. At the falling edge, an error detection signal (error factor identification signal) is read from the system. The read signal clock cycle (for example, 1 μs to 1
A transmission preparation signal (start signal) longer than 00 μs) is added, and if the “High” level period continues for a predetermined time (t _d1 : for example, 200 μs), the serial transmission mode is set. The abnormality factor identification signal latched by the control circuits 91 and 92 is read into a shift register in the transmission circuit 110.
As described above, updating the data in the shift register immediately before transmission prevents the occurrence of a bit shift of the serial signal when it is erroneously recognized that there is an abnormal factor output request signal due to noise during a period when there is no abnormal factor output request signal. This is to prevent it.

In FIG. 2, when the falling edge of the abnormal factor output request signal is detected, the data in the parallel-in / serial-out shift register in the transmission circuit 110 is shifted one bit at a time.
0 is sequentially output as an abnormal cause identification signal. On the system side (not shown), the signal at the alarm signal output terminal 130 is read at the rising edge of the error cause output request signal to determine what phase (a fatal error due to an alarm signal or a precursory error due to a warning signal). ) Can be identified.

When all the data of the parallel-in / serial-out shift register is output, or when the abnormal factor output request signal is held at the "Low" level for a predetermined period (t _d2 : for example, 200 μs), the serial transmission mode is set. Is released, and the mode changes to the alarm batch mode. Here, the collective alarm mode is a conventional mode in which one type of alarm signal is output collectively without distinguishing the cause of the abnormality. That is, it can be said that the alarm batch mode is normally set as long as no abnormal factor output request signal is input.

In this alarm batch mode, when there is at least one abnormality detection signal (alarm signal) indicating a fatal abnormality among the latch data of the control circuits 91 and 92 at the alarm signal output terminal 130, a signal of "Low" level is generated. Is output. Example of Fig. 2 (c) (when there is an alarm)
Is a case where an alarm factor occurs before the abnormal factor output request signal is input and the alarm factor continues. That is, an alarm signal indicating a fatal abnormality is output regardless of the presence or absence of an abnormality factor output request signal, and an abnormality factor output request signal is input as an abnormality factor identification signal relating to all abnormality detection signals including an alarm signal and a warning signal. Output for the first time.

In this embodiment, when the abnormal factor output request signal is not input or when this signal does not continue for a certain period of time or more, the same operation as the conventional IPM is performed in the alarm batch mode. When an output request signal is input, an abnormal cause identification signal is also output. For this reason, the output function of the alarm signal can be kept compatible with the conventional IPM, and when the abnormal cause output request signal is input and continues for a certain period of time or longer, the abnormal cause identification signal is set to the system in the serial transmission mode. Can be transmitted to the side. In the present embodiment, the alarm signal output terminal 130 is shared by the output terminal of the alarm signal and the output terminal of the abnormality factor identification signal. However, separate output terminals may be used.

FIG. 3 shows a second embodiment of the present invention. In this embodiment, encoders 141 and 142 are provided between abnormality detection logics 52 and 54 of the upper arm and level shifters 81a and 82a. Figure 1
This is the same configuration as. In this embodiment, the abnormality detection signals from the abnormality detection logics 52 and 54 are
1, 142, which are coded by the level shifters 81a,
The control signal is sent to the control circuits 91 and 92 in parallel from the level shifters 81a and 82a. Although not shown, a decoder is provided in the control circuits 91 and 92 or the transmission circuit 110.

In the embodiment of FIG. 1, the abnormality detection signal for each abnormality factor is sent individually to the level shifters 81 and 82 via the abnormality detection logics 52 and 54, respectively. In this embodiment, various abnormality detection signals are coded by the encoders 141 and 142, sent to the level shifters 81a and 82a, and converted into parallel signals for transmission. Therefore, the level shifter 8
The circuit configurations of 1a and 82a can be simplified as compared with FIG.

Next, FIG. 4 shows a third embodiment of the present invention. In this embodiment, the parallel-in / serial-out shift register 10 is provided between the abnormality detection logics 52 and 54 of the upper arm and the level shifters 81b and 82b.
The configuration is the same as that of FIG. 1 except that 1, 102 are provided. In this embodiment, the abnormality detection signal of the upper arm is subjected to parallel / serial conversion by the shift registers 101 and 102, and is again converted into parallel signals by the serial-in / parallel-out shift registers in the level shifters 81b and 82b. To be latched.

According to the present embodiment, the abnormality detection signal is converted into a serial signal by the parallel-in / serial-out shift registers 101 and 102, and the level shifter 81
By inputting the signals to b and 82b, the configurations of the level shifters 81b and 82b can be simplified as compared with the embodiment of FIG. 1, and this is particularly effective when the number of abnormality detection signals is large. As the shift clock of the abnormality detection signal in the shift registers 101 and 102, an oscillation circuit may be provided in the upper arm and the clock pulse may be used.
The control circuits 91 and 92 generate pulses synchronized with the on-pulses or the off-pulses of the level shifters 2 and 14, and the level shifter 8
The data may be transmitted to the shift registers 101 and 102 via 1b and 82b.

Hereinafter, a case in which the signal is synchronized with the off pulse will be described. Normally, the level shift signal is converted into an ON signal and an OFF signal as shown in FIG. 7 and transmitted to reduce loss, and is converted again into a state signal by a latch. Therefore, as shown in FIG. 8, there is no difference in the re-converted signal unless an off signal (or on signal) comes. Accordingly, as many pulses as the number of abnormality factor identification signals to be transmitted as the OFF signal (four signals in FIG. 8) are transmitted as shown in FIG. 8, and these can be used as shift clocks of the shift registers 101 and 102. In this case, since the timing of the shift clock is clear on the lower arm side, the reading on the lower arm can be facilitated. If an on-pulse arrives during the off-pulse transmission, the off-pulse transmission is stopped and the abnormal cause read signal from the upper arm is invalidated, so that the re-converted signal in the upper arm is kept normal and the erroneous abnormal cause is detected. Can be prevented from occurring. Also in the above case, it is effective to pulse the abnormal cause readout signal from the upper arm to reduce the loss.

As described above, according to the first to third embodiments, the IPM capable of outputting an abnormality factor identification signal as required while maintaining compatibility with a conventional system that outputs only one type of alarm signal. Therefore, when a fatal abnormality or a precursory abnormality occurs, the element or the like can be protected appropriately and promptly in response to the cause of the abnormality. In particular,
By enabling the output of the cause of the precursory abnormality, it is possible to construct a system for preventing operation stoppage as much as possible. Also,
As a secondary effect, by providing the drive voltage lowering warning circuit, it is possible to prevent a malfunction due to a time variation of the power supply voltage or the like, and to shorten a time required for transmitting a level shift signal by a low-pass filter or the like. Furthermore, the power consumption of the level shifter can be reduced by simplifying the configuration of the level shifter.

FIG. 5 shows a fourth embodiment of the present invention. According to the above-described first to third embodiments, it is possible to serially transmit an alarm signal and an abnormal cause identification signal from one alarm signal output terminal 130 of the transmission circuit 110, but a circuit for serially transmitting a signal. Has a complicated configuration, and a circuit for receiving and decoding the serial signal is also complicated, which tends to increase the total cost. Therefore, in the present embodiment, an alarm signal and various warning signals are separated and individually output, and the cause of the abnormality is identified by a combination of the output signals.

That is, in FIG. 5, the same components as those of the first to third embodiments are denoted by the same reference numerals. Although FIG. 5 shows the upper arm and the lower arm for one phase, the same configuration is also applied to the other phase arm. This intelligent power module IPM
In the figure, reference numeral 417 denotes a drive voltage drop detection circuit,
To have the functions of the drive voltage drop detection circuit 413 and the drive voltage drop warning circuit 415 in the third embodiment. Similarly, the drive voltage drop detection circuit 427 is also the drive voltage drop detection circuit 42 in the first to third embodiments.
3 and the function of the drive voltage lowering warning circuit 425. An IGBT overheat detection circuit 418 has both functions of the IGBT overheat detection circuit 412 and the IGBT overheat warning circuit 416 in the first to third embodiments. Similarly, the IGBT overheat detection circuit 428 is also an IGBT overheat detection circuit 422 and an IGBT overheat warning circuit 426 in the first to third embodiments.
It also has the function of.

The OR gate 429 provided on the upper arm has an overcurrent alarm signal from the overcurrent detection circuit 421 of the upper arm and an IGB signal from the IGBT overheat detection circuit 428.
The T overheat alarm signal and the voltage drop alarm signal from the drive voltage drop detection circuit 427 are input, and the output signal is applied to the IGBT drive circuit 32 and is supplied to one of the OR gates 451 via the high voltage level shifter 81c. Input terminal. Similarly, the OR gate 419 provided on the lower arm includes an overcurrent alarm signal from the overcurrent detection circuit 411 of the lower arm, an IGBT overheat alarm signal from the IGBT overheat detection circuit 418, and a drive voltage drop detection circuit 417. And an output signal thereof is applied to the IGBT drive circuit 31 and to the other input terminal of the OR gate 451. Note that the IGBT drive circuit 3
1 and 32 are connected to terminals INN,
A control signal is input via INP.

The voltage drop warning signal output from the upper arm drive voltage drop detection circuit 427 is applied to one input terminal of the OR gate 452 via the level shifter 81c, and is output from the lower arm drive voltage drop detection circuit 417. The low voltage warning signal is supplied to the OR gate 452.
Is applied to the other input terminal. The IGBT overheat warning signal output from the IGBT overheat detection circuit 428 of the upper arm is ORed via the level shifter 81c.
An IGBT overheat warning signal output from one of the input terminals of the gate 453 and output from the IGBT overheat detection circuit 418 of the lower arm is applied to the other input terminal of the OR gate 453.

The output signal of the OR gate 452 is output from the output terminal LVW as a voltage drop warning signal.
The output signal of the R gate 453 is output from the output terminal OHJW as an IGBT overheat warning signal. here,
As described above, the warning signal refers to the drive voltage drop or I
IGBT1 before the overheating of the GBT leads to a fatal abnormality
This signal is transmitted to the outside as a precursory abnormality without interrupting (self-tripping) the signals 1 and 12 to urge the system to stop the operation of the load (such as an AC motor).

As described above, in this embodiment, the output terminal AL
M, LVW, and OHJW output three types of signals (one type of alarm signal and two types of warning signals). Table 1 shows the combinations (eight types) of logic "1" and "0" of each signal. Such failure analysis is performed. Note that the logic "1" indicates that there is an abnormality, and the logic "0" indicates that there is no abnormality.

[0053]

[Table 1]

For example, in Table 1, the logic of the output signal is “1, 0, OHJW” in the order of the output terminals ALM, LVW, and OHJW.
In the case of "1", since the alarm signal and the IGBT overheat warning signal are simultaneously generated, it can be estimated that one of the IGBTs 12 and 11 of the upper arm or the lower arm has self-tripped due to overheating. When the logic of the output signal is “1, 0, 0”, since there is no drive voltage lowering warning signal and IGBT overheating warning signal, the upper arm or lower arm I
It can be estimated that one of the GBTs 12, 11 has self-tripped due to overcurrent. These are all cases in which a fatal abnormality has occurred. With respect to other combinations of logics, it is possible to perform the analysis as described in Table 1 in the same manner. In particular, if the alarm signal is “0” and any of the warning signals is “1”, it is not a fatal abnormality at present, but if it is left unchecked, a precursory abnormal factor leading to a fatal abnormality will occur. Can be estimated,
This is extremely effective in taking protective measures for elements and the like.

According to the fourth embodiment, instead of the method of serially outputting an alarm signal and an abnormal cause identification signal from a single output terminal as in the first to third embodiments,
An alarm signal and a warning signal are output from a plurality of output terminals, respectively, and an abnormal cause can be identified by a combination of their logics. For this reason, the first to first
A circuit configuration for serially outputting signals as in the third embodiment is not required, and appropriate protection measures can be taken at a precursory abnormality stage with a relatively simple circuit configuration. Note that the level shifter 81c and the OR gates 451 to 453 in FIG. 5 are not essential components of the present invention.
That is, an alarm signal, a voltage drop warning signal, and an IGBT overheat warning signal may be generated only by the upper arm or the lower arm, respectively, and failure analysis, that is, identification of an abnormal factor may be performed by a combination of the logic of these signals.

[0056]

As described above, according to the present invention, not only an alarm signal due to a fatal abnormality but also an abnormal factor including a precursory abnormality can be identified as necessary.
Compatibility with conventional systems can be provided, and detailed protection measures can be taken for elements, drive circuits, and the like. Further, since the cause of the abnormality can be identified without providing a large number of output terminals, the number of insulated signal transmission elements such as photocouplers can be reduced, and a low-cost IPM can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional technique.

FIG. 7 is an explanatory diagram of a level shift signal.

FIG. 8 is an explanatory diagram of a level shift signal.

[Explanation of symbols]

11-14 IGBT 21-24 Freewheeling diode 31-34 IGBT drive circuit 51-54 Abnormality detection logic 71,72,81,81a, 81b, 82,82a, 8
2b Level shifter 81c Level shifter 91,92 Control circuit 101,102 Shift register 110 Transmission circuit 120 Error factor output request signal input terminal 130 Alarm signal output terminal 141,142 Encoder 411,421,431,441 Overcurrent detection circuit 412,422,432 , 442 IGBT overheat detection circuit 418, 428 IGBT overheat detection circuit 413, 423, 433, 443 Driving voltage drop detection circuit 417, 427 Driving voltage drop detection circuit 414, 424, 434, 444 Free wheeling diode overheat detection circuit 415, 425 , 435, 445 Drive voltage drop warning circuit 416, 426, 436, 446 IGBT overheat warning circuit 419, 429, 451, 452, 453 OR gate P, N DC input terminal , V AC output terminal

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Naotaka Matsuda 1-1, Tanabe-Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa F-term within Fuji Electric Co., Ltd. 5G053 AA01 AA12 AA14 CA02 DA03 EA01 EB01 5H740 AA08 BA11 BB05 MM01 MM05 MM08 MM11

Claims (15)

[Claims] 1. A power semiconductor switching element, a driving means for the switching element, an abnormality detection means for detecting a fatal abnormality of the switching element or the driving means and a precursory abnormality at a stage preceding the fatal abnormality, and the abnormality detection means An intelligent power module comprising: a protection unit that performs a protection operation of the switching element when an abnormality is detected by the abnormality detection unit; and an abnormality output unit that outputs a signal based on an abnormality detection signal output by the abnormality detection unit. An output terminal for outputting an alarm signal when a fatal abnormality is detected by the abnormality detection means, and an output terminal for outputting an abnormal factor identification signal indicating an abnormal factor including fatal abnormalities and precursory abnormalities. An intelligent power module characterized by the following: 2. The intelligent power module according to claim 1, wherein the abnormality factor identification signal is output as a serial signal. 3. The intelligent power module according to claim 1, wherein an output terminal for outputting the alarm signal and an output terminal for outputting the abnormality cause identification signal are the same terminal. Power module. 4. The intelligent power module according to claim 1, wherein the abnormal factor identification signal is output in synchronization with an external factor output request signal input from outside. Power module. 5. The intelligent power module according to claim 4, wherein the abnormality factor output request signal has a transmission preparation signal for a fixed time, and the transmission preparation signal causes a parallel-in / serial outshift in the abnormality output means. An intelligent power module for updating an abnormal cause identification signal stored in a register and causing the shift register to output an abnormal cause identification signal in response to a read clock following the transmission preparation signal. 6. The intelligent power module according to claim 4, wherein when the fatal abnormality occurs, an alarm signal is output from the abnormality output means regardless of the presence or absence of the abnormality factor output request signal. An intelligent power module, wherein when the precursory abnormality occurs, an abnormality factor identification signal is temporally separated from the abnormality output means and output in synchronization with the abnormality factor output request signal. 7. The intelligent power module according to claim 1, wherein when the fatal abnormality occurs, the semiconductor switching element is shut off by itself. Power module. 8. The method of claim 1, 2, 3, 4, 5, 6, or 7.
2. The intelligent power module according to claim 1, wherein the semiconductor switching element has a single-phase bridge configuration. 9. The method of claim 1, 2, 3, 4, 5, 6, or 7.
2. The intelligent power module according to claim 1, wherein the semiconductor switching element has a three-phase bridge configuration. 10. The intelligent power module according to claim 8, wherein an abnormality detection signal from said abnormality detection means corresponding to a semiconductor switching element of an upper arm in a bridge configuration is transmitted to a lower arm side via a high withstand voltage level shifter. Intelligent power module characterized by transmission to 11. The intelligent power module according to claim 10, wherein the high withstand voltage level shifter transmits a plurality of abnormality detection signals in parallel. 12. The intelligent power module according to claim 10, wherein the plurality of abnormality detection signals are coded and transmitted in parallel by the high withstand voltage level shifter. 13. The intelligent power module according to claim 10, wherein the plurality of abnormality detection signals are converted into serial signals and serially transmitted to a high withstand voltage level shifter. 14. A power semiconductor switching element, driving means for the switching element, abnormality detecting means for detecting a fatal abnormality of the switching element or the driving means and a precursory abnormality at a stage before the abnormality, and abnormality detecting means for the abnormality An intelligent power module comprising: a protection unit that performs a protection operation of the switching element when an abnormality is detected by the abnormality detection unit; and an abnormality output unit that outputs a signal based on an abnormality detection signal output by the abnormality detection unit. An output terminal that outputs an alarm signal when a fatal abnormality is detected by the abnormality detection unit, and a separate output terminal that outputs a warning signal when a precursory abnormality is detected by the abnormality detection unit, Identify the cause of abnormalities by combining the output signals of these output terminals. Intelligent power module. 15. The intelligent power module according to claim 14, wherein the semiconductor switching element has a bridge configuration, and an abnormality detection indicating a fatal abnormality from the abnormality detecting means corresponding to the semiconductor switching element on the upper arm. ORing a signal and an abnormality detection signal indicating a fatal abnormality from the abnormality detection means corresponding to the semiconductor switching element in the lower arm to generate the alarm signal, and generating the alarm signal corresponding to the semiconductor switching element in the upper arm. Generating the warning signal by ORing an abnormality detection signal indicating a precursory abnormality from the detection unit with an abnormality detection signal indicating a precursory abnormality from the abnormality detection unit corresponding to the semiconductor switching element of the lower arm; Intelligent power module.