JP2002076337A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a further microminiaturization by allowing a reduction in an on-resistance of a transistor and an improvement in a breakdown voltage to be compatible. SOLUTION: A semiconductor device having an insulated gate type field effect transistor comprises: a semiconductor substrate having a first conductivity type semiconductor region on its main surface; a gate conductive film formed on a surface of a channel forming region of the main surface via a gate insulating film; a heavily doped source region formed at one end of the gate insulating film, and having a high second conductivity type impurity concentration; a lightly doped drain region formed on another end side opposed to the one end side and having a low second conductivity type impurity concentration; and a heavily doped drain region formed in the first conductivity region of the main surface at the other end side of the gate insulating film, and formed to interpose the lightly doped drain region together with the channel forming region and having a high second conductivity impurity concentration. In this device, the lightly doped drain region has a trapezoidal part protruding in its sectional shape at a position higher than the surface of the channel forming region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a technique effective when applied to a semiconductor device having an offset drain structure.

[0002]

2. Description of the Related Art A power amplification field effect transistor used in a transmission amplifier circuit power supply circuit of a mobile communication terminal device is required to have high efficiency and large power output. Therefore, it is necessary to increase the current and increase the breakdown voltage without increasing the on-resistance. As a method of achieving a large current, a channel width is generally increased in a field-effect transistor. Further, in order to achieve a higher power, a plurality of gate electrodes having, for example, a stripe-shaped gate electrode are provided. An attempt has been made to increase the channel width by connecting field effect transistors in parallel.

On the other hand, in order to increase the breakdown voltage, an offset drain structure in which an offset layer which is a low-concentration drain region is disposed between a channel region below a gate electrode and a high-concentration drain region is used. The technology of the offset drain structure is disclosed in US Pat. No. 4,172,26.
No. 0.

[0004]

However, the present inventors have found that the above structure has the following problems. That is, in the case of an offset drain structure,
Although the drain withstand voltage is improved, there arises a problem that the on-resistance is increased. As a countermeasure, it is conceivable to increase the impurity concentration of the offset drain region even though the drain withstand voltage is somewhat sacrificed.However, the punch-through phenomenon between the source and drain regions, the fluctuation of the threshold voltage, and the standby current ( The so-called short channel effect, which is known as an increase in off-state current, becomes a problem. In particular, with the miniaturization of semiconductor devices, the deterioration of the short channel effect has become severe.

In addition, since the impurity concentration of the offset layer is low, hot carriers are trapped at the interface between the semiconductor substrate and the insulating film in contact with the semiconductor substrate, thereby depleting the offset drain and increasing the on-resistance. Had occurred.

An object of the present invention is to provide a technique which solves such a problem, achieves both a reduction in on-resistance and an improvement in withstand voltage, and enables further miniaturization.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A semiconductor device having an insulated gate field effect transistor, having a first main surface and a second main surface facing each other, wherein the first main surface has a semiconductor region of a first conductivity type. A gate conductive film formed on the surface of the channel forming region on the first main surface via a gate insulating film; and a gate conductive film formed at one end of the gate insulating film in the first conductive type semiconductor region on the first main surface. A high-concentration source region having a high second-conductivity-type impurity concentration and a second-conductivity-type semiconductor region on the first main surface at the other end of the gate conductive film opposite to the one end; A low-concentration drain region having a low type impurity concentration, and a first conductive type semiconductor region formed on the first main surface at the other end opposite to the one end of the gate conductive film; So as to sandwich the lightly doped drain region A high-concentration drain region having a high second-conductivity-type impurity concentration, wherein the low-concentration drain region has a trapezoidal portion whose cross-sectional shape is raised at a position higher than the surface of the channel formation region. .

[0010] The trapezoid of the low concentration drain region is formed of an epitaxial semiconductor layer.

A method of manufacturing a semiconductor device having an insulated gate field effect transistor, the method comprising:
A gate conductive film having a main surface and a second main surface, wherein the first main surface is formed on a surface of the channel formation region of the first main surface of the semiconductor substrate having the semiconductor region of the first conductivity type via a gate insulating film; Forming a low-concentration drain region having a low second-conductivity-type impurity concentration formed in the first-conductivity-type semiconductor region on the first main surface at the other end of the gate conductive film opposite the one end. Forming a semiconductor substrate layer and forming an insulating or low-impurity-concentration epitaxial semiconductor layer by epitaxial growth with the semiconductor substrate layer of the low-concentration drain region as a base; introducing impurities into the epitaxial semiconductor layer; Forming a trapezoidal portion of the low-concentration drain region having a sectional shape raised to a position higher than the surface of the channel forming region; and forming a first trapezoidal portion of the first main surface at one end of the gate insulating film. Forming a high-concentration source region having a high second-conductivity-type impurity concentration formed in an electric-type semiconductor region; and forming a first main surface of the first main surface at the other end opposite to the one end of the gate conductive film. Forming a high-concentration drain region having a high second-conductivity-type impurity concentration formed in the conductive-type semiconductor region and formed so as to sandwich the low-concentration drain region together with the channel formation region.

A step of forming an insulating or low-impurity-concentration epitaxial semiconductor layer by epitaxial growth using a semiconductor substrate as a base; a step of introducing a impurity into the epitaxial semiconductor layer to form a high-impurity-concentration semiconductor region; A step of forming an insulating film covering the epitaxial semiconductor layer, forming an opening in the insulating film to expose the epitaxial semiconductor layer, and embedding a metal serving as a plug connected to the epitaxial semiconductor layer into the opening.

The semiconductor substrate having the opposing first main surface and the second main surface is formed by selective epitaxial growth using the first main surface as a base, so that the cross-sectional shape of the semiconductor substrate rises to a position higher than the main surface of the semiconductor substrate. Forming a low impurity concentration epitaxial semiconductor layer, introducing an impurity into the epitaxial semiconductor layer to form a high impurity concentration trapezoidal portion, forming an insulating film covering the epitaxial semiconductor layer; Forming an opening that exposes the epitaxial semiconductor layer in the film; and embedding a metal that becomes a plug connected to the epitaxial semiconductor layer into the opening.

In the field effect transistor of the present invention, the on-resistance can be reduced by providing the trapezoidal portion protruding from the surface of the channel formation region. Since the portion below the surface of the channel formation region has the same configuration as the conventional one, the breakdown voltage does not decrease. in addition,
Since depletion does not occur due to hot carrier traps, on-resistance is reduced.

That is, carriers passing through the channel formation region under the gate conductive film become hot carriers at the drain end of the gate conductive film, and trap at the interface between the insulating film covering the offset drain region and the drain region. However, since the offset drain has a trapezoidal portion raised from the surface of the channel forming region, hot carriers disappear during traveling in the semiconductor region of the trapezoidal portion, and carrier traps at the interface are prevented. You. As a result, carrier traps are eliminated, so that depletion due to carrier traps in the offset drain region is prevented, and an increase in on-resistance can be prevented.

Further, since the trapezoidal portion of the offset drain region is formed three-dimensionally, the on-resistance can be reduced without increasing the occupied area. In particular, it is suitable as a structure of a miniaturized semiconductor device.

Hereinafter, embodiments of the present invention will be described. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0018]

(Embodiment 1) FIG. 1 is a longitudinal sectional view showing a field effect transistor which is a main part of a semiconductor device according to an embodiment of the present invention.

The field-effect transistor of the present embodiment has an offset drain structure. For example, a low-concentration p-type epitaxial base layer 2 is epitaxially grown on a p-type high-impurity-concentration semiconductor base 1 made of single-crystal silicon. A p-type well 3 is formed on the main surface of the epitaxial base layer 2 using the semiconductor substrate thus formed. The well 3 defines the impurity concentration of the channel formation region and determines the threshold voltage. In addition, the well 3 having a relatively high impurity concentration with respect to the other region of the epitaxial base layer 2 forms a junction with a small area with the drain region, so that the capacity of the drain junction can be reduced. A high impurity concentration n-type source region 4 and an n-type low concentration drain region 5 are formed in a p-type well 3 formed on the main surface on the side of the epitaxial base layer 2, and between the source region 4 and the low concentration drain region 5. A gate conductive film 7 is formed on the channel formation region via a gate insulating film 6. The low-concentration drain region 5 is connected to the high-concentration drain region 8 at a predetermined distance from the end of the gate insulating film 6. The semiconductor substrate used in the present invention is not only a semiconductor substrate such as an epitaxial substrate layer 2 formed on a semiconductor substrate 1, but also a semiconductor substrate alone, and a semiconductor layer formed on a semiconductor substrate via an insulating layer. Various forms such as a substrate (SOI substrate) may be included. An insulating film 15 as an interlayer insulating film made of, for example, a silicon oxide film is formed on the main surface of the semiconductor substrate.

The low-concentration drain region 5 according to the present invention is formed at a position lower than the surface of the channel formation region, similarly to the source region 4, and at a position higher than the surface of the channel formation region. And a trapezoidal part.
The portion higher than the surface of the channel formation region can be formed by removing another portion of the semiconductor substrate, thereby raising a portion that is not removed.

In addition, as shown in FIG. 2, the low-concentration drain region 5 has a portion formed at a position lower than the surface of the channel formation region and a portion of the semiconductor substrate layer 5a higher than the surface of the channel formation region. And an epitaxial layer 5b which is formed to protrude at a position and becomes a trapezoidal portion. The epitaxial layer 5b is formed by selective epitaxial growth using the semiconductor substrate layer 5a as a base, and the impurity concentration of the epitaxial layer 5b is equal to or lower than the impurity concentration of the semiconductor substrate layer 5a.

FIG. 3 shows an impurity profile of the low concentration drain region 5. The vertical axis shows the position in the depth direction of the semiconductor substrate, and the horizontal axis shows the impurity concentration. With the surface of the channel formation region as the boundary surface, the upper side is the epitaxial layer 5
b, the lower side is the semiconductor substrate layer 5a. Before the formation of the epitaxial layer 5b, the semiconductor substrate layer 5a is ion-implanted with a profile indicated by a dashed line, and after the formation of the epitaxial layer 5b, the ion implantation is performed on the epitaxial layer 5b with a profile indicated by a two-dot chain line. As a result, the impurities implanted by the two ion implantations are superimposed to form an impurity profile indicated by a solid line, and a wide and flat impurity profile can be realized as a whole for the low concentration drain region 5. As a result, the drain depletion layer uniformly spreads over the whole, so that the breakdown voltage is improved, and the local concentration of the drain current does not occur, so that the on-resistance is reduced.

The on-resistance can be further reduced by setting the impurity concentration of the epitaxial layer 5b higher than that of the semiconductor substrate layer 5a. Epitaxial layer 5
By setting b to a lower impurity concentration than the semiconductor substrate layer 5a, the capacitance between the gate and the drain can be reduced. In this case, the impurity concentration can be lowered as the distance from the surface of the channel formation region increases.

Further, normally, the side surface of the gate conductive film 7 is covered with the silicon oxide film 9, and in the selective epitaxial growth for forming the epitaxial layer, since there is selectivity on the silicon oxide and the epitaxial layer is not formed,
No epitaxial layer is formed on the silicon oxide film 9 covering the side surface of the gate conductive film 7, and as shown in FIG.
A gap (hereinafter referred to as a facet) is formed between the epitaxial layer 5b and the gate conductive film 7. The formation of this facet allows the epitaxial layer 5
b can be formed in a trapezoidal shape close to the gate conductive film 7 on the surface of the channel formation region and gradually away from the gate conductive film 7 as the height increases from the surface.
Therefore, the capacitance between the gate and the drain can be reduced.

However, if ion implantation is performed while leaving the facet, the impurity concentration of the facet portion becomes higher than that of other portions, and uniformity of the impurity concentration cannot be maintained.
For this reason, as shown in FIG.
It is preferable to perform ion implantation after depositing a thin layer of 0 on the entire surface and filling the facet between the epitaxial layer and the gate electrode.

Here, the operation of the low-concentration drain region 5 of the present invention will be described with reference to FIG. In the low-concentration drain region 5 of the present invention, since a trapezoidal portion is formed so as to protrude from an interface on the surface of the semiconductor substrate to a high position, the low-concentration drain region 5 can be thickened to reduce the resistance. In this case as well, the impurity profile in the portion where the p-type well 3 for determining the drain breakdown voltage and the low-concentration drain region 5 overlap with each other can have the same configuration as before, and thus a high drain breakdown voltage can be maintained. .

In the low-concentration drain region 5 according to the present invention, when hot carriers he- are generated, the hot carriers are trapped at the interface of the surface of the semiconductor substrate where hot carriers have been trapped in the prior art, and in the present invention, at a high position from this interface. Since the trapezoidal portion is formed so as to protrude, the hot carrier h
There is no e- flow trapped and no depletion. The hot carrier h flowing into the trapezoidal portion h
Since e- disappears when it moves about 2 nm and becomes a normal carrier e- and flows into the high-concentration drain region 8, it is trapped at the interface between the trapezoidal portion and the insulating film by forming it to a thickness of at least about 20 nm. Never.

If silicon-germanium is used instead of silicon as the epitaxial layer 5b, the mobility of electrons increases, so that the resistance of the offset portion can be reduced. FIG. 6 is a diagram comparing the energy bands of silicon and silicon-germanium. p
In the case where the silicon and n-type silicon are joined (a),
Although the band gap does not change, when the p-type silicon and the n-type silicon-germanium are joined (b), the band gap is narrowed, so that the carrier concentration increases,
Mobility is improved. FIG. 7 is a diagram showing the mobility of silicon-germanium.
%, And the right end is germanium 100%. It can be seen that the mobility is improved by containing germanium.

This is presumably because in the case of silicon-germanium, stress is generated due to lattice distortion and electron mobility increases, that is, band bending becomes flatter and carrier concentration increases.

FIG. 8 is a plan view of the semiconductor device of the present embodiment. In particular, the layout of the upper metal wiring formed as an external terminal (pad) is shown. In this embodiment, a unit (cell) of a field effect transistor is provided on a semiconductor substrate 100 including a semiconductor substrate 1 and an epitaxial substrate layer 2.
In this example, four T1 to T4 are integrated and connected in parallel. As will be apparent from a sectional structure described later, a pair of transistor cells (T1, T2 or T3, T4) is formed in a transistor forming region (active region) Tr surrounded by an isolation insulating film (field insulating film). ing. A gate conductive layer 7 is formed across the active region.

The gate conductive layer 7 is electrically connected to each other via a through hole CH1 by a first (lower) metal wiring layer M1, and furthermore, a first metal wiring layer M1.
Is electrically connected to the second-layer (upper-layer) metal wiring M2 through the through hole CH2. A gate pad G is formed by the metal wiring M2, and contributes as a connection terminal to the outside. On the other hand, although not shown in FIG. 8, the source semiconductor region formed on the main surface of the semiconductor substrate 100 and the source connection region penetrating to the back surface of the semiconductor substrate 100 are connected to the first layer metal through the through hole CH3. It is electrically connected to the wiring M1. The first metal wiring layer M1 connected to the source region is electrically connected to the source pads S1 and S2 formed by the second metal wiring layer M2 via the through hole CH4. The source pad S2 can be used as a test terminal. As will be apparent from the following description, the external terminal of the source is connected to the back surface of the semiconductor substrate 1 (epitaxial substrate layer 2).
Can be taken out from the side on which the semiconductor substrate 100 is not formed), that is, from the back surface of the semiconductor substrate 100, but may be taken out from the front surface in some applications.

FIG. 9 is a partially enlarged plan view showing a pair of transistor forming regions Tr. The transistor forming region Tr is surrounded by an isolation insulating film 11, and two gate conductive films 7 are provided side by side in a range divided by the two connection conductive regions 12, 12. The epitaxial layer 5a and the high-concentration drain region 8 of the low-concentration drain region 5 are formed in the region sandwiched between the source region 4 and the connection conductive region 12 and the gate conductive film 7.

As described above, two pairs of basic cells having such a pattern are prepared to form a total of four transistor cells. The number of basic cells is not limited to four, but may be many in terms of current capacity. Each source region 4, high-concentration drain region 8, or gate conductive film 7 is connected in parallel by a wiring layer (described in detail later) formed on the semiconductor substrate via an interlayer insulating film, and functions as a single transistor. I do. The ends of the wiring layer are the gate pad G and the drain pad D in FIG. 8, and the source region is connected to the semiconductor substrate facing the main surface on the epitaxial substrate layer side by the connection conductive region 12. A source pad is provided on a metal film (not shown) formed on the entire main surface on the side.

Subsequently, a method of manufacturing the semiconductor device shown in FIG. 2 will be described for each step with reference to FIGS. In addition,
10 to 15, xx orthogonal to the gate conductive film 7 are used.
Cross sections along the lines are shown in FIGS.
Yy parallel to the gate conductive films 7 corresponding to 12 and 14
11, 13, and 15 show cross sections along the line, and FIGS. 16 to 41 show cross sections along the xx line.

First, as shown in FIGS. 10 and 11, the main surface on the side of the epitaxial base layer 2 of the semiconductor substrate obtained by growing the p-type epitaxial base layer 2 on the p + type semiconductor base 1 made of single crystal is subjected to surface oxidation. A silicon oxide film 21 is formed, and is patterned by photolithography on the silicon oxide film 21 to form a resist mask 22 having an opening in a region where the connection conductive region 12 is to be formed.
Boron is ion-implanted at 1.5E16 / cm ² to form a connection conductive region 12 having a p-type high-concentration impurity with a semiconductor containing impurities. The connection conductive region 12 has a width of 2.2.
and the distance between the connection conductive regions 12 is 10.8 μm.
m.

Next, after removing the resist mask 22, as shown in FIGS. 12 and 13, the selective oxidation method (LO
By using COS (LOCal Oxidation of Silicon), selective oxidation is performed on the main surface on the side of the epitaxial base layer 2 using the silicon nitride film 24 as a mask to form the isolation insulating film 11.

Next, as shown in FIGS. 14 and 15, a resist mask 25 patterned by photolithography is formed.
Boron is ion-implanted at 0 KeV and 2.0E13 / cm ² to form a p-type well 3.

Next, as shown in FIG. 16, a gate insulating film 6, a polycrystalline silicon film 7a to be a gate conductive film 7, a tungsten silicide 7b, and a silicon oxide film 9 are sequentially laminated, and as shown in FIG. Patterning is performed by photolithography to form a resist mask 26 covering a region where the gate conductive film 7 is formed, and the polycrystalline silicon film 7a, tungsten silicide 7b, and silicon oxide film 9 are patterned by dry etching using the resist mask 26. Then, as shown in FIG. 18, the gate conductive film 7 is formed to have a gate length of about 0.25 μm.

Next, using the gate conductive film 7 and the silicon oxide film 9 as a mask, 50 KeV, 1.0E13 / c
Implanting phosphorus at m ² , as shown in FIG.
The semiconductor substrate layer 5a of the-type low concentration drain region 5 is formed. Subsequently, as shown in FIG. 20, a silicon oxide film 13 is deposited on the entire surface and patterned by photolithography to form a resist mask 27 having an opening in a region where the low concentration drain region 5a is to be formed. Oxide film 13 and gate insulating film 6 in the region of semiconductor substrate layer 5a by dry etching using
Is removed to expose the semiconductor substrate layer 5a as shown in FIG.

Next, after removing the resist mask 27, an epitaxial layer 5b raised from the semiconductor substrate layer 5a is formed by selective epitaxial growth, as shown in FIG. In the selective epitaxial, since there is selectivity on silicon oxide, the epitaxial layer 5b is not formed on the silicon oxide film 13 covering the side surface of the gate conductive film 7, and a facet is formed between the epitaxial layer 5b and the silicon oxide film 13. it can. Therefore, as shown in FIG. 24, after a silicon oxide film 14 is thinly deposited on the entire surface and facets are buried, as shown in FIG.
The impurity concentration of the low-concentration drain region 5 is made uniform in the depth direction by implanting phosphorus at V, 1.0E13 / cm ² to make the impurity concentration of the epitaxial layer 5b substantially equal to that of the semiconductor substrate layer 5a.

Next, as shown in FIG. 26, patterning is performed by photolithography to form a resist mask 28 having an opening in a region where the source region 4 and the high-concentration drain region 8 are to be formed. Then, arsenic is ion-implanted at 60 KeV and 8.0E15 / cm ² to form the source region 4 and the high-concentration drain region 8. The distance from the end of the gate conductive film 7 to the end of the high-concentration drain region 8 is about 0.7 μm.
0.5 μm from the end of the high concentration drain region 8 to the end of the high concentration drain region 8.
The distance from the end of the gate conductive film 7 to the end of the connection conductive region 12 is about 2.65 μm. Subsequently, the resist mask 28 is removed, and as shown in FIG. 27, patterning is performed by photolithography to form a resist mask 29 in which an area of the connection conductive region 12 is opened.
V, ion implantation of boron fluoride at 2.0E15 / cm ² is performed to form the contact layer 14. The contact layer 14 is formed to reduce the connection resistance of the connection conductive region 12 and to form a diode for ESD protection.

Next, as shown in FIG. 28, the entire surface is formed of a plasma C using the silicon oxide film 15a and TEOS as a source.
Silicon oxide film formed by VD (hereinafter referred to as P-TE
An interlayer insulating film 15 is formed by sequentially laminating an OS film (referred to as an OS film) 15b, and as shown in FIG.
ical polishing) to flatten the interlayer insulating film 15 to about 1 μm.

Next, as shown in FIG. 30, a resist mask 30 is formed by patterning by photolithography to open a region where a contact hole is to be formed. A contact hole having a diameter of about 0.8 μm is formed as shown in FIG. Subsequently, as shown in FIG. 32, tungsten is buried in the contact hole to form a plug 16. 1.0 μm from the end of the gate conductive film 7 to the end of the plug 16 connected to the high-concentration drain region 8.
The distance from the end of the gate conductive film 7 to the end of the plug 16 connected to the source region 4 is about 1.05 μm.

Next, as shown in FIG. 33, an aluminum film 17 'is formed on the entire surface by sputtering, and the photoresist deposited on the entire surface is patterned by photolithography, and as shown in FIG. A resist mask 31 is formed to cover the region where the wiring layer is to be formed, and the aluminum film 17 ′ is patterned by dry etching using the resist mask 31. It is formed to a thickness of about 0.5 μm. The gap between the wiring layers 17 is about 1.5 μm. Each gate conductive layer 7, source region 4, and high-concentration drain region 8 are connected in parallel by the first wiring layer 17.

Next, as shown in FIG.
EOS film 18a, SOG (Spin On Glass) film 18b, P-
An interlayer insulating film 18 in which a TEOS film 18c is sequentially laminated is formed to a thickness of about 1.0 μm, and as shown in FIG. 37, patterning is performed by photolithography to form a resist mask 32 having an opening in a region where a through hole is to be formed. Then, through-holes having a diameter of 1 μm were formed by dry etching using the resist mask 32 as shown in FIG.
Formed to the extent. Subsequently, as shown in FIG. 39, an aluminum film 19 'is formed on the entire surface by sputtering, and the photoresist deposited on the entire surface is patterned by photolithography to form a second wiring layer as shown in FIG. A resist mask 33 covering the region to be formed is formed, and the aluminum film 19 ′ is patterned by dry etching using the resist mask 33, so that the second wiring layer 19 has a thickness of 1.2 μm as shown in FIG. Formed to the extent. The gap between the wiring layers 19 is about 1.2 μm.

Thereafter, the protective insulating film covering the wiring layer 19 is
-A gate pad G and a drain pad D shown in FIG. 8 are formed by forming a TEOS film, a silicon nitride film, or the like, and opening the protective insulating film at an end of the second wiring layer.
The high-concentration drain region 8 is electrically connected to the wiring layer 19 via the plug 16 and the wiring layer 17, and the gate conductive film 7 is similarly connected to the wiring layer 19 via the plug 16 and the wiring layer 17 although not shown in the drawing. Conducted. Source region 4 is plug 1
6, the conductive layer 12 is electrically connected to the connection conductive region 12 via the contact layer 14, and the metal film formed on the entire main surface of the semiconductor substrate 1 connected to the connection conductive region 12 becomes a source pad.

(Embodiment 2) FIG. 42 is a longitudinal sectional view showing a field effect transistor which is a main part of a semiconductor device according to another embodiment of the present invention.

According to the structure of the field effect transistor of the present embodiment, a trapezoidal portion is provided also in the source region of the above-described embodiment, and in addition, a plug 20 which traverses the epitaxial base layer 2 as a connection conductive region is formed. The source region 4 and the semiconductor substrate 1 are electrically connected by the plug 20. Other configurations are substantially the same as those of the transistor of the above-described embodiment.

The field effect transistor according to the present embodiment has an offset drain structure. For example, a semiconductor substrate obtained by epitaxially growing a p-type epitaxial base layer 2 on a p-type high impurity concentration semiconductor base 1 made of single crystal silicon. The n-type source region 4 and the n-type low-concentration drain region 5 having a high impurity concentration are formed in the p-type well 3 formed on the main surface on the side of the epitaxial base layer 2, and the source region 4 and the low-concentration drain region 5 are formed. A gate conductive film 7 in which a polycrystalline silicon film 7a and a tungsten silicide 7b are stacked with a gate insulating film 6 interposed therebetween is formed on the channel formation region therebetween. The low-concentration drain region 5 is connected to the high-concentration drain region 8 at a predetermined distance from the end of the gate insulating film 6. The semiconductor substrate used in the present invention is not only a semiconductor substrate such as an epitaxial substrate layer 2 formed on a semiconductor substrate 1, but also a semiconductor substrate alone, and a semiconductor layer formed on a semiconductor substrate via an insulating layer. Various forms such as a substrate (SOI substrate) may be included.

The low-concentration drain region 5 of the present invention includes a portion formed at a position lower than the surface of the channel formation region,
And a trapezoidal portion formed to protrude above the surface of the channel formation region. The portion higher than the surface of the channel formation region can be formed by removing the other portion of the semiconductor substrate so as to raise a portion that is not removed, but in this embodiment, the low concentration drain region 5 is formed. A semiconductor substrate layer 5a which is formed at a position lower than the surface of the channel formation region, and an epitaxial layer 5b which is formed so as to protrude at a position higher than the surface of the channel formation region and becomes a trapezoidal portion. Can be. The epitaxial layer 5b is formed by selective epitaxial growth using the semiconductor substrate layer 5a as a base, and the impurity concentration of the epitaxial layer 5b depends on the semiconductor substrate layer 5a.
The impurity concentration is equal to or lower than the impurity concentration.

In this embodiment, the source region 4 also
It comprises a portion formed at a position lower than the surface of the channel formation region and a trapezoidal portion formed to protrude at a position higher than the surface of the channel formation region. Source area 4
Is formed of a semiconductor substrate layer 4a which is formed at a position lower than the surface of the channel formation region, and an epitaxial layer 4b which is formed to be raised and formed at a position higher than the surface of the channel formation region and becomes a trapezoidal portion. . The epitaxial layer 4b is formed by selective epitaxial growth using the semiconductor substrate layer 4a as a base. However, since epitaxial growth is difficult with a base having a high impurity concentration, the semiconductor substrate layer 4b is formed.
Is made to have a low impurity concentration, ions are implanted after the epitaxial layer 4b is formed, the semiconductor substrate layer 4a and the epitaxial layer 4b are made to have a high impurity concentration, and the plug 16 is connected.

The on-resistance can be further reduced by changing the impurity profile in the depth direction so that the epitaxial layer 4b of the source region 4 has a higher impurity concentration than the semiconductor substrate layer 4a. By setting the epitaxial layer 4b to have a lower impurity concentration than the semiconductor substrate layer 4a, the capacitance between the gate and the source can be reduced. In this case, the impurity concentration can be lowered as the distance from the surface of the channel formation region increases.

The field effect transistor is covered with an interlayer insulating film 15 formed on the entire main surface on the side of the epitaxial base layer 2, and is provided with a plug 16 made of a metal such as tungsten penetrating the interlayer insulating film 15. Membrane 1
5, the wiring layer 17 is covered with an interlayer insulating film 18 formed on the entire surface, and is connected through a through hole provided in the interlayer insulating film 18. Reference numeral 17 is connected to the second wiring layer 19 formed on the interlayer insulating film 18.

The high-concentration drain region 8 is electrically connected to the wiring layer 19 by the plug 16 and the wiring layer 17, and an end of the wiring layer 19 is a drain pad which is a connection region with the outside. Although not shown in FIG. 42, the gate conductive film 7 is similarly electrically connected to the wiring layer 19 by the plug 16 and the wiring layer 17, and the end of the wiring layer 19 serves as a gate pad.

The source region 4 includes the plug 16 and the wiring layer 1.
The plug 7 is electrically connected to the plug 20, and the plug 20 is connected to the semiconductor substrate 1. The metal film formed on the entire main surface of the semiconductor substrate 1 serves as a source pad.

In the above-described embodiment, the connection conductive region 1
Although a diffusion layer having a high impurity concentration is formed as No. 2, the connection conductive region is the plug 20 using a metal in the field-effect transistor of the present embodiment. Therefore, in the present embodiment, the time required for the impurity implantation and the heat treatment for forming the diffusion layer can be reduced by employing the metal plug 20 formed by the same process as the plug 16. it can. Further, since a metal plug is used, the area required for connection with the semiconductor substrate 1 can be reduced, and the size of the basic cell or the size of the semiconductor chip can be reduced.

In addition, since a mask is not required for forming the epitaxial layers 4b and 5b, the process can be simplified. By using the metal plug 20, the resistance is reduced and the source resistance is reduced.

Further, as shown in FIG. 4, in the selective epitaxial growth for forming the epitaxial layer, the silicon oxide film 9 covering the side surface of the gate conductive film 7 has a selectivity on the silicon oxide and no epitaxial layer is formed. No epitaxial layer is formed and the epitaxial layer 4
The facet is formed between the gate conductive film 7 and the gate conductive film 7 so that the epitaxial layer 4b is close to the gate conductive film 7 on the surface of the channel formation region, and the gate is gradually increased from the surface. It can be formed in a trapezoidal shape away from the conductive film 7. Therefore, the capacitance between the gate and the source or between the gate and the drain can be reduced.

In addition, by utilizing this facet, a p-type pocket which is known as a technique for improving short channel characteristics by forming a region of the opposite conductivity type at the gate side end of a semiconductor region such as a source region is formed. It can be easily formed.

For example, as shown in FIG. 43, in a state where the facets are formed, a silicon oxide film 34 is thinly deposited on the entire surface to such an extent that the facets are not buried, and is patterned by photolithography to form a resist mask 35 having an opening in a predetermined region. Is formed, and a p-type impurity such as boron is ion-implanted using the resist mask 35 to form a p-type pocket 4c at an end of the semiconductor substrate layer 4a of the source region 4 on the gate conductive film 7 side. it can. After the ion implantation for forming the p-type pocket 4c, the facet is buried with an insulating film, and the process proceeds to the subsequent steps.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0062]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, since the low-concentration drain region can be thickened by the trapezoidal portion, there is an effect that on-resistance is reduced. (2) According to the present invention, the impurity profile of the low-concentration drain region below the channel formation region that determines the drain breakdown voltage is the same as before, so that a high value can be maintained without lowering the breakdown voltage. is there. (3) According to the present invention, the distance between the hot carrier generation point and the interface of the insulating film is sufficiently large, so that there is no influence of the hot carriers, and the low concentration drain region is less wrapped under the gate. This has the effect of improving short channel characteristics. That is, since the diffusion depth of the offset drain region can be made shallower, the wraparound of the drain impurity introduction region from the drain side to below the gate conductive layer can be reduced. Therefore, deterioration of the short channel effect can be prevented.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a field effect transistor which is a main part of a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a longitudinal sectional view showing a field effect transistor which is a main part of a semiconductor device according to one embodiment of the present invention.

FIG. 3 is a diagram showing an impurity profile of a low concentration drain region of the semiconductor device according to one embodiment of the present invention;

FIG. 4 is an enlarged partial longitudinal sectional view showing a field-effect transistor which is a main part of the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a diagram illustrating an operation of a low-concentration drain region of the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a diagram for explaining a difference in characteristics between silicon and silicon-germanium.

FIG. 7 is a diagram for explaining a difference in characteristics between silicon and silicon-germanium.

FIG. 8 is a plan view showing an arrangement of a semiconductor device according to an embodiment of the present invention.

FIG. 9 is an enlarged partial plan view showing a transistor formation region in FIG. 8;

FIG. 10 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 11 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 12 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 13 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 14 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 15 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 16 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 17 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 18 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 19 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 20 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 21 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 22 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 23 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 24 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 25 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each step.

FIG. 26 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 27 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 28 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 29 is a longitudinal cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each step.

FIG. 30 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 31 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 32 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 33 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 34 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 35 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 36 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 37 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 38 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 39 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 40 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 41 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 42 is a longitudinal sectional view showing a field effect transistor which is a main part of a semiconductor device according to another embodiment of the present invention.

FIG. 43 is a longitudinal sectional view showing a partially enlarged field-effect transistor as a main part of a semiconductor device according to another embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor base, 2 ... Epitaxial base layer, 3 ... P type well, 4 ... Source region, 5 ... Low concentration drain region, 5
a: semiconductor substrate layer, 5b: epitaxial layer, 6: gate insulating film, 7: gate conductive film, 8: high-concentration drain region, 9, 13, 21, 25, 34: silicon oxide film, 1
0: P-TEOS film, 11: isolation insulating film, 12: connection conductive region, 14: contact layer, 15, 18: interlayer insulating film, 16, 20: plug, 17, 19: wiring layer, 22,
24, 26, 27, 28, 29, 30, 31, 32, 3
3, 35: resist mask; 23: silicon nitride film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shiro Kambara 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Masatoshi Morikawa Gojojosomi, Kodaira-shi, Tokyo No. 20-1 in Hitachi Semiconductor Group, Ltd. (72) Inventor Masahiro Sugaya 5-20-1, Kamisumihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group, 4M104 BB01 BB18 CC01 CC05 DD08 DD16 FF26 FF31 GG09 GG10 GG14 HH20 5F040 DA20 DA22 DB01 EB01 EB02 EC07 EC13 EF09 EF11 EF18 EH02 FA05 FA12 FA16 FC06 FC11 FC21 5F048 AA00 AA01 AA05 AC01 BA05 BA14 BA16 BB05 BB08 BC01 DA03 BC03 BC03 DA03 BC03

Claims (15)

[Claims] 1. A semiconductor device comprising an insulated gate field effect transistor, comprising a first main surface and a second main surface facing each other, wherein the first main surface has a semiconductor region of a first conductivity type. A semiconductor substrate, a gate conductive film formed on a surface of the channel formation region on the first main surface via a gate insulating film, and a first conductive type semiconductor region on the first main surface at one end of the gate insulating film. A high-concentration source region having a high second-conductivity-type impurity concentration, and a first-conductivity-type semiconductor region on the first main surface at the other end opposite to the one end of the gate conductive film; A low-concentration drain region having a low 2-conductivity-type impurity concentration; and a second-conductivity-type drain region formed on the first-conductivity-type semiconductor region on the first main surface at the other end of the gate conductive film opposite to the one end. With the low concentration drain region And a high-concentration drain region having a high impurity concentration of the second conductivity type formed as described above, wherein the low-concentration drain region has a trapezoidal portion whose cross-sectional shape is raised at a position higher than the surface of the channel formation region. A semiconductor device. 2. The trapezoidal portion of the low-concentration drain region comprises an epitaxial semiconductor layer.
3. The semiconductor device according to claim 1. 3. An epitaxial semiconductor layer serving as the trapezoidal portion of the low-concentration drain region has an impurity concentration equal to or lower than that of a base semiconductor substrate on which the epitaxial layer is formed. 13. The semiconductor device according to claim 1. 4. The low-concentration drain region is doped with impurities by a plurality of ion implantations with different implantation energies.
The semiconductor device according to claim 1. 5. The semiconductor substrate according to claim 1, wherein said semiconductor substrate comprises a first conductive type high impurity concentration semiconductor substrate and a first conductive type low impurity concentration epitaxial substrate layer epitaxially grown on an upper surface of said semiconductor substrate. A base layer serving as a first main surface of the semiconductor substrate; the semiconductor base serving as a second main surface of the semiconductor substrate; the high-concentration source region of the second conductivity type penetrating the epitaxial base layer; 5. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected to the second main surface of the semiconductor substrate by a connection conductive region extending to the second surface. 6. 6. The semiconductor device according to claim 5, wherein said connection conductive region comprises a semiconductor region of a first conductivity type having a high impurity concentration. 7. The semiconductor device according to claim 5, wherein said connection conductive region comprises a metal plug. 8. The semiconductor device according to claim 2, wherein the epitaxial semiconductor layer serving as the trapezoid is made of silicon-germanium. 9. The multi-finger transistor formed in the transistor formation region of the first main surface of the semiconductor substrate, wherein the field effect transistor has a gate pad and a drain pad which are external connection regions of the transistor. 9. The semiconductor device according to claim 1, wherein a source pad is formed in another region of the first main surface, and a source pad is formed on the second main surface. 10. A method of manufacturing a semiconductor device having an insulated gate field effect transistor, comprising: a first main surface and a second main surface facing each other, wherein the first main surface is a semiconductor of a first conductivity type. The first region of the semiconductor substrate having a region;
Forming a gate conductive film on the surface of the channel forming region on the main surface with a gate insulating film interposed therebetween; and forming the first conductive type semiconductor on the first main surface at the other end of the gate conductive film opposite to the one end. Forming a semiconductor substrate layer of a low-concentration drain region formed in the region and having a low second conductivity type impurity concentration; Forming a semiconductor layer, introducing an impurity into the epitaxial semiconductor layer, and forming a trapezoidal portion of a low-concentration drain region whose sectional shape is raised at a position higher than the surface of the channel formation region; Forming a high-concentration source region having a high second-conductivity-type impurity concentration formed at one end of the first-conductivity-type semiconductor region on the first main surface; The other end of the gate conductive film opposite to the one end is formed in the first conductivity type semiconductor region on the first main surface, and is formed so as to sandwich the low-concentration drain region together with the channel formation region. Forming a high-concentration drain region having a high impurity concentration of the second conductivity type. 11. The method according to claim 10, wherein a silicon oxide film is formed on a side surface of the gate conductive film before forming the epitaxial semiconductor layer, and a facet is formed between the silicon oxide film and the epitaxial semiconductor layer. 13. The method for manufacturing a semiconductor device according to item 5. 12. The method according to claim 11, wherein said facets are buried with an insulating film. 13. A step of forming an insulating or low-impurity-concentration epitaxial semiconductor layer by epitaxial growth using a semiconductor substrate as a base, and a step of introducing an impurity into the epitaxial semiconductor layer to form a high-impurity-concentration semiconductor region. Forming an insulating film covering the epitaxial semiconductor layer, forming an opening in the insulating film to expose the epitaxial semiconductor layer, and embedding a metal serving as a plug connected to the epitaxial semiconductor layer in the opening. A method for manufacturing a semiconductor device, comprising: 14. An insulating substrate having a cross-sectional shape raised to a position higher than the semiconductor substrate main surface by selective epitaxial growth using the first main surface as a base of a semiconductor substrate having opposing first main surface and second main surface. Forming an epitaxial semiconductor layer having a low or high impurity concentration; introducing impurities into the epitaxial semiconductor layer to form a trapezoidal portion having a high impurity concentration; forming an insulating film covering the epitaxial semiconductor layer; A method for manufacturing a semiconductor device, comprising: a step of forming an opening exposing the epitaxial semiconductor layer in the insulating film; and a step of embedding a metal serving as a plug connected to the epitaxial semiconductor layer in the opening. 15. The method of manufacturing a semiconductor device according to claim 13, wherein a hole for plug embedding is formed in the epitaxial semiconductor layer to embed the metal.