JP2002064944A - Method and apparatus for charging capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the precision of charging a capacitor. SOLUTION: This is a method of charging a load capacitor to a set voltage. The apparatus therefor is provided with an inductance means which is in series with the primary or secondary winding of a transformer connected to the AC side of an inverter circuit, and comprises the leakage inductance of the transformer; and a switching means which is turned on by a charging stop command, short-circuits the output side of the inductance means, and prevents an inertia current by the magnetic energy of the inductance means from flowing in the load capacitor. In this capacitor charging method, an increase in charged voltage of the load capacitor during the delay time td from the charging stop command up to the real charging stop is computed and pre-estimated, and with that in view the charging stop command is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for charging a capacitor using an inverter circuit and inductance means.

[0002]

2. Description of the Related Art In a pulse laser such as an excimer laser, the charge of a capacitor charged to a high voltage of several kV to several tens of kV is discharged to a laser tube at high speed through a magnetic compression circuit or the like to excite laser light. In a pulse laser application device, as the number of times of excitation of laser light, that is, the number of times of repetition of charge / discharge of a capacitor is higher, the performance as a laser device is improved, and in recent years, high repetition of several kHz has become an issue. For this reason, the charging device for the load capacitor also needs to be capable of repeating the high-speed charging operation in which the charging is completed in a few hundred μs or less. Further, in the excimer laser, the output fluctuation of the laser light is detected every time, and the laser light output in the next cycle is controlled. Therefore, it is necessary to control the charging voltage every cycle, and high-speed controllability is also important.

FIG. 6 shows an example of a conventional resonance charging type capacitor charging device. Reference numeral 1 denotes a DC power supply such as a rectifier for rectifying a commercial AC voltage. The output of the DC power supply 1 is supplied to a voltage type bridge inverter circuit 2. The inverter circuit 2 comprises four IGBTs 4A, 4B, 4A, 4B, in which feedback diodes 3A, 3B, 3C, 3D are connected in anti-parallel, respectively.
4C and 4D. The AC side output of the inverter circuit 2 is connected to the primary winding 6A of the high-voltage transformer 6 via the inductance means 5, and becomes an AC high voltage boosted to a predetermined value by the secondary winding 6B. Is converted into a DC high voltage by the high voltage rectifier 7 and supplied to the load capacitor 8. The black dots on the primary winding 6A and the secondary winding 6B indicate the polarity of the winding. The high voltage rectifier 7 has four diodes 7
A bridge rectifier comprising A, 7B, 7C and 7D.
The inductance means 5 also includes the leakage inductance of the high voltage transformer 6.

[0004] Reference numerals 9 and 10 denote charging voltage detecting voltage dividing resistors, which convert the charging voltage Vc of the load capacitor 8 into a detection voltage Vd of several volts, and the detected voltage Vd is input to a voltage comparison circuit 11. Reference numeral 12 denotes a reference voltage source for setting a charging voltage, and has a reference voltage Vr. The voltage comparison circuit 11 compares the detection voltage Vd with the reference voltage Vr, and outputs an H-level comparison signal Vh until the detection voltage Vd reaches the reference voltage Vr.
When the reference voltage Vr is reached, an L-level comparison signal Vh signal is output. The voltage comparison circuit 11 is provided with a hysteresis of about 0.1% of the charging voltage so as not to oscillate at the switching point of the output signal Vh. Reference numeral 13 denotes an inverter control circuit, which outputs signals of two opposite phases, A-phase and B-phase, to AND gates 14 and 1
5, one turns on a pair of IGBTs 4A and 4D, and the other turns on a pair of IGBTs 4B and 4C alternately. In FIG. 6, a gate signal system of a pair of IGBTs is shared to show a signal path. However, in practice, each gate signal system of the IGBT is insulated and separated.

[0005] The inductance means 5 including the leakage inductance of the high-voltage transformer 6, the high-voltage rectifier circuit 7, and the load capacitor 8 constitute a half-wave series resonance circuit. Here, the inductance means 5 usually includes a leakage inductance of the high-voltage transformer 6 and an inductor having an appropriate inductance. The high voltage transformer 6 alone may be used. When a pair of IGBTs of the inverter circuit 2 are turned on in this resonance half cycle, the load capacitor 8 is charged resonantly toward a voltage that is approximately twice the value obtained by multiplying the DC power supply voltage by the transformation ratio of the high-voltage transformer 6. You.

Next, the operation will be described with reference to FIG.
FIG. 7A shows the current IL of the inductance means 5,
The current IL is composed of the IGBTs 4A to 4D and the anti-parallel diode 3A.
3D equal to the combined current of the
The currents of A to 3D are indicated by oblique lines. (2) is the load capacitor 8
Is the gate signal VgA of the IGBT 4A or 4D and the gate signal Vg of the IGBT 4B or 4C.
B is shown. If the load capacitor 8 is discharged at time t0, the detection voltage Vd is lower than the reference voltage Vr, the voltage comparison circuit 11 outputs an H signal, and the signal on the A-phase side of the control circuit 13 Pass through, inverter circuit 2
A pair of IGBTs 4A and 4D on the diagonal line are turned on.
By this turning on, the DC power supply voltage is applied to the resonance circuit, the resonance current IL flows through the inductance means 5, and the charging voltage Vc of the load capacitor 8 rises as shown in the figure. Time t
When 1, the charging voltage Vc of the load capacitor is set to 10 k.
When the voltage reaches V, the voltage comparison circuit 11 outputs an L-level comparison signal Vh, and the AND circuit 14 blocks the gate signal to turn off the pair of IGBTs 4A and 4D. However, the electromagnetic energy due to the current IL that has been flowing in the circuit up to that point is stored in the inductance means 5, and the inertial current due to this electromagnetic energy, that is, the feedback current, is indicated by the hatched portion in FIG.

This feedback current is supplied to the inductance unit 5
Right terminal → black point terminal of primary winding 6A of high voltage transformer 6 →
Black point terminal of secondary winding 6B of high voltage transformer 6 → diode 7A → load capacitor 8 → diode 7D → non-spot terminal of secondary winding 6B of high voltage transformer 6 → 1 of high voltage transformer 6
The non-spot terminal of the next winding 6A → the feedback diode 3A → from the positive electrode to the negative electrode of the DC power supply 1 → the feedback diode 3D → returns to the DC power supply 1 while charging the load capacitor 8 through the path of the left terminal of the inductance means 5. The load capacitor 8 is charged by the inertial current, and the charging voltage Vc exceeds the set voltage of 10 kV, and is overcharged by ΔV as shown in FIG.

After the load capacitor 8 is discharged to a load (not shown) at time t2, the inverter control circuit 13
Generates a B-phase signal, the IGBTs 3B and 3C on the opposite diagonal lines are turned on through the AND gate 15, and a current IL flows through the inductance means 8 and the transformer 6 in the opposite direction. The current of the secondary winding 6B of the transformer 6 is rectified and charges the load capacitor 8 again. When the inverter circuit 2 is turned on for one cycle, the load capacitor 8 is charged twice. The advantage of this bridge inverter type resonant charging is that the switching frequency of the IGBT may be １ ／ of the charging frequency of the load capacitor 8, and the switching frequency of 2 kHz is sufficient for 4 kHz repetition of, for example, an excimer laser. You can do less.

However, there is a problem, and a drawback of the conventional device is that even if the IGBT is turned off, the magnetic energy due to the current flowing through the inductance means 5 at that time becomes an inertial current and the load capacitor 8 is charged. IGB
Feedback diodes 3A to 3D connected in anti-parallel to T
Through the load capacitor 8
Is overcharged. Although not shown here, a resonance capacitor is connected in series with the inductance means, and even in a series resonance inverter that drives the IGBT at a frequency related to the resonance frequency, when the IGBT is turned off at a set value of the charging voltage, Load capacitor 8 by inertia current due to residual electromagnetic energy of inductance means
Overcharge occurs. That is, the capacitor charging device using the voltage type inverter using the inductance means on the AC side has a problem that the charging is continued by the inertial current and the load capacitor 8 is overcharged even if the IGBT of the inverter circuit is turned off. FIG. 8 shows this example. Even though the comparison signal Vh of the voltage comparison circuit 11 becomes L and the inverter circuit 2 is turned off, the charging voltage Vc of the load capacitor 8 becomes ΔV due to the inertial current of the inductance means 5. You can see that only overcharging is done.

In order to solve such a conventional problem, the present inventor disclosed in Japanese Patent Application No. 2000-193630 that, when the load capacitor was charged to a set voltage, it turned on to load the inertial current by the inductance means. It has been proposed that switch means be provided on the secondary side of the transformer to prevent charging by bypassing the capacitor, thereby preventing the load capacitor from being overcharged.

[0011]

[Problems to be Solved by the Invention]
Even in the invention according to the application of Japanese Patent Application No. 0-193630, the switch means and its driving circuit are not ideal in practice, and the operation delay time of the comparison circuit for comparing the charging voltage of the load capacitor with the reference voltage. There is a delay in the operation of the switch means itself and a delay time in the drive circuit. Since the total of these is about several hundred ns, the charging current continues to flow through the load capacitor during this operation delay time, and is very small. Is overcharged. In a charger such as an excimer laser, a voltage stability of about 0.1% is required, and this minute overcharging poses a problem. If the overcharge amount is constant, the control circuit may perform control in anticipation thereof, but the overcharge amount during the delay time is not constant due to the following reasons.

(1) Fluctuation of power supply voltage: Even if the delay time is constant, the fluctuation rate of the power supply voltage changes the rising speed of the charging voltage, and the overcharge amount changes. (2) Residual voltage of load capacitor and its fluctuation; after the load capacitor discharges to an excimer laser load, etc., there is a feedback current from the load side, the load capacitor is charged to a low voltage, and the residual voltage of the next charging cycle Becomes Particularly in the case of resonance charging, the magnitude of the resonance current changes depending on the difference between the power supply voltage and the initial voltage of the load capacitor. Therefore, even if the operation delay time is anticipated, the voltage accuracy is reduced due to the residual voltage of the load capacitor. (3) Other changes in the resistance value due to the temperature of the high-voltage transformer winding; at the start of operation of the charger and after several hours of operation, the temperature of the high-voltage transformer and the like rises, and the winding resistance changes.
Since the change in resistance in the resonance circuit changes the rate of rise of the charging voltage, the voltage stability is reduced even when the operation delay time is considered.

As a solution to this problem, a method is also conceivable in which data such as the amount of overcharge after the inverter circuit is turned off, the fluctuation of the power supply voltage, the residual voltage of the load capacitor, and the like are previously taken into the CPU, and the final charge voltage is predicted and controlled. Since high speed is required and the number of data is large, it is complicated and the stability is hardly obtained. According to the above-mentioned proposed invention, the amount of overcharge of the load capacitor after the inverter circuit is turned off can be minimized, so that the stability is greatly improved, but not completely due to the delay time of the bypass switch and its drive circuit. .

Therefore, the present invention takes into account the operation delay of the bypass switch means itself and the operation delay of its drive circuit, and provides a charging method having a capacitor charging accuracy that can be sufficiently satisfied even when an excimer laser is used as a load. And an apparatus.

[0015]

According to a first aspect of the present invention, there is provided a DC input terminal, an inverter circuit connected to the DC input terminal, and an AC circuit connected to the AC side of the inverter circuit. A transformer, inductance means in series with the primary or secondary winding of the transformer and including a leakage inductance of the transformer, and a load capacitor connected to a secondary side of the transformer and serving as a load A rectifier for supplying charging power to the transformer, and a rectifier provided on the secondary side of the transformer, which is turned on by a charge stop command to short-circuit the output side of the inductance means, and inertial current due to magnetic energy of the inductance means is supplied to the load capacitor. A switch means for preventing the current from flowing to the load capacitor, and charging the load capacitor to a set voltage. And calculating and estimating the charge voltage rise vc of the load capacitor during the operation delay time td associated with the switch means, and generating the charge stop command in anticipation thereof. I do.

According to a second aspect of the present invention, in order to solve the above-mentioned problem, in the first aspect, the charging voltage detection signal Vd of the load capacitor, the reference voltage Vr, and the operation delay time td are expressed by an equation (Vd + td · dVd / dt = Vr) ), And
A capacitor charging method is provided wherein a charge stop command is issued to turn on the switch means when this equation is satisfied.

According to another aspect of the present invention, a DC input terminal, an inverter circuit connected to the DC input terminal, a transformer connected to an AC side of the inverter circuit, Supplying charging power to inductance means including a leakage inductance of the transformer in series with a primary winding or a secondary winding of a transformer, and a load capacitor connected to a secondary side of the transformer and serving as a load. Rectifier, and switch means provided on the secondary side of the transformer, and when turned on, short-circuits the output side of the inductance means to prevent an inertial current due to magnetic energy of the inductance means from flowing to the load capacitor. With
Calculate the charge voltage rise vc of the load capacitor in the delay time from the generation of the ON signal from the pulse generation circuit to the stop of charging due to the turning on of the switch means, and calculate the charge stop command signal in anticipation of the charge voltage rise vc. There is provided a capacitor charging device comprising an arithmetic circuit for sending the pulse to the pulse generation circuit.

According to a fourth aspect of the present invention, a DC input terminal, an inverter circuit connected to the DC input terminal, a transformer connected to the AC side of the inverter circuit, Supplying charging power to inductance means including a leakage inductance of the transformer in series with a primary winding or a secondary winding of a transformer, and a load capacitor connected to a secondary side of the transformer and serving as a load. Rectifier, and switch means provided on the secondary side of the transformer, and when turned on, short-circuits the output side of the inductance means to prevent an inertial current due to magnetic energy of the inductance means from flowing to the load capacitor. The charge voltage detection signal Vd of the load capacitor, the set voltage signal Vr, and the operation delay time td are calculated by the equation (Vd + td · d).
Vd / dt = Vr), and a capacitor charging device comprising: an analog or digital arithmetic circuit that supplies a charge stop command signal to the pulse generation circuit when the above equation is satisfied.

[0019]

Embodiments and Examples of the Invention A resonance charging type capacitor charging apparatus according to an embodiment of the present invention will be described with reference to FIG. 6, the same symbols as those in FIG. 6 indicate corresponding members. In this embodiment, two diodes 16, across the secondary winding of the high-voltage transformer 6 of the capacitor charging device,
The cathodes of the high voltage rectifier 7 are connected in series with each other, and the short-circuiting switch means 18 is connected between the series point and the negative DC terminal of the high voltage rectifier 7. The charging voltage detection signal Vd is branched to a differentiating circuit 19 for calculating a voltage rise rate dVd / dt, and a differential signal (dVd / d) which is an output of the differentiating circuit 19 is obtained.
t) is applied to multiplier 20. The multiplier 20 multiplies the differential signal (dVd / dt) by the operation delay time td related to the switch means 18 and outputs an output signal (td × dVd / dt).
Is input to the adder 21.

Here, (td × dVd / dt) indicates a voltage increase vc of the charging voltage Vc of the load capacitor 8 at the operation delay time td associated with the switch means 18, and the multiplier 20 adds a resistance to the voltage increase vc. A signal vd obtained by multiplying the division ratios of 9 and 10 is output. This signal vd is
The adder 21 adds the charge voltage detection signal Vd to the charge voltage detection signal Vd, and the adder 21 outputs a predicted charge voltage signal Vd ′ = (Vd + vd). The predicted charging voltage signal Vd ′ is a charging voltage predicted after an operation delay time td related to the switch unit 18.
This predicted charging voltage signal Vd 'is compared with the reference voltage Vr of the reference voltage source 12 by the voltage comparison circuit 11, and when Vd'> Vr, the voltage comparison circuit 11 outputs the low level L comparison signal Vh.
Is output. When Vd ′ <Vr, the voltage comparison circuit 11 outputs a high-level H comparison signal Vh to turn on the inverter circuit 2 and turn off the switch means 18.

A pulse generation circuit 22 is connected to the output of the voltage comparison circuit 11, and when the comparison signal Vh becomes L, the pulse generation circuit 22 supplies a pulse of a predetermined width to the control electrode of the switch means 18. As the switch means 18,
Various semiconductor switches such as FETs, IGBTs, IEGTs, thyristors and the like can be used, and in particular, semiconductor devices without a positive turn-off function such as a silicon controlled rectifier (SCR) can be used for the reasons described later. When the charging voltage is as high as several kV and exceeds the withstand voltage of a normal semiconductor device, the required number of switch means 18 are connected in series. The circuit and the driving method of the series connection are not the gist of the present invention and are conventional techniques, and therefore will not be described in detail. The pulse width of the pulse generation circuit 22 may be continued until the switch unit 18 is turned on next time.

Next, the operation of this embodiment will be further described with reference to FIGS. FIG. 2 shows an entire charging cycle, and FIG. 3 shows an enlarged final period of charging. 2 and 3, (1) is the comparison signal Vh of the voltage comparison circuit 11, (2) is the charging current ic of the load capacitor 8 and the current Is of the switch means 18, (3) is the charging voltage Vc of the load capacitor 8,
(4) shows the charging voltage detection voltage Vd and the predicted charging voltage signal V
d ′.

Now, at time t0 in FIG.
Shall start charging. When the predicted charging voltage signal Vd ′, which is the sum of the charging voltage detection voltage Vd and the voltage vd corresponding to the voltage rise vc of the charging voltage Vc of the load capacitor 8, is lower than the reference voltage Vr, the voltage comparison circuit 11 compares H. A signal Vh is output, and a signal on the A-phase side of the inverter control circuit 13 passes through the AND circuit 14 to turn on a pair of IGBTs 4A and 4D on the diagonal line of the inverter circuit 2. With this on, a DC power supply voltage is applied to the resonance circuit, and a current due to resonance flows, and the charging voltage Vc of the load capacitor 8 is increased.
Rise toward the target voltage of 10 kV as shown in FIG. At this time, since the comparison signal Vh is H, the pulse generation circuit 22 does not output an ON signal, and the switch means 18 is OFF. In addition, the charging voltage detection signal Vd and the predicted charging voltage signal Vd ′ increase by the difference of the voltage vd as shown in FIG.

In FIG. 3, when the charging voltage Vc of the load capacitor 8 is just before the target value of 10 kV at time t1 and the predicted charging voltage signal Vd ′ that is higher than the charging voltage detection voltage Vd by the voltage vd exceeds the reference voltage Vr. , Voltage comparison circuit 1
The comparison signal Vh of 1 becomes L, and the AND circuit 14 blocks the gate signal from being sent to the pair of IGBTs 4A and 4D and turns off. At the same time, when the comparison signal Vh changes from H to L, the pulse generation circuit 22 is triggered, and a pulse is given to the control electrode of the switch means 18 to turn it on, whereby the secondary winding of the high-voltage transformer 6 is turned on. Short the sides. The charging voltage Vc of the load capacitor 8 increases during the operation delay time td from time t1 to time t2 when the secondary side of the high-voltage transformer 6 is completely short-circuited. Here, the time from the time t1 to the time t2 indicates a time corresponding to the operation delay of the switch means 18 itself and the operation delay time of the drive circuit. Further, since the increase vc of the charging voltage Vc is calculated in advance, the final charging voltage is very close to the target voltage 10 kV. In this operation, high voltage stability can be obtained because the voltage rise rate is sequentially calculated even if there is a power supply voltage fluctuation, a residual voltage fluctuation, a change in winding resistance, etc. in each charging cycle. In other words, the charge voltage increase vc of the load capacitor 8 during the operation delay time td from the generation of the charge stop command to the actual stop of the charge is calculated and predicted, and the charge stop command is generated in anticipation of this. Can be charged with very high accuracy.

FIG. 4 shows an embodiment in which an arithmetic circuit is constituted by an analog circuit. This circuit calculates a voltage rise rate from the charge voltage detection voltage Vd of the load capacitor 8 to calculate a predicted charge voltage signal Vd ′. That is, Vd '= Vd + t
An analog circuit that calculates d × (dVd / dt) is realized. The charging voltage detection voltage Vd is input to a point a of the non-inverting terminal of the operational amplifier 23. The output point b of the operational amplifier 23 is connected to the capacitor 24 through the resistor 24. A connection point c between the resistor 24 and the capacitor 25 is connected to the inverting terminal of the operational amplifier 23. The output point b of the operational amplifier 23 is also connected to the voltage comparison circuit 11 and is compared with the reference voltage Vr.

Next, the operation of this circuit will be described. The charging voltage detection voltage Vd is input to the non-inverting terminal of the operational amplifier 23, and the connection point c between the resistor 24 and the capacitor 25 is connected to the inverting terminal and is fed back. The voltage at the point acts as a simple buffer and charges the capacitor 25 to keep it equal to the charging voltage detection voltage Vd. Therefore, the capacitor 2 is connected to the resistor 24 having the resistance value R.
5, a charging current i flows. Therefore, the voltage Vb at point b
Is higher than the charging voltage detection voltage Vd at the point c by the voltage drop of the resistor 24, and Vb = Vd + ic × R. Here, assuming that the capacitance of the capacitor 25 is Cd, i = Cd × (dV
d / dt), Vb = Vd + Cd × R × (dV
d / dt). Here, if Cd × R = td, Vb = Vd + td × (dVd / dt). That is, Vb = Vd ′ = Vd + td × (dVd / dt) is calculated.

Next, a specific design example will be described. From the above equation, the capacitance Cd of the capacitor 25 is Cd = i
/ (DVd / dt), the output current i of the operational amplifier 23 is set to 10 mA based on the current capability of the operational amplifier 23, the charging time is 100 μs, and the charging voltage detection voltage Vd corresponding to the set charging voltage 10 kV of the load capacitor 8 is calculated. Assuming 10 V, dVd / dt becomes 100 kV / s. Therefore, the capacitance Cd of the capacitor 25 is 100 nF. That is, Cd = 100 nF. Further, the resistance value R of the resistor 24 is 10 ohms from Cd × R = td if the operation delay time td is set to 1 μs for easy calculation.
From these numerical values, the predicted charging voltage signal Vd 'is calculated. This predicted charging voltage signal Vd ′ is
And compared with the reference voltage Vr.

FIG. 5 shows the charging voltage V of the load capacitor 8.
This is another embodiment in which the voltage rise rate of c is detected and calculated by the following equation. The charging voltage Vc ′ after the time delay td of the charging voltage Vc of the load capacitor 8 is Vc ′ = Vc + td (dVc / d
t) = Vc + td (i / C), and the load capacitor 8
Is detected and divided by the capacitance C of the load capacitor, the rate of voltage rise is determined. Reference numeral 25 denotes a buffer operational amplifier that receives the charge voltage detection voltage Vd of the load capacitor 8 at a non-inverting terminal. The output of the operational amplifier 26 is a resistor 2
7 and is input to the voltage comparison circuit 11. Note that 28
Is a current transformer for detecting the charging current ic. The primary winding of the current transformer 28 has one turn, and the secondary winding has m turns. The black dots indicate the polarity of the winding. The detected current is resistance 2
7 and converted into a voltage (ic × R / m) of the indicated polarity. The condition that satisfies the above equation in this circuit will be described.
Charge voltage detection resistors 9 (resistance value R1) and 10 (resistance value R
If the voltage division ratio [R2 / (R1 + R2)] of 2) is 1 / n, the charging voltage Vc is detected as 1 / n. Therefore, both sides of the above equation are divided by n, and Vc '/ n = Vc / n + td ( ic /
C) / n. Since the detection voltage of the charging voltage Vc is Vd, the detection voltage Vd ′ after the time delay td is Vd ′ = V
d + td (ic / C) / n. Where ic × R /
If m = td (ic / C) / n, the resistance value R of the resistor 27 is R = (td × m) / (C × n). If this equation is satisfied, this conversion voltage (ic × R /
m) is added to the charging voltage detection voltage Vd, and the predicted charging voltage signal Vd ′ is added to the input of the voltage comparison circuit 11.

Specifically, td = 1 μs, n = 100
If 0, m = 100 and C = 50 nF, the resistance value R becomes 2Ω from the above equation. Therefore, the resistance value R of the resistor 27
Is set to 2Ω, the comparison circuit 11 supplies the predicted charging voltage signal V
d ′ is added, and predictive charging voltage control can be performed. The detection of the charging current ic is also possible with Hall CT. Also, even if the voltage of the resistor 27 is added to the reference voltage Vr of the reference voltage source 12 with the opposite polarity, the condition of the output change of the comparison circuit 11 is the same, and the predicted charging voltage control can be similarly performed. In short, if the expression Vd + td.dVd / dt = Vr is satisfied, the load capacitor 8 can be charged with very high accuracy.

The above embodiments are all configured by analog circuits, but can also be processed by digital operations. For example, the voltage rise rate can be easily calculated by holding the sampling value for each clock frequency and calculating the difference from the sampling value of the immediately preceding clock.

According to the present invention, the addition of the switch means makes it possible to easily calculate the amount of overcharge caused by the inertial current due to the inductance of the circuit. Since the voltage rise rate, which incorporates all factors such as voltage, is used as the calculation parameter, the charge voltage can be predicted and controlled easily and accurately, and the stability of the capacitor charge voltage of the excimer laser power supply can be extremely high. it can.

Incidentally, the connection of the switch means is not limited to the above-described embodiment, and specifically, is disclosed in Japanese Patent Application No. 200-200.
See the application specification No. 0-193630. In any case, the switch means is provided on the secondary side of the transformer,
What is necessary is just to be connected to a place where the energy from the secondary winding of the transformer can be selectively bypassed to the load capacitor.

[0033]

As described above, according to the present invention, the operation delay of the bypass switch means itself and the operation delay of the drive circuit are taken into consideration, and the load is controlled by the inertia current due to the inductance of the circuit during the operation delay time. By turning on the switch so that the capacitor is not charged, it is possible to achieve a sufficiently satisfactory capacitor charging accuracy even when an excimer laser is used as a load.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of a capacitor charging device according to the present invention.

FIG. 2 shows current and voltage waveforms for explaining the operation of FIG.

FIG. 3 shows current and voltage waveforms at the end of charging for explaining the operation of FIG.

FIG. 4 shows an embodiment of an arithmetic circuit of the capacitor charging device of the present invention.

FIG. 5 shows a second embodiment of the arithmetic circuit of the capacitor charging device of the present invention.

FIG. 6 is a diagram showing an example of a conventional capacitor charging device.

FIG. 7 shows current and voltage waveforms for explaining the operation of FIG.

8 shows current and voltage waveforms for explaining the operation of FIG.

[Explanation of symbols]

1 DC power supply 2 Inverter circuit 3A-3D feedback diode 4A-4D switching semiconductor element 5 inductance means 6 high voltage transformer 7 rectifier 8 load capacitor 9, 10 ..Resistance for voltage detection 11..comparative circuit 12..reference voltage source 13..inverter control circuit 14,15..AND circuit 16,17 ..
Diode 18. Switch means 19 Differentiator circuit 20 Multiplier circuit 21 Addition circuit 22 Pulse generation circuit 23 Operational amplifier 26 Operational amplifier for buffer 28 Current transformer

Claims (4)

[Claims] 1. A DC input terminal, an inverter circuit connected to the DC input terminal, a transformer connected to an AC side of the inverter circuit, and a primary winding or a secondary winding of the transformer. Inductance means including a leakage inductance of the transformer in series, a rectifier connected to a secondary side of the transformer and supplying a charging current to a load capacitor serving as a load, and a rectifier provided on the secondary side of the transformer. Switch means for turning on the load capacitor in response to a charge stop command and short-circuiting the output side of the inductance means to prevent the inertial current due to the magnetic energy of the inductance means from flowing to the load capacitor. A charging method, wherein the charging voltage of the load capacitor is reduced during an operation delay time td from the generation of the charging stop command to the actual stopping of charging. Predicts a minute calculated, capacitor charging method characterized by generating said charging stop command expects it. 2. The method according to claim 1, wherein the charge voltage detection signal Vd of the load capacitor, the reference voltage Vr, and the operation delay time td are expressed by an equation (Vd + td · dVd /
dt = Vr), and when this equation is satisfied, a charge stop command is issued to turn on the switch means. 3. A DC input terminal, an inverter circuit connected to the DC input terminal, a transformer connected to the AC side of the inverter circuit, and a primary winding or a secondary winding of the transformer. Inductance means including a leakage inductance of the transformer in series, a rectifier connected to a secondary side of the transformer to supply a charging current to a load capacitor serving as a load, and a rectifier connected to a secondary side of the transformer. Switch means for short-circuiting the output side of the inductance means when turned on to prevent an inertial current due to magnetic energy of the inductance means from flowing to the load capacitor, and generating an on signal from the pulse generation circuit. To calculate the rise in the charge voltage of the load capacitor during the operation delay time from when the switch means is turned on until the charge is stopped, and calculate the rise in the charge voltage. A capacitor charging device comprising an arithmetic circuit for sending a charge stop command signal to the pulse generation circuit in anticipation of a delay. 4. A DC input terminal, an inverter circuit connected to the DC input terminal, a transformer connected to the AC side of the inverter circuit, and a primary winding or a secondary winding of the transformer. An inductance means in series with a leakage inductance of the transformer, a rectifier connected to a secondary side of the transformer to supply charging power to a load capacitor serving as a load, and a rectifier connected to a secondary side of the transformer. Switch means for short-circuiting the output side of the inductance means when turned on to prevent an inertial current due to magnetic energy of the inductance means from flowing to the load capacitor, and a charge voltage detection signal Vd of the load capacitor. , A reference voltage Vr, and an operation delay time t associated with the switch means.
and d) performing an arithmetic operation on d in accordance with an equation (Vd + td.dVd / dt = Vr), and providing an analog or digital arithmetic circuit for providing a charge stop command signal to the pulse generation circuit when the equation is satisfied. apparatus.