JP2002057552A - Group delay generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a group delay generating circuit capable of generating satisfactory peaking characteristics and controlling a peaking quantity thereof without deteriorating the input/output matching characteristics of the group delay generating circuit. SOLUTION: This circuit is provided with an FET source ground amplifier 1 provided with a bipolar transistor or FET connecting a base or gate to an input terminal and connecting an emitter or source to a constant potential point, a variable inductor circuit 4 connecting one terminal to the collector side or drain side of the transistor and connecting the other terminal to the bias power source of the transistor, a variable capacitor circuit 2 connecting one terminal to the collector or drain of the transistor, and a variable resistor circuit 3 connecting one terminal to the other terminal of the variable capacitor circuit and connecting the other terminal to the constant potential point.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a group delay generating circuit for generating peaking in a group delay characteristic of a high-frequency electric signal and adjusting the amount of peaking.

[0002]

2. Description of the Related Art As a conventional group delay generation circuit of this kind,
As shown in FIG. 9, an input path of a current-voltage conversion type amplifier 11 also called a transimpedance amplifier is
One in which a resonance circuit 12 including an inductor and a capacitor is connected is known. Although not shown, in Japanese Patent Application Laid-Open No. 7-58591, a signal passing through the first and second resistors is supplied to a first capacitor and a buffer amplifier.
The output of this buffer amplifier is derived as an output signal, fed back to the output terminal of the first resistor via a second capacitor, the input signal is passed through a variable voltage divider, and the output is passed through a low-pass filter. In this case, a delay time characteristic can be varied by fixing the filter time constant by supplying it to the other end of the first capacitor.

[0003]

However, among the conventional group delay generation circuits, in the group delay generation circuit constituted by a resonance circuit, a resonance circuit is inserted in series with a signal line to have a peaking characteristic in the group delay. Therefore, the input / output matching characteristics of the circuit are deteriorated, the transfer characteristics are disturbed over a wide band, the stability of the active block is impaired, and the control of the peaking characteristics is difficult. In the configuration described in JP-A-7-58591,
There is a problem that it is difficult to generate peaking in the group delay characteristic and to control the amount thereof.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is possible to generate good peaking characteristics without deteriorating the input / output matching characteristics of a group delay generating circuit and control the amount of peaking. A group delay generation circuit is provided.

[0005]

The invention according to claim 1 is
An amplifier including a bipolar transistor or FET whose base or gate is connected to the input terminal and whose emitter or source is connected to a constant potential point, and one end connected to the collector or drain side of the transistor and the other end biased to the transistor A variable inductance circuit connected to a power supply, a variable capacitance circuit having one end connected to the collector or drain of the transistor, and a variable resistance having one end connected to the other end of the variable capacitance circuit and the other end connected to a constant potential point And a group delay generation circuit including a circuit. According to this configuration, the peaking of the group delay characteristic and the frequency thereof can be determined by the inductance value of the variable inductance circuit and the capacitance value of the variable capacitance circuit without deteriorating the input / output matching characteristics. The peaking amount can be adjusted.

According to a second aspect of the present invention, in the group delay generating circuit according to the first aspect, the amplifier uses a feedback type common emitter amplifier or a feedback type common source amplifier. According to this configuration, an effect of flattening the frequency characteristics of the gain of the group delay generation circuit can be obtained by using the feedback type amplifier.

According to a third aspect of the present invention, there is provided the group delay generating circuit according to the first or second aspect, further comprising an electric attenuator connected in series to a signal output path of the amplifier. According to this configuration, by attenuating the signal output by the electric attenuator, it is possible to obtain an effect that the gain of the group delay generation circuit can be compensated.

According to a fourth aspect of the present invention, there is provided the group delay generating circuit according to the first or second aspect, further comprising an electric attenuator connected in series to a signal input path of the amplifier. According to this configuration, by attenuating the signal output by the electric attenuator, it is possible to obtain an effect that the gain of the group delay generation circuit can be compensated.

According to a fifth aspect of the present invention, in the group delay generating circuit of the first aspect, the group delay generating circuit has a band-pass characteristic for selecting a signal in a peaking frequency band, and has one end connected to a signal output path of the amplifier. One band-pass filter, a first high-frequency signal detector having one end connected to the other end of the first band-pass filter, and a band-pass characteristic for selecting a signal in an arbitrary reference frequency band that does not generate peaking. A second band-pass filter having one end connected to the signal output path of the amplifier; a second high-frequency signal detector having one end connected to the other end of the second band-pass filter;
The other end of the first high-frequency signal detector is connected to the first input terminal, the other end of the second high-frequency signal detector is connected to the second input terminal, A variable resistance control circuit having an output terminal connected to a control signal input terminal of the variable resistance circuit and adjusting a resistance value of the variable resistance circuit so that a difference in intensity between output signals of the first and second high-frequency signal detectors becomes constant. It is provided with. According to this configuration, a signal in the peaking frequency band and a signal in an arbitrary reference frequency band that does not generate peaking are selected, and the strength of the obtained signal is detected by the high-frequency signal detection circuit. By controlling the resistance value of the variable resistor by comparing the strengths, the peaking amount can be automatically adjusted.

According to a sixth aspect of the present invention, in the group delay generating circuit according to the fifth aspect, the amplifier uses a feedback-type common emitter amplifier or a feedback-type common source amplifier. According to this configuration, an effect of flattening the frequency characteristics of the gain of the group delay generation circuit can be obtained by using the feedback type amplifier.

According to a seventh aspect of the present invention, in the group delay generation circuit according to the fifth or sixth aspect, the signal of the amplifier at a stage prior to the connection point to which one ends of the first and second bandpass filters are respectively connected. It has an electric attenuator connected in series to the output path. According to this configuration, by attenuating the signal output by the electric attenuator, it is possible to obtain an effect that the gain of the group delay generation circuit can be compensated.

According to an eighth aspect of the present invention, there is provided the group delay generating circuit according to the fifth or sixth aspect, further comprising an electric attenuator connected in series to a signal input path of the amplifier. According to this configuration, by attenuating the signal output by the electric attenuator, it is possible to obtain an effect that the gain of the group delay generation circuit can be compensated.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram showing the configuration of the first embodiment of the group delay generation circuit of the present invention. In FIG. 1, a FET grounded source amplifier 1 is an FET
Is grounded to earth as a constant voltage point,
This is to amplify the input signal. Variable capacitance circuit 2
Has one end connected to the drain side of the grounded FET source amplifier and the other end connected to one end of the variable resistance circuit 3.
The capacitance value is variably configured from outside. The other end of the variable resistance circuit 3 having one end connected to the other end of the variable capacitance circuit 2 is grounded, and its resistance value is variably configured by an external signal or the like. The variable inductance circuit 4 has one end connected to the drain side of the grounded FET source amplifier 1 and the other end connected to the driving power supply of the grounded FET source amplifier 1, and the inductance value thereof is configured to be variable from outside.

The operation of the first embodiment configured as described above will be described. The input high-frequency electric signal is amplified by the common FET source amplifier 1. At this time, the variable capacitance circuit 2, the variable resistance circuit 3 and the variable inductance circuit 4 connected to the drain side of the common FET source amplifier 1 are connected to the drain load combined with the amplifier-specific load from the FET of the common FET source amplifier 1. Therefore, the transfer characteristic can be changed by changing the drain load impedance, and therefore, the group delay characteristic can also be changed. In the vicinity of the cutoff frequency of the low-pass filter determined by the capacitance value of the variable capacitance circuit 2 and the inductance value of the variable inductance circuit 4, the combined real impedance becomes larger than the amplifier-specific impedance, and the transmission gain is improved. 2, peaking can be generated in the group delay characteristic as shown in FIG. On the other hand, the load peculiar to the amplifier is dominant in a region other than the cutoff frequency, so that the transfer characteristic is not affected. Further, by controlling the resistance value by the variable resistance circuit 3, the peaking amount of the group delay characteristic can be controlled. On the other hand, since the change in the combined load impedance is smaller than that of the load unique to the amplifier, the matching characteristic is substantially linear only with a slight decrease in some frequency bands as shown in FIG. Is almost none.

As described above, according to the first embodiment of the present invention, the variable inductance circuit 4 having one end connected to the drain side of the grounded FET source amplifier 1 and the other end connected to the drive power supply, Is provided with a variable capacitance circuit 2 connected to the drain side of the grounded FET source amplifier 1 and a variable resistance circuit 3 having one end connected to the other end of the variable capacitance circuit and the other end grounded. The peaking of the group delay characteristic and the frequency thereof can be determined by the inductance value of the variable inductance circuit 4 and the capacitance value of the variable capacitance circuit 2 without deteriorating the input / output matching characteristics of the circuit. A group delay generation circuit with a variable amount of peaking is obtained.

FIG. 4 is a block circuit diagram showing a configuration of a second embodiment of the group delay generation circuit of the present invention. In the figure, the same elements as those in FIG. 1 showing the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. This embodiment employs an FET
1 in that an electrical attenuator 15 for attenuating and outputting an input signal is newly added to the output path of the common-source amplifier 1. According to this configuration, the electric attenuator 15 uses the FET.
The gain characteristic of the group delay generation circuit can be compensated by attenuating the gain equivalent amount of the common source amplifier 1. In addition, as described above, the matching characteristic has almost no deterioration because the change in the combined load impedance is smaller than the load unique to the amplifier, and the output matching characteristic is rather improved by the attenuation of the electric attenuator 15. There is.

FIG. 5 is a block circuit diagram showing a configuration of a third embodiment of the group delay generation circuit of the present invention. In the figure, the same elements as those in FIG. 1 showing the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. This embodiment employs an FET
1 in that an electric attenuator 15 for attenuating and outputting an input signal is added to the input path of the common-source amplifier 1. According to this configuration, the gain characteristic of the group delay generation circuit can be compensated for by attenuating the gain equivalent amount of the common FET source amplifier 1 by the electric attenuator 15 and the output power of the common FET source amplifier 1 is suppressed. Therefore, distortion characteristics can be improved. On the other hand, the matching characteristic has almost no deterioration because the change in the combined load impedance is smaller than the load inherent to the amplifier, and the input matching characteristic is rather improved by the attenuation of the electric attenuator 15.

FIG. 6 is a block circuit diagram showing a configuration of a fourth embodiment of the group delay generation circuit of the present invention. In the figure, the same elements as those in FIG. 1 showing the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. In this embodiment, the input terminal is connected to the output terminal of the common FET source amplifier 1, and the band-pass filter 5 and the optional device that does not generate the peaking are selected because only the high-frequency electric signal in the band in which the peaking is generated in the group delay characteristic is selected. , And an input terminal connected to each output terminal of these bandpass filters, and a high-frequency signal detector 7 for detecting the strength of the selected high-frequency electric signal. And a high-frequency signal detector 8 connected to each output terminal of the high-frequency signal detectors 7 and 8 to compare the intensities of the detected high-frequency signals, and to adjust the variable resistance circuit 3 so that the intensity difference between the two becomes constant. The configuration differs from the first embodiment shown in FIG. 1 in that a variable resistance control circuit 9 for adjusting the resistance value is newly provided.

The operation of the fourth embodiment configured as described above will be described focusing on the point where a new element is added. A part of the signal amplified by the common FET source amplifier 1 is branched, and only the high-frequency electric signal in the band in which the peaking is generated in the group delay characteristic by the band-pass filter 5 is selected and transmitted to the high-frequency signal detector 7. . The high-frequency signal detector 7 detects the signal strength selected by the band-pass filter 5 and sends it to the variable resistance control circuit 9. Also, F
A part of the signal amplified by the grounded ET source amplifier 1 is branched, and only an electric signal in an arbitrary reference frequency band that does not cause peaking in the band-pass filter 6 is selected and sent to the high-frequency signal detector 8. It is desirable that the selection bandwidth of the band-pass filter 6 is substantially equal to that of the band-pass filter 5. The high-frequency signal detector 8 detects the signal strength of the reference frequency band selected by the band-pass filter 6 and sends the signal strength to the variable resistance control circuit 9. In the band in which the peaking has occurred in the group delay, the peaking characteristic is also generated in the amplitude characteristic. Therefore, the signal intensity detected by the high-frequency signal detector 7 is determined by the high-frequency signal detector 8 that has detected the signal intensity in the reference frequency band. The output signal strength is different. The variable resistance control circuit 9 controls the resistance value of the variable resistance circuit 3 so as to keep the difference in intensity detected by the high-frequency signal detector 7 and the high-frequency signal detector 8 constant, thereby automatically controlling the peaking amount of the group delay characteristic. Can be adjusted.

As described above, according to the fourth embodiment of the present invention, a signal component matched with the peaking frequency band of the group delay generating circuit is extracted from the signal amplified by the grounded FET source amplifier 1 with the peaking. Signal components of an arbitrary reference frequency band that are not generated are extracted, and the intensities of these signal components are detected. Since the resistance value of the variable resistor circuit 3 is controlled so as to keep the difference in intensity between them, peaking occurs. The amount can be adjusted automatically.

FIG. 7 is a block circuit diagram showing the configuration of a fifth embodiment of the group delay generation circuit of the present invention. In the figure, the same elements as those in FIG. This embodiment is different from FIG. 6 in that an electric attenuator 10 having an attenuating function of a high-frequency electric signal is connected in front of the band-pass filter 5 and the band-pass filter 6 connected to the output path of the common FET source amplifier 1. And the configuration is different. According to this configuration, the high-frequency electric signal amplified by the grounded FET source amplifier 1 is attenuated by the electric attenuator 10 so that the gain equivalent of the group delay generating circuit is attenuated, and then the band-pass filter 5 and the band-pass filter 6 respectively. A signal component that matches the peaking frequency band of the group delay generation circuit and a signal component of an arbitrary reference frequency band that does not generate peaking are extracted.

As described above, according to the fifth embodiment shown in FIG. 7, the signal output is attenuated by the electric attenuator 10 without deteriorating the input / output matching characteristics of the group delay generating circuit. The gain of the delay generation circuit can be compensated, and the peaking amount can be automatically adjusted.

FIG. 8 is a block circuit diagram showing a configuration of a sixth embodiment of the group delay generation circuit of the present invention. In the figure, the same elements as those of the fourth embodiment shown in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, F
6 in that an electric attenuator 10 having a function of attenuating a high-frequency electric signal is connected to an input path at a stage preceding the ET source grounded amplifier 1. According to this configuration, a high-frequency electric signal input from the outside is attenuated by the electric attenuator 10 by an amount corresponding to the gain of the group delay generation circuit, and then amplified by the common FET source amplifier 1. The other operations are the same as those of the fourth embodiment described with reference to FIG.

As described above, according to the sixth embodiment shown in FIG. 8, since the electric attenuator 10 connected to the input side of the high-frequency signal attenuates the gain by the amount equivalent to the gain of the group delay generating circuit, The signal output is attenuated by the electric attenuator 10 without deteriorating the input / output matching characteristics of the group delay generation circuit using the FET grounded source amplifier, thereby compensating the gain of the group delay generation circuit and automatically adjusting the peaking amount. You can do it.

In the above-described first to sixth embodiments, examples have been described in which each of the amplifiers is constituted by a common FET source amplifier. However, a feedback common FET source amplifier, a known common emitter amplifier using bipolar transistors, The same can be applied to the feedback-type common emitter amplifier. In particular, when the feedback-type common-source amplifier and the feedback-type common-emitter amplifier are used, in addition to the effects described above, the transmission frequency of the group delay generation circuit The effect that the characteristics can be further flattened is also obtained.

[0026]

As is apparent from the above description, according to the present invention, a group capable of generating a good peaking characteristic without deteriorating the input / output matching characteristics of the group delay generating circuit and controlling the peaking amount. It is possible to provide a delay generation circuit.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a configuration of a group delay generation circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a relationship between a frequency and a group delay in order to explain the operation of the first embodiment shown in FIG. 1;

FIG. 3 is a diagram showing a relationship between frequency and return loss in order to explain the operation of the first embodiment shown in FIG. 1;

FIG. 4 is a block circuit diagram showing a configuration of a second embodiment of the group delay generation circuit according to the present invention;

FIG. 5 is a block circuit diagram showing a configuration of a third embodiment of the group delay generation circuit according to the present invention;

FIG. 6 is a block circuit diagram showing a configuration of a fourth embodiment of the group delay generation circuit according to the present invention;

FIG. 7 is a block circuit diagram showing a configuration of a fifth embodiment of a group delay generation circuit according to the present invention;

FIG. 8 is a block circuit diagram showing a configuration of a sixth embodiment of a group delay generation circuit according to the present invention;

FIG. 9 is a block circuit diagram showing a configuration of a conventional group delay generation circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 FET source grounded amplifier 2 Variable capacitance circuit 3 Variable resistance circuit 4 Variable inductance circuit 5, 6 Bandpass filter 7, 8 High-frequency signal detector 9 Variable resistance control circuit 10, 15 Electric attenuator

Claims (8)

[Claims] An amplifier including a bipolar transistor or FET having a base or gate connected to an input terminal and an emitter or source connected to a constant potential point; one end connected to a collector side or a drain side of the transistor; A variable inductance circuit having the other end connected to the bias power supply of the transistor; a variable capacitance circuit having one end connected to the collector or drain of the transistor; one end connected to the other end of the variable capacitance circuit; And a variable resistance circuit connected to the constant potential point. 2. The group delay generating circuit according to claim 1, wherein said amplifier uses a feedback type common emitter amplifier or a feedback type common source amplifier. 3. The group delay generating circuit according to claim 1, further comprising an electric attenuator connected in series to a signal output path of the amplifier. 4. The group delay generating circuit according to claim 1, further comprising an electric attenuator connected in series to a signal input path of the amplifier. 5. A first band-pass filter having a band-pass characteristic for selecting a signal in a peaking frequency band, one end of which is connected to a signal output path of the amplifier, and one end of which is connected to the first band-pass filter. A first high-frequency signal detector connected to the other end, and a second high-frequency signal detector having a band-pass characteristic for selecting a signal in an arbitrary reference frequency band that does not generate peaking, one end of which is connected to a signal output path of the amplifier. A second high-frequency signal detector having one end connected to the other end of the second band-pass filter; first and second input terminals and an output terminal; The other end of the first high-frequency signal detector is connected to the input terminal, the other end of the second high-frequency signal detector is connected to the second input terminal, and the output terminal controls the variable resistor circuit. Connected to the signal input terminal, 2. The group delay generation circuit according to claim 1, further comprising: a variable resistance control circuit that adjusts a resistance value of the variable resistance circuit so that an intensity difference between output signals of the first and second high-frequency signal detectors becomes constant. . 6. The group delay generating circuit according to claim 5, wherein said amplifier uses a feedback type common emitter amplifier or a feedback type common source amplifier. 7. An electric attenuator connected in series to a signal output path of the amplifier before a connection point to which one ends of the first and second bandpass filters are connected, respectively. 7. The group delay generation circuit according to 6. 8. The group delay generating circuit according to claim 5, further comprising an electric attenuator connected in series to a signal input path of the amplifier.