JP2002043523A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method wherein high temperature heat treatment is unnecessary for forming a low resistance element by realizing single crystal film formation of low sheet resistance. SOLUTION: An insulating film 2 is formed on a silicon substrate 1, a resistance element forming part is selectively opened and eliminated by etching, and an arsenic-doped polycrystal silicon film 3 of about 0.1 μm in thickness is formed on the whole surface. In the pre-treatment of growth of the film 3, in order to eliminate a natural oxide film on the silicon substrate 1, the polycrystal silicon film 3 is epitaxially grown and turned into an arsenic-doped single crystal silicon film 5. After that, a resistance element is patterned by dry etching treatment, a cover insulating film 4 is formed, and a contact is opened by a similar technique. In order to form a transistor, emitter annealing (lamp annealing: about 1000 deg.C, about 30 seconds) is performed in a nitrogen atmosphere.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device using an arsenic-doped polycrystalline silicon film in forming a low-resistance element of a high-frequency bipolar IC and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional high-frequency bipolar IC requires a low-resistance element of about 50Ω for impedance matching.

Conventionally, for forming a low-resistance element, a method of doping impurities into a polycrystalline silicon film and forming a low-resistance element by heat treatment has been adopted.

FIG. 3 shows the structure of a low-resistance element using the prior art.

In this resistance element, an insulating film 2 is formed on a silicon substrate 1, and then a polycrystalline silicon film 8 is formed on the entire surface. Thereafter, impurities are implanted from the surface by ion implantation.

The ion implantation conditions are, for example, arsenic impurity ions, an implantation energy of 70 keV, and a dose of about 1.0E16 cm ⁻² .

After that, the resistive element is patterned by a known PR technique and a dry etching process. A cover insulating film 4 is formed, and a contact is opened in the same manner as described above. Thereafter, the transistor is subjected to an emitter annealing treatment (lamp annealing around 1000 ° C., a nitrogen atmosphere,
(About 30 seconds) to finally form the electrode 6.

In this prior art, since the polycrystalline silicon film 8 itself remains polycrystalline, the sheet resistance after impurity implantation and annealing is about 200 Ω / □. For this reason, there is a problem that chip shrink becomes difficult in order to obtain a low resistance element by increasing the area of the resistance element.

As another prior art, as shown in FIG.
A low resistance element using a diffusion resistance is formed.

In this resistance element, an insulation film 2 is formed on a silicon substrate 1 and the resistance element portion is patterned by the conventional PR method to expose the silicon substrate 1. After that, impurities are implanted by using an ion implantation method. The ion implantation conditions are, for example, impurity ions of boron, an implantation energy of 70 keV, and a dose of 1.0E15 cm ^−2.
Degree.

An annealing treatment is performed for the purpose of activation,
An impurity diffusion layer 6 is formed (about 1000 ° C., nitrogen atmosphere for about 20 minutes). Thereafter, a cover insulating film 4 is formed, and a contact is opened in the same manner as described above. Thereafter, the transistor is subjected to an emitter annealing treatment (lamp annealing, a nitrogen atmosphere at about 1000 ° C. for about 30 seconds), and finally the electrode 6 is formed.

At this time, the sheet resistance becomes about 100 Ω / □, which can be reduced to about の of that when the polycrystalline silicon film 8 is used.

[0013]

However, in the above-mentioned prior art, the pattern area can be reduced, but high-temperature heat treatment (1000 ° C.) is required, and it cannot be applied to an IC using a transistor having a shallow junction. Had.

One of the main objects of the present invention is to realize the formation of a single crystal film having a low sheet resistance and to reduce the element area.

Another main object of the present invention is to realize a transistor having a shallow junction because high-temperature heat treatment is not required to form a low-resistance element.

[0016]

According to the present invention, there is provided a semiconductor device comprising:
The first insulating layer partially covering the surface of the semiconductor substrate of the first conductivity type and the second insulating layer grown on the exposed portion of the semiconductor substrate are removed, and the second insulating layer coated on the first insulating layer is removed. A polycrystalline semiconductor layer containing a first impurity of a conductivity type and a single crystal semiconductor layer grown on an exposed portion of the semiconductor substrate and implanted with a second impurity ion of a second conductivity type; In this configuration, the semiconductor layer and the single crystal semiconductor layer are formed as resistors.

In the semiconductor device according to the present invention, the resistance of the resistor formed of the polycrystalline semiconductor layer is larger than the resistance of the resistor formed of the single crystal semiconductor layer. You can also.

Further, the semiconductor substrate of the first conductivity type of the semiconductor device of the present invention is a P-type silicon substrate, and the first and second insulator layers are silicon oxide films. The first impurity of the second conductivity type is arsenic, and the second impurity of the second conductivity type is arsenic.

Further, a method of manufacturing a semiconductor device according to the present invention
A first step of partially covering a surface of a semiconductor substrate of a first conductivity type with a first insulator layer, a second step of removing a second insulator layer grown on an exposed portion of the semiconductor substrate, A third step of covering the first insulator layer with a polycrystalline semiconductor layer containing a second conductivity type impurity, a fourth step of growing a single crystal semiconductor layer on an exposed portion of the semiconductor substrate, A fifth step of implanting impurity ions of the second conductivity type into the single crystal semiconductor layer grown on the exposed portion of the substrate.

[0020]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of the semiconductor device according to the first embodiment of the present invention.

Referring to FIG. 1, in a semiconductor device according to a first embodiment of the present invention, an insulating film 2 is formed on a silicon substrate 1, a resistive element forming portion is selectively opened by a known PR technique, and etching is performed. Remove.

Then, 8.0E20cm ^{-2 to} 1.3E
The arsenic-doped polycrystalline silicon film 3 of 21 cm ^-2 is
The film is formed on the entire surface at a temperature of ° C. to a thickness of about 0.1 μm. In the pre-growth process of the arsenic-doped polycrystalline silicon film 3, the arsenic-doped polycrystalline silicon film 3 is epitaxially grown into an arsenic-doped single-crystal silicon film 5 in order to remove the natural oxide film on the silicon substrate 1.

Thereafter, the resistive element is patterned by a known PR technique and dry etching. Thereafter, a cover insulating film 4 is formed, and contacts are opened by the same method as described above.

Thereafter, emitter annealing in a nitrogen atmosphere (lamp annealing: 100) is performed to form a transistor.
(Around 0 ° C for about 30 seconds). The emitter anneal can also serve as a resistance anneal.

The arsenic-doped single-crystal silicon film 5 has a low sheet resistance of about 30 Ω / □ after annealing, and can be an effective film in forming a low-resistance element. In addition, in the present embodiment, since the emitter annealing and the resistance annealing can be used in combination, it is possible to form a low-resistance element for impedance matching without affecting the formation of a transistor having a shallow junction. can get.

In the present invention, the high-concentration arsenic-doped polycrystalline film
By utilizing the epigenesis phenomenon occurring at the interface between the silicon substrate 3 and the silicon substrate 1, it is possible to form 5 parts of the arsenic-doped single-crystal silicon film having a low sheet resistance, and as a result, it is possible to reduce the element area.

The resistance value of the resistance element is expressed as resistance length (L) and resistance width (W) as follows: resistance value (Ω) = sheet resistance (Ω / □) * L (μm) / W
(Μm).

For example, the element area required to obtain a resistance of 50 (Ω) is, in the case of the prior art, area = 200 (Ω / □) * 10 μm / 40 μm = 400 μm ² , but according to the present invention. For example, the area is 30 (Ω / □) * 17 μm / 10 μm = 170 μm ² .

Since the annealing necessary for forming the resistor is also used as the emitter annealing for forming the transistor, it does not affect the formation of the transistor having a shallow junction.
A low resistance element can be formed.

Next, a second embodiment of the present invention will be described.

Although the first embodiment of the present invention has been applied to the formation of a low-resistance element of a bipolar IC, it can be applied to the formation of a medium-resistance element (200 to 300Ω) simultaneously with the formation of a low-resistance element. it can. The configuration is shown in FIG.

Referring to FIG. 2, an insulating film 2 is formed on a silicon substrate 1 and only a low resistance element portion is opened by a conventional PR method and selectively etched away.

Then, 8.0E20cm ^{-2 to} 1.3E
An arsenic-doped polycrystalline silicon film 3 of 21 cm ^-2 is formed on the entire surface, and the low resistance element and the medium resistance element are patterned by the same PR method and dry etching as described above.

Thereafter, the cover insulating film 4 is formed, and the contacts of the low-resistance portion and the medium-resistance portion are simultaneously opened in the same manner as described above. Thereafter, an emitter annealing process (lamp annealing, about 1000 ° C. for about 30 seconds) in nitrogen of the transistor is performed, and finally the electrode 6 is formed and patterned to form each resistance element.

In the second embodiment of the present invention, the low resistance portion can reduce the sheet resistance value because of the arsenic-doped single-crystal silicon film 5 as shown in the first embodiment of the present invention. is there. On the other hand, the medium-resistance element formed on the insulating film 2 is not a single crystal but an arsenic-doped polycrystalline silicon film 3, and the sheet resistance can be set higher.

It should be noted that, based on the results of the prototype test conducted by the inventor, the sheet resistance value may be about 250 to 300 (Ω / □).
found. As a result, an effect that two types of resistance elements can be formed by a single arsenic-doped polycrystalline silicon film formation without affecting the formation of a transistor having a shallow junction is obtained.

In this configuration, when the deposition temperature, concentration, and thickness of the arsenic-doped polycrystalline silicon film 3 are changed, the control range of the resistance value can be set in a wider range.

[0038]

As described above, the semiconductor device according to the present invention utilizes the arsenic-doped single-crystal silicon film having a low sheet resistance by utilizing the epitaxy phenomenon occurring at the interface between the high-concentration arsenic-doped polycrystalline film 3 and the silicon substrate. Five parts can be formed, and as a result, there is an effect that the element area can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a method of manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a cross-sectional view of a semiconductor device according to a conventional method of manufacturing a semiconductor device.

FIG. 4 is a cross-sectional view of another semiconductor device according to a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 insulating film 3 arsenic-doped polycrystalline silicon film 4 cover insulating film 5 arsenic-doped single-crystal silicon film 6 diffusion layer 7 electrode 8 polycrystalline silicon film

Claims (7)

[Claims] A first insulating layer partially covering a surface of a semiconductor substrate of a first conductivity type; and a second insulating layer grown on an exposed portion of the semiconductor substrate, wherein the first insulating layer is removed. A polycrystalline semiconductor layer containing a first impurity of the second conductivity type, which is coated on the semiconductor substrate;
A semiconductor device, comprising: a single crystal semiconductor layer into which impurity ions are implanted; wherein the polycrystalline semiconductor layer and the single crystal semiconductor layer are formed as resistors. 2. The semiconductor device according to claim 1, wherein a layer resistance of the resistor formed of the polycrystalline semiconductor layer is larger than a layer resistance of a resistor formed of the single crystal semiconductor layer. 3. The semiconductor device according to claim 1, wherein said first conductivity type semiconductor substrate is a P-type silicon substrate, and said first and second insulator layers are silicon oxide films. 4. The semiconductor device according to claim 1, wherein the first impurity of the second conductivity type is arsenic. 5. The semiconductor device according to claim 1, wherein said second impurity of the second conductivity type is arsenic. 6. A first step of partially covering a surface of a semiconductor substrate of a first conductivity type with a first insulator layer, and a second step of removing a second insulator layer grown on an exposed portion of the semiconductor substrate. A third step of covering the first insulator layer with a polycrystalline semiconductor layer containing a second conductivity type impurity, and a fourth step of growing a single crystal semiconductor layer on an exposed portion of the semiconductor substrate. 5. The method according to claim 1, further comprising the step of: implanting a second conductivity type impurity ion into the single crystal semiconductor layer grown on the exposed portion of the semiconductor substrate. Or the method of manufacturing a semiconductor device according to 5. 7. The method of manufacturing a semiconductor device according to claim 6, wherein in the third step, the polycrystalline semiconductor layer is grown at a temperature of about 660 ° C.