JP2001339258A - Voltage-current converting circuit - Google Patents
Voltage-current converting circuitInfo
- Publication number
- JP2001339258A JP2001339258A JP2000153859A JP2000153859A JP2001339258A JP 2001339258 A JP2001339258 A JP 2001339258A JP 2000153859 A JP2000153859 A JP 2000153859A JP 2000153859 A JP2000153859 A JP 2000153859A JP 2001339258 A JP2001339258 A JP 2001339258A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output
- output current
- input voltage
- vin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
- Amplifiers (AREA)
Abstract
Description
【0001】[0001]
【発明が属する技術分野】本発明は、電圧を入力して電
流を出力する回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for inputting a voltage and outputting a current.
【0002】[0002]
【従来の技術】従来の電圧電流変換回路を図6に、従来
の電圧電流変換回路の電圧−電流特性を図7に示す。従
来の電圧電流変換回路では、入力電圧Vinがトランジ
スタ2dのしきい値Vtnよりも高い電圧では、トラン
ジスタのサイズを十分大きくすれば、以下の式にしたが
って入力電圧Vinに対して出力電流Ioutが決ま
る。 Iout=(Vin−Vtn)/Rd (1) ここで、Rdは抵抗3dの抵抗値入力電圧Vinが、ト
ランジスタ2dのしきい値Vthよりも低い場合にはト
ランジスタ2dがONしないので、電流Ioutが流れ
ない。したがって、従来の電圧電流変換回路では、出力
電流Ioutをコントロールできる入力電圧Vinのレ
ンジはVDD−Vtnとなる。2. Description of the Related Art FIG. 6 shows a conventional voltage-current converter, and FIG. 7 shows voltage-current characteristics of the conventional voltage-current converter. In the conventional voltage-current converter, when the input voltage Vin is higher than the threshold value Vtn of the transistor 2d, the output current Iout is determined with respect to the input voltage Vin in accordance with the following equation if the size of the transistor is sufficiently increased. . Iout = (Vin−Vtn) / Rd (1) Here, when the resistance value input voltage Vin of the resistor 3d is lower than the threshold value Vth of the transistor 2d, the transistor 2d does not turn on. Not flowing. Therefore, in the conventional voltage-current conversion circuit, the range of the input voltage Vin that can control the output current Iout is VDD-Vtn.
【0003】しかし、電源電圧が低下してくると、出力
電流Ioutをコントロールできる入力電圧のレンジV
DD−Vtnは電圧の低下以上に狭くなる。なぜなら
ば、トランジスタのリーク電流許容値を満たすために、
通常、電源電圧の低下と同じ比率でトランジスタのしき
い値Vtnを低下させることは出来ないからである。However, when the power supply voltage decreases, the input voltage range V that can control the output current Iout is reduced.
DD-Vtn becomes narrower than the voltage drop. Because, to meet the transistor leakage current tolerance,
This is because normally, the threshold value Vtn of the transistor cannot be reduced at the same rate as the power supply voltage.
【0004】出力電流Ioutをコントロールできる入
力電圧のレンジが狭くなると、出力電流Iout/入力
電圧Vinの勾配が急になる。図8の示すPLLや図9
に示すDLLなどのフィードバック制御系に従来の電圧
電流変換回路を使った場合には、出力電流Ioutの入
力電圧Vinに対する勾配dIout/dVinが急で
あるために出力電流Ioutの変動が大きくなり、フィ
ードバック制御系の出力の変動が大きくなってしまっ
た。When the range of the input voltage that can control the output current Iout becomes narrow, the gradient of the output current Iout / input voltage Vin becomes steep. The PLL shown in FIG.
When a conventional voltage-current conversion circuit is used in a feedback control system such as a DLL shown in (1), the gradient dIout / dVin of the output current Iout with respect to the input voltage Vin is steep, so that the output current Iout fluctuates greatly, The output of the control system fluctuated greatly.
【0005】[0005]
【発明が解決しようとする課題】解決しようとする問題
点は、出力電流Ioutをコントロールできる入力電圧
のレンジが狭い点である。The problem to be solved is that the range of the input voltage that can control the output current Iout is narrow.
【0006】[0006]
【課題を解決するための手段】本発明は、出力電流Io
utをコントロール出来る入力電圧Vinのレンジを0
V〜電源電圧VDDに広げるため、抵抗に電流を流して
生じる電圧と入力電圧を比較して2つの電圧が一致する
ように電流を制御することを最も主要な特徴とする。The present invention provides an output current Io.
ut can be controlled by setting the input voltage Vin range to 0.
In order to extend the voltage from V to the power supply voltage VDD, the most main feature is to compare a voltage generated by flowing a current through the resistor with an input voltage and control the current so that the two voltages match.
【0007】[0007]
【発明の実施の形態】0V〜電源電圧VDDの範囲の入
力電圧に対して出力電流Ioutを制御可能にするとい
う目的を、抵抗に電流を流して生じる電圧と入力電圧を
オペアンプに入力し、オペアンプの出力でトランジスタ
を制御して電流を制御することで実現した。DESCRIPTION OF THE PREFERRED EMBODIMENTS The purpose of enabling the output current Iout to be controllable with respect to an input voltage in a range of 0 V to a power supply voltage VDD is to input a voltage generated by flowing a current through a resistor and an input voltage to an operational amplifier. This is achieved by controlling the current by controlling the transistor with the output.
【0008】[0008]
【実施例】図1は、本発明装置の1実施例の回路図であ
って、1はオペアンプ、2aはNMOSトランジスタ、
3aは抵抗である。1 is a circuit diagram of an embodiment of the device of the present invention, wherein 1 is an operational amplifier, 2a is an NMOS transistor,
3a is a resistor.
【0009】オペアンプ1の出力N2はNMOSトラン
ジスタ2aのゲートに接続され、オペアンプの出力電圧
が高くなれば出力電流Ioutが大きくなり,オペアン
プの出力電圧が低くなれば出力電流Ioutが小さくな
る。オペアンプ1はノードN1と入力電圧Vinの電位
差を増幅するので、ノードN1の電位が入力電圧Vin
に等しくなるようにこの回路は制御する。The output N2 of the operational amplifier 1 is connected to the gate of the NMOS transistor 2a. The output current Iout increases as the output voltage of the operational amplifier increases, and the output current Iout decreases as the output voltage of the operational amplifier decreases. The operational amplifier 1 amplifies the potential difference between the node N1 and the input voltage Vin.
This circuit controls to be equal to
【0010】このため、出力電流Ioutは次式できま
る。 Iout=Vin/Ra (2) ここで、Raは抵抗3aの抵抗値入力電圧Vinと出力
電流Ioutの関係を図2の実線に示す。Therefore, the output current Iout is given by the following equation. Iout = Vin / Ra (2) Here, Ra indicates the relationship between the resistance value input voltage Vin of the resistor 3a and the output current Iout by a solid line in FIG.
【0011】本実施例では、入力電圧Vinが0V〜V
DDの範囲で出力電流IoutをVinに比例させるこ
とができる。したがって、出力電流Ioutの最大値を
同じにした場合、本実施例では従来の方法よりも入力電
圧Vinの範囲を広く出来るので、入力電圧Vinに対
する出力電流の傾きdIout/dVinを小さく出来
る。これにより、入力電圧の変動によって生じる出力電
流の変動をより小さく出来る。このため、PLL、等の
フィードバック系に本回路を使用すれば、従来よりも変
動を小さく出来る。In this embodiment, the input voltage Vin is 0 V to V
The output current Iout can be made proportional to Vin in the range of DD. Therefore, when the maximum value of the output current Iout is the same, in this embodiment, the range of the input voltage Vin can be made wider than in the conventional method, and the slope dIout / dVin of the output current with respect to the input voltage Vin can be made smaller. As a result, fluctuations in the output current caused by fluctuations in the input voltage can be further reduced. Therefore, if this circuit is used for a feedback system such as a PLL, the fluctuation can be reduced as compared with the related art.
【0012】なお、本実施例ではノードN1が電源電圧
VDDまで到達するためにはオペアンプ1の出力N2は
VDD+Vtn以上の電圧を駆動する必要がある。も
し、オペアンプ1に供給する電圧をVDDとすると、図
2に破線で示すように入力電圧VinがVDD−Vtn
以上の領域では出力電流が一定になってしまう。従っ
て、オペアンプの出力N2がVDD+Vtn以上の電圧
を駆動するためには、オペアンプに供給する電源電圧を
VDD+Vtn以上にしなければならない。In this embodiment, in order for the node N1 to reach the power supply voltage VDD, the output N2 of the operational amplifier 1 needs to drive a voltage equal to or higher than VDD + Vtn. Assuming that the voltage supplied to the operational amplifier 1 is VDD, the input voltage Vin is equal to VDD−Vtn as shown by a broken line in FIG.
In the above region, the output current becomes constant. Therefore, in order for the output N2 of the operational amplifier to drive a voltage equal to or higher than VDD + Vtn, the power supply voltage supplied to the operational amplifier must be equal to or higher than VDD + Vtn.
【0013】図3の実施例は、図1の実施例の回路に昇
圧回路13を追加し、昇圧回路13の出力VCCでオペ
アンプ1に電源を供給している。この構成では、外部か
ら供給する電源はVDD1種類で済むので、1種類の電
源電圧しか供給されない場合には本実施例の方が図1の
実施例よりも適している。<BR>In the embodiment of FIG. 3, a booster circuit 13 is added to the circuit of the embodiment of FIG. 1, and power is supplied to the operational amplifier 1 at the output VCC of the booster circuit 13. In this configuration, only one type of power supply is required, VDD, so that the present embodiment is more suitable than the embodiment of FIG. 1 when only one type of power supply voltage is supplied. <BR>
【0014】図4の実施例は、図1の実施例の回路と図
5の従来例の回路を並列に接続している。In the embodiment of FIG. 4, the circuit of the embodiment of FIG. 1 and the conventional circuit of FIG. 5 are connected in parallel.
【0015】本実施例ではオペアンプ1の出力電圧の最
大は電源電圧VDDまでになっている。出力電流Iou
tは以下の式であらわされる。 Iout=Iout1+Iout2 (3) Iout1=Vin/Rb (0≦Vin<VDD−Vtn) =(VDD−Vtn)/Rb(VDD−Vtn≦Vin≦VDD) (4) Iout2=0 (0≦Vin<Vtn) =(Vin−Vtn)/Rc (Vtn≦Vin≦VDD) (5) ここで、Rbは抵抗3bの抵抗値、Rcは抵抗3cの抵
抗値In this embodiment, the maximum output voltage of the operational amplifier 1 is up to the power supply voltage VDD. Output current Iou
t is represented by the following equation. Iout = Iout1 + Iout2 (3) Iout1 = Vin / Rb (0 ≦ Vin <VDD−Vtn) = (VDD−Vtn) / Rb (VDD−Vtn ≦ Vin ≦ VDD) (4) Iout2 = 0 (0 ≦ Vin <Vtn) = (Vin−Vtn) / Rc (Vtn ≦ Vin ≦ VDD) (5) where Rb is the resistance of the resistor 3b, and Rc is the resistance of the resistor 3c.
【0016】本実施例でも、図1の実施例と同様に入力
電圧Vinが0V〜VDDの範囲で出力電流Ioutを
制御できる。さらに、本実施例では、オペアンプ1に供
給する電圧は電源電圧VDDでよいので、外部から2種
類の電源電圧を供給したり、昇圧回路を追加する必要が
無い。Also in this embodiment, the output current Iout can be controlled when the input voltage Vin is in the range of 0 V to VDD as in the embodiment of FIG. Further, in this embodiment, the voltage supplied to the operational amplifier 1 may be the power supply voltage VDD, so that it is not necessary to supply two kinds of power supply voltages from the outside or add a booster circuit.
【0017】また、本発明では、0≦Vin<Vtnと
VDD−Vtn≦Vin≦VDDの領域のIout/V
inの傾きを、それぞれ抵抗値RbとRcで独立に決め
ることが出来る。このため、入力電圧Vinの領域に応
じて出力電流Ioutの変動を変えることが出来る。例
えば、Rbの値をRcよりも大きくしてやれば、Iou
tが小さい場合のdIout/dVinをIoutが大
きい場合のdIout/dVinよりも小さくできる。
これにより、Ioutが小さい領域での電流制御性がよ
くなる。Further, in the present invention, Iout / V in the region of 0 ≦ Vin <Vtn and VDD−Vtn ≦ Vin ≦ VDD.
The slope of “in” can be independently determined by the resistance values Rb and Rc, respectively. For this reason, the variation of the output current Iout can be changed according to the region of the input voltage Vin. For example, if the value of Rb is made larger than Rc, Iou
dIout / dVin when t is small can be made smaller than dIout / dVin when Iout is large.
As a result, current controllability in a region where Iout is small is improved.
【0018】以上、本発明は実施例に基づいて説明され
たが、本発明は上述の実施例に限定されることなく、特
許請求の範囲に記載される範囲内で、自由に変形・変更
可能である。As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be freely modified and changed within the scope described in the claims. It is.
【0019】[0019]
【発明の効果】以上説明したように本発明の電圧電流変
換回路入力電圧範囲を広くすることが出来き、出力電流
/入力電圧の傾きを小さく出来るので、入力電圧の変動
による出力電流の変動を小さく出来る。また、入力電圧
の領域によって出力電流/入力電圧の傾きを変えること
が出来るので、入力電圧の領域に応じて出力電流の変動
を変えることが出来る。As described above, the input voltage range of the voltage-current conversion circuit of the present invention can be widened, and the output current / input voltage gradient can be reduced. Can be smaller. Further, since the output current / input voltage gradient can be changed depending on the input voltage region, the fluctuation of the output current can be changed according to the input voltage region.
【図1】電圧電流変換回路の実施方法を示した回路図で
ある。(実施例1)FIG. 1 is a circuit diagram showing a method for implementing a voltage-current conversion circuit. (Example 1)
【図2】実施例1の電圧−電流特性を示した図である。FIG. 2 is a diagram showing voltage-current characteristics of Example 1.
【図3】電圧電流変換回路の実施方法を示した回路図で
ある。(実施例2)FIG. 3 is a circuit diagram showing a method for implementing a voltage-current conversion circuit. (Example 2)
【図4】電圧電流変換回路の実施方法を示した回路図で
ある。(実施例3)FIG. 4 is a circuit diagram showing a method for implementing a voltage-current conversion circuit. (Example 3)
【図5】実施例2の電圧−電流特性を示した図である。FIG. 5 is a diagram showing voltage-current characteristics of Example 2.
【図6】従来の電圧電流変換回路の実施方法を示した回
路図である。FIG. 6 is a circuit diagram showing an implementation method of a conventional voltage-current conversion circuit.
【図7】従来の電圧電流変換回路の電圧−電流特性を示
した図である。FIG. 7 is a diagram showing a voltage-current characteristic of a conventional voltage-current converter.
【図8】PLLのブロック図である。FIG. 8 is a block diagram of a PLL.
【図9】<BR>DLLのブロック図である。FIG. 9 is a block diagram of a <BR> DLL.
1 オペアンプ 2a、2b、2c NMOSトランジスタ 3a、3b、3c 抵抗 4 位相周波数比較器 5 チャージポンプ 6 ループフィルタ 7 電圧制御発振器 8 電流電圧変換回路 9 電流制御発振器 10 位相比較器 11 電圧制御遅延線 12 電流制御遅延線 13 昇圧回路 DESCRIPTION OF SYMBOLS 1 Operational amplifier 2a, 2b, 2c NMOS transistor 3a, 3b, 3c Resistance 4 Phase frequency comparator 5 Charge pump 6 Loop filter 7 Voltage control oscillator 8 Current-voltage conversion circuit 9 Current control oscillator 10 Phase comparator 11 Voltage control delay line 12 Current Control delay line 13 Boost circuit
フロントページの続き Fターム(参考) 5H430 BB01 BB09 BB12 EE06 FF08 FF13 GG11 HH03 5J090 AA03 AA42 CA04 CA34 CA81 CN04 FA05 FA10 FA17 FN06 FN10 HA10 HA16 HA25 HN07 KA01 KA02 KA12 KA17 KA18 KA47 MA08 MA13 MA21 TA01 TA02 5J091 AA03 AA42 CA04 CA34 CA81 FA05 FA10 FA17 HA10 HA16 HA25 KA01 KA02 KA12 KA17 KA18 KA47 MA08 MA13 MA21 TA01 TA02 Continued on the front page F-term (reference) 5H430 BB01 BB09 BB12 EE06 FF08 FF13 GG11 HH03 5J090 AA03 AA42 CA04 CA34 CA81 CN04 FA05 FA10 FA17 FN06 FN10 HA10 HA16 HA25 HN07 KA01 KA02 KA12 KA17 KA18 MA03 MA03 MA04 CA81 FA05 FA10 FA17 HA10 HA16 HA25 KA01 KA02 KA12 KA17 KA18 KA47 MA08 MA13 MA21 TA01 TA02
Claims (5)
を会して第1の電位に接続し、ゲートに第1の差動増幅
器の出力を受ける一導電型の第1の絶縁ゲート型電界効
果トランジスタと、第1の入力信号をプラス入力、第1
の絶縁ゲート型電界効果トランジスタのソースをマイナ
ス入力とする第1の差動増幅器を具備することを特徴と
する電圧電流変換回路A drain is an output, a source is connected to a first resistor and connected to a first potential, and a gate is a first insulated gate type of one conductivity type receiving an output of a first differential amplifier. A field-effect transistor, a first input signal having a positive input,
Voltage-current conversion circuit, comprising a first differential amplifier having a source of the insulated gate field effect transistor as a negative input.
力信号の振幅よりも第1の絶縁ゲート型電界効果トラン
ジスタのしきい値電圧以上高いことを特徴とする請求項
1に記載の電圧電流変換回路2. The method according to claim 1, wherein the supply voltage to the first differential amplifier is higher than the amplitude of the first input signal by at least the threshold voltage of the first insulated gate field effect transistor. Voltage-current conversion circuit described
差動増幅器に電源を供給することを特徴とする請求項1
に記載の電圧電流変換回路3. The power supply circuit according to claim 1, further comprising a first booster circuit for supplying power to the first differential amplifier.
Voltage-current conversion circuit described in
を会して第1の電位に接続し、ゲートに第1の入力信号
を受ける一導電型の第2の絶縁ゲート型電界効果トラン
ジスタをさらに具備することを特徴とする請求項1に記
載の電圧電流変換回路4. An insulated gate field effect transistor of one conductivity type having a drain as an output, a source connected to a second resistor and connected to a first potential, and a gate receiving a first input signal. The voltage-current conversion circuit according to claim 1, further comprising:
きいことを特徴とする請求項4に記載の電圧電流変換回
路5. The voltage-current conversion circuit according to claim 4, wherein the value of the first resistor is larger than the value of the second resistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2000153859A JP2001339258A (en) | 2000-05-24 | 2000-05-24 | Voltage-current converting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000153859A JP2001339258A (en) | 2000-05-24 | 2000-05-24 | Voltage-current converting circuit |
Publications (1)
Publication Number | Publication Date |
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JP2001339258A true JP2001339258A (en) | 2001-12-07 |
Family
ID=18659041
Family Applications (1)
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JP2000153859A Pending JP2001339258A (en) | 2000-05-24 | 2000-05-24 | Voltage-current converting circuit |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006235767A (en) * | 2005-02-23 | 2006-09-07 | Nec Corp | Current control circuit with limiter |
US7170763B2 (en) | 2003-12-18 | 2007-01-30 | Richtek Technology Corp. | Apparatus and method for constant delta current control in a capacitor charger |
JP2009112169A (en) * | 2007-10-31 | 2009-05-21 | Honda Motor Co Ltd | Output controlling device of power generator |
CN102354241A (en) * | 2011-07-29 | 2012-02-15 | 美商威睿电通公司 | Voltage/current conversion circuit |
CN102722209A (en) * | 2012-07-12 | 2012-10-10 | 圣邦微电子(北京)股份有限公司 | Constant current source circuit |
-
2000
- 2000-05-24 JP JP2000153859A patent/JP2001339258A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7170763B2 (en) | 2003-12-18 | 2007-01-30 | Richtek Technology Corp. | Apparatus and method for constant delta current control in a capacitor charger |
JP2006235767A (en) * | 2005-02-23 | 2006-09-07 | Nec Corp | Current control circuit with limiter |
JP2009112169A (en) * | 2007-10-31 | 2009-05-21 | Honda Motor Co Ltd | Output controlling device of power generator |
CN102354241A (en) * | 2011-07-29 | 2012-02-15 | 美商威睿电通公司 | Voltage/current conversion circuit |
CN102722209A (en) * | 2012-07-12 | 2012-10-10 | 圣邦微电子(北京)股份有限公司 | Constant current source circuit |
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