JP2001324958A - Electronic device and driving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the problems starting with a lack of brightness caused by a decrease in a duty ratio (the ratio of the emitting period to the non- emitting period) by using a new driving method and circuit in an electronic device. SOLUTION: This method and circuit are characterized in that signals are written in pixels of plural different stages within a period for selecting one gate signal line. In such a manner, in the pixels in a certain stage, a high duty ratio is realized by setting an arbitrary sustain (lighting) period by securing a write time to the pixels and then setting arbitrarily to some extent a time from an input to the next input of a signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electronic device and a method for driving an electronic device. The present invention particularly relates to an active matrix electronic device having a thin film transistor (TFT) formed on an insulating substrate and a method of driving the active matrix electronic device. Among active matrix electronic devices, in particular, EL (Electro Lumine)
The present invention relates to an active matrix type electronic device using self-luminous elements including a scence device and a driving method of the active matrix type electronic device.

[0002] An EL element has a layer containing an organic compound capable of obtaining electroluminescence (electroluminescence generated by applying an electric field) (hereinafter, referred to as an EL layer), an anode, and a cathode. Luminescence of an organic compound includes light emission when returning from a singlet excited state to a ground state (fluorescence) and light emission when returning from a triplet excited state to a ground state (phosphorescence). The present invention can also be applied to a light emitting device using.

[0003] In this specification, all layers provided between an anode and a cathode are defined as EL layers. Specifically, the EL layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer,
An electron transport layer and the like are included. Basically, the EL element has an anode /
It has a structure in which a light emitting layer / cathode is laminated in order. In addition to this structure, an anode / hole injection layer / light emitting layer / cathode or anode / hole injection layer / light emitting layer / electron transport layer / cathode Etc. in some cases.

[0004] In this specification, an element formed by an anode, an EL layer, and a cathode is called an EL element.

[0005]

2. Description of the Related Art In recent years, an EL display has attracted attention as a flat display replacing an LCD (liquid crystal display), and active research has been conducted.

[0006] LCDs are roughly classified into two types as drive systems. One is a passive matrix type used for STN-LCDs and the like, and the other is an active matrix type used for TFT-LCDs and the like. Similarly, in the EL display, there are roughly two types of driving methods. One is a passive type, and the other is an active type.

In the case of the passive type, wirings serving as electrodes are arranged above and below the EL element. Then, a voltage is sequentially applied to the wiring, and a current is caused to flow through the EL element, thereby lighting the element. On the other hand, in the case of the active type, each pixel has a transistor so that a signal can be held in each pixel.

FIG. 2 is a schematic view of an active EL display device.
This is shown in FIG. A source signal line driver circuit 2151, a gate signal line driver circuit 2152, and a pixel portion 2153 are provided over a substrate 2150. The gate signal line drive circuit is
In FIG. 21A, it is arranged on both sides of the pixel portion, but it may be arranged on one side. The signal that drives the display device is a Flexible Print Circuit.
t: FPC) 2154 to each drive circuit.

FIG. 21B is an enlarged view of a part of the pixel portion 2153, and shows 3 × 3 pixels. A portion surrounded by a dotted frame 2100 is one pixel. 2101 is
A TFT (hereinafter, referred to as a switching TFT) that functions as a switching element when writing a signal to a pixel. In FIG. 21, the switching TFT is an n-channel type, but may be a p-channel type. 2102
Denotes a TFT (hereinafter, referred to as EL) which functions as an element (current control element) for controlling a current supplied to the EL element 2103
Driving TFT). When the EL driving TFT is a p-channel type, it is arranged between the anode of the EL element 2103 and the current supply line 2107. As another configuration method, an n-channel type can be used, or an EL element 2103 can be provided between a cathode and a cathode wiring.
However, a p-channel type is used for the EL driving TFT because of the good operation of the transistor and the grounding of the source and the manufacturing restrictions of the EL element 2103.
The method of arranging an EL driving TFT between the anode and the current supply line 2107 is the best, and is widely adopted. 21
Reference numeral 04 denotes a storage capacitor for holding a signal (voltage) input from the source signal line 2106. One terminal of the storage capacitor 2104 in FIG.
7, but a dedicated wiring may be used. The gate electrode of the switching TFT 2101 includes:
The gate signal line 2105 is connected to the source region, and the source signal line 2106 is connected to the source region. In addition, EL driving TFT
One of the source region and the drain region 2102 has an EL
The anode of the element 2103 has a current supply line 2107 on the other side.
Is connected.

E in an active EL display
The operation of the L element will be described. FIG. 22A shows the relationship between the current flowing through the EL element and the luminance of the EL element. FIG.
As can be seen from (A), the luminance of the EL element increases almost directly in proportion to the current flowing through the EL element. Therefore, hereinafter, the current mainly flowing through the EL element will be discussed. Next, FIGS. 22B and 22C show voltage-current characteristics of the EL element. When a voltage exceeding a certain threshold is applied to the EL element, an exponentially large current flows. From another viewpoint, even if the amount of current flowing through the EL element changes, the voltage value applied to the EL element does not change much. On the other hand, if the voltage value applied to the EL element changes even a little, the amount of current flowing through the EL element changes greatly. Therefore, it is difficult to control the amount of current flowing through the EL element, that is, the luminance of the EL element, by controlling the voltage value applied to the EL element. Therefore, in the EL element, the luminance is controlled by controlling the amount of current flowing through the EL element.

Referring to FIG. FIG. 23A shows FIG.
In the pixel portion of the EL element in FIG.
Only the components of the T2102 and the EL element 2103 are shown, and the current supply line 2301, the cathode wiring 23
02, an EL driving TFT 2304, its gate electrode 2303, and an EL element 2305. FIG.
FIG. 23B shows a voltage-current characteristic for analyzing an operating point of the circuit in FIG. Here, the voltage applied to the EL element 2305 is V _EL , the potential of the current supply line 2301 is V _DD , and the potential of the cathode wiring 2302 is V _GND (= 0).
[V]), the source-drain voltage of the EL driving TFT 2304 is V _DS , and the voltage between the gate electrode 2303 of the EL driving TFT 2304 and the current supply line 2301, that is, the gate-source voltage of the EL driving TFT 2304 is V
_GS . Here, in order to clarify the description, it is assumed that the EL driving TFT 2304 is a p-channel TFT, and the source terminal is a higher voltage terminal and the drain terminal is a lower voltage terminal. As can be seen from FIG. 23B, as the absolute value | V _GS | of the gate-source voltage of the EL driving TFT 2304 increases, the current flowing through the EL driving TFT 2304 also increases.

Next, the operating point of the EL circuit will be described. First, in the circuit of FIG.
The FT 2304 and the EL element 2305 are connected in series. Therefore, the current values flowing through both elements (the EL driving TFT 2304 and the EL element 2305) are equal. Therefore,
The operating point of the circuit in FIG. 23A is the intersection of the voltage-current characteristics graph of both elements (FIG. 23B). In FIG. _23B , V _EL is a voltage between V _GND and the potential at the operating point. V _DS is a voltage between V _DD and the potential at the operating point. That is, the voltage from V _DD to V _GND is equal to the sum of V _EL and V _DS .

Here, the case where V _GS is changed will be considered. Since the EL driving TFT 2304 is a p-channel type, the transistor becomes conductive when V _GS becomes lower than the threshold voltage V _th of the EL driving TFT 2304. And V
_{When GS} is further reduced, that is, when the absolute value | V _GS | is further increased, the current value flowing through the EL driving TFT 2304 further increases, and the current value flowing through the EL element 2305 naturally increases. The luminance of the EL element 2305 is
It increases in proportion to the value of the current flowing through the EL element 2305.
However, at that time, V _EL also increases.

In order to analyze the operation in more detail,
First, the EL driving TF when | V _GS |
The operation area of T2304 will be described. In general, the operation of a transistor can be roughly divided into two regions. One is that the current value hardly changes even if the source-drain voltage changes, that is, the saturation region where the current value is determined only by the gate-source voltage (| V _DS
|> | V _GS −V _th |). The other is a linear region (| V _DS | <| V _GS −V _th |) where the current value is determined by the source-drain voltage and the gate-source voltage. Based on the above, the EL driving TFT 2304
Consider the operation area of First, when the current value is low, that is, when | V _GS | is small, the EL driving TFT 2304 operates in a saturation region as illustrated in FIG. Then, as | V _GS | increases, the current value also increases. At the same time, _VEL gradually increases. Therefore, this time, by an amount corresponding to V _EL is increased, V _DS becomes smaller. However, in this case, since the EL driving TFT 2304 operates in the saturation region, the current value hardly changes even if V _DS changes. That is, when the EL driving TFT 2304 operates in the saturation region, the amount of current flowing through the EL element 2305 is:
| V _GS | alone.

Further, | V_GSWhen | is increased, EL
The driving TFT 2304 operates in a linear region.
You. And V_ELAlso grows gradually. Therefore,
V_ELAs much as V_DSIs getting smaller.
In the linear region, V_DSThe smaller the current, the smaller the current
You. Therefore, | V_GSEven if | is increased, the current value
It becomes difficult to increase. And suppose | V_GS| = ∞
Considering that the current value is equal to the current value = I_MAXBecomes Toes
And | V_GSNo matter how large |_MAXMore current
Does not flow. Where I_MAXIs V_ELIs (V_DD-V_GND)
Time (here, V_{GN D}= 0 [V], so V_EL= V
_DD) Is the current value flowing through the EL element 2305.

As a summary of the above operation analysis, | V _GS |
FIG. 24 shows a graph of the value of the current flowing through the EL element when is changed. When | V _GS | is increased and becomes larger than the absolute value | V _th | of the threshold voltage of the EL driving TFT, the EL driving TFT becomes conductive and current starts to flow. At this time, | V _GS | is referred to as a lighting start voltage. And as | V _GS | is further increased,
The current value increases, and eventually the current value saturates.
| V _GS | at that time is referred to as a luminance saturation voltage. As can be understood from FIG. 24, when | V _GS | is smaller than the lighting start voltage, almost no current flows. When | V _GS | is between the lighting start voltage and the luminance saturation voltage, the amount of current changes according to | V _GS |. When | V _GS | is sufficiently larger than the luminance saturation voltage, the current value flowing through the EL element hardly changes. As described above, by changing | V _GS |, the value of the current flowing through the EL element, that is, the luminance of the EL element can be controlled.

Next, the operation of the active EL circuit will be described. FIG. 21 is referred to again.

First, when the gate signal line 2105 is selected, the gate of the switching TFT 2101 opens, and the switching TFT 2101 becomes conductive. Then, the signal (voltage) of the source signal line 2106 is
104. The voltage of the storage capacitor 2104 is EL
Since the voltage between the gate and the source of the driving TFT 2102 becomes V _GS , a current corresponding to the voltage of the storage capacitor 2104 is EL.
It flows to the driving TFT 2102 and the EL element 2103. As a result, the EL element 2103 is turned on. FIG. 23 to FIG.
As mentioned in the description up to 4, the amount of current flowing luminance, that is, the EL elements 2103 of the EL element 2103 can be controlled by V _GS. V _GS is a voltage stored in the storage capacitor 2104, which is the source signal line 210.
6 is a signal (voltage). That is, the source signal line 210
6 by controlling the signal (voltage) of EL element 2
103 is controlled. Finally, the gate signal line 210
5 is not selected, the gate of the switching TFT 2101 is closed, and the switching TFT 2101 is turned off. At that time, the charge stored in the storage capacitor 2104 is held. Therefore, V _GS is maintained as it is and V _GS
A current corresponding to _GS continues to flow through the EL driving TFT 2102 and the EL element 2103.

Regarding the above contents, SID99 Digest: P
372: “Current Status and futureof Light-Emitting
Polymer Display Driven by Poly-Si TFT ”, ASIA DISP
LAY98: P217: “High Resolution Light Emitting Pol
ymer Display Driven by Low Temperature Polysilicon
Thin Film Transistor with Integrated Driver ”, Eu
ro Display99 Late News: P27: “3.8 Green EL wit
h Low Temperature Poly-Si TFT ”etc.

[0020]

Prior to the present invention, a method of gradation display of an EL element will be described. As can be seen from FIG. 24, when the absolute value | V _GS | of the gate voltage of the EL driving TFT is higher than the lighting start voltage and lower than the luminance saturation voltage, the brightness of the EL element is changed by changing the value of | V _GS | That is, the gradation can be controlled in an analog manner. Therefore, this method will be referred to as an analog gradation method.

The analog gray scale method has a drawback that it is weak against variations in the current characteristics of the EL driving TFT. That is,
If the current characteristics of the EL driving TFT are different, the current values flowing through the EL driving TFT and the EL element will be different even if the same gate voltage is applied. As a result, the brightness of the EL element,
That is, the gradation changes. FIG. 25 shows the EL driving T
When the threshold voltage or mobility of the FT changes,
Absolute value of gate voltage | V _GS | of EL driving TFT and EL
4 shows a graph of the current of the device. For example, EL driving TFT
When the threshold voltage of the TFT increases, the voltage (| V _GS | − | V _th |) substantially applied to the gate of the EL driving TFT
, The lighting start voltage increases. When the mobility of the EL driving TFT decreases,
Since the current flowing between the source and the drain of the EL driving TFT becomes small, the slope of the graph becomes small.

In order to reduce the influence of the variation in the characteristics of the EL driving TFT, a method called a digital gradation method has been devised. In this method, the absolute value | V _GS | of the gate voltage of the EL driving TFT is equal to or less than the lighting start voltage (almost no current flows), greater than the luminance saturation voltage (current value is almost I _MAX ), This is a method of controlling the gradation in two states. In this case, the EL driving TF
If the absolute value | V _GS | of the gate voltage of T is set sufficiently higher than the luminance saturation voltage, the current value approaches I _MAX even if the current characteristics of the EL driving TFT vary. Therefore, E
The influence of the variation of the L driving TFT can be extremely reduced. As described above, since the gray scale is controlled in two states of the ON state (bright because the maximum current flows) and the OFF state (dark because no current flows), this method is called a digital gray scale method. ing.

However, in the case of the digital gradation method,
In this state, only two gradations can be displayed. Therefore, a plurality of techniques for increasing the number of gradations in combination with another method have been proposed.

One of them is a method that combines the area gradation method and the digital gradation method. The area gray scale method is a method of controlling the area of a lit portion to output a gray scale. That is, one pixel is divided into a plurality of sub-pixels, and the number and area of the lit sub-pixels are controlled to express gradation. The disadvantage of this method is that it is difficult to increase the resolution and the number of gradations because the number of sub-pixels cannot be increased. For the area gradation method, see Euro Display 99 Late News: P71
: “TFT-LEPD with Image Uniformity by Area Ratio G
ray Scale ”, IEDM 99: P107:“ Technology for Acti
ve Matrix Light Emitting Polymer Displays ”.

As another method for increasing the number of gradations, there is a method of combining a time gradation method and a digital gradation method. The time gradation method controls the lighting time,
This is a method for producing gradation. That is, one frame period is divided into a plurality of sub-frame periods, and the number and length of the lit sub-frame periods are controlled to express gradation.

When the digital gradation method, the area gradation method, and the time gradation method are combined, see IDW'99: P171.
: “Low-Temperature Poly-Si TFT Driven Light-Emitt
ing-Polymer Displays and Digital Gray Scale for Un
iformity ”.

As a method of combining the digital gradation method and the time gradation method, a method filed in Japanese Patent Application No. 11-176521 will be described. Here, as an example, 3
A case where one frame period is divided into three sub-frame periods for bit gradation expression will be described.

Referring to FIG. As shown in FIG.
One frame period is divided into three sub-frame periods (SF). Here, it will be referred to as sub-frame periods of first and SF _1. The second and subsequent sub-frame periods will be similarly referred to as SF ₂ and SF ₃ . One sub-frame period further includes an address (write) period (T
a) and a sustain (lighting) period (Ts).
A sustain (lighting) period of SF ₁ is referred to as Ts _1. Similarly, in the case of SF ₂ and SF ₃ , Ts ₂ ,
It will be referred to as Ts _3.

The operation performed during the address (write) period (Ta) will be described. Please refer to FIG. 21 and FIG. First, the potential difference between the current supply line 2107 and the cathode wiring 2108 is set to 0 [V]. Specifically, the potential of the cathode wiring 2108 is raised to the same potential as the current supply line 2107. Since the cathode wiring 2108 is connected to all pixels, this operation is performed simultaneously for all pixels. The purpose of this operation is to hold the storage capacitor 2 of each pixel.
This is to prevent a current from flowing through the EL element 2103 regardless of the voltage value of the element 104. After that, a signal (voltage) is transferred to the storage capacitor 2 of each pixel through the source signal line 2106.
It accumulates in 104. If the pixel is to be displayed, the absolute value | V _GS | of the gate-source voltage of the EL driving TFT 2101 is set to a voltage sufficiently higher than the luminance saturation voltage. If you don't want the pixels to be displayed,
| V _GS | of the EL driving TFT 2101 is set to a voltage sufficiently lower than the lighting start voltage. Then, the signal (voltage) is accumulated in the storage capacitor 2104 over all the pixels. Thus, the operation in the address (write) period (Ta) is completed.

Next, a sustain (lighting) period (Ts ₁ )
Move on to In the address (writing) period (Ta), the potential difference between the current supply line 2107 and the cathode wiring 2108 was 0 [V]. Therefore, in the sustain (lighting) period (Ts ₁ ), a voltage is applied between the current supply line 2107 and the cathode wiring 2108 simultaneously over all the pixels. As a result, in a pixel where | V _GS | is a voltage sufficiently higher than the luminance saturation voltage, the EL driving TFT 210
1 flows through the EL element 2103, and the EL element starts to light. In pixels where | V _GS | is sufficiently lower than the lighting start voltage, the EL driving TFTs 2101 and E
No current flows through L element 2103, and the element remains dark. After that, the state continues, and the current supply line 2107 is again activated at the end of the sustain (lighting) period (Ts ₁ ).
The potential difference between the cathode wiring 2108 and the cathode wiring 2108 is set to 0 [V]. Naturally, this is performed simultaneously for all pixels. Then, the voltage value of the storage capacitor 2104 of each pixel, that is, | V
Regardless of _GS |, no current flows through the EL element 2103, and the EL element 2103 becomes dark.

The above is the operation in _one subframe period (SF ₁ ). Similar operations are performed in SF ₂ and SF ₃ . However, the length of the sustain (lighting) period differs depending on the subframe period. The length ratio is Ts
_{1: Ts 2: Ts 3 =} 2 2: 2 1: has a ^two-0. In other words, it is set to a power of 2 and sustained (lighted)
The period has been changed. As described above, changing the length of the sustain (lighting) period by a power of 2 is as follows.
This is to make it easier to adapt to digital operations.

Until the end of the address (write) period, a predetermined voltage is applied to the gate of the EL driving TFT 2101, and even if the EL driving TFT 2101 is turned on, the EL element 2103 is not turned on. The EL element 2103 is turned on simultaneously with the start of the sustain (lighting) period. This is for more accurately controlling the length of the sustain (lighting) period. In FIG.
4 shows a timing chart of a potential V _GND of a cathode wiring of an EL element 2103. Since the cathode wiring is connected to all pixels, 2601 in FIG. 26 indicates the potential V _GND of the cathode wiring of all pixels. In the address (writing) period (Ta), the potential of the cathode wiring is equal to or higher than the potential of the current supply line. Then, in the sustain (lighting) period, the potential of the cathode wiring is lowered to
Allow current to flow through the device.

As a method of gradation display, Ts ₁ to Ts ₃
During the sustain (lighting) period up to this, the luminance is controlled by controlling whether or not the EL element is lit. In this example, since 2 ³ = 8 different lighting time lengths can be determined by a combination of sustaining (lighting) periods for lighting, eight gradations can be displayed. Such a method of performing gradation expression using the length of the lighting time is called a time gradation method.

When the number of gradations is further increased, the number of divisions in one frame period may be increased. One frame period
When the period is divided into n subframes, the ratio of the length of the sustain (lighting) period is Ts ₁ : Ts ₂ :
_{Ts (n-1): Ts} n = 2 (n-1): 2 (n-2): ·····
2 ¹ : 2 ⁰ , which makes it possible to express 2 ⁿ gradations.

However, gradation display is possible even when the length of the sustain (lighting) period is not necessarily a ratio of a power of two.

The reason why the subframe period is divided into the address (writing) period and the sustain (lighting) period is that the length of the sustain (lighting) period can be freely set. . That is, by separating the periods, a sustain (lighting) period shorter than the address (writing) period can be set. If the periods are not separated, if the sustain (lighting) period is short, the address (writing) period may overlap with the address (writing) period of another subframe period, and signal writing may be performed normally. Will not be done.

[0037]

Next, mainly, Japanese Patent Application No. Hei.
In the case of a technique filed in Japanese Patent Application No. 1-176521, that is, in a case where a multi-gradation is achieved by combining a time gradation method and a digital gradation method, a method of separating an address (writing) period and a sustain (lighting) period is described below. The problem is described.

First, an address (write) period (Ta)
Then, the EL element does not light. Therefore, the ratio of the display period in one entire frame period (this is called a duty ratio) becomes small. If the ratio of the total time of the sustain (lighting) period (Ts) in one frame period is half, that is, if the duty ratio is 50 [%], it is half that in the case where the duty ratio is 100 [%]. Only brightness can be obtained. If it is desired to obtain a luminance equivalent to 100%, it is necessary to double the luminance when shining during the sustain (lighting) period, that is, the instantaneous luminance. For that purpose, it is necessary to pass twice the current to the EL element.

The second problem is that it is necessary to end the writing of signals to all the pixels during the address (writing) period (Ta), so that it is necessary to operate the circuit at high speed. . When the operation of the circuit is slow, the address (write) period (Ta) becomes long. As a result, the duty ratio becomes small, causing various problems. In addition, when the circuit operates at high speed, the power consumption increases, which is a problem.

The third problem is that it is difficult to increase the number of pixels. This is because the address (writing) period (Ta) becomes longer by increasing the number of pixels. As a result, the duty ratio becomes small.

The fourth problem is that it is difficult to increase the number of gradations. Because, in order to increase the number of gradations, it is necessary to increase the number of divisions in the subframe period. As a result, the number of address (write) periods (Ta) increases, and the duty ratio decreases.

According to the above-mentioned problems, it can be said that most of the problems are caused by insufficient luminance due to a decrease in the duty ratio. The present invention has been made in view of the above-described problems, and by using a novel driving method,
It is an object of the present invention to improve the duty ratio and to secure a sufficient sustain (lighting) period even when the operating frequency of the drive circuit is low, thereby achieving good image quality.

[0043]

According to the driving method of the present invention, a gate signal line selection period is divided into a plurality of sub-periods, so that signals are written to a plurality of different pixels in one gate signal line selection period. There is a feature in the point. Thus, in a pixel at a certain stage, the time from the input of a signal to the input of the next signal can be arbitrarily set to some extent as long as the writing time to the pixel is secured. That is, since the sustain (lighting) period can be arbitrarily set, the duty ratio is set to an apparent maximum of 100.
It can be increased to [%]. Therefore, various problems caused by a small duty ratio can be avoided.

The driving method of the present invention is characterized in that the EL element can be turned on even during the address (writing) period. Therefore, even when the address (writing) period is extended, the sustain (lighting) is performed.
It is possible to avoid pressing the period. That is, even when the circuit operation is slow, a sufficient sustain (lighting) period can be ensured. As a result, the operating frequency of the drive circuit can be kept low, and power consumption can be reduced.

The configuration of the electronic device and the method of driving the electronic device according to the present invention will be described below.

The drive of the electronic device according to the first aspect of the present invention.
According to the operation method, one frame period is composed of n subframes.
Time period SF₁, SF_Two, ..., SF_nAnd n
Each of the sub-frame periods is an address (write)
Period Ta₁, Ta_Two, ..., Ta_nAnd the sustain (dot
Light) period Ts₁, Ts_Two, ... Ts_nAnd the
The length of the stain (lighting) period is Ts₁: Ts_Two,: ・ ・
・ ： Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2⁰As self
N-bit gradation control by controlling the length of the light-emitting element lighting time
In the driving method of an electronic device for controlling,
At least one of the subframes in a frame period
In the period, the address (write) period and the
The stain (lighting) period has overlapping periods
Is also good.

The drive of the electronic device of the present invention according to claim 2
According to the operation method, one frame period is composed of n subframes.
Time period SF₁, SF_Two, ... SF_nWith n previous
Each sub-frame period is an address (write) period
Between Ta₁, Ta_Two, ... Ta_nAnd sustain (lit)
Period Ts₁, Ts_Two, ... Ts_nAnd the sustainer
The length of the in (lighting) period is Ts₁: Ts_Two,: ...:
Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2⁰As self-luminous
N-bit gradation control by controlling the length of element lighting time
In the method of driving an electronic device, the sub-frame period
A plurality of sub-gates in which a plurality of gate signal line selection periods are between
A signal line selection period, wherein the sub-gate signal line selection period
At most, writing to at most one gate signal line
Writing of signals to at most m gate signal lines
Is completed within one gate signal line selection period.
You may make it.

The drive of the electronic device of the present invention according to claim 3.
According to the operation method, one frame period is composed of n subframes.
Time period SF₁, SF_Two, ... SF_nWith n previous
Each sub-frame period is an address (write) period
Between Ta₁, Ta_Two, ... Ta_nAnd sustain (lit)
Period Ts₁, Ts_Two, ... Ts_nAnd the sustainer
The length of the in (lighting) period is Ts₁: Ts_Two,: ...:
Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2⁰As self-luminous
N-bit gradation control by controlling the length of element lighting time
In the method of driving an electronic device, the sub-frame period
A plurality of sub-gates in which a plurality of gate signal line selection periods are between
A signal line selection period, wherein the sub-gate signal line selection period
At most, writing to at most one gate signal line
Writing of signals to at most m gate signal lines
Is completed within one gate signal line selection period.
The same within the different sub-gate signal line selection periods.
The write periods of the gate signal lines do not overlap and are the same
Within the sub-gate signal line selection period.
Even if the write periods of the
No.

The drive of the electronic device of the present invention according to claim 4.
According to the operation method, one frame period is composed of n subframes.
Time period SF₁, SF_Two, ... SF_nWith n previous
Each sub-frame period is an address (write) period
Between Ta₁, Ta_Two, ... Ta_nAnd sustain (lit)
Period Ts₁, Ts_Two, ... Ts_nAnd the sustainer
The length of the in (lighting) period is Ts₁: Ts_Two,: ...:
Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2⁰As self-luminous
N-bit gradation control by controlling the length of element lighting time
In the method of driving an electronic device, the sub-frame period
A plurality of sub-gates in which a plurality of gate signal line selection periods are between
A signal line selection period, wherein the sub-gate signal line selection period
At most, writing to at most one gate signal line
Writing of signals to at most m gate signal lines
Is completed within one gate signal line selection period.
The address (write) in the different sub-frame period.
If the addresses overlap, the address (write
Only) The reset signal is input only during the overlapping period.
While the reset signal is being input,
May have a period in which the LED is in a non-lighting state.

According to a fifth aspect of the present invention, there is provided an electronic device comprising:
A source signal line drive circuit and a gate signal line drive circuit
Pixel units in which the number of self-luminous elements are arranged in a matrix.
An electronic device having one frame period of n
Subframe period SF₁, SF_Two, ... SF_nHas,
Each of the n subframe periods has an address (write
Including) period Ta₁, Ta_Two, ... Ta_nAnd the sustain
(Lighting) period Ts₁, Ts_Two, ... Ts_nAnd having
The length of the sustain (lighting) period is Ts₁: Ts_Two,:
...: Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2⁰age
Thus, the length of the lighting time of the self-luminous element is controlled to
In an electronic device for performing gradation control, n sub-frames may be used.
At least one of the sub-frame periods in a frame period
The address (write) period and the sustain
It is special that there is a period in which the
It is a sign.

The electronic device of the present invention according to claim 6 is
A source signal line drive circuit and a gate signal line drive circuit
Pixel units in which the number of self-luminous elements are arranged in a matrix.
An electronic device having one frame period of n
Subframe period SF₁, SF_Two, ... SF_nHas,
Each of the n subframe periods has an address (write
Including) period Ta₁, Ta_Two, ... Ta_nAnd the sustain
(Lighting) period Ts₁, Ts_Two, ... Ts_nAnd having
The length of the sustain (lighting) period is Ts₁: Ts_Two,:
...: Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2⁰age
Thus, the length of the lighting time of the self-luminous element is controlled to
In an electronic device that performs gradation control, within the subframe period
The plurality of gate signal line selection periods have m sub-gates.
A signal line selection period, wherein the sub-gate signal line selection period
At most, writing to at most one gate signal line
Writing of signals to at most m gate signal lines
Is completed within one gate signal line selection period.
It is characterized by that.

The electronic device according to the present invention described in claim 7 is:
A source signal line drive circuit and a gate signal line drive circuit
Pixel units in which the number of self-luminous elements are arranged in a matrix.
An electronic device having one frame period of n
Subframe period SF₁, SF_Two, ... SF_nHas,
Each of the n subframe periods has an address (write
Including) period Ta₁, Ta_Two, ... Ta_nAnd the sustain
(Lighting) period Ts₁, Ts_Two, ... Ts_nAnd having
The length of the sustain (lighting) period is Ts₁: Ts_Two,:
...: Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2⁰age
Thus, the length of the lighting time of the self-luminous element is controlled to
In the electronic device for performing gradation control, the sub-frame period
A plurality of sub-gates in which a plurality of gate signal line selection periods are between
A signal line selection period, wherein the sub-gate signal line selection period
At most, writing to at most one gate signal line
Writing of signals to at most m gate signal lines
Is completed within one gate signal line selection period.
The same within the different sub-gate signal line selection periods.
The write periods of the gate signal lines do not overlap and are the same
Within the sub-gate signal line selection period.
The feature is that the write period of the signal line does not overlap
I have.

The electronic device according to the present invention described in claim 8 is:
A source signal line drive circuit and a gate signal line drive circuit
Pixel units in which the number of self-luminous elements are arranged in a matrix.
An electronic device having one frame period of n
Subframe period SF₁, SF_Two, ... SF_nHas,
Each of the n subframe periods has an address (write
Including) period Ta₁, Ta_Two, ... Ta_nAnd the sustain
(Lighting) period Ts₁, Ts_Two, ... Ts_nAnd having
The length of the sustain (lighting) period is Ts₁: Ts_Two,:
...: Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2⁰age
Thus, the length of the lighting time of the self-luminous element is controlled to
In an electronic device that performs gradation control, within the subframe period
Sub-gate signals for which the plurality of gate signal line selection periods are m
A line selection period, and during the sub-gate signal line selection period,
In most cases, writing to at most one gate signal line is performed.
Signal writing to at most m gate signal lines
Completed within one of the gate signal line selection periods,
The address (write) period of the sub-frame period
Address overlap, the address (write) period
The reset signal is input only during the
The self-light-emitting element is not lit while the reset signal is being input.
It is characterized by having a period that becomes

According to the ninth aspect of the present invention, there is provided an electronic device comprising:
A source signal line driver circuit, a gate signal line driver circuit, and a pixel portion in which a plurality of self-luminous elements are arranged in a matrix of a rows and b columns, wherein the source signal line driver circuit has at least one A plurality of source driver circuits each including a first shift register circuit, a first storage circuit that stores a digital video signal, and a second storage circuit that stores an output signal of the first storage circuit; The gate signal line driving circuit includes at least one second shift register circuit;
Be using a plurality of gate driver circuit having at least one buffer circuit, one frame period n subframe periods SF _1, SF _2, has a · · · SF _n,
A plurality of gate signal line selection periods in the sub-frame period have m sub-gate signal line selection periods, and writing is performed on at most one gate signal line in the sub-gate signal line selection period, In an electronic device in which writing of signals to at most m gate signal lines is completed within one gate signal line selection period, one source signal line is connected to the maximum through the first switch circuit. The source signal line drive circuit is electrically connected to m source driver circuits, and one gate signal line is electrically connected to up to m gate driver circuits via a second switch circuit. The circuit has a maximum of b × m source driver circuits, the gate signal line drive circuit has a maximum of a × m gate driver circuits, and the first switch circuit has one dot data. In the data writing period, only one of the m electrically connected source driver circuits is selected and connected to the source signal line to perform signal writing, and the second switch circuit includes: In one sub-gate signal line selection period, only one of the m electrically connected gate driver circuits is selected and connected to the gate signal line to write a signal. .

[0055]

FIG. 27 shows an embodiment of the present invention. FIG. 27A is an overall view of an electronic device, which includes a source signal line driver circuit 2751, a gate signal line driver circuit 2752, and a pixel portion 2753. As a feature of the present invention, the gate signal line selection period is divided into a plurality of sub-periods. For this reason, the gate signal line driving circuit is similar to the conventional one from the shift register circuit to the buffer. Between the output terminal and the gate signal line. A clock signal, a start pulse, and the like are input to the shift register circuit (not shown), and a sub-gate period selection pulse is input from a pin 11 to the selection circuit. The source signal line driving circuit may be the same as the conventional one, and receives a clock signal, a start pulse, and the like (not shown).

The operation of the selection circuit will be described with reference to FIGS. FIG. 27B illustrates an example of a selection circuit used to divide a gate signal line selection period into two sub-gate signal line selection periods. FIG.
It is an example of a selection circuit used when dividing a gate signal line selection period into three sub-gate signal line selection periods. In any of the circuits, the buffer output pulse has a
By taking the logical product of each of the NAND circuits with the sub-gate period selection pulse input to the D circuit and input from the pin 11 (in FIG. 27, a plurality of pins are indicated as 11A, 11B and 11C to 11E). , The sub-period is divided. According to the timing charts shown in FIGS. 27B and 27C, the NAND output is output to the gate signal line via the inverter, and the gate signal line is set to the selected state for a certain period. Note that in FIG. 27, depending on the logic of the signal, an inverter, a buffer, or the like may be provided as appropriate, or a structure without the inverters 2703 and 2707 may be employed.

By doing so, when a certain gate signal line selection period is used as a reference unit, two different gate signal line selection periods can be provided in the same gate signal line selection period.

As an example, a case where the gate signal line selection period is divided into two sub-gate signal line selection periods will be described. FIG. 28 shows a timing chart. Since the number of sub-gate signal line selection periods is two, the same number of two stages of gate signal lines are simultaneously selected during the gate signal line selection period.

In a certain gate signal line selection period, it is assumed that the i-th gate signal line and the k-th gate signal line are simultaneously selected. However, the period during which the gate signal line of the i-th stage is actually selected and the switching TFT is in the conductive state is only the sub-gate signal line selection period in the first half of the gate signal line selection period. Further, the period during which the gate signal line of the k-th stage is actually selected and the switching TFT is in the conductive state is only the sub-gate signal line selection period in the latter half of the gate signal line selection period. In the first half of the gate signal line selection period, that is, when the i-th gate signal line is selected, a signal is written to the i-th pixel. In the latter half of the gate signal line selection period, that is, when the k-th gate signal line is selected, a signal is written to the k-th pixel.

Subsequently, the gate signal lines of the (i + 1) th stage and the (k + 1) th stage are similarly selected. Also in this case, the gate signal line of the (i + 1) th stage is selected only during the first half of the gate signal line selection period, and the gate signal line of the (k + 1) th stage is the second half of the gate signal line selection period. Only selected in. When the (i + 1) th gate signal line is selected, a signal is written to the (i + 1) th pixel. When the (k + 1) th gate signal line is selected, a signal is written to the (k + 1) th pixel. Similarly, the gate signal lines of the (i + 2) th stage and the (k + 2) th stage are selected, and writing is performed on the pixel at each timing. Here, the gate signal line selection pulse that has selected the i + n (n is an integer) stage from the i-th stage is the first gate signal line selection pulse, and the k + n (n is an integer) stage is selected from the k-th stage. The selected gate signal line selection pulse is referred to as a second gate signal line selection pulse.

When the scanning has progressed to a certain point, the first gate signal line selection pulse arrives at the k-th stage gate signal line. Similarly, the second gate signal line selection pulse eventually reaches the i-th gate signal line. Scanning subsequently proceeds, and vertical scanning is performed.

The above is the case where the gate signal line selection period is divided into two sub-gate signal line selection periods and two gate signal lines are selected. M within one gate signal line selection period
When a gate signal line of a stage (m is an integer) is selected, the gate signal line selection period may be divided into m in a similar manner to provide a sub-gate signal line selection period.

Next, the gradation method will be described. In the electronic device of the present invention, the gray scale expression is performed by combining the digital gray scale with the time gray scale. However, as long as the normal gray scale expression is performed, another method such as an area gray scale method is used. Further, they may be combined.

Here, for the sake of simplicity, a case where a 3-bit gray scale (2 ³ = 8 gray scales) is expressed by combining a digital gray scale and a time gray scale will be described. FIG. 1 (A),
(B) shows a timing chart. One frame period is divided into _three sub-frame periods SF _{1 to} SF ₃ . SF
Each length of _{1 to} SF ₃ is determined by a power of two. That is, in this case, SF ₁ : SF ₂ : SF ₃ = 4: 2: 1 (2 ² : 2
¹ : 2 ⁰ ).

First, in the first sub-frame period,
Signals are input to the pixels step by step. However, in this case,
The gate signal line is actually selected only in the first half sub-gate signal line selection period. During the latter half of the sub-gate signal line selection period, no gate signal line is selected, and no signal is input to the pixel. This operation is performed from the first stage to the last stage. Here, the address (write) period is
This is a period from when the first-stage gate signal line is selected to when the last-stage gate signal line is selected. Therefore, the length of the address (write) period is the same in any subframe period.

Subsequently, a second sub-frame period is entered.
Here, similarly, signals are input to the pixels one by one. Also in this case, the operation is performed only in the first half sub-gate signal line selection period. This operation is performed from the first stage to the last stage.

At this time, a constant voltage is applied to the cathode wires of all the pixels. Therefore, the sustain (lighting) period of a pixel in a certain subframe period is a period from when a signal is written to a pixel in a certain subframe period to when a signal is started to be written to the pixel in the next subframe period. Therefore, the sustain (lighting) period in each stage is different in time and equal in length.

Next, the third sub-frame period will be described. First, as in the first and second sub-frame periods, a case where a gate signal line is selected in the first half sub-gate signal line selection period and a signal is written to a pixel will be considered. In this case, when the writing of the signal to the pixel near the last stage starts, the writing period to the first stage pixel in the next frame period, that is, the address (writing)
It has entered the period. As a result, writing to pixels near the last stage in the third sub-frame period and writing to certain pixels in the first half of the first sub-frame period in the next frame period overlap. At the same time, signals of two different stages cannot be normally written to pixels of two different stages. Therefore, in the third sub-frame period, the gate signal lines are selected in the latter sub-gate signal line selection period. Then, in the first sub-frame period (the sub-frame period belongs to the next frame period), the selection of the gate signal line is performed in the first half of the sub-gate signal line selection period. Can be prevented from being written to.

As described above, according to the driving method of the present invention, when the address (write) period in one sub-frame period overlaps the address (write) period in another sub-frame period, a plurality of sub-gate signal line selections are performed. By allocating the writing period by using the period, a signal can be normally written to the pixel so that the selection timing of the gate signal line does not actually overlap. As a result, at a certain moment during an address (writing) period in one row, it is possible to turn on the EL element in another row regardless of the number of gray scale bits, thereby realizing a high duty ratio.

[0070]

Embodiments of the present invention will be described below.

[Embodiment 1] In this embodiment, as an example, there is a case where, when one frame period is divided, there are a plurality of sustain (lighting) periods (sub-frame periods) shorter than an address (writing) period. Will be explained.

Referring to FIGS. 2A and 2B. FIG.
5 shows a timing chart when a frame period is divided into five sub-frame periods. In this case, the first half of the gate signal line selection period, even if the writing of the signal by dividing the second half of the sub-gate signal line selection period, Ta ₁ address (writing) period Ta ₅ and the next frame period are overlapping I understand. Therefore, at this timing, signal writing cannot be performed normally.

One method is to use a long subframe period.
And the order of short subframe periods
This can solve this problem. FIG. 3 (A),
Refer to (B). FIG. 3 shows one frame period as in FIG.
Is divided into five subframe periods.
Chart. The order of the subframe period is SF
₁→ SF_Four→ SF_Three→ SF_Two→ SF_FiveAs
Gate signal line selection is performed in the first and second half of the gate signal line selection period.
By assigning the timing appropriately, the same sub game
In the signal line selection period, the address (write) period
It can be seen that no overlap has occurred (FIG. 3 (B)). each
Length of subframe period and address (write) period
The height is the same as that shown in FIG.
Write to pixels normally by using the method
be able to. In the method of the present embodiment, the circuit side
Implementation is possible without any changes.

[Embodiment 2] In this embodiment, Embodiment 1
The overlap of the address (write) period described in
A method of avoiding this by means different from that described above will be described.

In FIG. 2, the overlapping address (writing) period is Ta ₅ and Ta _{1 in the} next frame period.
Met. Therefore, the gate signal line selection period is divided into three sub-gate signal line selection periods, and signal writing is performed.
The solution is achieved by allocating to the first, second, and third sub-gate signal line selection periods. Referring to FIGS. 4A and 4B. In the first sub-gate signal line selection period, T
a ₁ , Ta ₂ , and Ta ₃ , and a signal is written in Ta ₄ during the second sub-gate signal line selection period, and a signal is written in Ta ₅ during the third sub-gate signal line selection period. I do. As a result, FIG.
Signal writing is performed at the timing shown in FIG. 2B, and duplication of a plurality of address (writing) periods in each sub-gate signal line selection period can be avoided.

According to the method described in the present embodiment, the sub-gate signal line selection period is shortened and the signal writing time is reduced by the increase in the number of divisions of the gate signal line selection period. This method is effective when the method cannot cope with the problem (for example, when the address (writing) period is long and there is an overlapping portion even if the order is rearranged).

[Embodiment 3] In this embodiment, a method of avoiding overlapping address (write) periods by means different from those in the first and second embodiments will be described.

Referring to FIGS. 5A and 5B. SF ₄ ,
Since SF ₅ itself has a short period, overlapping of address (writing) periods cannot be avoided at normal timing. Therefore, reset periods Tr ₄ and Tr ₅ are provided after each of SF 4 and SF ₅ . During the reset period, E
A signal is input so that the L element does not light. Specifically, the voltage to be written may be a voltage at which no charge is accumulated in the storage capacitor. Hereinafter, this signal is referred to as a reset signal. By changing the time from when the signal is written to the pixel to when the reset signal is input, the lengths of the sub-frame periods SF ₄ and SF ₅ are adjusted, and the address (writing) period and the reset period overlap. The timing should be no.

When the method described in this embodiment is used, since the EL element is not turned on until the next address (write) period appears after the reset signal is input, there arises a problem that the duty ratio slightly decreases. However, the reset signal used in this embodiment can also be used for the purpose of time adjustment when the sustain (lighting) period does not fit within one frame period.

[Embodiment 4] In Embodiments 1 to 3, a method for avoiding overlapping address (writing) periods by adjusting the timing of a drive signal by the circuit configuration shown in the embodiment has been described. Was. In this embodiment, a case where a circuit is configured by adding a gate signal line and a switching TFT will be described. As a specific example, a case where one gate signal line selection period is divided into two sub-gate signal line selection periods will be described.

Referring to FIG. On the substrate 650,
Source signal line drive circuit 651, gate signal line drive circuit 6
52, and a pixel portion 653 are arranged. In FIG. 6, the gate signal line driving circuit 652 is arranged on both sides, but may be arranged on only one side. A feature of the circuit shown in this embodiment is that two gate signal lines are provided for each pixel row. Here, FIG. 34 shows a detailed diagram of a driver circuit in the electronic device shown in FIG. FIG.
(A) is a source signal line driving circuit, and a series of paths from a shift register to a NAND to a first latch circuit to a second latch circuit to a buffer to a source signal line may be the same as the conventional one.

FIG. 34B shows a gate signal line driving circuit. The shift register to the buffer output may be the same as the conventional circuit. The buffer output is input to the two NAND circuits, and in each of the NAND circuits, the logical product of the buffer output and the sub-gate period selection pulse input from pins 9 and 10 is output to the gate signal lines (GatLine A and B). . This may be regarded as the same operation as that shown in FIG. That is, during one gate signal line selection period, sub-gate signal line selection pulses are sequentially output from the two NAND circuits.

FIG. 6B is an enlarged view of the pixel portion. The portion surrounded by the dotted frame 600 is one pixel,
A first switching TFT 601, a second switching TFT 602, an EL driving TFT 603, an EL element 604, a storage capacitor 605, a first gate signal line 606,
A second gate signal line 607, a source signal line 608, and a current supply line 609 are provided. A selection pulse from Gate Line A shown in FIG. 34B is input to the first gate signal line 606, and a selection pulse from Gate Line B is input to the second gate signal line 607. (Or vice versa).

As an example of the driving method, when the gate signal line selection period is divided into two sub-gate signal line selection periods as in the first embodiment, the input of the selection signals of the first half and the second half of the gate signal line is made two times. Two switching TFTs are sufficient. When a gate signal line is selected in the first half sub-gate signal line selection period, a signal is input from the first gate signal line 606 to drive the first switching TFT 601, and the gate signal is supplied in the second half sub-gate signal line selection period. When a line is selected, a signal may be input from the second gate signal line 607 to drive the second switching TFT 602.

[Embodiment 5] In this embodiment, an example in which an EL (electroluminescence) display device having a drive circuit of the present invention is manufactured will be described.

FIG. 7A is a top view of an EL display device using the present invention. In FIG. 7A, reference numeral 4001 denotes a substrate, 4002 denotes a pixel portion, 4003 denotes a source signal line driver circuit, and 4004 denotes a gate signal line driver circuit. The respective driver circuits are connected to the FPC 4008 via wirings 4005, 4006, and 4007. To the external device.

At this time, the cover member 400 is formed so as to surround at least the pixel portion, preferably the drive circuit and the pixel portion.
9, a sealing material 4010, and a sealing material (also referred to as a housing material) 4011 (shown in FIG. 7B).

FIG. 7B shows a cross-sectional structure of the EL display device of this embodiment, in which a TFT for a driving circuit (here, an n-channel TFT) is provided on a substrate 4001 and a base film 4012.
A CMOS circuit combining an FT and a p-channel TFT is shown) 4013 and a TFT 4014 for a pixel portion
(However, here, only the EL driving TFT for controlling the current to the EL element is shown). These TFTs may use a known structure (top gate structure or bottom gate structure).

Using a known manufacturing method, a TFT for a driving circuit
4013, when the pixel portion TFT 4014 is completed, a pixel electrode 4016 made of a transparent conductive film electrically connected to the drain of the pixel portion TFT 4014 is formed on an interlayer insulating film (flattening film) 4015 made of a resin material. As the transparent conductive film, a compound of indium oxide and tin oxide (IT
O) or a compound of indium oxide and zinc oxide. Then, the pixel electrode 4016
Is formed, an insulating film 4017 is formed, and the pixel electrode 40 is formed.
An opening is formed on 16.

Next, an EL layer 4018 is formed. The EL layer 4018 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

In this embodiment, the EL layer 4018 is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display is possible. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, and any method may be used. Of course, monochromatic EL
It can also be a display device.

After forming the EL layer 4018, a cathode 4019 is formed thereon. Cathode 4019 and EL layer 4018
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4018 and the cathode 40
It is necessary to devise a method of continuously forming the film 19 or forming the EL layer 4018 in an inert atmosphere and forming the cathode 4019 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, as the cathode 4019,
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed on the EL layer 4018 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4019 is connected to the wiring 4007 in a region indicated by 4020. A wiring 4007 is a power supply line for applying a predetermined voltage to the cathode 4019,
It is connected to the FPC 4008 through the conductive paste material 4021.

In the region indicated by 4020, the cathode 40
In order to electrically connect the wiring 19 and the wiring 4007, it is necessary to form a contact hole in the interlayer insulating film 4015 and the insulating film 4017. These are at the time of etching the interlayer insulating film 4015 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4017 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 17, etching may be performed all at once up to the interlayer insulating film 4015. In this case, the interlayer insulating film 40
If the insulating resin 4015 and the insulating film 4017 are made of the same resin material, the shape of the contact hole can be improved.

The passivation film 4022 and the filler 402 cover the surface of the EL element thus formed.
3. A cover material 4009 is formed.

Further, a sealing material 4 is placed inside the cover 4009 and the substrate 4001 so as to surround the EL element portion.
011 is provided, and a sealing material (second sealing material) 4010 is formed outside the sealing material 4011.

At this time, the filler 4023 also functions as an adhesive for bonding the cover member 4009.
As the filler 4023, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 4023 because a moisture absorbing effect can be maintained. Further, by disposing an antioxidant or the like having an effect of capturing oxygen inside the filler 4023, deterioration of the EL layer may be suppressed.

Further, a spacer may be contained in the filler 4023. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 4022 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 4009, a glass plate, an aluminum plate, a stainless steel plate, FRP (Fibergla
ss-Reinforced Plastics) plate, PVF (polyvinyl fluoride) film, mylar film, polyester film or acrylic film can be used. When PVB or EVA is used as the filler 4023, it is preferable to use a sheet having a structure in which aluminum foil of several tens [μm] is sandwiched between PVF films or mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 4009 needs to have translucency.

The wiring 4007 is made of a sealing material 401.
1 and the sealant 4010 and the substrate 4001, and electrically connected to the FPC 4008. Although the wiring 4007 has been described here, the other wiring 4007
5 and 4006 are also electrically connected to the FPC 4008 under the sealant 4011 and the sealant 4010 in the same manner.

In this embodiment, the sealing material 4011 is attached so as to cover the side surface (exposed surface) of the filling material 4023 after the filling material 4023 is provided and the cover material 4009 is adhered. Lumber 40
After attaching 11, the filler 4023 may be provided. In this case, an injection hole for a filler is provided to communicate with a space formed by the substrate 4001, the cover material 4009, and the sealing material 4011. Then, the gap is vacuumed (10
^-2 [Torr] or less), immerse the injection port in the water tank containing the filler, and then make the pressure outside the gap higher than the pressure inside the gap to fill the gap with the filler. .

[Embodiment 6] In this embodiment, an example in which an EL display device having a form different from that of Embodiment 5 is manufactured will be described with reference to FIG.
This will be described using (A) and (B). FIG. 7 (A), (B)
Those having the same numbers as those in FIG. 4 indicate the same parts, and thus description thereof will be omitted.

FIG. 8A is a top view of the EL display device of this embodiment, and FIG. 8B is a cross-sectional view of FIG. 8A taken along the line AA ′.

In accordance with Embodiment 5, a passivation film 4022 is formed to cover the surface of the EL element.

Further, a filler 4023 is provided so as to cover the EL element. The filler 4023 is used for the cover material 4
It also functions as an adhesive for bonding 009. As the filler 4023, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 4023 because a moisture absorbing effect can be maintained. Further, by disposing an antioxidant or the like having an effect of capturing oxygen inside the filler 4023, deterioration of the EL layer may be suppressed.

Further, a spacer may be contained in the filler 4023. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 4022 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

The cover material 4009 may be a glass plate, an aluminum plate, a stainless steel plate, FRP (Fiberga
ss-Reinforced Plastics) plate, PVF (polyvinyl fluoride) film, mylar film, polyester film or acrylic film can be used. When PVB or EVA is used as the filler 4023, it is preferable to use a sheet having a structure in which aluminum foil of several tens [μm] is sandwiched between PVF films or mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

Next, the cover material 4
After bonding 009, the side surface (exposure surface) of the filler 4023
The frame member 4024 is attached so as to cover the. The frame material 4024 is a sealing material (functioning as an adhesive)
Adhered by 4025. At this time, a photocurable resin is preferably used as the sealing material 4025, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that it is preferable that the sealing material 4025 be a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 4025.

The wiring 4007 is made of a sealing material 402.
5 is electrically connected to the FPC 4008 through a gap between the substrate 5 and the substrate 4001. Note that although the wiring 4007 is described here, the other wirings 4005 and 4006 similarly pass under the sealing material 4025 and are electrically connected to the FPC 4008.

In this embodiment, the frame member 4024 is attached so as to cover the side surface (exposed surface) of the filler material 4023 after the filler material 4023 is provided and then the cover material 4009 is bonded. Lumber 4025
And after attaching the frame material 4024,
23 may be provided. In this case, the substrate 4001, the cover material 4009, the sealing material 4025, and the frame material 40
An inlet for the filler material is provided to communicate with the void formed at 24. Then, the gap was evacuated to a vacuum state (10 ^-2 [Torr] or less), and the inlet was immersed in a water tank containing the filler.
Fill the voids with the filler.

[Embodiment 7] Here, a more detailed sectional structure of a pixel portion in an EL display panel is shown in FIG. 9, a top structure is shown in FIG. 10A, and a circuit diagram is shown in FIG. 10B. In FIGS. 9, 10A and 10B, a common reference numeral is used, so that they may be referred to each other.

In FIG. 9, as a switching TFT 4502 provided on a substrate 4501, an n-channel TFT formed by a known method is used. In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, there is an advantage that the double gate structure has a structure in which two TFTs are substantially connected in series, and the off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. Further, it may be formed using a p-channel TFT formed by a known method.

Further, as the EL driving TFT 4503, an n-channel TFT formed by a known method is used. A drain wiring 4504 of the switching TFT 4502 is electrically connected to a gate electrode 4506 of the EL driving TFT 4503 by a wiring 4505. Also, 4507
The wiring shown by is a gate wiring for electrically connecting the gate electrodes 4508 and 4509 of the switching TFT 4502.

The EL driving TFT 4503 includes the EL element 45.
Since it is an element for controlling the amount of current flowing through 10,
A large amount of current flows, and the element has a high risk of deterioration due to heat or hot carriers. Therefore, a structure in which an LDD region is provided on the drain side of the EL driving TFT 4503 so as to overlap the gate electrode with a gate insulating film interposed therebetween is extremely effective.

In this embodiment, the EL driving TFT 45 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

As shown in FIG. 10A, a wiring 4 including a gate electrode 4506 of an EL driving TFT 4503 is formed.
Reference numeral 505 denotes an area indicated by 4511, which is a TF for driving EL.
It overlaps with the drain wiring 4512 of T4503 via an insulating film. At this time, a storage capacitor is formed in a region indicated by 4511. The storage capacitor 4511 is connected to the current supply line 451
3, an insulating film (not shown) in the same layer as the gate insulating film, and a wiring 4505 electrically connected to the semiconductor film 4514. Further, a capacitor formed by the wiring 4505, the same layer (not shown) as the first interlayer insulating film, and the current supply line 4513 can be used as a storage capacitor.
The storage capacitor 4511 has a function of holding a voltage applied to the gate electrode 4506 of the EL driving TFT 4503. Note that the drain region of the EL driving TFT 4503 is connected to a current supply line (power supply line) 4513, and a constant voltage is constantly applied.

A first passivation film 4515 is provided on the switching TFT 4502 and the EL driving TFT 4503, and a flattening film 4516 made of a resin insulating film is formed thereon. Using the flattening film 4516, T
It is very important to flatten the step due to FT.
Since the light-emitting layer 4519 formed later is extremely thin, light emission failure may occur due to the presence of a step.
Therefore, it is preferable that the light emitting layer 4519 be planarized before the pixel electrode 4517 is formed so that the surface can be formed as flat as possible.

Reference numeral 4517 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity, and is used for driving EL through a contact hole provided in the first passivation film 4515 and the flattening film 4516. TFT4503
Is electrically connected to the drain region. Pixel electrode 451
As 7, it is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film or a silver alloy film, or a laminated film thereof. Of course, a stacked structure with another conductive film may be employed.

Next, a bank 4518 and a tap 4520 are formed by forming an organic resin film on the pixel electrode 4517 and the planarizing film 4516 and patterning the organic resin film. The bank 4518 is provided for separating a light-emitting layer or an EL layer of an adjacent pixel. Tap 4520
Is provided over a portion where the pixel electrode 4517 and the drain wiring 4512 of the EL driving TFT 4503 are connected. In some cases, a step is formed in the pixel electrode 4517 at a contact hole portion, and it is preferable that the pixel electrode 4517 be provided with a tap 4520 so as to be planarized in order to prevent a light-emitting layer 4519 to be formed later from emitting light. Note that the bank 4518 and the tap 4520 need not be formed to have the same thickness, and can be set as appropriate depending on the thickness of the light-emitting layer 4519 formed later.

An EL layer 4519 is formed in a groove (corresponding to a pixel) formed by the bank 4518. In FIG. 10A, some banks are omitted in order to clarify the position of the storage capacitor 4511;
13 and a part of the source wiring 4521 are provided between the pixels. Although only two pixels are shown here, light emitting layers corresponding to each of R (red), G (green), and B (blue) may be separately formed. As the EL material for the light emitting layer, a π-conjugated polymer material is used. Representative polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK),
Polyfluorenes and the like can be mentioned.

There are various types of PPV-based EL materials, for example, “H. Shenk, H. Becker, O. Gelse”.
n, E. Kluge, W. Kreuder and H. Spreitzer: “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As specific light-emitting layers, cyanopolyphenylenevinylene is used for a red light-emitting layer, polyphenylenevinylene is used for a green light-emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light-emitting layer. Good. The film thickness is 30 to 150
[Nm] (preferably 40 to 100 [nm]).

However, the above example is an example of the EL material that can be used for the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these EL materials and inorganic materials.

In this embodiment, the PED is formed on the light emitting layer 4519.
EL having a laminated structure provided with a hole injection layer 4522 made of OT (polythiophene) or PAni (polyaniline)
And layers. An anode 4523 made of a transparent conductive film is provided over the hole injection layer 4522. In the case of this embodiment, since the light generated in the light-emitting layer 4519 is emitted toward the upper surface (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

At the point where the anode 4523 is formed, the EL element 4510 is completed. Note that the EL element 45 here is used.
Reference numeral 10 denotes a pixel electrode (cathode) 4517 and a light emitting layer 451
9 and a storage capacitor formed by the hole injection layer 4522 and the anode 4523. As illustrated in FIG. 11A, the pixel electrode 4517 substantially corresponds to the area of the pixel, so that the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In this embodiment, a second passivation film 4524 is further provided on the anode 4523. As the second passivation film 4524, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose is
This is to shut off the EL element from the outside, and has both the meaning of preventing the deterioration of the EL material due to oxidation and the meaning of suppressing outgassing from the EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel described in the present embodiment has a pixel portion composed of pixels having a structure as shown in FIG. 9, and has a switching TFT having a sufficiently low off-current value.
It has an FT and an EL driving TFT that is resistant to hot carrier injection. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

[Embodiment 8] In this embodiment, a structure in which the EL element 4510 in the pixel portion shown in Embodiment 7 is inverted will be described. FIG. 11 is used for the description. Note that the difference from the structure of FIG. 9 is only the EL element portion and the EL driving TFT, and the other description will be omitted.

In FIG. 11, an EL driving TFT 450 is provided.
Reference numeral 3 uses a p-channel TFT formed by a known method.

In this embodiment, the pixel electrode (anode) 4525
Is used as a transparent conductive film. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

After the banks 4526 and taps 4527 made of an insulating film are formed, a light emitting layer 4528 made of polyvinyl carbazole is formed by applying a solution.
On top of this, potassium acetylacetonate (acacK
) And a cathode 4530 made of an aluminum alloy. In this case, the cathode 4530 also functions as a passivation film. Thus, an EL element 4531 is formed.

E having the structure described in this embodiment is
In the case of the L pixel, light generated in the light-emitting layer 4528 is emitted toward the substrate on which the TFT is formed, as indicated by an arrow.

[Embodiment 9] In this embodiment, FIGS. 12A to 12C show an example in which a pixel having a structure different from the circuit diagram shown in FIG. 10B is used. In this embodiment, reference numeral 3801 denotes a source signal line also serving as a source wiring of the switching TFT 3802, 3803 denotes a gate signal line also serving as a gate electrode of the switching TFT 3802, 3804 denotes an EL driving TFT, and 3805 denotes a storage capacitor. , 3806 and 3808 are current supply lines, and 3807 is E
L element.

FIG. 12A shows an example in which the current supply line 3806 is shared between two adjacent pixels. That is, it is characterized in that two adjacent pixels are formed to be line-symmetric with respect to the current supply line 3806. In this case, since the number of current supply lines can be reduced,
The pixel portion can be further refined.

FIG. 12B shows a current supply line 380.
8 is provided in parallel with the gate signal line 3803. Note that although FIG. 12B illustrates a structure in which the current supply line 3808 and the gate signal line 3803 are provided so as not to overlap with each other, if the wiring is formed in a different layer, the insulating film may be used. It can also be provided so as to overlap.
In this case, the current supply line 3808 and the gate signal line 3803
Since the occupied area can be shared by the pixels, the pixel portion can be further refined.

FIG. 12C shows that the current supply line 3808 is connected to the gate signal line 3803 similarly to the structure of FIG.
And two pixels are connected to the current supply line 380
It is characterized in that it is formed so as to be line-symmetric with respect to 8. Further, the current supply line 3808 is connected to the gate signal line 3803.
It is also effective to provide any one of them. In this case, the number of current supply lines can be reduced, so that the pixel portion can have higher definition.

[Embodiment 10] FIG. 10 shown in Embodiment 7
10A and 10B, a storage capacitor 451 for holding a voltage applied to the gate electrode of the EL driving TFT 4503 is used.
1 is provided, but the storage capacitor 4511 can be omitted. In the case of the seventh embodiment, the EL driving T
Since an n-channel TFT formed by a known method is used as the FT4503, it has a GOLD region provided so as to overlap the gate electrode with a gate insulating film interposed therebetween. A parasitic capacitance generally called a gate capacitance is formed in the overlapping region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the storage capacitor 4511.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the GOLD region overlap, the GOL included in the overlapping region
It is determined by the length of the D area.

FIG. 12A shown in the ninth embodiment,
Similarly, in the structures of FIGS.
05 can be omitted.

[Embodiment 11] In this embodiment, as an example of a method of manufacturing the electronic device described in Embodiments 1 to 10, an EL driving TFT which is a switching element of a pixel portion and a TFT provided around the pixel portion are provided. A method for forming TFTs of a driver circuit (a source signal line driver circuit, a gate signal line driver circuit, and the like) over the same substrate will be described in detail according to steps. However, for the sake of simplicity, a CMOS circuit, which is a basic configuration circuit, is shown as a driving circuit section, and a switching TFT and an EL driving TFT are shown as pixel sections.

Referring to FIG. As the substrate 5001, an alkali-free glass substrate represented by, for example, a 1737 glass substrate manufactured by Corning Incorporated was used. Then, a base film 5002 was formed over the surface of the substrate 5001 where the TFT was to be formed by a plasma CVD method or a sputtering method. The base film 5002 is
The silicon nitride film is 25 to 100 [nm], here 50
[Nm] to a thickness of 50 to 300 [n]
m], here, 150 [nm] in thickness (not shown). Further, as the base film 5002, only a silicon nitride film or a silicon nitride oxide film may be used.

Next, on this base film 5002, 50
An amorphous silicon film having a thickness of [nm] was formed by a plasma CVD method. The amorphous silicon film depends on the hydrogen content,
Preferably, dehydrogenation treatment is performed by heating at 400 to 550 [° C.] for several hours to reduce the hydrogen content to 5 [atom%] or less.
It is desirable to perform a crystallization step. Further, the amorphous silicon film may be formed by another method such as a sputtering method or an evaporation method; however, it is necessary to sufficiently reduce the content of impurity elements such as oxygen and nitrogen contained in the film. desirable.

Here, both the base film and the amorphous silicon film are formed by the plasma CVD method. At this time, even if the base film and the amorphous silicon film are continuously formed in vacuum. good. By performing this continuous formation, after forming the base film,
Since the surface of the base film can be prevented from being exposed to the atmosphere, the surface of the base film can be prevented from being contaminated, and the variation in characteristics of the TFT to be formed can be reduced.

In the step of crystallizing the amorphous silicon film, a known laser crystallization technique or thermal crystallization technique may be used. In this embodiment, a crystalline silicon film is formed by condensing a pulse oscillation type KrF excimer laser beam linearly and irradiating the amorphous silicon film.

In this embodiment, a method of crystallizing an amorphous silicon film by laser or heat is used for forming a semiconductor layer. However, a microcrystalline silicon film may be used, or a crystalline silicon film may be directly used. A film may be formed.

By patterning the crystalline silicon film thus formed, island-like semiconductor layers 5003, 5004,
5005 and 5006 were formed.

Next, island-shaped semiconductor layers 5003 and 500
A gate insulating film 5007 containing silicon oxide or silicon nitride as a main component was formed to cover 4, 5005 and 5006. The gate insulating film 5007 is formed of a silicon nitride oxide film using N ₂ O and SiH ₄ as raw materials by a plasma CVD method.
The thickness may be from 200 to 200 [nm], preferably from 50 to 150 [nm]. In this embodiment, 100 [nm]
It was formed in thickness.

Then, a first conductive film 5008 serving as a first gate electrode and a second conductive film 5009 serving as a second gate electrode were formed on the surface of the gate insulating film 5007.
The first conductive film 5008 may be formed using one kind of element selected from Si and Ge, or a semiconductor film containing these elements as main components. The thickness of the first conductive film 5007 is 5
５０50 [nm], preferably 10-30 [nm]. In this embodiment, the thickness of Si is set to 20 [nm].
A film was formed.

[0154] An impurity element imparting n-type or p-type conductivity may be added to the semiconductor film used as the first conductive film. The method of forming the semiconductor film may be in accordance with a known method.
0 to 500 [° C.], disilane (Si ₂ H ₆ ) is 25
It can be formed by introducing 0 [sccm] and 300 [sccm] of helium (He). At this time, an n-type semiconductor film may be formed by mixing PH ₃ with Si ₂ H ₆ by 0.1 to ₂ %.

A second conductive film serving as a second gate electrode is
It may be formed of a conductive material having a selectivity by etching or a compound containing these as a main component. This is considered in order to reduce the electric resistance of the gate electrode. For example, a Mo-W compound may be used. Here, Ta is used, and 200 to 1000
[Nm], typically 400 [nm] in thickness.
(FIG. 13A)

Next, a step of forming a resist mask using a known patterning technique and etching the second conductive film 5009 to form a second gate electrode was performed. Second
Since the conductive film 5009 is formed of a Ta film, the conductive film 5009 was formed using a dry etching method. As dry etching conditions, Cl ₂ was introduced at 80 [sccm] and 100 [mTor
r] and 500 [W] of high-frequency power. Then, as shown in FIG. 12B, the second gate electrode 50 is formed.
10, 5011, 5012, 5013, 5014 and a wiring 5501 were formed.

When a residue is confirmed after etching,
What is necessary is just to remove by washing with a solution such as SPX washing solution or EKC.

[0158] The second conductive film 5009 may be removed by a wet etching method. For example, in the case of Ta, it can be easily removed using a hydrofluoric acid-based etchant.

Then, a step of adding a first impurity element imparting n-type was performed. This step is for forming the second impurity region. In this embodiment, the ion doping method using phosphine (PH ₃ ) was performed. In this step, in order to add phosphorus (P) to the semiconductor layer therebelow through the gate insulating film 5007 and the first conductive film 5008, the acceleration voltage needs to be set as high as 80 keV. The concentration of phosphorus added to the semiconductor layer is 1
It is preferably in the range of ^{× 10 16 ~1 × 10 19 [} atoms / cm 3], where was ^{1 × 10 18 [atoms / cm} 3].
Then, the regions 5015, 5
016, 5017, 5018, 5019, 5020, 5
Nos. 021, 5022, and 5023 were formed. (FIG. 13
(B))

At this time, in the first conductive film 5008, the second gate electrodes 5010, 5011, 5012,
Phosphorus was also added to a region which did not overlap with the wirings 5013 and 5014 and the wiring 5501. Although the phosphorus concentration in this region is not particularly limited, an effect of lowering the resistivity of the first conductive film was obtained.

Next, a step of covering a region where an n-channel TFT was to be formed with resist masks 5024 and 5025 and removing part of the first conductive film 5008 was performed. In this embodiment, dry etching is performed. The first conductive film 5008 is made of Si. As dry etching conditions, CF ₄ is introduced at 50 [sccm] and O ₂ is introduced at 45 [sccm].
At 0 [mTorr], high-frequency power of 200 [W] was applied to carry out the test. As a result, a portion of the first conductive film 5026 which is covered with the resist masks 5024 and 5025 and the second gate conductive film remains.

Then, a step of adding a third impurity element imparting p-type to the region where the p-channel TFT is formed was performed. Here, diborane (B ₂ H ₆ ) was added by an ion doping method. Again, the accelerating voltage is 80
As [keV], boron was added to a concentration of 2 × 10 ²⁰ [atoms / cm ³ ]. Then, the third impurity regions 5027, 5028, 5029, 503 to which boron is added at a high concentration are added.
0 was formed. (FIG. 13 (C))

Referring to FIG. After the addition of the third impurity element, the resist masks 5024 and 5025 are completely removed, and the resist masks 5031 and 503 are again removed.
2, 5033, 5034, 5035, and 5502 were formed. Then, the resist masks 5031, 5033, 50
34, the first conductive film is etched to form a new first conductive film.
Of conductive films 5036, 5037, and 5038 were formed.
(FIG. 14A)

Then, a step of adding a second impurity element imparting n-type was performed. In this embodiment, the ion doping method using phosphine (PH ₃ ) was performed. Also in this step, the acceleration voltage is 80 [ke] in order to add phosphorus to the underlying semiconductor layer through the gate insulating film 5007.
V]. Then, the regions 5039, 5040, 5041, 5042, and 504 to which phosphorus is added are added.
3 was formed. The concentration of phosphorus in this region is higher than that in the step of adding the first impurity element imparting n-type, and is preferably 1 × 10 ¹⁹ to 1 × 10 ²¹ [atoms / cm ³ ]. In this embodiment, 1 × 10 ²⁰ [atoms / cm
³ ]. (FIG. 14A)

Further, resist masks 5031 and 503
2, 5033, 5034, 5035, and 5502 are removed, and resist masks 5044, 5045, and 504 are newly added.
6, 5047, 5048, and 5503 were formed, and the first conductive film was etched. In this step, a resist mask 5044, 5
The lengths of 046 and 5047 in the channel length direction are important in determining the structure of the TFT. Resist mask 5044,
5046 and 5047 are first conductive films 5036 and 503
7, 5038 are provided for the purpose of removing a part of the resist mask. Due to the length of the resist mask, a region where the second impurity region does not overlap with a region where the first conductive film overlaps is formed.
It can be freely determined within a certain range. (FIG. 14
(B))

Then, as shown in FIG. 14C, first gate electrodes 5049, 5050, and 5051 were formed.

Through the above steps, the channel formation region 5052, the first impurity regions 5053 and 5054, the second impurity region 5055,
5056 was formed. Here, the second impurity region is
A region (GOLD region) 5055a overlapping with the gate electrode;
5056a and regions (LDD regions) 5055b and 5056b which do not overlap with the gate electrode are formed. Then, the first impurity region 5053 serves as a source region, and the first impurity region 5054 serves as a drain region.

In the p-channel type TFT, similarly, a gate electrode having a clad structure is formed, and a channel formation region 505 is formed.
7. Third impurity regions 5058 and 5059 were formed. The third impurity region 5059 is a source region,
The third impurity region 5058 serves as a drain region.

N-channel type TF for switching pixel part
T is a multi-gate, and a channel formation region 5060,
5061 and first impurity regions 5062, 5063, 50
64 and second impurity regions 5065, 5066, 506
7, 5068 were formed. Here, the second impurity region is a region 5065a, 5066a overlapping with the gate electrode,
5067a, 5068a and regions 5065b, 5066b, 5067b, 5068b which do not overlap with the gate electrode
Was formed.

The p-channel TFT for EL driving is
With a structure similar to that of the p-channel TFT in the CMOS circuit, a channel formation region 5069 and third impurity regions 5070 and 5071 are formed. Third impurity region 5
070 is a source region, and the third impurity region 5071 is a drain region. (FIG. 14C)

Subsequently, a step of forming a silicon nitride film 5504 and a first interlayer insulating film 5072 was performed. First, a silicon nitride film 5504 was formed to a thickness of 50 [nm].
The silicon nitride film 5504 is formed by a plasma CVD method. SiH ₄ is 5 [sccm], NH ₃ is 40 [sccm], and N _{2 is} N _2.
100 [sccm] and 0.7 [Torr], 300
This was performed by supplying the high-frequency power of [W]. Next, a first interlayer insulating film 5072 was formed. First interlayer insulating film 507
As 2, an insulating film containing silicon may be used as a single layer or a stacked film in which the insulating films are combined. Further, the film thickness may be 400 [nm] to 1.5 [μm]. In this embodiment, 800 nm is formed on the silicon nitride oxide film having a thickness of 200 nm.
It has a structure in which silicon oxide films each having a thickness of [nm] are stacked (not shown).

Further, in an atmosphere containing 3 to 100% of hydrogen, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours to perform a hydrogenation treatment. This step is a step of terminating dangling bonds of the semiconductor film with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

The hydrogenation process is performed on the first interlayer insulating film 50.
It may be inserted while forming 72. That is, 200 [nm]
After forming the thick silicon nitride oxide film, the hydrogenation treatment may be performed as described above, and then, the remaining 800 nm thick silicon oxide film may be formed.

Next, contact holes are formed in the first interlayer insulating film 5072, and the source wirings 5073 and 5073 are formed.
75, 5076, 5078, drain wiring 5074,
5077 and 5079 were formed. In this embodiment, this electrode has a three-layer structure (not shown) in which a Ti film is continuously formed by a sputtering method with a Ti film of 100 [nm], a Ti-containing aluminum film of 300 [nm], and a Ti film of 150 [nm]. However, other conductive films may of course be used.

Next, 50 to 500 [nm] (typically,
The first passivation film 5080 was formed to a thickness of 100 to 300 [nm]. In this embodiment, a silicon nitride oxide film having a thickness of 300 [nm] is used as the first passivation film 5080. This may be replaced by a silicon nitride film.
Note that it is effective to perform plasma treatment using a gas containing hydrogen such as H ₂ or NH ₃ before forming the silicon nitride oxide film. Hydrogen excited by this pretreatment was supplied to the first interlayer insulating film 5072, and a heat treatment was performed, whereby the film quality of the first passivation film 5080 was improved. At the same time, the hydrogen added to the first interlayer insulating film 5072 diffuses to the lower layer side, so that the active layer can be effectively hydrogenated. (FIG. 15 (A))

Next, a second interlayer insulating film 5081 made of an organic resin was formed. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, the second interlayer insulating film 50
Since 81 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, the acrylic film is formed to a thickness that can sufficiently flatten the step formed by the TFT. Preferably 1 to 5 μm (more preferably 2 to 5 μm)
４4 [μm]).

Next, the second interlayer insulating film 5081 and the first
Wiring 5079 on the passivation film 5080
Is formed, and a pixel electrode 5082 is formed.
Was formed. In this embodiment, as the pixel electrode 5082, a transparent conductive film formed by adding 10 to 20% by weight of zinc oxide to indium oxide was formed to a thickness of 120 nm. (FIG. 15
(B))

Next, as shown in FIG. 16, a bank 5083 and a tap 5505 made of a resin material were formed. The bank 5083 may be formed by patterning an acrylic film or a polyimide film having a thickness of 1 to 2 [μm]. The bank 5083 is formed in a stripe shape between pixels. In this embodiment, it is formed along the source wiring 5076, but may be formed along the wiring 5501. Note that the bank 5083 may be used as a shielding film by mixing a pigment or the like with a resin material forming the bank 5083.

Next, the EL layer 5084 and the cathode (MgAg
(Electrode) 5085 was continuously formed by using a vacuum deposition method without opening to the atmosphere. Note that the thickness of the EL layer 5084 is 80 to
200 [nm] (typically 100 to 120 [nm]), and the thickness of the cathode 5085 may be 180 to 300 [nm] (typically 200 to 250 [nm]). Although only one pixel is shown in this embodiment, an EL layer that emits red light, an EL layer that emits green light, and an EL layer that emits blue light are formed at this time.

In this step, pixels corresponding to red, pixels corresponding to green and pixels corresponding to blue are sequentially subjected to E
An L layer 5084 and a cathode 5085 were formed. However, EL
The layer 5084 has poor resistance to a solution, and must be formed individually for each color without using a photolithography technique. Therefore, a pixel other than the desired pixel is hidden using a metal mask, and the EL layer 5084 and the cathode 50
Preferably, 85 is formed.

That is, first, a mask for hiding all pixels other than the pixel corresponding to red is set, and the EL layer and the cathode for emitting red light are selectively formed using the mask. Next, a mask for hiding all pixels other than pixels corresponding to green is set, and the EL layer and the cathode for emitting green light are selectively formed using the mask. Next, similarly, a mask for hiding all pixels other than the pixel corresponding to blue is set, and the EL for blue light emission is set using the mask.
The layer and the cathode are selectively formed. Note that all the masks are described herein as being different, but the same mask may be used again. In addition, it is preferable to perform processing without breaking vacuum until an EL layer and a cathode are formed in all pixels.

In this embodiment, the EL layer 5084 has a single-layer structure composed of only a light emitting layer. However, the EL layer is a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer in addition to the light emitting layer. Etc. may be provided. Various examples of such combinations have already been reported, and any of these configurations may be used. As the EL layer 5084, a known material can be used. As a known material, it is preferable to use an organic material in consideration of a driving voltage. In this embodiment, an example is shown in which an MgAg electrode is used as a cathode of an EL element, but other known materials may be used.

Finally, the second passivation film 508
6 is formed. Thus, an active matrix substrate having a structure as shown in FIG. 16 was completed. The bank 508
It is effective to continuously perform the steps from the formation of No. 3 to the formation of the second passivation film 5086 by using a multi-chamber type (or in-line type) thin film forming apparatus without opening to the atmosphere. .

By the way, the active matrix substrate of this embodiment exhibits extremely high reliability by arranging the TFT having the optimum structure not only in the pixel portion but also in the driving circuit portion, and the operating characteristics can be improved. In the crystallization step, N
It is also possible to increase the crystallinity by adding a metal catalyst such as i. Thus, the driving frequency of the source signal line driving circuit can be increased to 10 [MHz] or more.

First, a TFT having a structure in which hot carrier injection is reduced so as not to lower the operation speed as much as possible,
N-channel type TF of CMOS circuit forming drive circuit section
Used as T. In addition, as the drive circuit here,
It includes a shift register, a buffer, a level shifter, a latch in line-sequential driving, a transmission gate in point-sequential driving, and the like.

In the case of this embodiment, as shown in FIGS. 14C and 16, the active layers of the n-channel TFT are composed of a source region 5053, a drain region 5054, and a GOLD region 50.
55a, 5056a, LDD regions 5055b, 5056
b and the channel formation region 5052, and the GOLD regions 5055a and 5056a overlap with the gate electrode 5049 via the gate insulating film.

Also, a p-channel type TFT of a CMOS circuit
Since there is almost no concern about deterioration due to hot carrier injection, it is not necessary to provide an LDD region. Needless to say, it is also possible to provide an LDD region similarly to the n-channel type TFT and take measures against hot carriers.

In addition, in the case where a CMOS circuit in which a current flows bidirectionally in the channel formation region, that is, a CMOS circuit in which the roles of the source region and the drain region are exchanged is used in the driver circuit, n In the channel type TFT, it is preferable to form an LDD region on both sides of the channel formation region so as to sandwich the channel formation region. An example of such a transmission gate is a transmission gate used for dot-sequential driving. In the case where a CMOS circuit that requires an off-current value to be kept as low as possible is used in a driving circuit, a CMOS
The n-channel TFT forming a circuit preferably has a structure in which a part of an LDD region overlaps with a gate electrode through a gate insulating film. As such an example, a transmission gate used for dot-sequential driving is also mentioned.

In fact, when the structure shown in FIG. 16 is completed, a protective film (laminate film, ultraviolet curable resin film, etc.) with high airtightness and low degassing, or a light-transmitting material is provided so as not to be further exposed to the outside air. It is preferable to package (enclose) with a sealing material. At this time, the reliability of the EL element is improved by setting the inside of the sealing material to an inert atmosphere or disposing a hygroscopic material (for example, barium oxide) inside.

When the airtightness is enhanced by processing such as packaging, an FP for connecting a terminal led from an element or a circuit formed on the substrate to an external signal terminal is provided.
C is attached to complete the product. Such a state in which the product can be shipped is referred to as an EL display (or EL module) in this specification.

[Embodiment 12] In this embodiment, a circuit configuration for implementing the driving method of the present invention will be described.

Referring to FIG. FIG. 17A shows a circuit configuration of a gate signal line driver circuit for performing a plurality of alternate selections of gate signal lines according to the present invention. In this embodiment, for simplicity, a case will be described as an example in which the gate signal line selection period is divided into two sub-gate signal line selection periods for driving. Gate signal line driver circuits 1752 are provided on both sides of the pixel portion 1753, and switch circuits 1754 and 1755 are provided between the buffer output of each gate signal line driver circuit and the pixel portion 1753. FIG. 17B illustrates an example of a structure of the switch circuits 1754 and 1755.
It is shown in (C).

A gate signal line selection timing switching signal is input to the switch circuits 1754 and 1755 via one or more signal lines. In FIG. 17A, signals are input from pins 11 and 12 to a switch circuit in each gate signal line driving circuit. Alternatively, it may be inverted and input to the other. Thereby, the switch circuit 175
4, 1755 operate exclusively and are controlled so that they do not open at the same time. One switch circuit 1754 opens during the first half of the sub-gate signal line selection period, and the other switch circuit 1755 operates at the latter half of the sub-gate signal line. Opening during the line selection period allows the gate signal line to be normally selected for the two sub-gate signal line selection periods.

Referring to FIG. FIG. 18 shows a circuit configuration of a source signal line driving circuit used when a plurality of gate signal lines are alternately selected according to the present invention.

FIG. 18A is a diagram showing an example using a source signal line drive circuit having the same configuration as the conventional one. The shift register circuit (SR) receives a clock signal from pins 21 and 22 and a start pulse from pin 23, and sequentially outputs pulses. This is the first latch pulse. A digital video signal is input to the first latch circuit (LAT1) from the pin 24, and holds the digital video signal according to the timing of the first latch pulse. Subsequently, when the second latch pulse is input from the pin 25 during the horizontal blanking period, the digital video signals held in the first latch circuit are simultaneously sent to the second latch circuit (LAT2). The digital video signal is transferred and written to the pixels line-sequentially. Subsequently, in the first half and the second half of the next gate signal line selection period, writing and lighting are performed on the pixels, respectively.

At this time, when the gate signal line selection period has two sub-gate signal line selection periods, the source signal line is written in the first and second half sub-gate signal line selection periods in one gate signal line selection period. In order to complete signal sampling and latching, it is necessary to double the operating clock frequency of the source signal line driver circuit.
This will be described with reference to FIGS.

FIG. 29 is a timing chart in the ordinary time gray scale method. This figure shows VGA, 4-bit gradation,
The case where the frame frequency is 60 [Hz] (display of 60 frames per second) is shown. The description is given below.

A period during which an image for one display area is completely displayed is called one frame. One frame period, as shown in FIGS. 1-5, a plurality of sub-frame periods, 1 each sub frame period is the address (writing) period _{(Ta n: n = 1,2,} ···) And sustain (lit)
Period _{(Ts n: n = 1,2,} ···) has a. The number of sub-frame periods included in one frame period is equal to the number of bits of the gray scale to be displayed. To express an n-bit gray scale, the length of the sustain (lighting) period is expressed by Ts ₁ : Ts ₂ :
_{··· Ts n-1: Ts n} = 2 n-1: 2 n-2: ···: 2 1: 2 0 and then, controls the brightness by the length of the lighting period. In FIG. 29, since it is a 4-bit gradation, Ts ₁ : Ts ₂ : Ts ₃ : T
s ₄ = 2 ³ : 2 ² : 2 ¹ : 2 ⁰

The address (write) period is 482 (48
A gate signal line selection period (horizontal period) of 0 stage + 2 dummy stages) is provided. In a dot data sampling period in the first half of one gate signal line selection period, data for one horizontal period is sequentially held in the first latch circuit. In the subsequent line data latch period, data for one horizontal period is simultaneously transferred to the second latch circuit.

FIG. 30 shows a timing chart for implementing the driving method of the present invention using the circuits shown in FIGS. 17 and 18A. FIG. 29 shows one frame period.
As in the case of the first embodiment, the number of sub-frame periods is equal to the number of display bits. However, when the driving method of the present invention is used, one gate signal line selection period has a plurality of (two in this embodiment) sub-gate signal line selection periods. However, while writing is being performed in a certain sub-gate signal line selection period, the pixels that have been written in the immediately preceding sub-gate signal line selection period have already started lighting, so that the address (writing) period and the sustain (lighting) period have been started. ) The periods are not apparently separated.

In this example, one gate signal line selection period (horizontal period) is divided into two sub-gate signal line selection periods. Therefore, one source signal line drive circuit must complete sampling and latching of a signal to be written in each of the first and second sub-gate signal line selection periods within one horizontal period. That is, as shown in FIG. 30, the dot data sampling period and the data latch period are half as long as those in FIG. Therefore, in order to implement the driving method of the present invention using the source signal line driving circuit described in this embodiment, it is necessary to double the operating clock frequency of the source signal line driving circuit.

FIG. 18B shows an example in which two sets of source signal line driving circuits are arranged on both sides of a pixel matrix. The circuit described in this example includes switch circuits 1854 and 1855 between the second latch circuit and the pixel portion. A series of operations of the shift register circuit, the first latch circuit, and the second latch circuit are the same as those in FIG. 18A, and thus description thereof is omitted. However, one of the two source signal line driver circuits is the first half. The other is in charge of writing in the sub-gate signal line selection period, and the other is in charge of writing in the latter sub-gate signal line selection period. As for the gate signal line driving circuit 1852, FIG.
May be used.

The switch output signals are input to the switch circuits 1854 and 1855 via one or more signal lines. In FIG. 18B, the pins 31, 32
Although it is shown that the latch output switching signal is input to each switch circuit, the latch output switching signal input to one switch circuit may be inverted through an inverter and input to the other. That is, the switch circuits 1854 and 1855 operate exclusively, and are controlled so that they do not open at the same time. One switch circuit 1854 opens during the period of writing a signal during the first half of the sub-gate signal line selection period, and the other one opens. The switch circuit 1855 is opened during a period of writing a signal during a sub-gate signal line selection period in the latter half. The same operation is performed even if this order is reversed. By using a circuit having such a structure, a signal can be normally written to a pixel in each of the two sub-gate signal line selection periods without increasing the driving frequency of the source signal line driver circuit. On the other hand, since the drive circuits are arranged on both sides of the pixel matrix, the occupied area of the entire device is increased.

Referring to FIG. FIG. 31 is FIG. 17, FIG.
8 shows a timing chart for implementing the driving method of the present invention using the circuit shown in FIG. One frame period has subframe periods for the number of display bits,
Further, the subframe period includes a gate signal line selection period (horizontal period) of 482 (480 stages + two dummy stages) as in FIG.

Here, as shown in FIG.
A plurality of source signal lines (two in the example shown in this embodiment)
18A), and a signal from one of the source signal line driving circuits is input to the source signal line by a switch circuit, unlike the circuit in FIG. Writing to the signal line selection period is performed by each source signal line driver circuit, so that parallel processing can be performed. Therefore, as shown in FIG. 31, different source signal line driving circuits perform sampling / latch operations in parallel within one horizontal period for the first half and the second half of the sub-gate signal line selection period. Therefore, processing equivalent to that of the circuit illustrated in FIG. 18A can be performed without increasing the operation clock frequency of the source signal line driver circuit.

Note that the switch circuit in the circuit shown in this embodiment may have any structure as long as it can be turned on and off by input of a control signal from the outside. In a simple example, the switch circuit used in the gate signal line drive circuit (shown in FIGS. 17B and 17C)
The same thing as above may be used.

[Embodiment 13] In this embodiment, an example of a configuration of a source signal line drive circuit different from that of Embodiment 12 will be described. In this embodiment, for simplicity, a case will be described as an example in which the gate signal line selection period is divided into two sub-gate signal line selection periods for driving.

Referring to FIG. FIG. 19 shows a circuit configuration in which two sets of source signal line driving circuits are arranged on one side of a pixel matrix by using a common shift register circuit. In FIG. 18B shown in Embodiment 12, if one is a first source signal line driver circuit and the other is a second source signal line driver circuit, in FIG. 19A, a shift register circuit (SR ), The part composed of the flow of the shift register circuit, the first latch circuit A (L1A), the second latch circuit A (L2A), and the switch circuit (SW) drives the first source signal line. A portion composed of a circuit, a shift register circuit, a first latch circuit B (L1B), a second latch circuit B (L2B), and a switch circuit (SW) corresponds to a second source signal line driver circuit. . As the gate signal line driver circuit, the circuit shown in FIG. 17 may be used.

The operation of the circuit will be described. A clock signal is input from the pins 41 and 42 to the shift register circuit, and a start pulse is input from the pin 43, and pulses are sequentially output to the first latch circuits L1A and L1B. This is the first latch pulse. First latch circuit L1A
Digital data signals 1 and 2 are input to pins L1B and L1B from pin 44, and data is sequentially written according to the first latch pulse. At this time, L1A, L1B
Share the first latch pulse, the first source signal line driver circuit and the second source signal line driver circuit operate simultaneously. Subsequently, during the horizontal retrace period, a second latch pulse is input from the pin 45, and the first latch circuits L1A, L1
1B are simultaneously stored in the second latch circuit L
2A and L2B. At this time, from the first source signal line driving circuit, data to be written during the first half of the sub-gate signal line selection period (referred to as data A) is output from L2A, and the second source signal line From the drive circuit, data to be written during the latter half of the sub-gate signal line selection period (this is referred to as data B) is output from L2B.

Subsequently, during the next gate signal line selection period, the switch circuit 1954 disposed between the second latch circuit and the pixel matrix outputs a latch output switching signal via one or more signal lines. By being input, either data A or data B is selected and output to the pixel portion, and signal writing is performed. By using such a circuit, the area of the circuit can be reduced as compared with the circuit example shown in the twelfth embodiment.

The circuit shown in this embodiment can also sample and latch the signals to be written in the two sub-gate signal line selection periods in parallel, and increase the operating clock frequency of the source signal line drive circuit. Thus, the same processing as that of the circuit shown in FIG. 18A can be performed.

In the circuit configuration shown in this embodiment, conventional shift register circuits and latch circuits may be used as they are, and the switch circuit may have a plurality of inputs (two inputs in this embodiment). Any structure may be used as long as one can select and output one. FIG. 19 shows an example of the switch circuit 1954 in this embodiment.
It is shown in (B). Here, an example of a two-input one-output type is shown. However, even in the case of three or more inputs, basically the same circuit may be used by increasing the number of switches. However, the circuit configuration is not limited to this.

[Embodiment 14] In this embodiment, a description will be given of a part of the embodiment 12 and an embodiment having a circuit configuration different from that of the circuit shown in the embodiment 13. In this embodiment, for simplicity, a case will be described as an example in which the gate signal line selection period is divided into two sub-gate signal line selection periods for driving.

Referring to FIG. FIG. 20 shows an example in which a source signal line driver circuit is integrated on one side by sharing a shift register circuit with two types of latch circuits as in FIG. The circuit shown in this embodiment is a two-input NAND circuit between a shift register circuit and a first latch circuit.
It is characterized by having a circuit. This two-input NAN
The D circuit in which the output line is connected to the first latch circuit L1A is referred to as NAND-A, and the D circuit in which the output line is connected to the first latch circuit L1B is referred to as NAND-B. In the driving circuit shown in this embodiment, the driving circuit of the thirteenth embodiment
Similarly to the above, two source signal line driving circuits are integrated by sharing a shift register circuit.
A first source signal line driver circuit and a second source signal line driver circuit are provided. As for the gate signal line driving circuit,
Similar to the thirteenth embodiment, the one shown in FIG. 17 may be used.

The operation of the circuit will be described. A clock signal (hereinafter, referred to as a first clock signal) is input to the shift register circuit from pins 41 and 42, a start pulse is input from pin 43, and pulses are output in order.
Subsequently, this pulse is input to one of the two input terminals of the NAND circuit. A signal having twice the frequency of the first clock signal input to the shift register circuit (hereinafter, referred to as a “input signal” hereinafter) is input to the other input terminal of the NAND-A.
(Referred to as a second clock signal) is input, and a NAND
An inverted signal of the second clock signal is input to the other input terminal of -B. As a result, a pulse having a pulse width that is half the output pulse from the shift register circuit is input to the first latch circuits L1A and L1B. At this time, the pulse input to L1A is output at the first half of the output pulse from the shift register circuit, and the pulse input to L1B is output at the second half of the output pulse from the shift register circuit. Hereinafter, Example 1
According to the operation method described in 3, the writing is performed on the pixel portion.

That is, by using the circuit shown in the present embodiment, the operation after the first latch circuit realizes the same operation as that of the circuit shown in the thirteenth embodiment, and the operation clock of the shift register is used as the operation clock. Since it can be suppressed to half of the circuit shown in Example 13, it is advantageous in terms of improving the reliability of the circuit. On the other hand, the number of elements in the drive circuit slightly increases.

In the circuit shown in this embodiment, the dot data sampling period and the line data latch period in the source signal line driving circuit can be set to the same time as in the case of normal time gray scale display. 18 without increasing the operating clock frequency of the circuit.
Processing equivalent to that of the circuit shown in FIG. In addition, the shift register circuit can reduce the operation clock frequency to half that of the normal time gray scale display.

Note that the shift register circuit, the latch circuit, and the NAND circuit may be the same as the shift register circuit, the latch circuit, and the NAND circuit, and the switch circuit 2054 may have a plurality of inputs (in this embodiment, Any structure may be used as long as it can select and output one of two inputs. A simple example may be the same as that shown in FIG. 19B used in the thirteenth embodiment. Also, N
The inverted signal of the second clock signal input to AND-B is created by inverting the second clock signal using an inverter in FIG. 20, but an inverted signal of the second clock signal from the outside. May be directly input.

[Embodiment 15] When the driving method of the present invention is actually used in an electronic device, a problem may occur due to a timing shift due to a signal delay occurring inside a circuit. In this embodiment, a driving method based on these problems will be described.

When a timing shift occurs due to a signal delay inside the drive circuit, a design is generally made with a margin so as to allow a certain delay. For example, one frame period = 1 horizontal period × the number of gate signal lines + retrace period. If a delay occurs in the gate signal line selection pulse, the delay is absorbed in the retrace period, and the delay occurs in the next frame period. Is trying not to affect.

In the present invention, when one horizontal period is divided into, for example, two sub-gate signal line selection periods, FIG.
As shown in FIG. 7, a sub-gate period selection pulse is output. The output timing of the sub-gate period selection pulse must be such that exactly one cycle is included in the width of one gate signal line selection pulse. This is shown as a sub-gate period selection pulse (normal) in FIG. The first gate signal line selection pulse i-th row, the first gate signal line selection pulse i + 1-th row, the second gate signal line selection pulse i-th row, and the second
It can be seen that exactly one cycle of the sub-gate period selection pulse (normal) is included in each pulse width of the gate signal line selection pulse i + 1 row.

In the first half of the sub-gate signal line selection period, the sub-gate period selection pulse is Hi, and the first gate signal line selection pulse in the i-th row is Hi (selected state).
In a selected state, the gate signal line in the i-th row is selected at the time of the selection state. In the latter half of the sub-gate signal line selection period, the sub-gate period selection pulse is Lo, and the second gate signal line selection pulse in the i-th row is Hi (selected state. Depending on how the circuit is assembled, it is Lo in the selected state. In this case, the gate signal line in the i-th row is selected.

Here, consider a case where a timing shift occurs between the sub-gate period selection pulse and the gate signal line selection pulse. As a mode of the timing shift, there are a case where the sub-gate period selection pulse is delayed with respect to the gate signal line selection pulse and a case where the gate signal line selection pulse is delayed with respect to the sub-gate period selection pulse. In order to clarify the description, the sub-gate period selection pulse is output with a delay with respect to the gate signal line selection pulse, and when the sub-gate period selection pulse is output earlier,
It is relatively taken.

(1) When the sub-gate period selection pulse is output with a delay: FIG. 36A is referred to. Sub-gate period selection pulse when output at normal timing is 9001
The sub-gate period selection pulse output with a delay of 9002
Indicated by In the figure, each gate signal line is selected in the first half of the gate signal line selection period when the sub-gate period selection pulse is Hi, and is selected in the second half of the gate signal line selection period when it is Lo.

In the first half of the gate signal line selection period,
After the first gate signal line selection pulse 9003 of the i-th row is output, the sub-gate period selection pulse 900 is slightly delayed.
2 becomes Hi. Therefore, the gate signal line in the i-th row is in a selected state during the period indicated by the pulse 9007. On the other hand, in the latter half of the gate signal line selection period, at the moment when the second gate signal line selection pulse in the i-th row is output, the sub-gate period selection pulse has not yet become Hi because of a delay. Therefore, during the period indicated by the pulse 9009, the gate signal line in the i-th row is in a selected state. After that, the sub-gate period selection pulse becomes Hi, the period from when it becomes Lo again until the second gate signal line selection pulse in the i-th row becomes Lo (non-selection state), that is, the period indicated by the pulse 9010, i The gate signal line in the row is in a selected state. i
Similarly, the selection of the gate signal line of the (+1) th row is performed only during the periods indicated by the pulses 9008, 9011, and 9012, respectively.

At this time, what kind of operation will be considered when a signal is written in each of the first half and the second half of the sub-gate signal line selection period. As a specific example,
Consider a case in which a video signal is written in one of the sub-gate signal line selection periods and a reset signal is written in the other during the sub-gate signal line selection period described in the third embodiment.

(1-1) When a video signal is written in the first half and a reset signal is written in the second half The gate signal lines of the i-th row and the (i + 1) -th row are in the selected state in the first half of the sub-gate period, respectively.
As shown by 008, although slightly delayed from the original timing, the video signal on the i-th row is written at this timing, so that there is no major problem in operation.

On the other hand, the periods in which the gate signal lines in the i-th row and the (i + 1) -th row are in the selected state in the latter half of the sub-gate period are 9009, 9010, 9011, and 901 respectively.
As shown by 2, each gate signal line selection period is divided into two periods. In this case, the period in which the gate signal line in the i-th row is selected at the timing indicated by 9009 is a period in which the gate signal line in the (i-1) -th row should be selected. Similarly, when the gate signal line of the (i + 1) -th row is selected at the timing indicated by 9011, it is originally i
This is the period in which the gate signal line in the row should be selected.
That is, in the i-th row, a reset signal to be written to the (i-1) -th row is written at the timing shown by 9009, and a reset signal to be written to the i-th row is written to the i + 1-th row at the timing shown by 9011. . As a result, the EL element is turned off at a timing earlier by one horizontal period than the original timing. Although the gradation is slightly lowered, it can be said that this is not a serious problem since the gradation does not reverse in the whole. After the reset signal of the previous row is written, 9010, 9010
At the timing indicated by 12, the original reset signals are output in the i-th row and the (i + 1) -th row, respectively. However, since the EL element is already turned off, there is no change in display due to this operation. (FIG. 36 (B))

(1-2) When a reset signal is written in the first half and a video signal is written in the second half As described above, when a gate signal line is selected in the first half sub-gate selection period, the selection period is simply delayed. No problem. After the end of the sustain period of the correct length, the reset signal is written and the EL element is turned off.

When the gate signal lines of the i-th row and the (i + 1) -th row are selected in the periods indicated by 9009 and 9011, the i-th row is written with the video signal of the (i-1) -th row, and the i +
In the first row, the video signal in the i-th row is written. However, immediately after that, the gate signal lines are again selected at the timings indicated by 9010 and 9012, and during this period, the correct video signal is written, so that the video signal is overwritten in each row. No. (FIG. 36 (C))

(2) A case where the sub-gate period selection pulse is output earlier Reference is made to FIG. The sub-gate period selection pulse output at the normal timing is
The sub-gate period selection pulse output earlier is denoted by 9002. In the figure, each gate signal line is selected in the first half of the gate signal line selection period when the sub-gate period selection pulse is Hi, and is selected in the second half of the gate signal line selection period when it is Lo.

In the first half of the gate signal line selection period,
At the moment when the first gate signal line selection pulse 9103 in the i-th row is output, the sub-gate period selection pulse is already Hi.
(9102), the gate signal line in the i-th row is immediately selected (9107). Thereafter, the sub-gate period selection pulse becomes Lo, and the gate signal line in the i-th row returns to the non-selected state. However, immediately after that, the sub-gate period selection pulse becomes Hi again, so that the gate signal line in the i-th row is again in the selected state. (9108). On the other hand, in the latter half of the gate signal line selection period, the second gate signal line selection pulse output 9106 in the i-th row becomes Hi, and the sub-gate period selection pulse becomes Lo during the period in which it is selected (9111). Regarding the gate signal line of the (i + 1) th row,
Similarly, pulses 9109, 9110, 9112, respectively
Is selected only during the period indicated by.

Here, as described above, a case is considered in which a video signal is written in one of the sub-gate signal line selection periods and a reset signal is written in the other.

(2-1) When writing a video signal in the first half and a reset signal in the second half The periods in which the gate signal lines of the i-th row and the (i + 1) -th row are in the selected state in the first half of the sub-gate period are 9107 and 9
As shown by 108, 9109, and 9110, each gate signal line selection period is divided into two periods.
In this case, the period in which the gate signal line in the i-th row is selected at the timing indicated by 9108 is a period in which the gate signal line in the (i + 1) -th row should be selected. Similarly,
The period in which the gate signal line in the (i + 1) th row is selected at the timing indicated by 9110 is a period in which the gate signal line in the (i + 2) th row should be selected. At this time, assuming that the video signal is written in the first half of the gate signal line selection period, the writing of the video signal is performed in the period indicated by 9107 in the i-th row. However, immediately after that, in the period indicated by 9108, the video signal to be written to the (i + 1) th row is further written, and in the subsequent sustain (lighting) period, the display is performed in a state where the video of the (i + 1) th row is written. Will be done. Alternatively, since the period indicated by 9108 is short, a sustain (lighting) period starts without the video signal of the (i + 1) th row being written satisfactorily. In this case, the EL element cannot be lit normally. Similarly, in the (i + 1) -th row, immediately after the writing of the original video signal is completed, the video signal of the next column is written, so that there is a problem that a normal display cannot be performed. (FIG. 37 (B))

On the other hand, in the latter half of the gate signal line selection period, the timing at which the gate signal line is selected becomes slightly earlier, so that the reset signal is written slightly earlier. In other words, each sustain (lighting) period is shortened by the difference between the output timing of the sub-gate period selection pulse and the output timing of the gate signal line selection pulse, but this is not a problem.

(2-2) Writing a reset signal in the first half and a video signal in the second half The selection periods of the gate signal lines are 9107, 9108, and 91.
Considering a case where a reset signal is written in a portion corresponding to a period indicated by 09 and 9110, as shown in FIG. 37C, a reset signal is written in the i-th row and the (i + 1) -th row at normal timing. It is a non-display period. Immediately thereafter, at timings indicated by 9108 and 9110, respectively,
The reset signal of the (i + 1) th row is written in the i-th row, and the reset signal of the (i + 2) -th row is written in the (i + 1) th row.
No change, no problem.

As described above, when the output timing of the pulse is shifted, the magnitude of the problem varies greatly depending on which processing is performed in the first half and the second half of the gate signal line selection period. Considering all the cases described here, writing of the reset signal in the first half of the gate signal line selection period (for the sake of safety, the reset signal referred to here is the sustain signal in each row in the previous subframe period). This is a signal for providing a non-display period after the lighting period), and writing a video signal in the latter half of the gate signal line selection period.

As described above, the electronic device of the present invention and the method of driving the same can be easily implemented, and the method can be implemented using any of the methods shown in Examples 1 to 15. Or a combination of a plurality of embodiments may be used.

[Embodiment 16] In the present invention, by using an EL material capable of utilizing phosphorescence from a triplet exciton for light emission, external light emission quantum efficiency can be remarkably improved. As a result, the power consumption and the life of the EL element can be reduced,
And weight reduction becomes possible.

Here, a report is shown in which the triplet exciton is used to improve the external emission quantum efficiency. (T.Tsutsui, C.Ada
chi, S. Saito, Photochemical Processes in Organized
Molecular Systems, ed.K.Honda, (Elsevier Sci.Pu
b., Tokyo, 1991) p.437.) The molecular formula of the EL material (coumarin dye) reported in the above article is shown below.

[0241]

Embedded image

(MABaldo, DFO'Brien, Y. You, A. Sho
ustikov, S. Sibley, METhompson, SRForrest, Natu
re 395 (1998) p.151.) The molecular formula of the EL material (Pt complex) reported by the above paper is shown below.

[0243]

Embedded image

(MABaldo, S. Lamansky, PEBurrrows,
METhompson, SRForrest, Appl.Phys.Lett., 75 (19
99) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T.Wa
tanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguch
i, Jpn. Appl. Phys., 38 (12B) (1999) L1502.) The molecular formula of the EL material (Ir complex) reported by the above-mentioned paper is shown below.

[0245]

Embedded image

As described above, if the phosphorescence emission from the triplet exciton can be used, the external emission quantum efficiency three to four times higher than the case of using the fluorescence emission from the singlet exciton can be realized in principle. . Note that the configuration of this embodiment is the same as that of Embodiments 1 to
It can be implemented by freely combining with any configuration of the fifteenth embodiment.

[Embodiment 17] Since the EL display of the present invention is a self-luminous type, it has excellent visibility in a bright place and a wide viewing angle as compared with a liquid crystal display. Therefore, it can be used as a display portion of various electronic devices. For example, to watch a TV broadcast on a large screen, a diagonal 3
EL display device of 0 inches or more (typically 40 inches or more) (display device having an EL display incorporated in a housing)
It is preferable to use the EL display of the present invention as a display unit of the present invention.

The EL display device includes all information display devices such as a personal computer display device, a TV broadcast reception display device, and an advertisement display device. In addition, the EL display of the present invention can be used as a display portion of various electronic devices.

[0249] Such electronic devices of the present invention include a video camera, a digital camera, a goggle type display device (head mounted display), a navigation system,
Sound playback devices (car audio, audio components, etc.), notebook personal computers, game machines,
A portable information terminal (a mobile computer, a mobile phone, a portable game machine, an electronic book, or the like), and an image reproducing apparatus provided with a recording medium (specifically, a digital video disc (DV
D) and the like, a device having a display capable of reproducing a recording medium and displaying its image). In particular, for a portable information terminal that is often viewed from an oblique direction, a wide viewing angle is regarded as important, and it is desirable to use an EL display. Specific examples of these electronic devices are shown in FIGS.

FIG. 32A shows an EL display.
A housing 3201, a support 3202, a display portion 3203, and the like are included. The present invention can be used for the display portion 3203. E
Since the L display is a self-luminous type, it does not require a backlight and can be a display portion thinner than a liquid crystal display.

FIG. 32B shows a video camera, which includes a main body 3211, a display portion 3212, an audio input portion 3213, an operation switch 3214, a battery 3215, and an image receiving portion 321.
6 and so on. The EL display of the present invention has a display unit 321.
2 can be used.

FIG. 32C shows a part (right side) of the head mounted EL display, which includes a main body 3221, a signal cable 3222, a head fixing band 3223, and a display section 32.
24, an optical system 3225, an EL display 3226, and the like. The present invention can be used for the EL display 3226.

FIG. 32D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
1. Recording medium (DVD, etc.) 3232, operation switch 32
33, a display unit (a) 3234, a display unit (b) 3235, and the like. The display unit (a) 3234 mainly displays image information, and the display unit (b) 3235 mainly displays character information. In the EL display of the present invention, the display unit (a) 3234 and the display unit (b) 3235 Can be used. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 32E shows a goggle type display device (head mounted display), which includes a main body 3241, a display portion 3242, and an arm portion 3243. The EL display of the present invention can be used for the display portion 3242.

FIG. 32F shows a personal computer, which includes a main body 3251, a housing 3252, a display portion 3253,
And a keyboard 3254 and the like. The EL display of the present invention can be used for the display portion 3253.

If the emission luminance of the EL material is increased in the future, it becomes possible to enlarge and project the light including the output image information with a lens or the like and use it for a front-type or rear-type projector.

[0257] The electronic device may be the Internet or C.
Information distributed through an electronic communication line such as an ATV (cable television) is frequently displayed, and in particular, opportunities to display moving image information are increasing. Since the response speed of the EL material is very high, the EL display is preferable for displaying moving images.

In the EL display, since the light emitting portion consumes power, it is desirable to display information so that the light emitting portion is reduced as much as possible. Therefore, when an EL display is used for a portable information terminal, particularly a display unit mainly including character information such as a mobile phone or a sound reproducing device,
It is desirable to drive such that character information is formed in the light emitting portion with the non-light emitting portion as a background.

FIG. 33A shows a mobile phone,
01, audio output unit 3302, audio input unit 3303, display unit 3304, operation switch 3305, antenna 3306
including. The EL display of the present invention can be used for the display portion 3304. Note that the display portion 3304 can reduce power consumption of the mobile phone by displaying white characters on a black background.

FIG. 33 (B) shows a sound reproducing apparatus, specifically, a car audio system.
2, including operation switches 3313 and 3314. The EL display of the present invention can be used for the display portion 3312. In this embodiment, the in-vehicle audio is shown, but the present invention may be applied to a portable or home-use audio reproducing apparatus. Note that the display unit 3312 can reduce power consumption by displaying white characters on a black background. This is particularly effective in a portable sound reproducing device.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be used for electronic devices in various fields. Further, the electronic apparatus of this embodiment may use the EL display having any of the configurations shown in Embodiments 1 to 16.

[0262]

The effects of the present invention will be described. According to the driving method of the present invention, a signal can be written to a plurality of pixels in one gate signal line selection period by dividing the gate signal line selection period into a plurality of sub-gate signal line selection periods. Thus, in a pixel at a certain stage, the time from the input of a signal to the input of the next signal can be arbitrarily set to some extent as long as the writing time to the pixel is secured. Therefore, unlike the conventional driving method, the sustain (lighting) period can be arbitrarily set without separating the address (writing) period and the sustain (lighting) period. ] Can be increased. Therefore, various problems caused by a small duty ratio can be avoided.

The EL element can be turned on even during the address (writing) period. Therefore, even when the address (writing) period becomes long, it is possible to avoid pressing the sustain (lighting) period. That is, even when the circuit operation is slow, a sufficient sustain (lighting) period can be ensured. As a result, the operating frequency of the drive circuit can be kept low, and power consumption can be reduced.

Further, since writing to the pixel can be started again before writing to the pixel in the preceding stage is completed in a certain sub-frame period, there is no problem even when the signal holding ability of the pixel is small. As a result, the switching TFT
And the size of the holding capacity can be designed to be small.

Further, since the configuration of the pixel may be the same as the conventional one, the number of TFTs, capacitors, wirings and the like can be reduced. As a result, an improvement in the aperture ratio of the pixel portion can be expected.

[Brief description of the drawings]

FIG. 1 is a diagram showing a timing chart of simultaneous selection of a plurality of gate signal lines.

FIG. 2 is a diagram showing a timing chart in which overlapping of address (write) periods occurs.

FIG. 3 is a diagram showing a timing chart according to the driving method of the present invention shown in the first embodiment.

FIG. 4 is a diagram showing a timing chart according to the driving method of the present invention shown in the second embodiment.

FIG. 5 is a diagram showing a timing chart according to the driving method of the present invention shown in Embodiment 3.

FIG. 6 is a circuit diagram of a driving circuit of the present invention shown in Embodiment 4.

7A and 7B are a top view and a cross-sectional view of an EL display device described in Embodiment 5.

8A and 8B are a top view and a cross-sectional view of an EL display device described in Embodiment 6.

FIG. 9 is a cross-sectional view of the EL display device described in Embodiment 7.

FIGS. 10A and 10B are a partial view of a pixel matrix and an equivalent circuit diagram of an EL display device described in Embodiment 7. FIGS.

FIG. 11 is a cross-sectional view of an EL display device described in Embodiment 8.

FIG. 12 is a diagram illustrating a circuit configuration example of a pixel portion of an EL display device described in Embodiment 9;

FIG. 13 is a view showing an example of a manufacturing process of the EL display device described in Embodiment 11;

FIG. 14 illustrates an example of a manufacturing process of the EL display device described in Embodiment 11;

15 illustrates an example of a manufacturing process of an EL display device described in Embodiment 11. FIG.

FIG. 16 is a diagram showing an example of a manufacturing process of the EL display device described in Embodiment 11;

FIG. 17 is a diagram showing a circuit configuration example of the EL display device shown in Embodiment 12;

FIG. 18 is a diagram showing a circuit configuration example of the EL display device shown in Embodiment 12;

FIG. 19 is a diagram showing a circuit configuration example of an EL display device shown in Embodiment 13;

FIG. 20 is a diagram showing a circuit configuration example of the EL display device shown in Embodiment 14;

FIG. 21 is a circuit diagram of a pixel portion of an EL display device.

FIG. 22 is a diagram schematically illustrating luminance characteristics and voltage-current characteristics of an EL element.

FIG 23 illustrates an operating point of an EL element.

FIG. 24 shows EL in analog gradation and digital gradation.
FIG. 4 is a diagram showing an operation region of the element.

FIG. 25 shows the relationship between the threshold value and the mobility of the EL driving TFT.
FIG. 5 is a diagram illustrating an influence on an EL lighting start voltage.

FIG. 26 is a diagram showing an example of dividing a frame period.

FIG. 27 is a diagram showing an embodiment of the present invention.

FIG. 28 is a diagram showing simultaneous selection of a plurality of gate signal lines.

FIG. 29 is a diagram showing an example of a timing chart in a time gray scale display method.

FIG. 30 is a diagram showing an example of a timing chart in the circuit configuration of the twelfth embodiment.

FIG. 31 is a diagram showing an example of a timing chart in the circuit configurations of Examples 12 to 14.

FIG. 32 is a diagram showing an example of an electronic device used for an EL display device incorporating the electronic device of the present invention.

FIG. 33 is a diagram showing an example of an electronic device used for an EL display device incorporating the electronic device of the present invention.

FIG. 34 is a diagram illustrating a configuration example of a gate signal line driver circuit for implementing the present invention.

FIG. 35 is a diagram showing a normal timing chart and a signal writing state according to the driving method of the present invention shown in Embodiment 15;

FIG. 36 is a diagram showing a timing chart and a state of signal writing in a case where there is a shift due to a signal delay or the like in the driving method of the present invention shown in Embodiment 15;

FIG. 37 is a diagram showing a timing chart and a state of signal writing in a case where there is a shift due to a signal delay or the like in the driving method of the present invention shown in Embodiment 15;

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 680 G09G 3/20 680S 680P

Claims (11)

[Claims] 1. One frame period is n sub-frame periods
SF₁, SF_Two, ..., SF_nEach of the sub-frame periods has an address (write)
Period Ta₁, Ta_Two, ..., Ta_nAnd the sustain (dot
Light) period Ts₁, Ts_Two, ... Ts_nAnd the
The length of the stain (lighting) period is Ts₁: Ts_Two,: ・ ・
・ ： Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2⁰By controlling the length of the lighting time of the self-luminous element, the n-bit gradation
The method of driving an electronic device for controlling, wherein at least one of the n subframe periods is
During the sub-frame period, the address (write
Only) period and the sustain (lighting) period overlap
A method for driving an electronic device, comprising a period. 2. One frame period is n sub-frame periods
SF₁, SF_Two, ... SF_nEach of the sub-frame periods has an address (write)
Period Ta₁, Ta_Two, ... Ta_nAnd the sustain (dot
Light) period Ts₁, Ts_Two, ... Ts_nAnd the length of the sustain (lighting) period is Ts₁: T
s_Two,: ...: Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2
⁰By controlling the length of the lighting time of the self-luminous element, the n-bit gradation
In the method of driving an electronic device for controlling, a plurality of gate signal line selection periods in the sub-frame period
Have m sub-gate signal line selection periods, respectively.
During the sub-gate signal line selection period, at most one gate
A vertical signal line is selected up to m × n times in one frame period.
And a driving method of the electronic device. 3. One frame period is n sub-frame periods
SF₁, SF_Two, ... SF_nEach of the sub-frame periods has an address (write)
Period Ta₁, Ta_Two, ... Ta_nAnd the sustain (dot
Light) period Ts₁, Ts_Two, ... Ts_nAnd the length of the sustain (lighting) period is Ts₁: T
s_Two,: ...: Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2
⁰By controlling the length of the lighting time of the self-luminous element, the n-bit gradation
In the method of driving an electronic device for controlling, a plurality of gate signal line selection periods in the sub-frame period
Have m sub-gate signal line selection periods, respectively.
During the sub-gate signal line selection period, at most one gate
A gate signal line is selected, and in the gate signal line selection period, a maximum of m
A gate signal line is selected.
Driving method of child device. 4. One frame period is n sub-frame periods
SF₁, SF_Two, ... SF_nEach of the sub-frame periods has an address (write)
Period Ta₁, Ta_Two, ... Ta_nAnd the sustain (dot
Light) period Ts₁, Ts_Two, ... Ts_nAnd the length of the sustain (lighting) period is Ts₁: T
s_Two,: ...: Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2
⁰By controlling the length of the lighting time of the self-luminous element, the n-bit gradation
In the method of driving an electronic device for controlling, a plurality of gate signal line selection periods in the sub-frame period
Have m sub-gate signal line selection periods, respectively.
During the sub-gate signal line selection period, at most one gate
A gate signal line is selected, and in the gate signal line selection period, a maximum of m
Is selected, and the address (write) in different sub-frame periods is selected.
If the write (write) period overlaps, the address (write
Only) Reset signal for a length equal to the period where the period overlaps
While the reset signal is being input.
Driving an electronic device characterized in that the child is turned off
Method. 5. A source signal line drive circuit and a gate signal line drive circuit.
An active circuit and a plurality of self-luminous elements are arranged in a matrix.
An electronic device having a pixel portion, wherein one frame period includes n sub-frame periods SF₁, S
F_Two, ... SF_nEach of the n sub-frame periods has an address (write
Including) period Ta₁, Ta_Two, ... Ta_nAnd the sustain
(Lighting) period Ts₁, Ts_Two, ... Ts_nAnd the length of the sustain (lighting) period is Ts₁: T
s_Two,: ...: Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2
⁰The length of the lighting time of the self-luminous element is controlled to
An electronic device for performing gradation control, wherein at least one of the n sub-frame periods is
During the sub-frame period, the address (write
Only) period and the sustain (lighting) period overlap
An electronic device having a period. 6. A source signal line driving circuit and a gate signal line driving circuit.
An active circuit and a plurality of self-luminous elements are arranged in a matrix.
An electronic device having a pixel portion, wherein one frame period includes n sub-frame periods SF₁, S
F_Two, ... SF_nEach of the sub-frame periods has an address (write)
Period Ta₁, Ta_Two, ... Ta_nAnd the sustain (dot
Light) period Ts₁, Ts_Two, ... Ts_nAnd the length of the sustain (lighting) period is Ts₁: T
s_Two,: ...: Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2
⁰By controlling the length of the lighting time of the self-luminous element, the n-bit gradation
In the electronic device that performs control, a plurality of gate signal line selection periods within the sub-frame period
Have m sub-gate signal line selection periods, respectively.
During the sub-gate signal line selection period, at most one gate
A vertical signal line is selected up to m × n times in one frame period.
An electronic device characterized in that: 7. A source signal line driving circuit and a gate signal line driving circuit.
An active circuit and a plurality of self-luminous elements are arranged in a matrix.
An electronic device having a pixel portion, wherein one frame period includes n sub-frame periods SF₁, S
F_Two, ... SF_nEach of the sub-frame periods has an address (write)
Period Ta₁, Ta_Two, ... Ta_nAnd the sustain (dot
Light) period Ts₁, Ts_Two, ... Ts_nAnd the length of the sustain (lighting) period is Ts₁: T
s_Two,: ...: Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2
⁰By controlling the length of the lighting time of the self-luminous element, the n-bit gradation
In the electronic device that performs control, a plurality of gate signal line selection periods within the sub-frame period
Have m sub-gate signal line selection periods, respectively.
During the sub-gate signal line selection period, at most one gate
A gate signal line is selected, and in the gate signal line selection period, a maximum of m
A gate signal line is selected.
Child device. 8. A source signal line driving circuit and a gate signal line driving circuit.
An active circuit and a plurality of self-luminous elements are arranged in a matrix.
An electronic device having a pixel portion, wherein one frame period includes n sub-frame periods SF₁, S
F_Two, ... SF_nEach of the sub-frame periods has an address (write)
Period Ta₁, Ta_Two, ... Ta_nAnd the sustain (dot
Light) period Ts₁, Ts_Two, ... Ts_nAnd the length of the sustain (lighting) period is Ts₁: T
s_Two,: ...: Ts_n= 2^{( n-1)}: 2^(n-2): ・ ・ ・: 2
⁰By controlling the length of the lighting time of the self-luminous element, the n-bit gradation
In the electronic device that performs control, a plurality of gate signal line selection periods within the sub-frame period
Have m sub-gate signal line selection periods, respectively.
During the sub-gate signal line selection period, at most one gate
A gate signal line is selected, and in the gate signal line selection period, a maximum of m
Is selected, and the address (write) in different sub-frame periods is selected.
If the write (write) period overlaps, the address (write
Only) Reset signal for a length equal to the period where the period overlaps
While the reset signal is being input.
An electronic device, wherein the child is turned off. 9. A source signal line driving circuit, a gate signal line driving circuit, and a pixel portion in which a plurality of self-luminous elements are arranged in a matrix of a rows and b columns, wherein the source signal line driving circuit A source driver circuit having at least one first shift register circuit, a first storage circuit for storing a digital video signal, and a second storage circuit for storing an output signal of the first storage circuit. The gate signal line drive circuit includes a plurality of gate driver circuits each including at least one second shift register circuit and at least one buffer circuit, and one frame period includes n gate driver circuits. Subframe periods SF ₁ , S
F ₂ ,... SF _n , wherein the plurality of gate signal line selection periods in the sub-frame period have m sub-gate signal line selection periods, and at most one sub-gate signal line selection period In the electronic device in which a maximum of m different gate signal lines are selected during the gate signal line selection period, one source signal line connects the first switch circuit. The gate signal line is electrically connected to a maximum of m gate driver circuits via a second switch circuit; and the source is connected to a maximum of m source driver circuits via a second switch circuit. The signal line drive circuit has a maximum of b × m source driver circuits; the gate signal line drive circuit has a maximum of a × m gate driver circuits; In the dot data writing period, only one of the m electrically connected source driver circuits is selected and connected to the source signal line to write a signal, and the second switch circuit In one sub-gate signal line selection period, only one of the m electrically connected gate driver circuits is selected and connected to the gate signal line to select a gate signal line. Electronic device characterized by. 10. A method of driving an electronic device according to claim 1, wherein the driving method comprises the steps of:
L display, video camera, head mounted display, DVD player, personal computer, mobile phone, or car audio. 11. An EL display, a video camera, a head-mounted display, and a digital camera, comprising the electronic device according to claim 5.
VD player, personal computer, mobile phone, or car audio.