JP2001318111A - Capacitance measuring circuit capacitance comparator and buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a capacitance measuring circuit whose circuit scale can be reduced and which can control a current in a charging and discharge operation. SOLUTION: NMOS transistors 3 and 4 by which a current according to a constant current from a constant current source 11 is made to flow are connected to a power supply via PMOS transistors 1 and 2 which are turned on/off by a single-phase clock from a clock generation circuit 10. The electric charge of a capacitance 8, to be measured, which is charged at a time when the PMOS transistor 2 is turned on is discharged via the NMOS transistor 4 at a time when the transistor is turned off. On the basis of a DC current which flows in the NMOS transistor 3, on the basis of a DC current which flows in the NMOS transistor 4 on the basis of the frequency of the clock and on the basis of the voltage of the power supply, the capacitance of the capacitance to be measured is found.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance measuring circuit for measuring a minute capacitance such as a wiring capacitance between AL (aluminum), and further utilizes the principle of the capacitance measuring circuit. The present invention relates to a capacitance comparator and a buffer circuit for automatically selecting a driver size using the capacitance comparator.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a conventional capacitance measuring circuit. In the figure, reference numerals 1 and 2 denote PMOS transistors whose gates are connected to each other and whose sources are each connected to a power supply of a voltage Vdd. Reference numerals 3 and 4 denote NMs whose gates are connected to each other and whose sources are each connected to the ground.
The NMOS transistor 3 is an OS transistor.
Are the drain of the PMOS transistor 1 and N
The drain of the MOS transistor 4 is connected to the drain of the PMOS transistor 2, respectively. 5 is PMO
An ammeter for measuring a DC current value flowing through a series circuit of the S transistor 1 and the NMOS transistor 3 is shown.
This is an ammeter for measuring a DC current value flowing through a series circuit of the OS transistor 2 and the NMOS transistor 4.

Reference numeral 7 denotes a gate of the PMOS transistor 1 and P
A connection point between the gate of the MOS transistor 2 and the NMOS
This is a two-phase clock generation circuit that supplies non-overlapping two-phase clocks CK1 and CK2 to a connection point between the gate of the transistor 3 and the gate of the NMOS transistor 4. 8 is a drain of the PMOS transistor 2 and an NMOS
This is a capacitance to be measured such as a wiring capacitance between ALs, which is connected to a connection point with the drain of the transistor 4 and whose capacitance is measured.

Next, the operation will be described. Measured capacity 8
When measuring the capacitance value of the two-phase clock generation circuit 7,
Two-phase clocks CK that are more non-overlapping with each other
1, CK2, and one of them (clock CK2) is
The other (clock CK1) is supplied to the gate of the MOS transistor 1 and the gate of the PMOS transistor 2, and to the gate of the NMOS transistor 3 and the gate of the NMOS transistor 4, respectively. The PMOS transistors 1 and 2 and the NMOS transistors 3 and 4 are turned on / off in accordance with the two-phase clocks CK1 and CK2, and the measured capacitor 8 is charged / discharged in accordance with the on / off of the PMOS transistor 2 and the NMOS transistor 4. in this way,
This non-overlapping 2 is applied to ON / OFF of the PMOS transistors 1 and 2 and the NMOS transistors 3 and 4.
By using the phase clocks CK1 and CK2, it is possible to prevent a through current from flowing when the measured capacitor 8 is charged and discharged.

FIG. 6 is a waveform diagram showing an example of non-overlapping two-phase clocks CK1 and CK2 output from the two-phase clock generation circuit 7. As shown, the frequency of the non-overlapping two-phase clocks CK1 and CK2 output from the two-phase clock generation circuit 7 is assumed to be f. These two-phase clocks CK1,
When the measured capacitance 8 is charged and discharged by CK2, P
The direct current value I1 flowing through the series circuit of the MOS transistor 1 and the NMOS transistor 3 is calculated by the ammeter 5 as P
A DC current value I2 flowing through a series circuit of the MOS transistor 2 and the NMOS transistor 4 is measured by the ammeter 6, respectively. The capacitance value C of the capacitance 8 to be measured can be obtained from the voltage Vdd of the power supply, the DC current values I1 and I2, and the frequency f of the two-phase clocks CK1 and CK2 according to the following equation.

I1-I2 = C.Vdd.f

As a conventional capacitance measuring circuit,
In addition to this, for example, the capacitor to be measured and the auxiliary capacitor are charged with a constant current, and when the charging voltage becomes a constant value, those charges are discharged, and the charging time is measured by counting a clock from a clock generation circuit. To obtain the capacitance value of the capacitor to be measured.
And the like disclosed in the official gazette.

[0008]

Since the conventional capacitance measuring circuit is constructed as described above, a non-overlapping circuit is provided to prevent a through current from flowing when charging and discharging the capacitance 8 to be measured. A two-phase clock is required.
Two-phase clock generation circuit 7 for generating phase clocks
Not only will the circuit scale be large,
At the time of charging / discharging of the measured capacitor 8, the PMOS transistors 1, 2
Since the drain voltage instantaneously changes to the power supply or the ground, there is a problem that an instantaneous current flows when the measured capacitor 8 is charged or discharged.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a capacitance measuring circuit capable of reducing a circuit scale and controlling a current when charging and discharging a measured capacitance. With the goal.

Another object of the present invention is to provide a capacitance comparator for comparing capacitances by utilizing the principle of the capacitance measuring circuit.

Another object of the present invention is to provide a buffer circuit for automatically selecting a driver size by using the above-mentioned capacitance comparator.

[0012]

The capacitance measuring circuit according to the present invention comprises a third and a fourth element for supplying a current corresponding to a constant current from a constant current source, to a single-phase signal from a clock generating circuit. It is connected to a power supply via first and second elements that are turned on / off by a clock, and charges the measured capacitance charged when the second element is in an on state, and charges the electric charge of the capacitance to be measured when the second element is in an off state. And the DC current flowing through the series circuit of the first element and the third element, the series current flowing through the series circuit of the second element and the fourth element, The capacitance of the capacitance to be measured is obtained based on the frequency and the voltage of the power supply.

In the capacitance measuring circuit according to the present invention, a fifth element is provided in series with a constant current source, and a third element and a fourth element are provided.
Current flowing through the third element or the fourth element
And a constant current value proportional to the element size of the element.

The capacitance comparator according to the present invention turns on / off the third and fourth elements for supplying a current corresponding to the constant current from the constant current source with a single-phase clock from the clock generation circuit.
Connected to a power supply via the first and second elements to be turned off,
When the first and second elements are off, the charge of each comparison capacitor charged when the first and second elements are on is discharged via the third and fourth elements when the first and second elements are off. The comparison of the electrostatic capacity of each comparison capacitor is performed by comparing the charging voltage of each comparison capacitor by the comparator.

In the capacitance comparator according to the present invention, a fifth element is provided in series with a constant current source, and a current flowing through the third element and the fourth element is supplied to the third element or the fourth element. The constant current value is proportional to the element size with the element.

In the buffer circuit according to the present invention, the capacitance of the pad is compared with the reference capacitance by the capacitance comparator, and the switch element is turned on / off according to the comparison result, thereby expanding the driver size of the buffer circuit. For activating the extended driver element for this purpose.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a capacitance measuring circuit according to Embodiment 1 of the present invention. In the figure, reference numeral 1 denotes a PMOS transistor as a first element which is turned on / off by a clock CK input to a gate and whose source is connected to a power supply of a voltage Vdd, and 2 denotes a clock input to a gate. It is a PMOS transistor as a second element that is on / off controlled by CK and whose source is connected to the power supply of the voltage Vdd. 3 has a constant current input to the gate, a source connected to ground, and a drain connected to PMO.
An NMOS transistor as a third element is connected to the drain of the S transistor 1. A constant current is input to the gate, a source is connected to the ground, and a drain is connected to the drain of the PMOS transistor 2. An NMOS transistor as a fourth element.

Reference numeral 5 denotes an ammeter for measuring a DC current value I1 flowing through a series circuit of the PMOS transistor 1 and the NMOS transistor 3. Reference numeral 6 denotes a PMOS transistor and an NM.
DC current value I2 flowing through the series circuit of OS transistor 4
Is an ammeter that measures 8 is a PMOS transistor 2
Is a minute capacitance to be measured such as a wiring capacitance between ALs, which is connected to a connection point between the drain of the NMOS transistor 4 and the drain of the NMOS transistor 4 and whose capacitance value is measured. These are the parts corresponding to the respective parts of the conventional capacitance measuring circuit indicated by the same reference numerals in FIG.

Reference numeral 10 denotes a gate of the PMOS transistor 1 and a gate of the PMOS transistor 2 which are connected to each other;
This is a clock generation circuit that supplies a single-phase clock CK. Reference numeral 11 denotes a constant current source that supplies a constant DC current to the gate of the NMOS transistor 3 and the gate of the NMOS transistor 4 that are connected to each other. 12 is a gate with NMO
The source of the S transistor 3 and the gate of the NMOS transistor 4 are connected to the ground, and the drain is connected to the constant current source 1.
1 connected to its own gate and flowing through NMOS transistors 3 and 4
An NMOS transistor as a fifth element for obtaining a constant current value in proportion to the element size of the transistor 3 or the NMOS transistor 4.

As described above, in the first embodiment, in the conventional capacitance measuring circuit, one of the non-overlapping two-phase clocks CK1 and CK2 is supplied to the NMO.
The DC constant current generated in the series circuit of the constant current source 11 and the NMOS transistor 12 is supplied to the gates of the S transistor 3 and the NMOS transistor 4.

Next, the operation will be described. Here, FIG.
FIG. 4 is a waveform diagram showing an example of a single-phase clock CK output from the two-phase clock generation circuit. When measuring the capacitance value of the capacitance 8 to be measured, the clock generation circuit 10 generates a single-phase clock CK having a frequency f as shown in FIG.
Supply to the gate of transistor 2. PMOS transistors 1 and 2 receive clock CK input to their gates.
Is on during the period of “L” (low level), and NM
The drains of the OS transistors 3 and 4 are connected to the power supply of the voltage Vdd. Accordingly, the capacitor 8 to be measured connected to the drain of the NMOS transistor 4 is charged with electric charge, and a constant current also flows through the NMOS transistors 3 and 4 where no current has flowed until then.

Here, NMOS transistors 3 and 4
Is connected to the gate and drain of the NMOS transistor 12 and supplied with a DC constant current from the constant current source 11, so that when the PMOS transistors 1 and 2 are turned on, the NMOS transistors 3 and The constant current flowing through 4 has a current value proportional to the element size of NMOS transistors 3 and 4 and NMOS transistor 12. Therefore, it is possible to prevent a through current from flowing when charging the measured capacitance 8, and to reduce the PM during charging.
It is possible to prevent the drain voltages of the OS transistors 1 and 2 from instantaneously changing to the power supply or the ground.

On the other hand, when the clock CK input to each gate becomes "H" (high level), the PMOS transistors 1 and 2 are turned off, and the drains of the NMOS transistors 3 and 4 are disconnected from the power supply. Accordingly, the constant current flowing through the NMOS transistor 3 is cut off, and the electric charge charged in the capacitor 8 to be measured becomes NM.
Discharged through the OS transistor 4. At that time, NM
The gate and the drain of the NMOS transistor 12 are connected to the gate of the OS transistor 4 and a DC constant current from the constant current source 11 is supplied.
A constant current flows through the OS transistor 4 from the capacitor 8 to be measured in proportion to the element size of the NMOS transistor 12. With this constant current, the electric charge charged in the capacitor 8 to be measured is discharged to the ground via the NMOS transistor 4.

As described above, the gates and drains of the NMOS transistors 12 are connected to the gates of the NMOS transistors 3 and 4, and the DC constant current from the constant current source 11 is supplied. A current proportional to the element size of the transistor and the NMOS transistor 12 flows, and the electric charge charged in the capacitor 8 to be measured is discharged by this current. Therefore, a through current does not occur when the measured capacitor 8 is discharged, and it is possible to prevent the drain voltages of the PMOS transistors 1 and 2 from instantaneously changing to the power supply or the ground during the discharge.

The period T of the clock CK requires a sufficient time for the charge of the measured capacitor 8 to be charged and discharged.
Here, it is assumed that the frequency of the clock CK output from the clock generation circuit 10 is f (f = 1 / T) as shown in FIG. When the PMOS transistors 1 and 2 are turned on / off by the clock CK having the frequency f from the clock generation circuit 10, the PMOS transistor 1
The DC current value I1 flowing through the series circuit of the PMOS transistor 2
The DC current value I2 flowing through the series circuit of the NMOS transistor 4 and the NMOS transistor 4 is measured by the ammeter 6, respectively. From the DC current values I1 and I2, the power supply voltage Vdd and the frequency f of the clock CK, the capacitance to be measured 8
Can be obtained.

I1−I2 = C · Vdd · f

As described above, according to the first embodiment, a constant DC current is supplied from the constant current source 11 to the NMOS transistors 3 and 4 so that the through current flowing during charging and discharging of the capacitor 8 to be measured is reduced. Since the drain can be prevented from instantaneously changing to a power supply or a ground when the PMOS transistors 1 and 2 are charged and discharged, a through current can be prevented from flowing when charging and discharging the capacitance to be measured conventionally. A non-overlapping two-phase clock that was necessary for
A simple circuit can be used as the clock generation circuit 10, and the effect that the capacitance measurement circuit can be downsized can be obtained.

According to the first embodiment, the NMOS transistor 12 having the drain and the gate connected to each other is
Since it is connected in series to the constant current source 11, the NMO
The current flowing through S transistors 3 and 4 is
Since a constant current value can be obtained in proportion to the element size of the OS transistors 3 and 4 and the NMOS transistor 12, the degree of freedom in setting the current flowing through the NMOS transistors 3 and 4 in the capacitance measuring circuit is increased. The effect that it can be obtained is also obtained.

In the above description, the first element is a PMO
The S transistor 1, the second element is a PMOS transistor 2, the third element is an NMOS transistor 3, the fourth element is an NMOS transistor 4, and the measured capacitor 8 is a PMO.
Drain of S transistor 2 and NMOS transistor 4
The one connected to the connection point with the drain of
Element is a PMOS transistor 2 and the second element is a PMO
S transistor 1, the third element is NMOS transistor 4, and the fourth element is NMOS transistor 3, PM
The capacitance 8 to be measured may be connected to a connection point between the drain of the OS transistor 1 and the drain of the NMOS transistor 3.

Embodiment 2 FIG. Next, as a second embodiment of the present invention, a capacitance comparator using the principle of the capacitance measuring circuit described in the first embodiment will be described. FIG. 3 is a circuit diagram showing such a capacitance comparator according to the second embodiment of the present invention. In the figure, 1 is a PMOS transistor as a first element, 2 is a PMOS transistor as a first element, and 3 is N as a third element.
MOS transistor 4 is NMOS as a fourth element
The transistor 10 is a clock generation circuit, 11 is a constant current source, 12 is an NMOS transistor as a fifth element, and these correspond to those of the first embodiment shown in FIG. Part.

Reference numerals 13 and 14 denote comparison capacitors whose capacitances are compared with each other. The comparison capacitor 13 is connected to the connection point between the drain of the PMOS transistor 1 and the drain of the NMOS transistor 3, and the comparison capacitor 14 is connected to the PMOS transistor 2
And the drain of the NMOS transistor 4 are connected to each other. Reference numeral 15 denotes one of the input terminals (−) having the drain of the PMOS transistor 1 and the NMOS.
A comparator is connected to a connection point between the drain of the transistor 3 and the other (+) to a connection point between the drain of the PMOS transistor 2 and the drain of the NMOS transistor 4 to compare their voltages. This is a latch for temporarily holding the output of. The comparator 15 and the latch 16 are controlled by a clock CK generated by the clock generation circuit 10.

Next, the operation will be described. Embodiment 1
Similarly to the case described above, while the clock CK generated by the clock generation circuit 10 is “L”, the PMOS transistors 1 and 2 are turned on, and the comparison capacitor 13 is turned on.
And 14 are charged. Note that this clock C
During the period when K is “L”, the comparator 15 does not operate, and the latch 16 holds the data of the previous cycle.

After a lapse of time sufficient to complete the charging of the comparison capacitors 13 and 14, the clock CK generated by the clock generation circuit 10 becomes "H". This clock C
During the period when K is “H”, the PMOS transistors 1 and 2 are turned off, and the charges charged in the comparison capacitors 13 and 14 are discharged via the NMOS transistor 3 or the NMOS transistor 4. Here, the gates of the NMOS transistors 3 and 4 have N
Since the gate and drain of the MOS transistor 12 are connected and a DC constant current is supplied from the constant current source 11, the NMOS transistor 3 has a comparison capacitor 13
Therefore, the NMOS transistor 4 has a comparison capacitance 14
A constant current flows in proportion to the element size with the NMOS transistor 12. With this constant current, the comparison capacity 13
And 14 are discharged to ground via NMOS transistor 3 or 4.

At this time, the PMOS transistor 1 and the NMOS transistor
A difference occurs between the drain voltage of the transistor 3 (the charging voltage of the comparison capacitor 13) and the drain voltages of the PMOS transistor 2 and the NMOS transistor 4 (the charging voltage of the comparison capacitor 14). These voltages are input to the respective input terminals of the comparator 15, and are compared with each other when the clock CK becomes "H". The comparison result of the comparator 15 is held in the latch 16 when the clock CK becomes “H”, and is output as a comparison result of the capacitances of the comparison capacitors 13 and 14. By repeating this operation in accordance with the clock CK, the capacitance comparison between the comparison capacitors 13 and 14 can be performed every cycle.

As described above, according to the second embodiment, the NMOS transistors 3 and 4 are
, The comparison capacitors 13 and 14 can be discharged slowly, and the conventional capacitance measurement circuit instantaneously changes to a power supply or a ground during charging and discharging. PMOS transistor 1 (NMO
The drain voltage of the S transistor 3) and the drain voltage of the PMOS transistor 2 (NMOS transistor 4) can be slowly changed, and the capacitance of the comparison capacitors 13 and 14 is made using the difference between the drain voltages. Can be realized.

Embodiment 3 FIG. By using the capacitance comparator according to the second embodiment, it is possible to realize a buffer circuit that automatically selects an I / O driver size. FIG. 4 is a circuit diagram showing such a buffer circuit according to Embodiment 3 of the present invention. In the figure, reference numeral 20 denotes a capacitance comparator having the configuration shown in the second embodiment, and reference numeral 21 denotes an inverter for inverting the output of the capacitance comparator 20. Reference numeral 22 denotes a PMOS transistor as a switch element which is turned on / off according to a comparison result output from the output terminal OUT of the capacitance comparator 20. Reference numeral 23 denotes a capacitance transistor whose polarity is inverted by the inverter 21. This is an NMOS transistor as a switch element that is turned on / off according to the comparison result.

Reference numeral 24 denotes a PMOS transistor as a driver element in the buffer circuit, and reference numeral 25 denotes an NMOS transistor similarly as a driver element.
The drains of the PMOS transistor 24 and the NMOS transistor 25 are connected to each other, and a buffer input is input to each gate. Also, PMOS
The source of the transistor 24 is connected to the power supply, and the source of the NMOS transistor 25 is connected to the ground.

A PMOS transistor 26 is connected in parallel with the PMOS transistor 24 to extend the driver size, and serves as an extended driver element.
An NMOS transistor 27 is connected in parallel to the NMOS transistor 25 and serves as an extended driver element for expanding the driver size. These PMOs
The drains of the S transistor 26 and the NMOS transistor 27 are connected to each other, and a buffer input is input to each gate. The source of the PMOS transistor 26 is connected to the power supply via the PMOS transistor 22, and the source of the NMOS transistor 27 is connected to the ground via the NMOS transistor 23. The PMOS transistor 26 and the NMOS transistor 27 are connected to the PMOS transistor 22. And NMO
Activation / inactivation is controlled by turning on / off the S transistor 23.

Reference numeral 28 is a reference capacitance which is connected to one of the input terminals (IN1) of the capacitance comparator 20 and is compared with a load capacitance. 29 is a PMOS transistor 24
And a connection point between the drain of the NMOS transistor 25 and the drain of the PMOS transistor 26 and the drain of the NMOS transistor 27 to output the buffer output of the buffer circuit. It is connected to the other input terminal (IN2) of the capacitance comparator 20, and its load capacitance is compared with the reference capacitance.

Next, the operation will be described. If the reference capacitance connected to one input terminal IN1 is larger than the load capacitance connected to the other input terminal IN2, the capacitance comparator 20 compares the comparison result output from the output terminal OUT with “H”. ”,“ L ”if smaller, PMO
The polarity is inverted by an inverter 21 and applied to the gate of the NMOS transistor 23 directly to the gate of the S transistor 22. Therefore, when the comparison result of the capacitance comparator 20 is “H”, the PMOS transistor 22 and the NMOS transistor
Transistor 23 is turned off, and PMOS transistor 26 and NMOS transistor 27 are deactivated. When a buffer input is input during a period when the comparison result of the capacitance comparator 20 is "H", only the PMOS transistor 24 and the NMOS transistor 25 perform on / off operations according to the buffer input, and output the buffer output. Output to pad 29. At this time, if the load capacity of the pad 29 increases, the driver size becomes insufficient and the delay time of the buffer output increases.

Therefore, the pad 29 is connected to one input terminal IN2 of the capacitance comparator 20, and the load capacitance is connected to the reference capacitor 28 connected to the other input terminal IN1 of the capacitance comparator 20. Compare with as a result,
When the load capacitance of the pad 29 becomes larger than the reference capacitance 28, the capacitance comparator 20 sets the output comparison result to "L". Accordingly, the PMOS transistor 22 and the NMOS transistor 23 shift to the ON state, and the PMOS transistor 26 and the NMOS transistor 27 are activated. Therefore, the PMOS transistor 2
4 and the PMOS transistor 26, and the NMOS transistor 25 and the NMOS transistor 27 perform an on / off operation based on the buffer input, and output a buffer output corresponding to the on / off operation to the pad 29. Thus, pad 2
When the load capacitance of No. 9 exceeds the reference capacitance 28, the PMOS transistor 22 and the NMOS transistor 23 are turned on to automatically increase the driver size, so that the delay time of the buffer output is reduced.

A plurality of reference capacitors are prepared.
By performing on / off control of a plurality of pairs of switch elements based on the result of comparison with each of the reference capacitors, it is also possible to automatically select several types of driver sizes.

As described above, according to the third embodiment, based on the comparison result between the reference capacitance 28 and the load capacitance of the pad 29 by the capacitance comparator 20, the PMOS
Since the PMOS transistor 22 that connects the source of the transistor 26 to the power supply and the NMOS transistor 23 that connects the source of the NMOS transistor 27 to the ground are turned on / off, even if the load capacitance changes in the middle, every time the clock period changes. In this case, the driver size can be automatically selected, and a buffer circuit that can prevent an increase in the delay time of the buffer output due to a shortage of the driver size can be realized even if the load capacity of the pad 29 increases.

[0044]

As described above, according to the present invention, the first current flowing from the constant current source through the first and second elements turned on / off by the single-phase clock is supplied. The third element and the fourth element are connected to a power supply, and the electric charge of the capacitor to be measured charged when the second element is turned on is discharged via the fourth element when the second element is turned off. Since the capacitance of the capacitance to be measured is obtained by using the DC current flowing through the DC circuit and the series current flowing through the DC circuits of the second and fourth elements, a through current is generated when charging and discharging the capacitance to be measured. Is eliminated, so that a non-overlapping two-phase clock, which was necessary to prevent a through current in the conventional capacitance measurement circuit, is not required, and the capacitance of the capacitance to be measured is measured with a single-phase clock. Clock can be measured because The circuit is simplified, the circuit scale of the capacitance measuring circuit can be reduced, and the effect of obtaining the capacitance measuring circuit that can control the current when charging and discharging the measured capacitance is obtained. is there.

According to the invention, the fifth element is provided in series with the constant current source, and the current flowing through the third element and the fourth element is proportional to the element size of the fifth element and the fourth element. Since the configuration is such that the current value is constant, there is an effect that it is possible to obtain a capacitance measuring circuit having a greater degree of freedom in setting the current flowing through the third element and the fourth element.

According to the present invention, the third and fourth elements, which supply a current according to the constant current from the constant current source, through the first and second elements which are turned on / off by a single-phase clock, are used. When the first and second elements are turned on, the respective comparison capacitors charged are charged, and when the first and second elements are turned off, the respective comparison capacitors are discharged via the third and fourth elements. By comparing the charging voltage by a comparator, the configuration is such that the capacitance of each comparison capacitor is compared.
Since the current flowing through the third and fourth elements is defined by the constant current source and the comparison capacitor can be slowly discharged, the capacitance of each of the comparison capacitors is used by utilizing the difference between the charging voltages of the respective comparison capacitors. This is effective in obtaining a capacitance comparator for comparing.

According to the present invention, the fifth element is provided in series with the constant current source, and the current flowing through the third element and the fourth element is proportional to the element size of these elements and the fifth element. Since the configuration is such that the current value is constant, there is an effect that it is possible to obtain a capacitance comparator having a greater degree of freedom in setting the current flowing through the third element and the fourth element.

According to the present invention, the switch element is turned on / off according to the comparison result between the load capacity of the pad and the reference capacity by the capacitance comparator, and the expansion driver element for expanding the driver size of the buffer circuit is activated. The driver size can be automatically selected for each clock cycle even if the load capacity changes in the middle. There is an effect that a buffer circuit capable of preventing an increase in time can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a capacitance measuring circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating an example of a single-phase clock in the capacitance measuring circuit according to the first embodiment.

FIG. 3 is a circuit diagram showing a capacitance comparator according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a buffer circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional capacitance measuring circuit.

FIG. 6 is a waveform diagram showing an example of a non-overlapping two-phase clock in a conventional capacitance measuring circuit.

[Explanation of symbols]

1 PMOS transistor (first element), 2 PMO
S transistor (second element), 3 NMOS transistor (third element), 4 NMOS transistor (fourth element)
Element), 5, 6 ammeter, 8 capacitance to be measured, 10 clock generation circuit, 11 constant current source, 12 NMOS transistor (fifth element), 13, 14 comparison capacitance, 15
Comparator, 16 latch, 20 capacitance comparator,
21 inverter, 22 PMOS transistor (switch element), 23 NMOS transistor (switch element), 24 PMOS transistor (driver element),
25 NMOS transistor (driver element), 26
PMOS transistor (extended driver element), 27 N
MOS transistor (extended driver element), 28 reference capacitors.

Claims (5)

[Claims] A first element for turning on / off the connection of a power supply according to a single-phase clock; and a first element for turning on / off the connection of a power supply according to the single-phase clock, and charging a capacitance to be measured in an on state. A second element, a third element that is connected to a power supply when the first element is in an on state, and flows a current corresponding to an input constant current, and is connected to a power supply when the second element is in an on state. And flowing a current according to the input constant current, and discharging the electric charge charged in the capacitance to be measured by the current according to the input constant current when the second element is off. A fourth element, a clock generation circuit that generates a single-phase clock to be supplied to the first element and the second element, and a constant that generates a constant current to be supplied to the third element and the fourth element. Capacitance measurement with current source Circuit. A fifth element for setting a current flowing through the third element and the fourth element to a constant current value proportional to the element size of the third element or the fourth element;
2. The capacitance measuring circuit according to claim 1, wherein the capacitance measuring circuit is provided in series with the constant current source. 3. A first and a second circuit for turning on / off a connection of a power supply according to a single-phase clock, and charging comparison capacitors whose capacitances are compared with each other in an on state.
An element connected to a power supply when the first element is in an on-state, allowing a current corresponding to an input constant current to flow, and charging one of the comparison capacitors when the first element is in an off-state. A third element for discharging the received electric charge by a current corresponding to the input constant current, and a third element connected to a power supply when the second element is in an on state, to flow a current corresponding to the input constant current. And a fourth element for discharging a charge charged to the other of the comparison capacitors by a current corresponding to the input constant current when the second element is in an off state; A comparator that compares a charging voltage according to the single-phase clock; a clock generation circuit that generates a single-phase clock to be supplied to the first element, the second element, and the comparator; Capacitance comparator and a constant current source for generating constant current supplied to the element. 4. A fifth element for setting a current flowing through the third element and the fourth element to a constant current value proportional to the element size of the third element or the fourth element,
4. The capacitance comparator according to claim 3, wherein the capacitance comparator is provided in series with the constant current source. 5. A driver element for outputting a buffer output according to a buffer input to the buffer circuit to a pad, and an extended driver element connected in parallel to the driver element for expanding a driver size. A capacitance comparator that compares a load capacitance of the pad to which a buffer output is output with a reference capacitance; and a switch element that controls activation / inactivation of the extended driver element according to a comparison result of the capacitance comparator. And a buffer circuit comprising: