JP2001308036A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problems of decrease in a throughput of dicing, as a result of unavoidable adopting a complicated dicing technology due to the presence of a metal pattern formed on a cutting region of a semiconductor wafer, adverse effects of a cutout or the like occurring on the main surface and a rear surface of the outer periphery of the cut region, the so-called chipping to a semiconductor chip, when the cutting region is intended to be simply cut, an occurrence of a cutting residue of a pad or the like for a TEG, even after a cutting step and an occurrence of a short circuit fault. SOLUTION: A method for manufacturing a semiconductor device comprises the steps of removing parts of a film of the cutting region 3 of the semiconductor wafer and the wafer by etching, and then cutting the wafer by dicing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a dicing technique for cutting a semiconductor chip from a semiconductor wafer.

[0002]

2. Description of the Related Art A dicing process is basically a simple process of cutting out individual semiconductor chips from a semiconductor wafer after a wafer process (previous process) is completed. Various technologies have been accumulated in order to respond to a demand for a large diameter semiconductor wafer and a demand for high productivity. Specifically, after a semiconductor wafer for which a wafer process has been completed is attached to a carrier tape, the semiconductor wafer is cut by applying a dicer blade to a cutting region of the semiconductor wafer while rotating the blade at a high speed.

[0003] The dicing technology is described in, for example, “Electronic Materials Separate Volume, 1998 Edition, Ultra LSI Manufacturing and Testing Equipment Guidebook”, pp. 23 to 28, published by the Industrial Research Institute, November 25, 1997. Are described in detail.

[0004]

However, the present inventor has found that the above dicing technique has the following problems.

[0005] First, there is a problem that the presence of a metal pattern formed in a cutting region of a semiconductor wafer necessitates the use of a complicated dicing technique, resulting in a significant decrease in dicing throughput. A metal pattern such as a TEG (Test Element Group) pad is formed in the cutting area. Further, a metal pattern may be arranged for a reason of a future wafer process. For this reason, if the cutting area is simply cut, chipping or the like occurs on the main surface and the back surface of the outer periphery of the cutting area, so-called chipping has an adverse effect on the semiconductor chip. A pad or the like may be left behind, resulting in short-circuit failure. For example, when cutting is performed only with a wide blade, a problem due to chipping occurs. Conversely, when cutting is performed only with a narrow blade, the problem of chipping can be avoided, but pad cutting remains. As a result, there is a problem that the yield of the semiconductor device during the dicing process is reduced. Therefore, in the dicing technology studied by the present inventor, a so-called step-cut dicing technology is employed, in which after a TEG pad or the like is removed with a wide blade, the semiconductor wafer is cut with a narrow blade. However, in this case, there is a problem that the dicing throughput is reduced because two types of blades are used.

Secondly, since a metal material such as a pad for TEG is cut, the blade is liable to be clogged or deteriorated, and the life of the blade is shortened.

Third, there is a problem that it is impossible to cope with the reduction of the cutting area of the semiconductor wafer. If the number of semiconductor chips obtained from one semiconductor wafer increases, the yield can be improved, so that the diameter of the semiconductor wafer is increased and the cutting area is reduced. However, for example, the TEG pad or the like cannot be made very small due to the contact with the inspection probe. Therefore, as the cutting region is narrowed, the TEG pad covers most of the cutting region in the width direction. Will be placed in.
When the step cut dicing is performed in such a situation, the problem of chipping failure becomes remarkable if a wide blade is used to remove the TEG pad, whereas if only a narrow blade is used, the above problem occurs. Short failures occur due to excessive pad cutting residue. In addition, problems such as shortening of the life of the blade become more remarkable.
For this reason, there is a problem in that narrowing of the width of the cutting region is inhibited.

A fourth problem is that the uncut portion of the pad comes into contact with the bonding wire and a short circuit occurs. In recent years, the reverse bonding method has been adopted from the viewpoint of reducing the thickness of the package by reducing the wire loop of the bonding wire. this is,
In the bonding wire process, a first bonding is performed on a land of a wiring board, and then a second bonding is performed on a bonding pad of a semiconductor chip. In the case of this method, the wire loop of the bonding wire can be lowered, but as a result, the bonding wire approaches the semiconductor chip. As a result, the bonding wire and the uncut portion of the pad are short-circuited. Therefore, the yield and reliability of the semiconductor device decrease.

An object of the present invention is to provide a technique capable of improving the throughput during dicing.

Another object of the present invention is to provide a technique capable of improving the throughput at the time of dicing without reducing the yield.

Another object of the present invention is to provide a technique capable of improving the life of a dicing blade.

Still another object of the present invention is to provide a technique capable of coping with a reduction in a cutting area of a semiconductor wafer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention has a step of cutting the semiconductor wafer by dicing after partially or entirely removing the film in the cutting region of the semiconductor wafer.

Further, the present invention has a step of cutting the semiconductor wafer by dicing after removing the film in the cutting region of the semiconductor wafer and part of the semiconductor wafer by etching.

In the present invention, the film has a TEG pattern.

In the present invention, the film is made of a metal.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) A method of manufacturing a semiconductor device according to Embodiment 1 will be described with reference to FIGS.

First, a semiconductor wafer shown in FIGS. 1 to 4 is obtained through a wafer process (step 100). 2 is an overall plan view of the semiconductor wafer 1 after the wafer processing step, FIG. 3 is an enlarged plan view of a main part of FIG. 2, and FIG. 4 is a sectional view taken along line AA of FIG. 3, respectively. The wafer process is also referred to as a pre-process, starting from a mirror-polished wafer (mirror wafer), passing through a device and wiring forming process, forming a surface protection film, and finally performing an electrical test using a probe. This refers to the process up to the next step.

The semiconductor wafer 1 at this stage consists of a thin plate having a substantially circular shape having a multilayer wiring structure on a semiconductor substrate 1s made of, for example, silicon single crystal. The diameter of the semiconductor wafer 1 used here is, for example, 6 to 8 inches (150 to 8 inches).
200 mm).

On the main surface of the semiconductor wafer 1, for example, a plurality of chip forming regions 2 each having a rectangular shape in a plane are regularly arranged so as to sandwich a dicing region (cutting region) 3 between adjacent regions. The dicing region 3 is also called a street or a scribing region, is a boundary region arranged at a predetermined interval between the adjacent chip forming regions 2 and 2, and is a region that is cut in a dicing step described later. . The width of the dicing region 3 (the interval between the adjacent chip forming regions 2) is, for example, 50 to 100.
It is about μm.

In each chip forming area 2, for example, a DRAM
(Dynamic Random Access Memory), SRAM (Static
Random Access Memory) or Flash EEPROM
M (Electric Erasable Programmable Read Only Memor
y) and the like, a logic circuit such as a microprocessor, or a hybrid integrated circuit in which the memory circuit and the logic circuit are formed in the same chip formation region 2;
Alternatively, a predetermined integrated circuit such as an integrated circuit for special use such as a gate array or a cell-based IC has already been formed. The electrodes of this predetermined integrated circuit are connected to each chip formation region 2
Is drawn out to the outside through the bonding pad 4. The bonding pad 4 is made of, for example, a conductor pattern (for example, aluminum, aluminum-silicon-copper alloy, etc.) formed in a plane quadrangular shape. Are formed in the uppermost wiring layer in cross section.

FIG. 4 shows a MIS • FET (Metal Insulator Semiconducto) as an element constituting the integrated circuit.
r Field Effect Transistor) Q is illustrated. Note that the present invention provides an n-channel or p-channel MI
The present invention can be applied to an integrated circuit having any one of the S.FET and the channel-type MIS.F of both.
Since the present invention can be applied to an integrated circuit having a CMIS (Complementary MIS) circuit configured by ETQ,
The conductivity type of the S-FET Q is not specified. The elements constituting the above-mentioned predetermined integrated circuit are MIS-FET Q
However, the present invention is not limited to this. For example, a bipolar transistor, a diode, a diffused resistor, a resistor made of polysilicon, a combination of these,
Various changes such as a combination with ETQ can be made.

In the chip formation region 2, the MIS / FE
The TQ is formed in an active region surrounded by the isolation part 5. The separation unit 5 is made of silicon oxide or the like formed on the main surface of the semiconductor substrate 1s, and is, for example, LOCOS (Local Ox
idization of Silicon). However, the structure of the isolation part 5 is not limited to this, and may be, for example, a groove type structure (trench isolation). That is, the isolation portion 5 may be formed by embedding an insulating film made of silicon oxide or the like in an isolation trench dug in the thickness direction of the semiconductor substrate 1s. This MIS
Elements such as the FETQ are covered with an insulating film 6a deposited on the main surface of the semiconductor substrate 1s (the chip forming region 2 and the dicing region 3). On the insulating film 6a, the first
The layer wiring 7a is formed. This first layer wiring 7a is
It is covered with the insulating film 6b on the insulating film 6a. The second layer wiring 7b is formed on the insulating film 6b. The second layer wiring 7b is covered with an insulating film 6c on the insulating film 6b, and the third layer wiring 7c formed on the insulating film 6c is covered with a surface protection film 8 on the insulating film 6c. ing. Part of the surface protection film 8 includes a third-layer wiring 7c.
An opening 9 is formed such that a part of is exposed,
Thereby, the bonding pad 4 is formed.
Although not particularly limited, the insulating films 6a to 6c are made of, for example, silicon oxide. The first-layer wiring 7a, the second-layer wiring 7b, and the third-layer wiring 7c are made of a metal such as aluminum or an aluminum-silicon-copper alloy. The surface protective film 8 is formed of, for example, a laminated film in which a silicon nitride film is laminated on a silicon oxide film, or a laminated film in which an organic insulating film such as a polyimide resin is further laminated thereon. The insulating films 6b and 6c, the second layer wiring 7
b, the third-layer wiring 7c and the surface protection film 8 have been partially (selectively) removed in the dicing region 3 so that a groove is formed.

On the other hand, in the dicing region 3, TEG (Te
elements and patterns are arranged. The TEG elements and patterns are, for example, inspection elements and patterns used for obtaining manufacturing process data and element data of a semiconductor device, and are not incorporated in the above-mentioned predetermined integrated circuit. here,
The case where a TEG pad pattern (TEG pattern) 10 is formed on the insulating film 6a in the dicing region 3 is illustrated. This pad pattern 10
For example, in the same step as the patterning of the first layer wiring 7a, the first layer wiring 7a is patterned in a plane quadrilateral or the like, and is made of a metal such as aluminum or an aluminum-silicon-copper alloy. A TEG element formed on the semiconductor substrate 1s in the dicing region 3 (for example, the MIS formed in the same step as the MIS • FET constituting the above-mentioned predetermined integrated circuit)
An FET and a resistor (diffusion resistor or polysilicon resistor) are electrically connected to the pad pattern 10. That is, at the time of inspection after the wafer process step, predetermined electrical characteristics are tested in a state in which an inspection probe or the like is in direct mechanical (physical) contact with the pad pattern 10. I have. This makes it possible to indirectly measure the characteristics of the elements constituting a predetermined integrated circuit. As described above, the pad pattern 10 cannot be made very small because of the direct contact of the probe or the like. The area of the pad pattern 10 is substantially equal to (slightly smaller than) the area of the bonding pad 4. On the other hand, the width of the dicing region 3 tends to be reduced in order to increase the number of chips obtained without making the semiconductor wafer too large in diameter. For this reason, the area of the pad pattern 10 occupying in the dicing region 3 tends to increase as illustrated in FIG. That is, the pad pattern 10
The distance between the semiconductor device and the chip forming region 3 is becoming smaller. Therefore, in the dicing process described later, if dicing is performed with a wide blade that removes the pad pattern 10, chipping (the main surface and the back surface of the semiconductor wafer) reaches the chip formation region 2, causing a defect. Therefore, in that case, the dicing region 3 cannot be made too narrow (regulated by the pattern in the dicing region 3). The cross-sectional and planar structures in the dicing region 3 are not limited to those described above, and can be variously changed. For example, in addition to the elements and patterns for TEG, a pattern for positioning (conductor or insulating) may be used. In some cases, a structure in which another pattern is arranged, such as a body, or another insulating film or a conductor film is deposited.

Next, the process shifts to the inspection process shown in FIG. 1 (Step 101). Here, as shown in FIG. 5, for example, the electrical characteristics of the TEG element are measured in a state where the inspection probe 11 is in direct mechanical contact with the TEG pad pattern 10 arranged in the dicing region 3. By measuring, the electrical characteristics of the predetermined integrated circuit are inspected indirectly.

Next, as shown in FIG. 6, a photoresist pattern 12 is formed on the main surface (device formation surface) of the semiconductor wafer 1 by photolithography. The photoresist pattern 12 covers the chip formation region 2 and at least the pad pattern 1 in the dicing region 3.
The pattern is formed so that the surface of the “0” is exposed.
Subsequently, using the photoresist pattern 12 as an etching mask, the pad pattern 10 exposed therefrom is removed by a dry etching method or a wet etching method as shown in FIG. Here, the over-etching process is performed so that the pad pattern 10 is surely removed, so that a part of the dicing region 6a exposed from the photoresist pattern 12 is removed by etching. As described above, in the first embodiment, after the inspection process and prior to the dicing process, the TEG pad pattern 1 formed in the dicing region 3 is formed.
0 is removed. After that, the photoresist pattern 12 is removed (Step 102). In addition, since the etching process can be performed at a time, the throughput is not significantly reduced.

Next, the process proceeds to a dicing step (step 103). In the dicing step, first, the semiconductor wafer 1 is mounted on the wafer ring 13 as shown in FIG. 8A shows a plan view of the wafer ring 13 to which the semiconductor wafer 1 is attached, and FIG. 8B shows a cross-sectional view taken along line AA of FIG. The wafer ring 13 includes a wafer sheet 13a and a frame 13 attached along an outer periphery thereof.
b. The wafer sheet 13a is formed, for example, by applying an adhesive on an organic film, and has a function of bonding and fixing the semiconductor wafer 1. Here, for example, an ultraviolet (UV) curable resin is used as an adhesive for the wafer sheet 13a in order to maintain the adhesive force during the dicing step and reduce the adhesive force during the die bonding step after the dicing step.

Subsequently, the wafer ring 13 is carried into a dicing apparatus. The dicing apparatus is also called a dicer or a dicing saw, and is an apparatus that cuts or cuts a groove along the dicing area 3 of the semiconductor wafer 1 by using an ultra-thin blade attached to a tip of a spindle that rotates at a high speed. The cutting method includes, for example, a half-cut method in which a kerf having a thickness of about half of the semiconductor wafer 1 is provided, a semi-full-cut method in which a kerf is left while leaving the semiconductor wafer 1 in about 10 to 50 μm, or a full-cut method in which the semiconductor wafer 1 is completely cut. There are methods. Although either method may be used, FIG. 9 illustrates a full cut method. That is, the blade 14 which rotates at a high speed of the dicing apparatus is applied to the dicing region 3 of the semiconductor wafer 1 to completely cut the portion. At this time, for the purpose of cooling the heat generated during cutting, ultrapure water or the like is injected under high pressure and supplied to the cutting section. Here, for example, a single cutting method of cutting the dicing region 3 line by line is used. In the first embodiment, since the dicing process can be performed without performing the step cut dicing, the throughput of the dicing process can be improved. This makes it possible to improve the productivity of the semiconductor device. In the above example, the case where the single cut method is employed has been described. However, the dual cut method may be employed in order to improve the throughput. The dual cut method is a cutting method in which a blade is attached to each of two main spindles to perform a cutting process in parallel.
Since it is expected that the dicing region 3 becomes longer and the dicing throughput decreases as the diameter of the semiconductor wafer 1 increases, it is particularly preferable to adopt the dual cut method in such a case.

FIG. 10 is a schematic plan view of the dicing region 3 of the semiconductor wafer 1 after the dicing process according to the first embodiment, and FIG. 11 is an enlarged plan view of FIG. . Reference numeral 15 denotes an actual cut groove area (calf),
Reference numeral 16 indicates a chipping area. The chipping referred to here is an irregular break (chip) generated on the outer periphery (edge) of the cutting line. For comparison, FIGS. 12 and 13 are schematic plan views of the dicing region 51 of the semiconductor wafer after the normal dicing processing without the etching removal step 102. FIG. FIG. 13 shows FIG.
2 shows an enlarged plan view of FIG. Reference numeral 52 denotes an actual cutting area, reference numeral 53 denotes a chipping area, and reference numeral 54 denotes a TEG pad pattern.

As described above, in the first embodiment, at the time of the dicing step, the TEG pad pattern 10 and the like in the dicing region 3 have already been removed, and there is no need to use a wide blade. ,
It is possible to reduce or prevent defects in the chip formation region 2 due to chipping. Therefore, it is possible to improve the yield of the semiconductor device during the dicing step.

In the dicing step, TEG
Pad pattern 10 and the like have already been removed,
Cutting residue 54 of pad pattern 54 as shown in FIG.
a does not occur. Therefore, it is also possible to prevent short-circuit failure caused by the remaining cutting 54a. For this reason,
It is possible to improve the yield of semiconductor devices.

Since the problems of chipping and remaining cutting can be avoided, it is possible to cope with the narrowing of the dicing region 3. Therefore, the number of semiconductor chips that can be arranged on one semiconductor wafer 1 can be increased. Therefore, it is possible to promote the improvement of the yield of the semiconductor device.

Furthermore, since the TEG pad pattern 10 and the like are removed at the time of the dicing step, blade clogging and deterioration that occur when the pad pattern 10 and the like are cut can be prevented. Therefore, the life of the blade 14 can be extended. Therefore, it is possible to promote cost reduction of the semiconductor device.

Subsequent steps are the same as the ordinary assembling steps of a semiconductor device. An example will be described below. First, a semiconductor chip 2 (chip formation region 2) cut out from a semiconductor wafer 1 is picked up. At this time, by irradiating the wafer sheet 13a with ultraviolet rays, the adhesive of the wafer sheet 13a is cured and the adhesive force is reduced. Thus, the semiconductor chip 2 can be easily picked up without causing any trouble.
Subsequently, as shown in FIG. 14, the picked-up semiconductor chip 2 is mounted on the main surface of the interposer substrate 17 with its back surface facing the main surface of the interposer substrate 17 (step 104). Subsequently, as shown in FIG. 15, the bonding pads 4 of the semiconductor chip 2a and the lands (terminals) on the main surface of the interposer substrate 17 are electrically connected by bonding wires 18 made of, for example, gold. The connection method of the bonding wire 18 is shown in FIG.
The forward bonding shown in (b) or the reverse bonding shown in FIG. The positive bonding is a method in which the first bonding of the bonding wires 18 is performed on the bonding pads 4 of the semiconductor chip 2a, and then the second bonding is performed on the lands of the interposer substrate 17. On the other hand, the reverse bonding is the reverse of the normal bonding, in which the first bonding of the bonding wires 18 is made to the land of the interposer substrate 17 and then the second bonding is performed to the bonding pads 4 of the semiconductor chip 2a. In the case of the reverse bonding, the wire loop of the bonding wire 18 can be made lower than that of the normal bonding, so that the package of the semiconductor device can be made thinner.
Further, in the first embodiment, since there is no remaining portion of the pad, there is no problem that the bonding wire 18 and the remaining portion of the pad are short-circuited even if either the forward or reverse bonding method is adopted. Thereafter, as shown in FIG. 16, the semiconductor chip 2a is sealed with the sealing resin 19 (Step 105). Finally, as shown in FIG. 17, a bump electrode 20 made of, for example, a lead-tin alloy is formed on a land (terminal) on the back surface of the interposer substrate 17. Thus, a semiconductor device having a BGA (Ball Grid Array) type package structure is manufactured. However, the package structure is not limited to this and can be variously changed. For example, a CSP (Chip Size P
The present invention can be applied to a semiconductor device having an (ackage) structure. In this structure, the semiconductor chip 2a and the interposer substrate 17 are electrically connected through a bump electrode 21 interposed therebetween.

(Embodiment 2) In Embodiment 2, after the steps up to the step of FIG. 6 are performed in the same manner as in Embodiment 1, the etching removal step 102 of FIG. 1 is performed as shown in FIG. Next, the upper portion of the semiconductor substrate 1s in the dicing region 3 (a depth sufficient to remove the element for TEG) is removed by etching. The thickness of the semiconductor substrate 1s left in this portion may be, for example, about 200 μm.
Thus, the dicing region 3 of the semiconductor wafer 1 is thinned. Subsequently, as shown in FIG. 20, the semiconductor chips 2 are cut out from the semiconductor wafer 1 by performing dicing as in the first embodiment. Subsequent steps are the same as in the first embodiment, and will not be described.

According to the second embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained.

That is, the thickness of the semiconductor substrate 1s in the dicing region 3 can be reduced by removing the upper portion of the semiconductor substrate 1s in the dicing region 3 during the etching removing process before the dicing process. In addition, the dicing process can be further facilitated. In particular, it is possible to further improve the throughput, narrow the width of the chipping region, and further improve the life of the blade 14.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, in the first and second embodiments,
The case where the present invention is applied to the dicing technique of a semiconductor wafer having a diameter of about 6 to 8 inches (150 to 200 mm) has been described. However, the present invention is not limited to this, and various applications are possible. Inches (300
(mm to 400 mm). When the diameter of the semiconductor wafer is increased, the semiconductor wafer may be forced to remain thick without back grinding after the wafer process in order to maintain the mechanical strength of the semiconductor wafer. In that case, the thickness of the semiconductor substrate is
For example, about 720 μm is required. In that case, the thickness of the semiconductor wafer becomes larger than the width of the cutting region, and if a normal dicing process is performed, it becomes difficult to supply ultrapure water to the cut portion of the semiconductor wafer satisfactorily. Becomes difficult. On the other hand, when the present invention is applied, the cut thickness of the semiconductor wafer in the dicing region can be reduced, so that the easiness of the dicing process can be improved.

In the above description, the invention made mainly by the present inventor is applied to a normal semiconductor wafer cut out from a semiconductor ingot formed by a predetermined semiconductor growth method from a semiconductor single crystal, which is an application field in which the invention is based. However, the present invention is not limited to this. For example, an epitaxial wafer or SOI (Silico
n On Insulator) It can also be applied to wafer dicing. An epitaxial wafer is a wafer having a structure in which a single crystal of a semiconductor is deposited on the surface of a normal semiconductor wafer by an epitaxial method. The SOI wafer is a wafer having a structure in which a semiconductor layer for element formation is provided on a normal semiconductor wafer via a buried insulating layer. In the case of an SOI wafer, prior to the dicing process, the semiconductor layer for element formation in the dicing region may be removed by etching until the surface of the buried insulating layer is exposed. That is, the semiconductor layer portion for element formation in the dicing region may be removed by etching using the buried insulating layer as an etching stopper.

[0044]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows. (1) According to the present invention, it is possible to improve the dicing throughput by removing part or all of the film in the cutting region in advance. (2) According to the present invention, dicing can be performed without causing a chipping or a defect due to a remaining film by removing a part or the whole of the film in the cutting region in advance. Therefore, it is possible to improve the dicing throughput without lowering the yield. (3) According to the present invention, the life of the dicing blade can be improved by removing part or all of the film in the cutting region in advance. (4) According to the present invention, by partially or entirely removing the film in the cut region in advance by an etching process capable of fine processing, dicing can be performed without causing defects due to chipping and remaining film, It is possible to cope with narrowing of the cutting area of the semiconductor wafer. (5) According to the present invention, it is possible to improve the yield of semiconductor devices.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a manufacturing process flow of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor wafer during a manufacturing process of the semiconductor device of FIG. 1;

FIG. 3 is an enlarged plan view of a main part of the semiconductor wafer of FIG. 2;

FIG. 4 is a sectional view taken along line AA of FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device, following FIG. 4;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device, following FIG. 5;

7 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device, following FIG. 6;

8A is a plan view of a semiconductor wafer during a manufacturing step of a semiconductor device following FIG. 7, and FIG.
It is sectional drawing of a line.

9 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device, following FIG. 8;

10 is a plan view schematically showing a cut region of the semiconductor wafer after the manufacturing process of the semiconductor device of FIG. 9;

FIG. 11 is an enlarged plan view of a main part of FIG. 10;

FIG. 12 is a partial plan view schematically showing a cutting region of a semiconductor wafer after a dicing step studied by the present inventors.

13 is a partially enlarged plan view of FIG.

FIG. 14 is a cross-sectional view of one example of the semiconductor device during a manufacturing step following that of FIG. 10;

FIG. 15 is a cross-sectional view of one example of the semiconductor device during a manufacturing step following that of FIG. 14;

16 is a cross-sectional view of one example of the semiconductor device during a manufacturing step following that of FIG. 15;

FIG. 17 is a cross-sectional view of one example of the semiconductor device during a manufacturing step following that of FIG. 16;

FIG. 18 is a sectional view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 19 is a fragmentary cross-sectional view of a semiconductor wafer during a manufacturing step of a semiconductor device according to still another embodiment of the present invention;

20 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device, following FIG. 19;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Chip formation area 2a Semiconductor chip 3 Dicing area (cutting area) 4 Bonding pad 5 Separation part 6a-6c Insulating film 7a First layer wiring 7b Second layer wiring 7c Third layer wiring 8 Surface protection film 9 Opening DESCRIPTION OF SYMBOLS 10 Pad pattern 11 Inspection probe 12 Photoresist pattern 13 Wafer ring 13a Wafer sheet 13b Frame 14 Blade 15 Cutting groove area 16 Chipping area 17 Interposer substrate 18 Bonding wire 19 Sealing resin 20 Bump electrode 21 Bump electrode Q MIS / FET

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsue Ueno 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo F-term in the Semiconductor Group, Hitachi, Ltd. 4M106 AA01 AA08 AD02

Claims (5)

[Claims] 1. A semiconductor wafer is cut along a cutting region after removing all or a part of a film deposited on the semiconductor wafer in a cutting region of the semiconductor wafer by an etching process. A method for manufacturing a semiconductor device, comprising a step of cutting out a semiconductor chip. 2. A semiconductor chip is cut out from the semiconductor wafer by cutting the semiconductor wafer along the cutting region after removing a TEG pattern formed on the semiconductor wafer in the cutting region of the semiconductor wafer by etching. A method for manufacturing a semiconductor device, comprising the steps of: 3. A step of forming a predetermined pattern on a semiconductor wafer, and a step of performing a predetermined inspection using a TEG pattern arranged in a cutting region of the semiconductor wafer after the step of forming the predetermined pattern. (C) removing the TEG pattern formed on the semiconductor wafer in the cutting region after the inspection step by etching, and (d) removing the semiconductor along the cutting region after the etching processing. Cutting a plurality of semiconductor chips from the semiconductor wafer by cutting the wafer. 4. The semiconductor wafer is cut along a cutting region after a film deposited on the semiconductor wafer and a part of the semiconductor wafer are removed by an etching process in a cutting region of the semiconductor wafer. A method for manufacturing a semiconductor device, comprising a step of cutting a semiconductor chip from a semiconductor chip. 5. A step of: (a) forming a predetermined pattern on a semiconductor wafer; and (b) after the step of forming the predetermined pattern, a predetermined inspection using a TEG pattern arranged in a cutting region of the semiconductor wafer. (C) removing the TEG pattern formed on the semiconductor wafer in the cutting region and part of the semiconductor wafer by an etching process after the inspection process, and (d) removing the etching process after the etching process. Cutting a plurality of semiconductor chips from the semiconductor wafer by cutting the semiconductor wafer along the cutting region.