JP2001223569A - Signal transition detection circuit and pulse width extending circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the required stable operation of a function including the circuit of a post stage while suppressing the increase of a circuit area even when the logic state of a signal being the object of the detection of a logic state change changes and subsequently changes again in a short time in a signal transition detection circuit. SOLUTION: A signal transition detection circuit for detecting the change of the logic state of a signal and outputting a signal showing the presence of signal shift is constituted of a signal transition detection circuit 1 and a pulse reinforcing circuit 5 which are conventional. The pulse reinforcing circuit 5 extends the pulse width of the signal which is equivalent to a period during which the signal showing the presence of signal transition is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transition detecting circuit which detects a change in a logical state of a signal and outputs a signal having a signal transition, or a signal transition detecting circuit which is next to the signal transition detecting circuit. The signal transition presence signal is input to the most input end of a plurality of buffers connected in series with respect to individual inputs and outputs, and the signals extracted from a plurality of positions in the middle of the plurality of buffers and the plurality of buffers are used. By performing a logical OR operation between the signals at the most output terminals of the buffer, a signal having an extended pulse width of the signal having a signal transition is generated and output to the outside, and according to the logic state of the pulse width adjustment input signal input from the outside. By using a logic gate controlled in the middle of the plurality of buffers, the pulse width adjustment circuit adjusts the degree of extension according to the logic state of the pulse width adjustment input signal. In particular, even in the case where the logic state of the signal whose logic state change is to be detected in the signal transition detection circuit changes again in a short period of time, it is required to suppress the increase in the circuit area and to include the subsequent circuits. The present invention relates to a signal transition detection circuit and a pulse width extension circuit that can ensure stable operation of a function.

[0002]

2. Description of the Related Art FIG. 1 is a circuit diagram of a signal transition detection circuit which detects a change in a logic state of a signal and outputs a signal indicating a signal transition when the change occurs.

[0003] In this figure, the target of the logical state change detection is:
These address signals are transmitted through a total of n address lines AD1 to ADn and constitute a bus used when accessing a memory or the like in a computer system. In the signal transition detection circuit, the logic state change detection is not limited to the address signal. However, when the logic state change detection is performed, the signal transition detection circuit generally uses an ATD (Address tracing).
nsition detector) circuit.

In FIG. 1, address lines AD1 to AD
Each of the n signals is input to the most input end of the plurality of buffers connected in series for each input and output, and is also input to one input of an exclusive OR gate. The other input of the exclusive OR operation gate is supplied with the output of the entire most output terminal of the plurality of buffers. Here, the delay time of the signal from the most input terminal to the most output terminal in the entirety of the plurality of buffers is defined as td.

The output of the exclusive OR operation gate provided for each signal of each address line AD1 to ADn is
All are input to the same multiple-input OR operation gate.

FIG. 2 is a time chart showing the operation of the signal transition detection circuit.

FIG. 1 shows a time chart of signals of the respective parts of the signal transition detection circuit shown in FIG.

At time t1, the logic state of the address line AD1, which is the signal indicated by the code, which has been input to the most input end of the entirety of the aforementioned plurality of buffers, becomes the H state. Then, the logic state of the signal indicated by the code, which is output from the most output end of the above-described plurality of buffers as a whole, becomes the H state at time t2, which is a delay time td after time t1.

As a result, the signal indicated by the sign, which is the output of the exclusive OR gate for inputting these signals and the signal, rises at time t1 and falls at time t2.

At time t3, the logic state of the address line AD1 indicated by the reference sign inputted to the most input terminal of the entirety of the plurality of buffers becomes L state. Then, the signal output from the most output end of the above-mentioned plurality of buffers as indicated by the code is at time t3
At time t4 after the delay time td, the logic state becomes L state.

As a result, the signal indicated by the sign, which is the output of the exclusive-OR gate for inputting these signals, rises at time t3 and falls at time t4.

FIG. 3 shows a signal transition detection circuit similar to FIG.
FIG. 3 is a circuit diagram of a pulse width extension circuit used in the next stage of the signal transition detection circuit.

The pulse width extending circuit has three buffers connected in series for each input and output. These three buffers are connected in series for each input and output. Then, a signal having a signal transition, which is output by the signal transition detection circuit at the preceding stage, is input to the most input terminals of the three buffers as a whole.

In the middle of the plurality of buffers, that is,
The pulse width of the signal having the signal transition is extended by the logical sum operation of the plurality of signals extracted from the plurality of points, which are the connection points between the plurality of buffers, and the signals of the most output terminals of the three buffers. Generates a signal and outputs it to the outside.

Further, a logic gate controlled according to the logic state of the pulse width adjustment input signals E1 and E2 input from the outside, that is, a two-input AND operation gate is used in the middle of the plurality of buffers. Thereby, the extension degree is adjusted according to the logic state of the pulse width adjustment input signal.

That is, in FIG. 3, when the pulse width adjustment input signals E1 and E2 are both in the H state, the degree of extension becomes the longest. Next, when the pulse width adjustment input signal E1 is in the H state and the pulse width adjustment input signal E2 is in the L state,
The degree of extension is then longer. Further, when the pulse width adjustment input signals E1 and E2 are both in the L state, the degree of extension becomes the shortest.

FIG. 4 is a time chart showing the operation of the pulse width extending circuit.

In this figure, a time chart of signals of respective parts of the signal transition detection circuit of FIG. The pulse width adjustment input signals E1 and E2 are
In each case, it is assumed that the H state is input.

The signals in the signal transition detection circuit of the pulse width extension circuit are described with reference to FIGS.
This is the same operation as the signal transition detection circuit of FIG. When the input other than the signal does not change in the multi-input OR operation gate signal, the signal becomes the same as the signal.

In FIG. 4, at time t11, the logic state of the signal input to the most input terminal of the three buffers described above in the pulse width extending circuit becomes H state. Then, assuming that the delay time of the input buffer of the three buffers is td1, the logic state of the signal becomes H state after the delay time td1 from time t11. Next, assuming that the delay time of the second of the three buffers from the input side is td2, the logic state of the signal becomes H state after the delay time (td1 + td2) from time t11. Further, assuming that the delay time of the most output side of the three buffers is td3, the logic state of the signal becomes the H state after a delay time (td1 + td2 + td3) from time t11.

In FIG. 4, at time t12, the logic state of the signal becomes L state. Then, after a delay time td1 from the time t12, the logic state of the signal becomes the L state. Next, delay time (td1 + td2) from time t12
Only later, the logic state of the signal goes to the L state. Further, after a delay time (td1 + td2 + td3) from the time t12, the logic state of the signal becomes the L state.

In the pulse width extending circuit, a signal is generated and output by the OR operation of these signals by a 4-input OR operation gate. This signal is a signal obtained by extending the pulse width of the signal with signal transition output from the signal transition detection circuit, and is a signal from time t11 to t1 in FIG.
Up to 3, it is in the H state.

It should be noted that, for the signal 〜, at time t21
At times to t23, the H state and the L state propagate similarly to the times t11 to t13 described above. In this way, a signal in which the pulse width of the signal with signal transition is extended is obtained.

[0024]

However, in the signal transition detection circuit, if the logic state of the signal whose logic state change is to be detected changes in a short time after the change, the circuits subsequent to the signal transition detection circuit operate normally. May not work. For example, in the circuits shown in FIGS. 1 and 3, the pulse width extension circuit does not operate normally.

In FIG. 4, the signal, that is, the logical state of the signal whose logic state change is to be detected, changes to the H state at time t31, and then returns to the L state again after a relatively short time.

Then, the signal output from the signal transition detection circuit, or a signal substantially equivalent to the signal, is
As shown in the figure, the voltage level in the H state is low, and the pulse signal rises and falls more gradually than vertically. The signal depending on the signal is a pulse signal whose voltage level in the H state is further lower and whose rising and falling are gentler than vertical. In addition, for a signal that depends on a signal and a signal that depends on the signal, there is no pulse signal that can be generated, and the pulse signal has disappeared.

As described above, if the voltage level in the H state is low and the pulse signal rises or falls more slowly than the vertical, or the pulse signal disappears,
The output signal of the multi-input OR operation gate becomes incomplete, and the circuit operation after the pulse width extension circuit becomes unstable.

The present invention has been made in order to solve the above-mentioned conventional problems, and is intended for a case in which the logic state of a signal whose logic state change is to be detected in a signal transition detection circuit changes again in a short time. Another object of the present invention is to provide a signal transition detection circuit and a pulse width extension circuit that can ensure stable operation of required functions including a circuit at a later stage while suppressing an increase in circuit area.

[0029]

First, a signal transition detection circuit according to the first invention of the present application detects a change in a logical state of a signal and outputs a signal having a signal transition when the change occurs. This object has been achieved by providing a transition detection circuit including a pulse enhancement circuit that extends the pulse width of the signal corresponding to the time during which the signal with transition signal is output.

Next, the pulse width extension circuit of the second invention of the present application is a signal transition detection circuit that detects a change in the logical state of a signal and outputs a signal indicating a signal transition when the change occurs. The signal transition presence signal is input to the most input end of a plurality of buffers connected in series with respect to individual inputs and outputs, and the signals extracted from a plurality of positions in the middle of the plurality of buffers and the plurality of buffers are used. By performing a logical OR operation between the signals at the most output terminals of the buffer, a signal having an extended pulse width of the signal having a signal transition is generated and output to the outside, and according to the logic state of the pulse width adjustment input signal input from the outside. In a pulse width extension circuit that adjusts the degree of extension according to the logic state of the pulse width adjustment input signal by using a logic gate controlled in the middle of the plurality of buffers, , Including the insertion of the logic gate, the output loads at the respective buffers constituting the plurality buffer is set to be uniform with each other, it is obtained by solving the above problems.

Hereinafter, the operation of the present invention will be briefly described.

First, in the first invention of the present application, when a change in the logic state of a signal occurs, a signal transition detection circuit that detects the change and outputs a signal indicating that there is a signal transition, as shown in FIG. Conventional signal transition detection circuit 1, for example, FIG.
Next to the signal transition detection circuit shown in FIG.
Is provided. The pulse intensifying circuit 5 extends the pulse width of the signal corresponding to the time during which the signal with transition is output.

Therefore, according to the present invention, even in a case where the logic state of a signal whose logic state change is to be detected in the signal transition detection circuit changes again in a short time, the increase in circuit area can be suppressed. In addition, a stable operation of a required function including a circuit at a subsequent stage can be ensured.

Next, as shown in FIG. 6, a second invention of the present application is a signal transition detecting circuit which detects a change in a logical state of a signal and outputs a signal with a signal transition when the change occurs. 1, for example, a pulse width extension circuit 3A used in the next stage of the signal transition detection circuit 1 shown in FIG. The pulse width extending circuit 3A can be said to be an improved version of the conventional pulse width extending circuit, for example, the pulse width extending circuit 3 of FIG.

In the present invention, including the insertion of the logic gate, the output loads of the individual buffers constituting the plurality of buffers are made to be mutually uniform. Therefore, the signal propagates stably in the pulse width extension circuit.

Therefore, according to the present invention, even when the logic state of a signal whose logic state change is to be detected in the signal transition detection circuit changes again in a short time, the increase in circuit area can be suppressed. In addition, a stable operation of a required function including a circuit at a subsequent stage can be ensured.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 8 shows a first embodiment to which the first invention of the present application is applied.
It is a circuit diagram of a signal transition detection circuit of an embodiment.

The signal transition detecting circuit according to the present embodiment is provided with a pulse intensifying circuit 5 at the next stage of the conventional signal transition detecting circuit 1. The pulse intensifying circuit 5 includes a P-channel MOS transistor TP and an N-channel MOS transistor TN, and an inverter I.

The P-channel MOS transistor TP has its gate connected to the ground GND and is always on, and functions as a pull-up resistor. The P-channel MOS transistor TP has a lower driving force and a higher on-resistance than the N-channel MOS transistor TN. For example, the channel region has a length of 0.8 μm and a width of 0.8 μm.

The signal from the preceding stage is input to the gate of the N-channel MOS transistor TN. N channel M
The OS transistor TN amplifies the input signal and outputs it to the next stage. Therefore, the N-channel MOS transistor TN has a higher driving force and a lower on-resistance than the P-channel MOS transistor TP. For example, the channel region has a length of 0.25 μm and a width of 2 μm.
m.

The inverter I inverts the signal inverted by the above-described P-channel MOS transistor TP and N-channel MOS transistor TN operating as an inverter again, and restores the signal polarity.

FIG. 9 is a time chart showing the operation of the pulse intensifying circuit 5.

The signal, that is, the signal output from the signal transition detection circuit 1 is changed as shown in FIG. As shown in FIG. 9, the voltage level in the H state is lower than the power supply voltage VDD, and the pulse signal rises and falls more gradually than in the vertical direction.

At time t1, the signal rises. Then, the signal pulled up by the P-channel MOS transistor TP starts to fall when the N-channel MOS transistor TN is turned on.

At time t2, the signal falls. As a result, the N-channel MOS transistor TN is turned off. However, P-channel MOS transistor TP
Has a large on-resistance compared to the on-resistance of the N-channel MOS transistor TN, so that the signal rises slowly and reaches the power supply voltage VDD near time t3.

As described above, as the rise of the signal becomes gentler, the pulse width is extended and the pulse is enhanced. Also, the signal output from the inverter I to which the expanded pulse signal is input, that is, the signal, has a sharp rise or fall.

Therefore, in the present embodiment, even when the logic state of the signal whose logic state change is to be detected in the signal transition detection circuit changes again in a short time, the increase in the circuit area can be suppressed. The stable operation of the required functions including the circuits at the subsequent stage can be ensured.

FIG. 10 is a circuit diagram of a modification of the first embodiment.

In this modification, the same pulse width extending circuit 3 as that of FIG. 3 is provided on the output side of the first embodiment. The first embodiment may be used in this way.

FIG. 11 is a circuit diagram of a pulse width extending circuit according to a second embodiment to which the second invention of the present application is applied.

The pulse width extending circuit 3B includes three buffers connected in series for each input and output. These three buffers are connected in series for each input and output. Then, a signal having a signal transition, which is output by the signal transition detection circuit at the preceding stage, or a signal which is output from the pulse enhancement circuit 5 which has taken in the signal, is input to the most input terminals of the three buffers as a whole.

In the middle of the plurality of buffers, that is,
The pulse width of the signal having the signal transition is extended by the logical sum operation of the plurality of signals extracted from the plurality of points, which are the connection points between the plurality of buffers, and the signals of the most output terminals of the three buffers. Generates a signal and outputs it to the outside.

Further, an N-channel MOS transistor is provided for extracting a signal from a plurality of locations as described above. The extension is adjusted in accordance with the logic state of the pulse width adjustment input signal input to the gate of the N-channel MOS transistor.

That is, in FIG. 11, when the pulse width adjustment input signals E1 and E2 are both in the H state, the degree of extension becomes the longest. Next, when the pulse width adjustment input signal E1 is in the H state and the pulse width adjustment input signal E2 is in the L state,
The degree of extension is then longer. Further, when the pulse width adjustment input signals E1 and E2 are both in the L state, the degree of extension becomes the shortest.

FIG. 12 is a time chart showing the operation of the pulse width extending circuit in the present embodiment.

In this figure, a time chart of the signals of the respective parts of the signal transition detection circuit of FIG. In FIG. 12, when both the pulse width adjustment input signals E1 and E2 are in the L state, the signal has a waveform of signal-1. Pulse width adjustment input signal E
When 1 is in the H state and the pulse width adjustment input signal E2 is in the L state, the waveform becomes signal-2. When both the pulse width adjustment input signals E1 and E2 are in the H state, the signal -3
Waveform.

In FIG. 12, at time t1, an H-state signal having a predetermined pulse width tw is input to the most input terminal of the above-described three buffers in the pulse width extending circuit. Then, assuming that the delay time of the most input side of the three buffers is td1, the signal has a predetermined pulse width tw after the delay time td1 from time t1.
It becomes a state signal. Next, assuming that the delay time of the second of the three buffers from the input side is td2, the time t
After a delay time (td1 + td2) from 1, the signal becomes an H-state signal having a predetermined pulse width tw. Further, assuming that the delay time of the output buffer of the three buffers is td3, the delay time (td1 + td2 + td) from time t1.
Only after 3), the signal becomes an H-state signal having a predetermined pulse width tw.

Then, any one of signals -1 to -3 is output by the logical OR operation of signals 〜 and in response to pulse width adjustment input signals E1 and E2.

When the pulse width adjustment input signals E1 and E2 are both in the L state, the waveform becomes a signal-1 having a pulse width from time t1 to time t2. Pulse width adjustment input signal E1
Is in the H state and the pulse width adjustment input signal E2 is in the L state, a signal-2 having a pulse width from time t1 to t3, the pulse width of which has been extended from the waveform of the signal-1.
Waveform. When the pulse width adjustment input signals E1 and E2 are both in the H state, the waveform of the signal-3, which is the pulse width from the time t1 to the time t4, is obtained by extending the pulse width from the waveform of the signal-2.

As described above, the pulse width extending circuit of the present embodiment has the same function as the conventional example of FIG. Further, in the conventional example, a logical product operation gate is provided so as to be inserted into a serially connected portion of three buffers. On the other hand, in the present embodiment, instead of inserting in this way,
In the process of extracting and inputting to the OR gate,
An N-channel MOS transistor is provided. Therefore,
Regardless of the logic state of the pulse width adjustment input signals E1 and E2, the signals input to the most input terminals of the three buffers are transmitted to the most output terminals of these buffers. Therefore, the signal propagation is stabilized, so that a stable operation can be performed even with a pulse signal having a short pulse width.

Thus, in the present embodiment, even when the logic state of the signal whose logic state change is to be detected in the signal transition detection circuit changes and then changes again in a short time, an increase in the circuit area is suppressed. However, it is possible to ensure stable operation of required functions including the circuit at the subsequent stage.

FIG. 13 is a circuit diagram of a pulse width extending circuit according to a third embodiment to which the second invention of the present application is applied.

This embodiment is a modification of the above-described second embodiment. In the present embodiment, in the process of extracting a signal from a serially connected portion of three buffers and inputting the signal to an OR gate, two N-channel MOS transistors are provided in each extracted portion. That is,
The load at the lead-out portion of these buffers becomes the gate of the N-channel MOS transistor on the left side in the figure.

Therefore, the load of the third embodiment is lower than that of the second embodiment in which the load of the input of the multi-input OR gate via the source and the drain of the N-channel MOS transistor is a load. It has been reduced.
In the second embodiment, the pulse width adjustment input signal E
Depending on the logic states of 1 and E2, a load corresponding to the input of the multi-input OR operation gate may or may not be generated. However, in the third embodiment, this is not the case, and the load is constant.

Accordingly, in the present embodiment, the signal propagation is more stable than in the second embodiment, so that a stable operation can be performed even with a pulse signal having a short pulse width.

As a result, in this embodiment, even when the logic state of the signal whose logic state change is to be detected in the signal transition detection circuit changes and then changes again in a short time, an increase in circuit area is suppressed. However, it is possible to ensure stable operation of required functions including the circuit at the subsequent stage.

[0068]

According to the present invention, it is possible to suppress an increase in circuit area even when the logic state of a signal whose logic state change is to be detected in the signal transition detection circuit changes again in a short time. In addition, a stable operation of a required function including a circuit at a subsequent stage can be ensured.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a conventional signal transition detection circuit.

FIG. 2 is a time chart showing an operation of the signal transition detection circuit.

FIG. 3 is a circuit diagram of a conventional signal transition detection circuit and a pulse width extension circuit used in the next stage of the signal transition detection circuit.

FIG. 4 is a time chart showing the operation of the pulse width extension circuit.

FIG. 5 is a block diagram showing a configuration of a signal transition detection circuit according to the first invention of the present application;

FIG. 6 is a block diagram showing a first example of an arrangement of a pulse width extending circuit according to the second invention of the present application;

FIG. 7 is a block diagram showing a second example of the arrangement of the pulse width extension circuit according to the second invention of the present application;

FIG. 8 is a circuit diagram of a signal transition detection circuit according to the first embodiment to which the first invention of the present application is applied;

FIG. 9 is a time chart showing the operation of the pulse intensifier circuit of the first embodiment.

FIG. 10 is a circuit diagram of a modification of the first embodiment.

FIG. 11 is a circuit diagram of a pulse width extending circuit according to a second embodiment to which the second invention of the present application is applied.

FIG. 12 is a time chart illustrating an operation of the pulse width extension circuit according to the embodiment;

FIG. 13 is a circuit diagram of a pulse width extending circuit according to a third embodiment to which the second invention of the present application is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Signal transition detection circuit 3, 3A, 3B ... Pulse width extension circuit 5 ... Pulse enhancement circuit TP ... P channel MOS transistor TN ... N channel MOS transistor I ... Inverter

Claims (2)

[Claims] 1. A signal transition detecting circuit for detecting a change in a logical state of a signal and outputting a signal indicating a signal transition, the signal corresponding to a time during which the signal indicating a signal transition is output. A signal intensifying circuit for expanding a pulse width of the signal. 2. The method according to claim 1, wherein when a change in the logical state of the signal occurs, the signal is used in the next stage of a signal transition detection circuit that detects the change and outputs a signal having a signal transition. The signal transition presence signal is input to the most input terminal of the connected plurality of buffers as a whole, and a signal extracted from a plurality of locations in the middle of the plurality of buffers and a signal at the most output terminal of the plurality of buffers are ORed with each other. Generating a signal having an extended pulse width of the signal transition presence signal and outputting the signal to the outside, and a logic gate controlled in accordance with the logic state of the pulse width adjustment input signal input from the outside in the middle of the plurality of buffers. In the pulse width extension circuit that adjusts the degree of extension according to the logic state of the pulse width adjustment input signal, the plurality of buffers including the insertion of the logic gate are used. A pulse width extending circuit characterized in that the output loads of the individual buffers constituting the amplifier are made uniform to each other.