JP2001223326A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high density mounting by preventing a wire short circuit and reducing in size and thickness in a small-sized semiconductor device of a chip laminated type. SOLUTION: The semiconductor device comprises a tape board 3 for supporting a first chip 1 of a lowermost stage by flip-chip connecting, a wiring film 4 for supporting a second chip 2 laminated and disposed on the first chip by flip-chip connecting, a wire 9 for connecting a connecting electrode 4b of the film 4 to a connecting electrode 3b of the board 3, a plurality of solder bumps 11 disposed on a rear surface 3d of the board 3, and a sealing part 10 for resin-sealing two semiconductor chips, the wire 9 and the like. In this case, the laminated and disposed first and second chips 1, 2 are face down mounted. The flip-chip connecting and the wire bonding are combined to reduce a wire density in the part 10 to prevent a wire short circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technology effective when applied to high-density mounting of a chip-stacked semiconductor device.

[0002]

2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

In recent years, as an example of a miniaturized semiconductor package, a CSP (Chip Size Package or Chip Sca) has been developed.
There is known a small semiconductor package called a “le package” which is almost equal to or slightly larger than a semiconductor chip.

[0004] Further, miniaturization of a chip stacked type semiconductor device (also referred to as a stacked package) in which a plurality of semiconductor chips are stacked is also required, and development of a stacked package having a CSP structure has been promoted. I have.

A stacked package in which semiconductor chips are stacked in two stages is described in, for example,
No. 204720 describes its structure and manufacturing method.

[0006]

However, in the case of the stacked package described in Japanese Patent Application Laid-Open No. 11-204720, when the package is applied to a CSP, the outer size of the package is small. Wiring area is very small.

[0007] Therefore, when wire bonding is performed in two stages by this CSP, the density of the wires becomes extremely high, and as a result, wire shortage between adjacent wires occurs due to the wire flow during molding. Becomes

Further, since the uppermost (second) semiconductor chip is face-up mounted and wire bonding is performed on the uppermost semiconductor chip, a wire molding region is formed above the uppermost semiconductor chip. Must be secured.

Therefore, in the CSP having this structure, there is a problem that the package cannot be made thin.

SUMMARY OF THE INVENTION An object of the present invention is to provide a chip-stacked semiconductor device which realizes high-density mounting by miniaturizing and thinning while preventing a wire short.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor device of the present invention is a device in which a plurality of semiconductor chips are stacked and assembled, and a common wiring substrate for supporting the lowermost semiconductor chip by flip-chip connection via bump electrodes. And an upper semiconductor chip, which is arranged on a surface opposite to the main surface of the lowermost semiconductor chip to which flip chip connection is performed and is stacked with the lowermost semiconductor chip, via an upper projection electrode. An upper wiring substrate supported by chip connection, a bonding wire for connecting a connection electrode of the upper wiring substrate connected to the upper protruding electrode via a wiring and a connection electrode of the common wiring substrate, and A plurality of external terminals arranged on a surface opposite to the chip supporting surface of the wiring board, and a plurality of the semiconductor chips arranged in a stack While being mounted face down, the surface electrodes of the upper semiconductor chip and the connection electrodes of the common wiring board are connected by flip chip connection and wire bonding, and the lowermost semiconductor chip is flip chip mounted on the common wiring board. What is connected.

According to the present invention, since the lowermost semiconductor chip is connected only by flip chip connection, the connection between the plurality of semiconductor chips and the lowermost common wiring board is divided into flip chip connection and wire bonding. Can be.

As a result, it is possible to reduce the density of the wires in the sealing portion, thereby preventing wire shorts.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a sectional view showing an example of the structure of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a view showing the arrangement of wiring and connection electrodes on a common wiring board and an upper wiring board of the semiconductor device shown in FIG. FIG. 3 is an enlarged partial plan view showing an example. FIG. 3 is a cross-sectional view showing an example of a state of forming an underfill material on a common wiring substrate in the method for manufacturing the semiconductor device shown in FIG.
FIG. 5 is a cross-sectional view showing an example of the first chip mounting on the common wiring substrate and the mounting state of the upper wiring substrate in the method of manufacturing the semiconductor device shown in FIG. 1; FIG. 6 is a cross-sectional view showing an example of a 2nd chip attachment state of FIG. 6, FIG. 6 is a cross-sectional view showing an example of a connection state of wire bonding in the method of manufacturing the semiconductor device shown in FIG. 1, and FIG. 7 is a method of manufacturing the semiconductor device shown in FIG. FIG. 8 is a cross-sectional view showing an example of a state of a mold, and FIG. 8 is a cross-sectional view showing an example of a solder bump mounting state in the method of manufacturing the semiconductor device shown in FIG.

The semiconductor device of the present embodiment shown in FIG.
A chip stacked type in which a plurality of semiconductor chips are stacked and arranged. Each of the semiconductor chips is flip-chip connected by face-down mounting, and the electrical connection between the plurality of semiconductor chips and a common wiring substrate serving as an interposer is established. The connection uses a combination of flip-chip connection and wire bonding.

Further, the semiconductor device is of an area array type in which a plurality of external terminals are arranged on a surface of the common wiring board opposite to the chip supporting surface 3c (hereinafter referred to as a back surface 3d).

In this embodiment, a case will be described in which the semiconductor chips are stacked in two stages and the semiconductor device is a CSP 12 which is a small semiconductor package.

Therefore, the CSP 12 is a stack type C
Also called SP, for example, it is incorporated in a small consumer device such as a portable electronic device. However, since it is a small semiconductor package having two semiconductor chips, the MCM
(Multi-Chip-Module) and system LSI (Large Scale)
Integration).

The structure of the CSP 12 shown in FIG. 1 of the present embodiment will be described. A tape for supporting the first chip 1, which is a semiconductor chip disposed at the lowest level, by flip-chip connection via Au bumps 6 (protruding electrodes) Substrate 3 (common wiring substrate) and back surface 1c opposite to main surface 1a where flip chip connection of 1st chip 1 is performed
And a 2nd chip 2 (upper semiconductor chip) stacked on the 1st chip 1 and supported by flip-chip connection via an upper Au bump 7 (upper projecting electrode). A bonding wire 9 for connecting a connection electrode 4b, which is a bonding pad of the wiring film 4 connected to the upper Au bump 7 via the wiring 4a, to a connection electrode 3b, which is a bonding pad of the tape substrate 3. Solder bumps 11 which are a plurality of external terminals arranged on the back surface 3d of the tape substrate 3, and an underfill material 5 which fills a gap between the tape substrate 3 and the first chip 1 and a gap between the wiring film 4 and the second chip 2. 1st stack consisting of two semiconductor chips and a sealing portion 10 formed by resin-sealing the wires 9 and the like. The flip chip 1 and the 2nd chip 2 are flip-chip connected by face-down mounting, respectively, and the pads 2b (surface electrodes) of the 2nd chip 2 and the connection electrodes 3b of the tape substrate 3 are connected by flip chip connection and wire bonding. Things.

Thus, the CSP 12 according to the present embodiment
Is a chip stacked type, and by combining flip chip connection and wire bonding, reduces the wire density in the sealing portion 10 and prevents wire shorting due to wire flow during molding.

Further, by combining flip-chip connection and wire bonding, the number of connection electrodes 3b on the tape substrate 3 is reduced, and the chip-stacked CS
The area of the P12 in the horizontal direction is reduced to thereby reduce the size of the package, and the 2nd chip 2, which is the uppermost semiconductor chip, is mounted face-down to reduce the thickness of the package.

Here, in the CSP 12, the first chip 1
Is connected to the wiring 3a of the tape substrate 3 only by flip-chip connection.
Is connected by flip-chip connection to the wiring 4a of the wiring film 4 attached to the back surface 1c, which is the upper side of the first chip 1, and the connection electrode 4b of the wiring film 4 connected to this wiring 4a and the common wiring board (interposer) )
And the connection electrodes 3b of the tape substrate 3 are connected by wires 9 by wire bonding.

That is, the first chip 1 is a tape substrate 3
Connected only by flip chip connection to
The nd chip 2 is connected to the tape substrate 3 by flip chip connection and wire bonding.

Accordingly, the first chip 1 has its pad 1 b whose wiring 3 a of the tape substrate 3 is
On the other hand, the pad 2b of the second chip 2 is flip-chip connected to the wiring 4a of the wiring film 4 by the upper Au bump 7.

The tape substrate 3 is formed of, for example, a polyimide tape or the like, and has a wiring 3a made of a metal such as copper, gold or silver, as shown in FIG.
A connection electrode 3b serving as a bonding pad, a bump land 3e for mounting a solder bump, and the like are formed. The bump land 3e is exposed on the back surface 3d side by hollowing out the tape substrate 3, and the external surface shown in FIG. A plurality of solder bumps 11 as terminals are attached.

The wiring film 4 has a rear surface 4d.
Is bonded to the back surface 1c side of the 1st chip 1, that is, the upper side by a thermoplastic adhesive 8 or a double-sided tape having high heat resistance, and is formed of, for example, a polyimide tape or the like, like the tape substrate 3. A wiring 4a made of a metal such as copper, gold or silver and a connection electrode 4b as a bonding pad are formed on the surface.

In place of the underfill material 5, an insulating paste material may be used, but as the underfill material 5, ACF (Anisotropic Conductive Film, ACF) may be used.
It is preferable to use an anisotropic conductive film).

That is, the first chip 1 using the ACF
In this case, the connection between the Au bump 6 and the upper Au bump 7 can be conducted, and an insulating member can be embedded around the connection.

On the chip supporting surface side of the tape substrate 3, a sealing portion 10 is formed by molding using a molding resin, for example, a thermosetting epoxy resin. 2. The wiring film 4 and the wire 9 are sealed.

The bonding wire 9 is, for example, a gold wire.

As a function of the semiconductor chip mounted on the CSP 12, for example, the first chip 1 is an ASIC.
(Application Specific Integrated Circuit), 2nd
Chip 2 is a DRAM (Dynamic Random Access Memory)
And a multi-chip package having semiconductor chips of different functions.

This is because the first chip 1 is larger than the second chip 2 so that it can handle a large number of pins, and it is preferable to incorporate the upper semiconductor chip for a memory.

However, all of the plurality of semiconductor chips may be used as a memory, or a combination of a microcomputer and a flash memory may be used.

Next, the semiconductor device C of this embodiment is
A method for manufacturing SP12 will be described.

First, as shown in FIG. 3, a tape substrate 3 is prepared, and an underfill material 5 is applied or affixed to a first chip mounting area of the chip supporting surface 3c.

In this embodiment, a case where ACF is used as the underfill material 5 will be described. However, an insulating paste material or the like may be applied instead of the underfill material 5.

Subsequently, as shown in FIG. 4, the first chip 1 is mounted face-down on the chip supporting surface 3c of the tape substrate 3.

That is, the chip supporting surface 3 of the tape substrate 3
c and the main surface 1a of the first chip 1 are opposed to each other, and the first chip 1 is placed on the ACF as the underfill material 5,
The first chip 1 is fixed (mounted) on the tape substrate 3 by thermocompression bonding.

As a result, the first chip 1 is flip-chip connected to the chip supporting surface 3c of the tape substrate 3 via the Au bump 6.

That is, each pad 1b of the first chip 1
And the corresponding wiring 3 a of the tape substrate 3 are connected via the Au bumps 6.

The wiring film 4 on the back surface 1c of the first chip 1 is previously bonded at the wafer stage using a thermoplastic adhesive 8 or the like. Therefore, the first chip 1 is obtained by dicing. In this case, the wiring film 4 is already attached to the back surface 1c via the adhesive 8.

Thereafter, as shown in FIG. 5, the ACF as the underfill material 5 is placed on the second chip mounting area of the chip supporting surface 4c of the wiring film 4 on the upper stage side of the first chip 1, which is on the back surface 1c side of the first chip 1. Deploy.

Subsequently, on the upper side of the first chip 1, the second chip 2 is connected to the chip supporting surface 4 of the wiring film 4.
Mount face down on c.

That is, the chip supporting surface 4c of the wiring film 4 and the main surface 2a of the chip 2 are opposed to each other, and the chip 2 is placed on the ACF which is the underfill material 5, and the chip 2 is thermally compressed. Is fixed (mounted) on the wiring film 4.

As a result, the second chip 2 is flip-chip connected to the chip supporting surface 4 c of the wiring film 4 via the upper Au bump 7, and as a result, the second chip 2 is stacked on the first chip 1.

That is, each pad 2b of the second chip 2
And the corresponding wiring 4 a of the wiring film 4 are connected via the upper Au bump 7.

The underfill material 5 used for fixing the second chip 2 is not ACF but, for example,
A conductive adhesive or the like may be used.

That is, similarly to the ACF, even when the conductive adhesive is used, the second chip 2 does not need to be scrubbed when fixed, so that the impact on the first chip 1 can be reduced.

Thereafter, as shown in FIG. 6, the connection electrode 4b, which is a bonding pad of the wiring film 4, and the connection electrode 3b, which is a bonding pad of the tape substrate 3, are wire-bonded using gold wires 9.

Thus, the second chip 2 and the tape substrate 3 as an interposer are electrically connected by flip chip connection and wire bonding.

Thereafter, as shown in FIG. 7, the chip supporting surface 3c side of the tape substrate 3 is resin-sealed by transfer molding, and a sealing portion 10 is formed on the chip supporting surface 3c side.

Subsequently, as shown in FIG. 8, the CSP 12 is turned upside down so that the back surface 3d side of the tape substrate 3 faces upward, and a plurality of bump lands 3e exposed on the back surface 3d side.
Solder bumps 11 are attached to the substrate.

Attachment (mounting) of solder bump 11
Is performed by, for example, a transfer method.

As a result, C of the present embodiment shown in FIG.
SP12 is completed.

In the CSP 12, there is a case where only the second chip 2 is connected for chip selection. In this case, for example, the corresponding pad 1 of the first chip 1 is connected.
It is assumed that no Au bump 6 is connected to b.

That is, the Au bumps 6 are not always connected to all the pads 1b.

Semiconductor device of this embodiment (CSP 12)
According to this, the following operation and effect can be obtained.

That is, a plurality of semiconductor chips arranged in a stack are face-down mounted respectively, whereby
Since the first chip 1 (the lowermost semiconductor chip) is connected only by flip-chip connection, the lowermost tape substrate 3 serving as an interposer with the plurality of semiconductor chips.
The connection with the (common wiring board) can be divided into flip chip connection and wire bonding.

As a result, the density of the wires 9 in the sealing portion 10 can be reduced, thereby preventing a wire short due to a wire flow during molding.

That is, the combination of flip-chip connection and wire bonding greatly reduces the density of the wires 9 in the sealing portion 10 as compared with a conventional chip-stacked semiconductor device using only wire bonding. As a result, in the chip-stacked CSP 12 of the present embodiment, it is possible to prevent occurrence of wire short-circuit.

Further, as compared with a conventional chip-stacked semiconductor device using only flip-chip connection, the chip-stacked CSP 12 of the present embodiment has an area array type of solder bumps 11 as external terminals. Yes, therefore, while suitable for high-density mounting, the conventional chip-stacked semiconductor device using only the flip-chip connection has a structure in which the outer leads serving as external terminals protrude from the sealing portion 10. However, the mounting area of the semiconductor device increases, and as a result, it is not suitable for high-density mounting.

Thus, the chip-stacked CSP 12 of the present embodiment, in which flip-chip connection and wire bonding are combined, is more suitable for high-density mounting.

The connection between the plurality of semiconductor chips and the tape substrate 3 as an interposer is divided into flip-chip connection and wire bonding, so that the tape substrate 3
The installation area of the connection electrode 3b, which is a bonding pad for wire bonding, can be reduced.
Thereby, the chip-stacked semiconductor device of the present embodiment can be realized as the CSP 12.

Therefore, the miniaturization of the chip-stacked semiconductor device can be realized.

Further, a plurality of stacked semiconductor chips are mounted face-down, so that the second chip 2 (the uppermost semiconductor chip) is also flip-chip connected, so that the wires 9 are provided on the second chip 2. There is no need to secure an area for the sealing portion 10.

As a result, the sealing portion 10 above the back surface 2c of the second chip 2 can be formed very thin, whereby the chip stack type CSP 12 can be further thinned.

That is, the CSP 12 of the present embodiment can be made thinner than a conventional chip-stacked semiconductor device of the type in which wire bonding is performed on the uppermost semiconductor chip.

Therefore, the chip-stacked CSP 12 of the present embodiment can be reduced in size and thickness, and can be mounted at a high density.

Further, since the 2nd chips 2 arranged in a stack are connected to the tape substrate 3 (common wiring substrate) as an interposer by flip-chip connection and connection by wire bonding, new capital investment is not required and existing equipment can be used. Thus, a small-sized semiconductor device (CSP 12) of a chip-stacked type can be manufactured, so that an increase in the cost of the semiconductor device can be suppressed.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the invention, and does not depart from the gist of the invention. It is needless to say that various changes can be made.

For example, in the above-described embodiment, in the method of manufacturing a semiconductor device, the first chip 1 having the wiring film 4 adhered to the back surface 1c in advance is prepared.
Although the case where the 2nd chip 2 is laminated on the t chip 1 has been described, the flip chip connection of the 2nd chip 2 to the wiring film 4 is performed in another process different from the method of manufacturing the semiconductor device, and the back surface 1c ( The lamination of the 2nd chip 2 on the upper stage) may be performed together with the wiring film 4.

In the above embodiment, the case where the number of stacked chips is two is described. However, the number of stacked chips may be any number as long as it is two or more.

Further, in the above embodiment, the case where the common wiring substrate and the wiring film 4 are made of a substrate such as a polyimide tape has been described. However, the two substrates are not limited to the substrate of the polyimide tape. A resin substrate or a ceramic substrate made of epoxy resin or the like may be used.

Further, in the above embodiment, the sealing portion 10
Is formed by transfer molding, but the sealing portion 10 may be formed by potting.

In the above embodiment, the case where the semiconductor device is the CSP 12 has been described. However, the semiconductor device is of a chip stack type, the external terminals are arranged in an area array, and each semiconductor chip is a face-to-face type. If the flip-chip connection is performed by down mounting and the connection is a combination of the flip-chip connection and the wire bonding, for example, an LGA other than the CSP 12 may be used.
(Land Grid Array).

[0079]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). A plurality of semiconductor chips arranged in a stack are mounted face-down, and the lowermost semiconductor chip is connected only by flip-chip connection, so that the connection between the plurality of semiconductor chips and the lowermost common wiring board is flipped. It can be divided into chip connection and wire bonding. As a result, it is possible to reduce the density of the wires in the sealing portion, thereby preventing a wire short due to a wire flow during molding.

(2). By dividing the connection between the plurality of semiconductor chips and the lowermost common wiring board into flip-chip connection and wire bonding, the installation area of the connection electrodes for wire bonding on the common wiring board can also be reduced, whereby The chip-stacked semiconductor device can be compatible with the CSP. Therefore, miniaturization of a chip-stacked semiconductor device can be realized.

(3). A plurality of stacked semiconductor chips are mounted face-down, so the topmost semiconductor chip is also flip-chip connected. Therefore, it is necessary to secure an area for a sealing portion for wires on this semiconductor chip. Disappears. As a result, the thickness of the chip-stacked semiconductor device can be reduced.

(4). According to the above (2) and (3), the chip stacked semiconductor device can be reduced in size and thickness, so that high-density mounting of the semiconductor device can be realized.

(5). Since the stacked semiconductor chips are connected to a common wiring board by flip chip connection and wire bonding connection, no new capital investment is required, and a small semiconductor device of a chip stacked type can be manufactured by utilizing existing equipment, and therefore, Thus, an increase in the cost of the semiconductor device can be suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of a structure of a semiconductor device according to an embodiment of the present invention.

2 is an enlarged partial plan view showing an example of an arrangement state of wiring and connection electrodes on a common wiring board and an upper wiring board of the semiconductor device shown in FIG. 1;

3 is a cross-sectional view showing an example of a state in which an underfill material is formed on a common wiring board in the method of manufacturing the semiconductor device shown in FIG. 1;

FIG. 4 is a cross-sectional view showing an example of a first chip attached to a common wiring board and an attached state of an upper wiring board in the method of manufacturing the semiconductor device shown in FIG. 1;

5 is a cross-sectional view showing an example of a state in which a 2nd chip is mounted on an upper wiring board in the method of manufacturing the semiconductor device shown in FIG. 1;

6 is a cross-sectional view illustrating an example of a connection state of wire bonding in the method of manufacturing the semiconductor device illustrated in FIG.

FIG. 7 is a cross-sectional view showing an example of a state of a mold in the method of manufacturing the semiconductor device shown in FIG.

8 is a cross-sectional view illustrating an example of a state in which solder bumps (external terminals) are attached in the method of manufacturing the semiconductor device illustrated in FIG. 1;

[Explanation of symbols]

 1 1st chip (lowest stage semiconductor chip) 1a main surface 1b pad (front surface electrode) 1c back surface (opposite surface) 2 2nd chip (upper stage semiconductor chip) 2a main surface 2b pad (front surface electrode) 2c back surface 3 tape substrate (Common wiring substrate) 3a Wiring 3b Connection electrode 3c Chip support surface 3d Back surface (opposite surface) 3e Bump land 4 Wiring film (upper wiring substrate) 4a Wiring 4b Connection electrode 4c Chip support surface 4d Back surface 5 Underfill material 6 Au Bump (projecting electrode) 7 Upper Au bump (upper projecting electrode) 8 Adhesive 9 Wire 10 Sealing part 11 Solder bump (external terminal) 12 CSP (Semiconductor device)

Claims (1)

[Claims] 1. A semiconductor device in which a plurality of semiconductor chips are stacked and incorporated, wherein a common wiring board supporting a lowermost semiconductor chip by flip-chip connection via a protruding electrode; The lower semiconductor chip is disposed on the surface opposite to the main surface where the flip chip connection of the semiconductor chip is performed, and the upper semiconductor chip stacked and disposed with the lowermost semiconductor chip is supported by the flip chip connection via the upper projecting electrode. An upper wiring board; a connection electrode of the upper wiring board connected to the upper protruding electrode via a wiring; a bonding wire connecting the connection electrode of the common wiring board; and a chip of the common wiring board. A plurality of external terminals arranged on a surface opposite to the supporting surface, and the plurality of semiconductor chips arranged in a stack are face-down And the surface electrodes of the upper semiconductor chip and the connection electrodes of the common wiring board are connected by flip chip connection and wire bonding, and the lowermost semiconductor chip is flip chip connected to the common wiring board. A semiconductor device.