JP2001211098A - Mobile communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a mobile communication equipment for high data communication with a reduction of parts count, the equipment is employing as a receiving/transmitting equipment in a direct conversion system adapting to a large scale integration. SOLUTION: In this communication equipment, a direct-conversion reception is used, and a frequency divider is used to reduce VCO count by supplying a local oscillation signal in RF band to a receiver and a transmitter. A frequency divider with a fixed frequency division ratio is used to generate a local oscillation signal for the receiver, a frequency divider with a selectable of a frequency division ratio is used to generate a local oscillation signal for the transmitter. A DC offset voltage detecting means and a DC offset correcting means are provided at a variable gain amplifier for a base band signal to adapt to the high data communication, then the DC offset is corrected at high speed without any filter intervention in a feed back loop for offset correction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile communication device capable of reducing the number of components, and more particularly, to a transceiver using a direct conversion method suitable for large-scale integration.

[0002]

2. Description of the Related Art With the explosive spread of mobile communication devices, there is an increasing demand for reduction in size and cost. Therefore, V
It is desired to apply a CO (voltage controlled oscillator) or an integrated circuit with a reduced number of filters and an increased degree of integration. As a conventional example of a transceiver, I, E, E, E, 1999, 25th European Integrated Circuit Conference Proceedings 2
“GSM, DCS18 published on pages 78 to 281
00 Dual-Band Transceiver IC High-Frequency Technology "(K. Takikawa et. Al. RF Circuits Technique of Du
al-Band Transceiver IC for GSM and DCS1800 applica
^{tions, IEEE 25 th European Solid-} State Circuits Con
ference pp. 278-281, 1999). The configuration diagram is shown in FIG. (1016) is an integrated circuit, and other components (1001 to 1015) are externally attached. This conventional example corresponds to two frequency bands of a 900 MHz band and a 1.8 GHz band. Also, a superheterodyne method is applied as a receiver, and an offset PL
The L system is adopted. In the superheterodyne receiver, two RF (high-frequency) filters (1001, 1002) for suppressing out-of-band interference waves, and two image removal filters (1003, 1004) for removing interference waves in an image frequency band due to frequency conversion. IF (intermediate frequency) filter for removing interfering waves near the receiving channel (1005)
Is required. In order to support two frequency bands, 900 MHz band and 1.8 GHz band, a local oscillator (1006,
1007) are required.

[0003] A receiving method that can reduce the number of external parts
There is a direct conversion method. Conventional examples of direct conversion receivers include eye, e, e,
E, 1997, VLSI Circuit Symposium Proceedings 1
"900MHz Direct Conversion Receiver" published on pages 13 to 114 (Behzad Razavi, "A 900-
MHz CMOS Direct Conversion Receiver, "IEEE Symposi
um on VLSI Circuits, pp. 113-114, 1997). The configuration diagram is shown in FIG. Since there is no image response in principle, the direct conversion method does not require an image removing filter. Further, the IF filter becomes unnecessary because it can be substituted by a filter integrated in the IC. In this embodiment, the VCO (1025) oscillates at twice the frequency of the input frequency of the receiver, and its frequency is 1
850 to 1920 MHz. This receiver is GSM,
When applied to a DCS1800 dual band receiver, the VCO (1025) is 1850-1920 MHz
(GSM) and 3610-3760 MHz (DCS180
It is necessary to oscillate at 0). However, it is difficult to cover these frequency bands with one VCO, and
Required.

[0004] A widely known disadvantage of direct conversion receivers is the DC offset voltage. This occurs because the frequency of the input signal of the mixer (1019, 1020) is equal to the frequency of the local oscillation signal. For example, when the local oscillation signal leaks to the input terminal of the input signal, multiplication of the local oscillation signals occurs, and a DC offset voltage is generated. Conventional examples of the method of calibrating the DC offset voltage are eye,
E, E, E, "Direct Conversion Transceiver for Digital Communication" (As), published in Semiconductor Device Circuit Journal, pages 1399 to 1410, 1995.
ad A. Abidi et. al., "Direct-Conversion Radio Tran
sceivers for Digital Communications, "IEEE Journal
of Solid-State Circuits, pp. 1399-1410, vol. 30,
no. 12, Dec., 1995). The configuration diagram is shown in FIG. Variable gain amplifier (1101, 1103, 1105)
The output DC offset voltage of the variable gain amplifier consisting of the low pass filter (1102, 1104)
106). Based on the information, the DSP (1
106) outputs a DC offset voltage calibration signal to the input of the low-pass filter (1101).

[0005]

As described above, the direct conversion receiver can reduce the number of external filters. However, the GSM, DCS shown in FIG.
When a direct conversion receiver is used instead of a super heterodyne receiver in a 1800 dual-band transceiver, the number of local oscillators increases. This is because the local oscillation frequency is 115 in the transmitter.
0 to 1185 MHz (GSM), 1575 to 1650 M
Hz (DCS1800) is 1850-19
20MHz (GSM), 3610-3760MHz (D
CS1800), and it is difficult to cover a plurality of bands with one VCO. The first issue is to reduce the number of VCOs for further cost reduction.

Further, GPRS (General Packet Ra) for realizing high-speed data communication in the GSM system.
In the “dio service”, a plurality of slots are allocated to reception or transmission. Therefore, high-speed DC offset voltage calibration is required. Further, the DC offset voltage calibration needs to be performed for each operation frame. First, the necessity of high-speed offset calibration will be described with reference to FIG. GS
One frame of M is composed of eight slots, and the time of one slot is 577 μsec. Suppose a severe condition for DC offset voltage calibration, that is, a case where four slots are allocated to reception (RX) and one slot is allocated to transmission (TX). The transmission slot TX1 'is allocated to the slot 7, but considering the propagation delay to the base station, the slot 7 is used.
Is transmitted at the timing of TX1 237 μsec before In addition to the transmission and reception, a monitoring period of about 500 μsec and a PLL synchronization period are required. 1 during PLL synchronization period
If it takes about 50 μsec, the time for performing the DC offset voltage calibration without operating the transmitting / receiving circuit is 1154−
500−237−150 * 2 = 117 μsec,
High-speed DC offset calibration is required.

Next, the necessity of performing offset calibration for each frame will be described with reference to FIG. FIG. 5 shows a measurement circuit for measuring the reception frequency dependency of the output DC offset voltage of the mixer and the measurement results. The measurement results show that the output DC offset voltage has frequency dependence. Therefore, in a system such as GSM and DCS1800 in which the reception frequency during a call is not fixed and frequency hopping is performed within a reception band, it is difficult to predict the DC offset voltage in advance. Therefore, it is necessary to calibrate the DC offset voltage for each operation frame.

The method of the embodiment (FIG. 11) is not suitable for high-speed data communication because it is difficult to perform high-speed offset calibration because a filter is interposed in a feedback loop for offset calibration. Therefore, realization of a high-speed offset calibration method suitable for high-speed data communication is a second problem.

[0009]

In order to achieve the first object, in the present invention, a local oscillation signal in the RF band is supplied from one VCO to a receiver and a transmitter using a frequency divider.
A frequency divider having a fixed frequency division ratio is used for generating a local oscillation signal for a receiver, and a frequency divider capable of switching the frequency division ratio is used for generating a local oscillation signal for a transmitter.

In order to achieve the second object, in the present invention, a DC offset voltage detecting means and a DC offset calibrating means are provided in a variable gain amplifier for a baseband signal.
The DC offset is calibrated at high speed without a filter in the feedback loop for offset calibration.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. Here, as applications, European cellular telephone GSM (900 MHz band), DCS1800
(1800 MHz band) is used.

A direct conversion method for directly converting an RF signal into a baseband signal is applied to a receiver,
The transmitter employs the offset PLL method already described in the conventional example. The receiver is a low noise amplifier (101, 10
2), a mixer (103, 104), and a variable gain low-pass filter (139). The mixer converts the signal frequency from the RF band to the baseband,
Demodulation for separating into n component and cos component is also performed at the same time. For this reason, it is necessary to add local oscillation signals having a 90 ° phase difference to the mixers (103, 104), and the frequency dividers (105, 115)
Generated using The local oscillation signal is VCO (111)
And a PLL (112) to form a PLL loop. If a 3600 MHz band oscillation is used as the VCO (111), the output of the frequency divider (115) becomes 1800M
In the Hz band, a local oscillation signal for DCS1800 is obtained.
In addition, by disposing the frequency divider (116) in front of the frequency divider (105), the output frequency of the frequency divider (105) becomes 900
In the MHz band, a local oscillation signal for GSM is obtained. The output baseband signals of the mixers (103, 104) are input to a variable gain low-pass filter (139), where level adjustment and interference wave removal are performed. Variable gain low pass filter (1
39) is a low-pass filter (106, 107, 137,
138) and variable gain amplifiers (108, 109). Further, in order to suppress the DC offset voltage at the output of the variable gain low-pass filter (139), a DC offset voltage calibration circuit (110) having DC offset voltage detection means and DC offset calibration means is provided.

To reduce the number of external components, the transmitter uses the same VCO (111) as the receiver. How to determine the IF frequency (fIF) used in the transmitter will be described below. The reception frequency received by the antenna (136) is represented by fr _G (GS
M) and fr _D (DCS1800), and the transmission frequencies to be transmitted are ft _G (GSM) and ft _D (DCS1800).
As described above, since the oscillation frequency of the VCO (111) is four times the GSM reception frequency and twice the DCS1800 reception frequency, the oscillation frequency of the VCO (111) is 4 · fr _G = 2
· Fr can be expressed as _D. The oscillation frequency m division (GSM), if the divide-by-n (DCS1800) signal is used as the local oscillation signal of the mixer (126) of the offset PLL, IF frequency fIF _G during GSM is expressed as in Equation 1.

[0014]

(Equation 1)

Similarly, IF frequency fI at DCS 1800
F _D can be expressed as in Equation 2.

[0016]

(Equation 2)

Here, fr _G = 925 MHz, ft _G = 8
80 MHz, fr _D = 1805 MHz, ft _D = 1710
MHz. FIG. 12 shows the result of calculating fIF _G for m, and FIG. 13 shows the result of calculating fIF _D for n.
Shown in Since a two-frequency divider is used for the frequency division, 2i-th power (i is a positive integer) is used as m and n. In order to use one VCO for IF frequency generation, m and n cannot be freely selected, and fIF _G and fIF _D need to be substantially equal.
Alternatively, if a 2 divider is used, fIF _G and fIF _D
Should be approximately equal to 2 to the power of j (j is a positive integer). Here, “substantially equal” means that even if the two frequencies do not exactly match, it is sufficient that they are included in the oscillation frequency range of the VCO. 12 and 13, combinations of m and n that satisfy the above conditions are, for example, (m, n) = (2, 1) or (4, 2). This m,
The fIF is finally determined from the combination of n in consideration of the power consumption and the presence / absence of unnecessary spurious signals. In this embodiment, (m, n) = (4, 2). Frequency divider (117, 118) and changeover switch (121)
Is provided after the VCO (111).
(111) The output frequency is controlled so as to divide by 4, and in DCS 1800, to divide by 2. Next, the oscillation frequency of the VCO (114) is determined by the power consumption, the scale of passive elements built in the IC, and the like. In this embodiment, the oscillation frequency is 30
0 MHz band, and a frequency divider (11
9, 120) and the changeover switch (122), the frequency is divided by 8 in GSM, and divided by 4 in DCS1800 to generate fIF _G = 45 MHz and fIF _D = 95 MHz.

The spurious problem will be described more specifically. 17 and 18 show spurious signals when the IF frequency is fixed and the local oscillation frequency is changed. 17 and 18
Corresponds to GSM and DCS1800, and when a transmission signal is generated from a transmission oscillator (128, 124), I
This figure shows the spurious caused by the difference between the integral multiple (m times) of the F frequency and the local oscillation frequency. Where fIF
Indicates the IF frequency, and fVCO indicates the transmission frequency. The numerical values entered in the respective columns indicate the difference between the spurious signal and the transmission frequency in MHz. The hatched area is 10 MH
This is a case where spurious signals are generated in the vicinity of z, and it is difficult to remove them with the loop filter (127) of the transmitter. As can be seen from FIGS. 17 and 18, if the IF frequency is fixed to one, it is difficult to avoid an area where spurious appears near the transmission frequency in the transmission band, and it is difficult to change the IF frequency according to the transmission frequency. The effectiveness is understood. For example, in the GSM example shown in FIG.
Select an IF frequency of 45 MHz from z to 888 MHz and an I frequency of 46 MHz from 888 MHz to 914 MHz.
By selecting the F frequency, spurious can be avoided.

In this embodiment, the mixer circuit (12
The local oscillation signal applied to 6) exists in the reception band. FIG. 16 shows an enlarged view of the transmitting section of this embodiment. (23
The local oscillation signal in the reception band leaks through the path indicated by 09) and is amplified and radiated by the amplifier at the subsequent stage.
FIG. 19 summarizes the standards for GSM spurious suspensions. The spurious of the reception band is -36 dB only for 5 points
m spurs are allowed, but in principle -79dBm /
It is desired to suppress to 100kHz. FIG. 20 summarizes the oscillation frequencies of the VCOs described in the above embodiments. DC
S1800 reception band (2701) and transmission band (270)
3) is the same and the GSM reception band (2702)
And the transmission band (2704) also match. To shift this, consider a frequency arrangement as shown in FIG. DC
The transmission band (2705) shifted from the reception band (2701) in S1800 does not overlap, and local oscillation leakage having a frequency within the reception band during transmission can be avoided. The same applies to GSM.

Next, a second embodiment of the receiver according to the present invention will be described.

The receiver includes a low noise amplifier (102), a mixer (104), a frequency divider (105), a low-pass filter (106, 137), and a variable gain amplifier (108, 20).
1), DC offset voltage calibration circuit (110, 206)
And a decoder (205). The low-noise amplifier includes a load resistor (207) and a transistor (208).
And a capacitor (209), and the DC offset voltage calibration circuit (110) is a digital-to-analog converter DAC.
(202), analog-to-digital converter ADC (203)
And a control circuit (204). Mixer (10
4) is composed of mixers (210, 206).

The output DC voltage of the variable gain amplifier (108) is converted into a digital signal by the ADC (203) and input to the control circuit (204). The DC offset voltage at the output of the variable gain amplifier (108) is measured by the control circuit (204), and a calibration signal for calibrating the DC offset voltage is output. The calibration signal is converted from a digital signal to an analog signal by the DAC (202), and the DAC (202)
The DC offset voltage of the variable gain amplifier (108) is calibrated by the output signal. The DC offset voltage calibration circuit (110) is selected by the decoder (205),
Only the selected circuit operates. As described above, since no filter is interposed in the feedback loop including the variable gain amplifier and the DC offset voltage calibration circuit, there is no delay in the filter, and high-speed offset calibration can be realized. Where AD
The number of bits of C is 1 bit, that is, a simple comparator can be applied.

A third embodiment of the variable gain amplifier and the DC offset voltage calibration circuit according to the present invention will be described with reference to FIG.

The variable gain amplifier has resistors (307, 30).
8, 312) and transistors (309, 310, 31)
1). Transistor (309, 310)
The input voltage is input to the base of, and the output voltage is output from the collector. The gain is determined, for example, by the transistor (31
It can be controlled by the base voltage of 1). DAC
(313) is a transistor (301, 302, 30)
3) and resistors (304, 305, 306). The output of the control circuit (204) is connected to a transistor (30
1, 302, 303), the control circuit (204) controls the transistors (301, 302, 3).
03) The collector direct current can be controlled. The collector DC current is added to the collector current of the transistor (309) and converted into a voltage by the resistor (307). Now, it is assumed that there is a DC offset voltage ΔV (= V ₂ −V ₁ ). The resistance values of the resistors (307, 308) are R _L , DA
The output direct current of C (313) is _converted to I _DAC1 and DAC (31
The output DC current of 4) is represented by I _DAC2 . At this time, the control circuit (204) controls the DACs (313, 314) so that the relationship of Expression 3 holds.

[0025]

(Equation 3)

A fourth embodiment of the variable gain amplifier according to the present invention will be described with reference to FIG. FIG. 6A shows an ideal variable gain amplifier (60) having no DC offset voltage.
3) shows the input-converted DC offset voltage source (606) of the variable gain amplifier (603). In this case, since there is no means for suppressing the offset voltage, the output terminals (604, 60
During 5), an offset occurs in which the output voltage of the offset voltage source (606) is multiplied by the gain of the variable gain amplifier (603). Next, a third embodiment according to the present invention, in which the changeover switches (607, 608) are connected to the input / output of the variable gain amplifier (603), is shown in FIGS. 6 (b, c). Since the connection relations of the changeover switches (607, 608) are reversed in FIGS. 6B and 6C, the connection relation between the input and output terminals is maintained while the offset voltage source (60) is maintained.
6) The output terminals for transmitting the output voltage are reversed. Therefore, the changeover switches (607, 608) shown above
Is switched periodically, the offset voltage source (60
The output voltage of 6) is generated at the output terminals (604) and (605) for the same time, and the offset voltage between the output terminals becomes zero.

A fifth embodiment of the receiver according to the present invention will be described with reference to FIG. This embodiment uses the variable gain amplifier (609) shown in the third embodiment instead of the variable gain amplifier (201) and the DC offset voltage calibration circuit (206) in the second embodiment. (609) A receiver characterized in that a low-pass filter (702) and a buffer amplifier (701) are connected at a subsequent stage.

A receiver according to a sixth embodiment of the present invention will be described with reference to FIG. This embodiment is a receiver characterized in that a switch (801) is connected between the low-pass filter (140) and the variable gain amplifier (201) in the second embodiment. At the time of DC offset voltage calibration, the switch (801) is turned on to short-circuit the input of the variable gain amplifier (201), and the switch (801) is turned off except during calibration. Switch for calibration (801)
Is turned on, the variable gain amplifier (201) can perform calibration without being affected by the DC offset voltage from the preceding stage.

A mobile communication device according to a seventh embodiment of the present invention will be described with reference to FIG. The present embodiment is a mobile communication device characterized by adding a baseband circuit (901) to the first embodiment. (907) contains the first
In this embodiment, all the circuits except the antenna (139) and the circuit (143) built in the IC are included. The baseband circuit (901) performs signal processing such as conversion of the received baseband signals (902, 903) to audio signals and conversion of audio signals to transmission baseband signals (905, 906). Further, the baseband circuit (90
1) outputs a DC offset cancel start signal (904) for determining the timing of starting the calibration of the DC offset voltage in the circuit (143), and inputs the signal to the circuit (143). This start signal is sent before the receiver starts receiving the signal, and removes the DC offset generated in the circuit of (143) before receiving the signal.

An eighth embodiment of the mobile communication device according to the present invention will be described with reference to FIG. Filter (14
0) capacity (1403) and resistance (1404, 1405)
The switches (1401, 1402) are inserted between them to reduce the time constant during DC offset calibration. As a result, the propagation delay in the filter (140) can be reduced, so that the DC offset calibration can be performed at high speed without using the input short-circuit switch (801) shown in FIG. In addition, each amplifier (10
8, 201) are formed of bipolar transistors as shown in FIG.
05) is performed. For this reason,
The DC offset voltage can be calibrated including the bias offset due to the base current variation and the filter resistance variation. In contrast, in the sixth embodiment using the short-circuit switch (801), the bias offset cannot be calibrated. Also, if the DC offset is removed in order from the previous stage,
Since the residual error is removed by the DC offset calibration function at the subsequent stage, more accurate DC offset removal can be achieved.

A ninth embodiment of the mobile communication device according to the present invention will be described with reference to FIG. When the propagation delay of the filter is reduced as in the eighth embodiment, the filter can be interposed in the feedback loop for DC offset voltage calibration. Therefore, the number of ADCs can be reduced and the circuit scale can be reduced as compared with the eighth embodiment.

[0032]

According to the present invention, as compared with the case where a conventional superheterodyne receiver is applied, an external filter 3 is provided.
And one external VCO can be reduced. Further, by adopting a method of removing a DC offset voltage, which is a problem in a direct conversion receiver, at high speed, a mobile communication device capable of supporting a high-speed packet transmission mode while reducing the number of components can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a mobile communication device according to a first embodiment of the present invention.

FIG. 2 is a partial configuration diagram of a receiver of the mobile communication device of the present invention.

FIG. 3 is a detailed diagram of a circuit for removing a DC offset of the receiver of the present invention.

FIG. 4 is an operation timing chart according to the GSM standard.

FIG. 5 is a diagram showing a method of measuring a DC offset voltage generated by a mixer circuit and a measurement result.

FIG. 6 is an operation principle diagram of a chopper type amplifier applicable to the present invention.

FIG. 7 is an embodiment in which a chopper type amplifier is applied to a receiver according to the present invention.

FIG. 8 is a configuration diagram of a circuit that performs direct offset voltage calibration of a variable gain amplifier without being affected by a preceding circuit according to the receiver of the present invention.

FIG. 9 is a diagram showing that a timing signal for removing a DC offset is given from a baseband circuit.

FIG. 10A is a configuration diagram of a mobile communication device to which a conventional superheterodyne system is applied. (B) Configuration diagram of a conventional direct conversion receiver.

FIG. 11 shows a conventional DC offset voltage calibration method.

FIG. 12 is a diagram showing a transmitter IF frequency during GSM operation.

FIG. 13 is a diagram showing a transmitter IF frequency during DCS1800 operation.

FIG. 14 is a diagram illustrating a method of separating a filter capacitance and accelerating a DC offset removing operation.

FIG. 15 is a diagram showing a method of separating a filter capacitance and simplifying a DC offset removing circuit.

FIG. 16 is a diagram showing a GSM / DCS1800 dual-band transmission circuit.

FIG. 17 is a diagram showing a list of spurious signals at the time of GSM transmission.

FIG. 18 is a diagram showing a list of spurious signals at the time of transmission of DCS1800.

FIG. 19 is a diagram showing a GSM spurious standard.

FIG. 20 is a diagram showing V in which the local oscillation frequency bands of transmission and reception match.
The figure which shows a CO oscillation frequency arrangement | positioning.

FIG. 21 is a diagram showing a VCO oscillation frequency arrangement in which local oscillation frequency bands for transmission and reception do not overlap.

[Explanation of symbols]

101, 102 Low noise amplifier 103, 104, 123, 126, 206, 21
0, 1019, 1020 Mixer 105, 115, 116, 117, 118, 11
9, 120, 139 divider 106, 107, 127, 131, 132, 13
7, 138, 702, 1012, 1013, 102
1, 1022, 1101, 1103, 1105 Low-pass filters 108, 109, 201, 603, 1102, 1
104 Variable gain amplifier 110 DC offset voltage calibration circuit 111, 114, 128, 129, 1006, 1
007, 1008, 1009 VCO 112, 113 PLL 121, 122 Changeover switch 127 Phase comparator 130, 1010, 1011 Power amplifier 133, 134, 1001, 1002, 1003,
1004, 1005 band-pass filter 135, 1014 antenna switch 136, 1015 antenna 139 variable gain low-pass filter 140, 1016 IC built-in circuit 202 DAC 203 ADC 205 decoder 701 buffer amplifier 801, 1401, 1402, switch 901 baseband circuit 1403 1404, 1405 Resistance 2301, 2302, 2305, 2306 Limiter amplifier 2303, 2304, 2307, 2308 Low-pass filter 2309 Transmission local oscillation signal leakage path 2701, 2702 VCO oscillation frequency band at reception 2703, 2704, 2705, 2706 Transmission VCO oscillation frequency.

Continued on the front page (72) Inventor Masao Hotta 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Toyohiko Hongo 5--20, Josuihoncho, Kodaira-shi, Tokyo No. 1 Hitachi, Ltd. Semiconductor Group (72) Inventor Daizo Yamawaki 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. No. 20 No. 1 Hitachi, Ltd. Semiconductor Group (72) Inventor Kumiko Takigawa 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.

Claims (13)

[Claims] 1. A first VCO, first and second frequency dividers connected to the output of the first VCO, an output signal of the first frequency divider and a first RF signal. And a second mixer to which an output signal of the second frequency divider and a second RF signal are input, and an output of the first VCO. Connected to the first frequency dividing ratio and the second
A third frequency divider having means for switching the frequency division ratio of the second VCO, a second VCO, and a third frequency divider connected to an output of the second VCO.
And a fourth frequency divider having means for switching a fourth frequency division ratio, a third mixer to which an output signal of the fourth frequency divider and a baseband signal are input, and a third frequency divider. A transmitter including: a frequency conversion circuit that frequency-converts an output signal of the third mixer using an output signal of a frequency divider. 2. The transceiver according to claim 1, wherein the first
The frequency division ratio of the second frequency divider is 2, and the frequency division ratio of the second frequency divider is 4
A transceiver. 3. The transceiver according to claim 2, wherein the first
When the frequency of the RF signal is frf1, the frequency of the second RF signal is frf2, and the first and second output frequencies of the frequency conversion circuit are ftx1 and ftx2, respectively, the first division ratio m The second frequency division ratio n is obtained by switching the frequency division ratio of the fourth frequency divider within the frequency range in which the second VCO can oscillate, thereby changing the third mixer output frequency to | (2・
A transceiver that satisfies the condition that (frf1) / n-ftx1 | and | (4 · frf2) / m-ftx2 |. 4. The transceiver according to claim 3, wherein said frequency conversion circuit has a phase comparator, a first low-pass filter, third and fourth VCOs, and a fourth mixer. , The phase comparator outputs a signal proportional to a phase difference between the third mixer output signal and the fourth mixer output signal, and the first low-pass filter is connected to an output of the phase comparator. , The third
And a fourth VCO are connected to the output of the first low-pass filter, and the fourth mixer is connected to the third or fourth VCO.
P for mixing the output signal and the third frequency divider output signal
A transceiver which is a frequency conversion circuit using LL. 5. A variable gain low-pass filter having a variable gain low-pass filter to which a baseband signal is input, and an offset voltage calibration circuit having means for calibrating a DC offset voltage of the low-pass filter. The transceiver comprises a plurality of variable gain amplifiers and a plurality of low-pass filters. 6. The transceiver according to claim 5, wherein the offset voltage calibration circuit detects an ADC to which the output signal of the variable gain amplifier is input, and detects a DC offset voltage of the variable gain amplifier from the ADC output signal. A control circuit for outputting a signal for calibrating the DC offset voltage, and a D for receiving the control circuit output signal and outputting a signal to the variable gain amplifier
A transceiver comprising: an AC; 7. A transceiver according to claim 6, wherein said variable gain amplifier comprises a first and a second transistor having their emitters connected to each other, and a first and a second transistor connected to a collector and a power supply of said first transistor. A resistor, a collector of the second transistor, a second resistor connected to the power supply, and a variable current source connected to the emitter.
A variable gain amplifier characterized in that a signal is output from the collector and a signal is input from the base of the third transistor. The DAC includes a third transistor, a third transistor connected to the emitter of the third transistor, and the ground. And a collector of the third transistor is connected to a collector of the first transistor, and a base of the third transistor is connected to an output of the control circuit. A transceiver. 8. A transceiver according to claim 6, wherein said variable gain low-pass filter is constituted by a differential circuit, and first and second input terminals of at least one of said variable gain amplifiers. A first switch connected between the first and second switches, and the first switch is brought into a short-circuit state or an open state by switch switching control. 9. The transceiver according to claim 6, wherein said variable gain low-pass filter is constituted by a differential circuit, and at least one first low-pass filter among said low-pass filters is a second low-pass filter. And a third switch and a first capacitor, wherein the second switch is connected to a first signal line and the first capacitor of the first low-pass filter, and the third switch is connected to the first switch. A second signal line of the first low-pass filter and the first signal line;
Wherein the second and third switches are brought into a short-circuit state or an open state in synchronization by switch switching control. 10. The transceiver according to claim 9, wherein the control circuit for calibrating the DC offset voltage of the first variable gain amplifier connected before the first low-pass filter comprises:
The first control circuit includes a first DAC and a first control circuit. The first control circuit controls a DC offset voltage of a second variable gain amplifier connected to a stage subsequent to the first low-pass filter. A transceiver characterized by being identical to a circuit. 11. The transceiver according to claim 5, wherein said variable gain low-pass filter is constituted by a differential circuit, and at least one of said variable gain amplifiers has third and fourth input terminals and a first input terminal. And a chopper-type amplifier having a second output terminal and a chopper-type amplifier, wherein the chopper-type amplifier has fifth and sixth input terminals and third and fourth output terminals. A third variable gain amplifier, a fourth switch, and a fifth switch, wherein the third input terminal, the fifth input terminal, and the third input terminal are controlled by switching control of the fourth and fifth switches. A fourth input terminal, the sixth input terminal, and the first input terminal;
And a third state in which the second output terminal and the fourth output terminal are connected to each other, and a third state in which the third input terminal and the sixth input terminal are connected to each other. And the second state in which the first output terminal and the fourth output terminal are connected to each other, and the second output terminal and the third output terminal are connected to each other. Wherein the first and second states are switched periodically. 12. An antenna, an antenna switch connected to the antenna, a plurality of power amplifiers for outputting signals to the antenna switch, a plurality of band-pass filters connected to the antenna switch, and the band-pass filter And a transceiver connected to the power amplifier and a baseband circuit, the transceiver comprising:
12. The mobile communication device according to any one of claims 1 to 11, wherein the baseband circuit outputs to the transceiver a signal defining a timing for starting a DC offset voltage calibration operation. 13. A mobile communication device according to claim 12, wherein a duplexer is used in place of said antenna switch.