JP2001203942A - Output signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an output signal processor, which removes noise components from the output signal of a solid-state image pickup element and outputs a signal component with good S/N, small in space and low in power consumption suitably to, specially, small-sized equipment. SOLUTION: The output signal processor comprises an A/D converter 3 which converts the output signal of the solid-state image pickup element having a signal part and a feed-through part into a digital signal, a correlative double sampling circuit 5 which extracts a signal component having noise components removed from the difference between the level of the signal part of the output signal converted into the digital signal and the level of the feed-through part, and a reference level control circuit 5 which holds constant the level of an optical black area of the video signal outputted from the correlative double sampling circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output signal processing device for removing a noise component from an output signal output from a solid-state imaging device or the like and outputting a video signal having a good S / N ratio, and more particularly to a space saving and The present invention relates to an output signal processing device suitable for a small device such as a mobile phone that requires low power consumption.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a configuration of a conventional output signal processing device. In FIG.
Is output from the correlated double sampling (C
DS) circuit 32 to remove noise components. Further, the optical black (OB) control circuit 33 performs a clamp control by a clamp pulse CP so that the reference level is always constant, and the digital / analog (A)
/ D) is input to the converter 34.

[0003] The video signal converted into a digital signal by the A / D converter 34 is output to a video signal processing unit 35 after being added with horizontal and vertical synchronizing signals. A / D converter 34
The video signal processing unit 35 is integrated with the drive signal generation unit 36 and the frequency divider 37 to form a DSP (digital signal processing) unit.

FIG. 8 is a block diagram showing a configuration of the CDS circuit 32. In the figure, a charge-coupled device (CCD)
An output signal output from the image sensor 31 is connected to two sample / hold (S / H) circuits 32 connected in parallel.
a and 32b. The S / H circuits 32a and 32b sample / hold the output signals at different timings by the sampling pulses SP1 and SP2 having different phases. Outputs of the S / H circuits 32a and 32b are subjected to subtraction processing by a subtraction circuit 32c to output a video signal.

Next, referring to the waveform diagram shown in FIG.
The operation of the circuit 32 will be described. In the figure, (a) is an output signal output from the image sensor 31;
(B) is a sampling pulse SP1, (c) is a reset pulse RP, and (d) is a sampling pulse SP2.

[0006] The output signal shown in (a) is an output waveform of a CCD, and a pixel signal for one pixel is composed of a reset level Vr, a feed-through level Vf, and a signal level Vs according to a signal charge.

[0007] The sampling pulse SP1 shown in (b) samples the feedthrough portion of the output signal at the timing of the time point t1 and holds it in the S / H circuit 32a.
The sampling pulse SP2 shown in (d) samples the signal portion of the output signal at the timing of the time point t2 and performs S /
Hold in the H circuit 32b. As a result, the subtraction circuit 32
From c, only the signal component from which the reset noise superimposed on the feedthrough portion and the signal portion has been removed is output.

As described above, due to the reset noise generated by the reset operation by the reset pulse RP shown in (c), the potentials at the times t1 and t3 slightly vary, but as shown at the times t1 and t2. The same pixel is affected by the same noise, and the noise has a correlation. Therefore, reset noise can be removed by taking the potential difference between two samples in one pixel.

[0009]

By the way, in order to mount the above-mentioned output signal processing device on a small device such as a portable telephone, it is required to reduce the circuit space and power consumption. However, in the conventional output signal processing device, C
There is a problem that it is difficult to integrate the DS circuit and the OB control circuit, which is not suitable for saving space and reducing power consumption.

The present invention has been made to solve such a conventional problem, and provides an output signal processing device suitable for a small device such as a mobile phone by saving space and reducing power consumption. Is to do.

[0011]

According to the present invention, there is provided an output signal processing apparatus comprising: an A / D converter for converting an output signal of a solid-state image sensor into a digital signal; A correlated double sampling circuit for extracting a signal component from which a noise component has been removed by taking a difference between the level of the portion and the level of the feedthrough portion;
A reference level control circuit for keeping the level of an optical black region of the video signal output from the correlated double sampling circuit constant, wherein the correlated double sampling circuit and the reference level control circuit output from the A / D converter It has a configuration for digitally processing a signal.

According to this configuration, the correlated double sampling circuit and the reference level control circuit are configured as digital circuits at the subsequent stage of the A / D converter, so that the circuit can be integrated, and the saving suitable for small devices can be achieved. An output signal processing device suitable for space saving and low power consumption can be obtained.

The output signal processing device according to the present invention is further characterized in that the reference level control circuit outputs a value obtained by averaging the levels of the optical black areas of the video signal output from the correlated double sampling circuit; A subtraction circuit that performs a subtraction process between the video signal output from the correlated double sampling circuit and the signal output from the averaging circuit to keep the level of the optical black area constant.

With this configuration, the black level, which is the reference level, is kept constant by subtracting the average value of the optical black area from the video signal output from the correlated double sampling circuit.

Further, in the output signal processing device of the present invention, a signal selection circuit is provided on the output side of the correlated double sampling circuit, and the signal selection circuit includes an output signal of the correlated double sampling circuit and a signal of the correlated double sampling circuit. It has a configuration in which either an inverted output signal or an output signal bypassing the correlated double sampling circuit is selected and output.

With this configuration, it is possible to select the polarity of the output signal from the correlated double sampling circuit, and to bypass the correlated double sampling circuit when an image pickup device having a CDS function is connected inside. .

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of an output signal processing device according to the present invention. The output signal processing device according to the present embodiment includes an image sensor 1 and a direct current (DC).
A bias circuit 2, an A / D (digital / analog) converter 3, a CDS (correlated double sampling) circuit 4,
An OB (optical black) control circuit 5 as a reference level control circuit and a video signal processing unit 6 are provided.

The A / D converter 3, the CDS circuit 4, the OB control circuit 5, and the video signal processing unit 6, the drive signal generating unit 7 for supplying the device drive pulse to the image sensor 1, and the clock φ are divided by two. The frequency divider 8 that divides the frequency by 1 is integrated by a digital circuit configuration to form a DSP unit.

FIG. 2A is a configuration diagram of the DC bias circuit 2. The DC bias circuit 2 adjusts the DC level so that the level of the sensor signal falls within a specified input signal level range of the A / D converter 3, and the input terminal IN and the power supply terminal TH of the A / D converter 3 are adjusted. , TL, a resistor RH,
RL is connected.

The DC voltage VH is supplied to the reference voltage input terminal TH, and the DC voltage VH is supplied to the reference voltage input terminal TL.
L is supplied. Then, the values of the resistors RH and RL are determined so that the level of the output signal falls within a specified input signal level between the DC voltages VH and VL as shown in FIG.

The DC bias circuit 2 is not limited to a resistor circuit, but may be a diode clamp circuit.
For example, if a clamp diode is connected between the input terminal IN of the A / D converter 3 and the reference voltage input terminal TH, the upper level of the sensor signal is fixed to the DC voltage VH. , VL within a defined input signal level.

FIG. 3 is a block diagram showing a configuration of the CDS circuit 4 having a digital circuit configuration, and also shows the A / D converter 3 and the frequency divider 8 which are peripheral circuits. The CDS circuit 4 includes two latch circuits 4a and 4b for latching output signals converted into a plurality of n-bit digital signals, and a subtraction circuit 4c for subtracting outputs of the latch circuits 4a and 4b. Although a D-type flip-flop is used as the latch circuit in this example, the present invention is not limited to this.

The clock terminals CL of the latch circuits 4a and 4b
K is supplied with the clock 2φ, the enable terminal EN of the latch circuit 4a is supplied with the clock φ divided by half the frequency, and the enable terminal E of the latch circuit 4b is supplied.
N is supplied with a clock φ inverted by an inversion circuit 4d.

A polarity inversion circuit 4e and a signal selection circuit 4f are provided on the output side of the subtraction circuit 4c.
f, the output of the latch circuit 4a, the output of the subtraction circuit 4c, and the output of the polarity inversion circuit 4e for inverting the output of the subtraction circuit 4c,
You may comprise so that it may each select.

In this configuration, if the output of the latch circuit 4a is selected, the signal from the image sensor having the CDS function inside can bypass the CDS circuit 4, and if the output of the subtraction circuit 4c is selected, the CDS The output signal of the circuit 4 can be selected, and if the output of the polarity inversion circuit 4e is selected, the inverted output signal of the CDS circuit 4 can be selected.

FIG. 4 is a waveform diagram for explaining the operation of the CDS circuit 4. (A) is an output signal output from the image sensor 1, (b) is a clock 2φ which is an A / D conversion timing pulse, (c) is an output signal output from the A / D converter 3, and (d) is an output signal. The clock φ, which is a latch pulse, (e) is an output signal output from the latch circuit 4b, and (f) is an output signal output from the latch circuit 4a. Image sensor 1
Are output of the CMOS sensor in this example, the periods A1, A2,... Are feed-through portions, and the periods B1, B2,.

The A / D converter 3 converts the sensor signal into a digital signal at the time when the clock 2φ rises. The converted sensor signal is latched by the latch circuit 4a during the H level of the clock φ, and is latched by the latch circuit 4b during the L level of the clock φ.

Therefore, the signal portion of the output signal is latched by the latch circuit 4a, and the feedthrough portion of the output signal is latched by the latch circuit 4b. For this reason, since the noise component is superimposed on both portions, only the signal component from which the noise component has been removed is output from the subtraction circuit 4c.

FIG. 5 is a block diagram showing the configuration of the OB control circuit 5 having a digital circuit configuration. The horizontal OB for calculating the average value of the OB area in the horizontal direction from the output of the CDS circuit 4 is shown in FIG.
Average value calculation circuit 5a and vertical OB average value calculation circuit 5b for calculating a vertical average value of the OB area from its output
And a subtraction circuit 5c for subtracting the output from the CDS circuit 4. Horizontal OB average value calculation circuit 5
a and the vertical OB average value calculation circuit 5b constitute an addition average circuit.

As shown in FIG. 6, the image sensor 1 comprises an effective pixel area 1a and an OB area 1b.
A predetermined region in the horizontal scanning position setting pulse S
The average value in the OB sampling area SPE specified by the PH and the vertical sampling position setting pulse SPV is calculated for each frame or each field.

Then, by subtracting the averaged signal in the OB sampling area SPE from the output signal of the CDS circuit 4 by the subtraction circuit 5c, the black level, which is the reference in the subsequent signal processing, is always kept constant. it can.

Thus, the DC level of the output signal output from the image sensor 1 is adjusted by the DC bias circuit 2 so that the output signal falls within the specified input signal level range of the A / D converter 3. At 3 the digital signal is converted at the rise of the clock 2φ.

The video signal converted into a digital signal is
The signal is latched by latch circuit 4a at the rise of clock φ, and latched by latch circuit 4b during the L level period of clock φ. Since the rising point of the clock φ is the signal output part of the sensor signal and the falling point of the clock φ is the feedthrough part of the sensor signal, only the signal component from which the noise component has been removed is output from the subtraction circuit 4c. .

The video signal from which the noise component has been removed is controlled by the OB control circuit 5 so that the level of the retrace period is kept constant, and is input to the video signal processing unit 6. The video signal input to the video signal processing unit 6 is added with a horizontal and vertical synchronizing signal and output as a composite video signal.

When the output signal is delayed between the image pickup device 1 and the A / D converter 3, a clock is used to prevent the image quality from being deteriorated by the sampling error in the A / D converter 3 and the CDS circuit 4. May be configured to be variable. In this case, the conventional CDS circuit 3
Although it was necessary to change the phase of the sampling pulse 2 and the phase of the clock pulse of the A / D converter 34, in the present embodiment, it is only necessary to change the phase of the clock 2φ.

[0037]

As described above, according to the present invention, since the CDS circuit and the OB control circuit are provided at the subsequent stage of the A / D converter and are constituted by digital circuits, integration is easy, space saving and low power consumption are achieved. An output signal processing device capable of reducing power consumption can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an output signal processing device according to the present invention.

2A is a configuration diagram of a DC bias circuit, and FIG. 2B is an explanatory diagram of its operation.

FIG. 3 is a block diagram showing a configuration of the CDS circuit shown in FIG.

FIG. 4 is a waveform chart illustrating the operation of the CDS circuit.

FIG. 5 is a block diagram showing a configuration of the OB control circuit shown in FIG. 1;

FIG. 6 is a diagram showing an effective pixel area and an OB area of the image sensor;

FIG. 7 is a block diagram showing a conventional output signal processing device.

8 is a block diagram showing a configuration of the CDS circuit shown in FIG.

9 is a waveform chart illustrating the operation of the CDS circuit shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image sensor 1a Effective pixel area 1b OB (optical black) area 2 DC bias circuit 3 A / D converter 4 CDS (correlated double sampling) circuit 4a, 4b Latch circuit 4c Subtraction circuit 4d Inversion circuit 4e Polarity inversion circuit 4f Signal selection circuit 5 OB control circuit 5a Horizontal OB average value calculation circuit 5a Vertical OB average value calculation circuit 5c Subtraction circuit 6 Video signal processing unit 7 Drive signal generation unit 8 Divider

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C021 PA13 PA66 PA76 PA83 PA95 PA96 SA08 XA41 5C024 AX01 CX06 CX31 CY42 DX07 HX01 HX09 HX21 HX23 HX29 HX35 HX44 JX34

Claims (3)

[Claims] An A / D converter for converting an output signal of the solid-state imaging device into a digital signal; and a level of a signal portion of the output signal of the solid-state imaging device converted into the digital signal and a level of a feedthrough portion. A correlated double sampling circuit that extracts a signal component from which a noise component has been removed by taking a difference; and a reference level control circuit that keeps a level of an optical black region of a video signal output from the correlated double sampling circuit constant. An output signal processing device, wherein the correlated double sampling circuit and the reference level control circuit digitally process an output signal from the A / D converter. 2. The reference level control circuit, comprising: an averaging circuit that outputs a value obtained by averaging levels of an optical black area of the video signal output from the correlated double sampling circuit; A subtraction circuit that performs a subtraction process between the video signal output from the circuit and the signal output from the averaging circuit to keep the level of the optical black region constant. The output signal processing device according to claim 1. 3. A signal selection circuit is provided on an output side of the correlated double sampling circuit, wherein the signal selection circuit outputs an output signal of the correlated double sampling circuit, an inverted output signal of the correlated double sampling circuit, or 2. The output signal processing device according to claim 1, wherein the output signal processing device is configured to select and output any one of the output signals bypassing the correlated double sampling circuit.